arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/gpio.h>
  26 #include <plat/dma.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/mcbsp.h>
  29 #include <plat/mmc.h>
  30
  31 #include "omap_hwmod_common_data.h"
  32
  33 #include "cm1_44xx.h"
  34 #include "cm2_44xx.h"
  35 #include "prm44xx.h"
  36 #include "prm-regbits-44xx.h"
  37 #include "wd_timer.h"
  38
  39 /* Base offset for all OMAP4 interrupts external to MPUSS */
  40 #define OMAP44XX_IRQ_GIC_START  32
  41
  42 /* Base offset for all OMAP4 dma requests */
  43 #define OMAP44XX_DMA_REQ_START  1
  44
  45 /* Backward references (IPs with Bus Master capability) */
  46 static struct omap_hwmod omap44xx_aess_hwmod;
  47 static struct omap_hwmod omap44xx_dma_system_hwmod;
  48 static struct omap_hwmod omap44xx_dmm_hwmod;
  49 static struct omap_hwmod omap44xx_dsp_hwmod;
  50 static struct omap_hwmod omap44xx_dss_hwmod;
  51 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  52 static struct omap_hwmod omap44xx_hsi_hwmod;
  53 static struct omap_hwmod omap44xx_ipu_hwmod;
  54 static struct omap_hwmod omap44xx_iss_hwmod;
  55 static struct omap_hwmod omap44xx_iva_hwmod;
  56 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  57 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  58 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  59 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  60 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  61 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  62 static struct omap_hwmod omap44xx_l4_per_hwmod;
  63 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  64 static struct omap_hwmod omap44xx_mmc1_hwmod;
  65 static struct omap_hwmod omap44xx_mmc2_hwmod;
  66 static struct omap_hwmod omap44xx_mpu_hwmod;
  67 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  68 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  69
  70 /*
  71  * Interconnects omap_hwmod structures
  72  * hwmods that compose the global OMAP interconnect
  73  */
  74
  75 /*
  76  * 'dmm' class
  77  * instance(s): dmm
  78  */
  79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  80         .name   = "dmm",
  81 };
  82
  83 /* dmm interface data */
  84 /* l3_main_1 -> dmm */
  85 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  86         .master         = &omap44xx_l3_main_1_hwmod,
  87         .slave          = &omap44xx_dmm_hwmod,
  88         .clk            = "l3_div_ck",
  89         .user           = OCP_USER_SDMA,
  90 };
  91
  92 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
  93         {
  94                 .pa_start       = 0x4e000000,
  95                 .pa_end         = 0x4e0007ff,
  96                 .flags          = ADDR_TYPE_RT
  97         },
  98         { }
  99 };
 100
 101 /* mpu -> dmm */
 102 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 103         .master         = &omap44xx_mpu_hwmod,
 104         .slave          = &omap44xx_dmm_hwmod,
 105         .clk            = "l3_div_ck",
 106         .addr           = omap44xx_dmm_addrs,
 107         .user           = OCP_USER_MPU,
 108 };
 109
 110 /* dmm slave ports */
 111 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 112         &omap44xx_l3_main_1__dmm,
 113         &omap44xx_mpu__dmm,
 114 };
 115
 116 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
 117         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
 118         { .irq = -1 }
 119 };
 120
 121 static struct omap_hwmod omap44xx_dmm_hwmod = {
 122         .name           = "dmm",
 123         .class          = &omap44xx_dmm_hwmod_class,
 124         .slaves         = omap44xx_dmm_slaves,
 125         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 126         .mpu_irqs       = omap44xx_dmm_irqs,
 127         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 128 };
 129
 130 /*
 131  * 'emif_fw' class
 132  * instance(s): emif_fw
 133  */
 134 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 135         .name   = "emif_fw",
 136 };
 137
 138 /* emif_fw interface data */
 139 /* dmm -> emif_fw */
 140 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 141         .master         = &omap44xx_dmm_hwmod,
 142         .slave          = &omap44xx_emif_fw_hwmod,
 143         .clk            = "l3_div_ck",
 144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 145 };
 146
 147 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 148         {
 149                 .pa_start       = 0x4a20c000,
 150                 .pa_end         = 0x4a20c0ff,
 151                 .flags          = ADDR_TYPE_RT
 152         },
 153         { }
 154 };
 155
 156 /* l4_cfg -> emif_fw */
 157 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 158         .master         = &omap44xx_l4_cfg_hwmod,
 159         .slave          = &omap44xx_emif_fw_hwmod,
 160         .clk            = "l4_div_ck",
 161         .addr           = omap44xx_emif_fw_addrs,
 162         .user           = OCP_USER_MPU,
 163 };
 164
 165 /* emif_fw slave ports */
 166 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 167         &omap44xx_dmm__emif_fw,
 168         &omap44xx_l4_cfg__emif_fw,
 169 };
 170
 171 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 172         .name           = "emif_fw",
 173         .class          = &omap44xx_emif_fw_hwmod_class,
 174         .slaves         = omap44xx_emif_fw_slaves,
 175         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 176         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 177 };
 178
 179 /*
 180  * 'l3' class
 181  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 182  */
 183 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 184         .name   = "l3",
 185 };
 186
 187 /* l3_instr interface data */
 188 /* iva -> l3_instr */
 189 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 190         .master         = &omap44xx_iva_hwmod,
 191         .slave          = &omap44xx_l3_instr_hwmod,
 192         .clk            = "l3_div_ck",
 193         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 194 };
 195
 196 /* l3_main_3 -> l3_instr */
 197 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 198         .master         = &omap44xx_l3_main_3_hwmod,
 199         .slave          = &omap44xx_l3_instr_hwmod,
 200         .clk            = "l3_div_ck",
 201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 202 };
 203
 204 /* l3_instr slave ports */
 205 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 206         &omap44xx_iva__l3_instr,
 207         &omap44xx_l3_main_3__l3_instr,
 208 };
 209
 210 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 211         .name           = "l3_instr",
 212         .class          = &omap44xx_l3_hwmod_class,
 213         .slaves         = omap44xx_l3_instr_slaves,
 214         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 215         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 216 };
 217
 218 /* l3_main_1 interface data */
 219 /* dsp -> l3_main_1 */
 220 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 221         .master         = &omap44xx_dsp_hwmod,
 222         .slave          = &omap44xx_l3_main_1_hwmod,
 223         .clk            = "l3_div_ck",
 224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 225 };
 226
 227 /* dss -> l3_main_1 */
 228 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 229         .master         = &omap44xx_dss_hwmod,
 230         .slave          = &omap44xx_l3_main_1_hwmod,
 231         .clk            = "l3_div_ck",
 232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 233 };
 234
 235 /* l3_main_2 -> l3_main_1 */
 236 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 237         .master         = &omap44xx_l3_main_2_hwmod,
 238         .slave          = &omap44xx_l3_main_1_hwmod,
 239         .clk            = "l3_div_ck",
 240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 241 };
 242
 243 /* l4_cfg -> l3_main_1 */
 244 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 245         .master         = &omap44xx_l4_cfg_hwmod,
 246         .slave          = &omap44xx_l3_main_1_hwmod,
 247         .clk            = "l4_div_ck",
 248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 249 };
 250
 251 /* mmc1 -> l3_main_1 */
 252 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 253         .master         = &omap44xx_mmc1_hwmod,
 254         .slave          = &omap44xx_l3_main_1_hwmod,
 255         .clk            = "l3_div_ck",
 256         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 257 };
 258
 259 /* mmc2 -> l3_main_1 */
 260 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 261         .master         = &omap44xx_mmc2_hwmod,
 262         .slave          = &omap44xx_l3_main_1_hwmod,
 263         .clk            = "l3_div_ck",
 264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 265 };
 266
 267 /* L3 target configuration and error log registers */
 268 static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
 269         { .irq = 9  + OMAP44XX_IRQ_GIC_START },
 270         { .irq = 10 + OMAP44XX_IRQ_GIC_START },
 271         { .irq = -1 }
 272 };
 273
 274 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
 275         {
 276                 .pa_start       = 0x44000000,
 277                 .pa_end         = 0x44000fff,
 278                 .flags          = ADDR_TYPE_RT,
 279         },
 280         { }
 281 };
 282
 283 /* mpu -> l3_main_1 */
 284 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 285         .master         = &omap44xx_mpu_hwmod,
 286         .slave          = &omap44xx_l3_main_1_hwmod,
 287         .clk            = "l3_div_ck",
 288         .addr           = omap44xx_l3_main_1_addrs,
 289         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 290 };
 291
 292 /* l3_main_1 slave ports */
 293 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 294         &omap44xx_dsp__l3_main_1,
 295         &omap44xx_dss__l3_main_1,
 296         &omap44xx_l3_main_2__l3_main_1,
 297         &omap44xx_l4_cfg__l3_main_1,
 298         &omap44xx_mmc1__l3_main_1,
 299         &omap44xx_mmc2__l3_main_1,
 300         &omap44xx_mpu__l3_main_1,
 301 };
 302
 303 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 304         .name           = "l3_main_1",
 305         .class          = &omap44xx_l3_hwmod_class,
 306         .mpu_irqs       = omap44xx_l3_targ_irqs,
 307         .slaves         = omap44xx_l3_main_1_slaves,
 308         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 309         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 310 };
 311
 312 /* l3_main_2 interface data */
 313 /* dma_system -> l3_main_2 */
 314 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 315         .master         = &omap44xx_dma_system_hwmod,
 316         .slave          = &omap44xx_l3_main_2_hwmod,
 317         .clk            = "l3_div_ck",
 318         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 319 };
 320
 321 /* hsi -> l3_main_2 */
 322 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 323         .master         = &omap44xx_hsi_hwmod,
 324         .slave          = &omap44xx_l3_main_2_hwmod,
 325         .clk            = "l3_div_ck",
 326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 327 };
 328
 329 /* ipu -> l3_main_2 */
 330 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 331         .master         = &omap44xx_ipu_hwmod,
 332         .slave          = &omap44xx_l3_main_2_hwmod,
 333         .clk            = "l3_div_ck",
 334         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 335 };
 336
 337 /* iss -> l3_main_2 */
 338 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 339         .master         = &omap44xx_iss_hwmod,
 340         .slave          = &omap44xx_l3_main_2_hwmod,
 341         .clk            = "l3_div_ck",
 342         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 343 };
 344
 345 /* iva -> l3_main_2 */
 346 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 347         .master         = &omap44xx_iva_hwmod,
 348         .slave          = &omap44xx_l3_main_2_hwmod,
 349         .clk            = "l3_div_ck",
 350         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 351 };
 352
 353 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
 354         {
 355                 .pa_start       = 0x44800000,
 356                 .pa_end         = 0x44801fff,
 357                 .flags          = ADDR_TYPE_RT,
 358         },
 359         { }
 360 };
 361
 362 /* l3_main_1 -> l3_main_2 */
 363 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 364         .master         = &omap44xx_l3_main_1_hwmod,
 365         .slave          = &omap44xx_l3_main_2_hwmod,
 366         .clk            = "l3_div_ck",
 367         .addr           = omap44xx_l3_main_2_addrs,
 368         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 369 };
 370
 371 /* l4_cfg -> l3_main_2 */
 372 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 373         .master         = &omap44xx_l4_cfg_hwmod,
 374         .slave          = &omap44xx_l3_main_2_hwmod,
 375         .clk            = "l4_div_ck",
 376         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 377 };
 378
 379 /* usb_otg_hs -> l3_main_2 */
 380 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 381         .master         = &omap44xx_usb_otg_hs_hwmod,
 382         .slave          = &omap44xx_l3_main_2_hwmod,
 383         .clk            = "l3_div_ck",
 384         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 385 };
 386
 387 /* l3_main_2 slave ports */
 388 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 389         &omap44xx_dma_system__l3_main_2,
 390         &omap44xx_hsi__l3_main_2,
 391         &omap44xx_ipu__l3_main_2,
 392         &omap44xx_iss__l3_main_2,
 393         &omap44xx_iva__l3_main_2,
 394         &omap44xx_l3_main_1__l3_main_2,
 395         &omap44xx_l4_cfg__l3_main_2,
 396         &omap44xx_usb_otg_hs__l3_main_2,
 397 };
 398
 399 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 400         .name           = "l3_main_2",
 401         .class          = &omap44xx_l3_hwmod_class,
 402         .slaves         = omap44xx_l3_main_2_slaves,
 403         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 404         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 405 };
 406
 407 /* l3_main_3 interface data */
 408 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
 409         {
 410                 .pa_start       = 0x45000000,
 411                 .pa_end         = 0x45000fff,
 412                 .flags          = ADDR_TYPE_RT,
 413         },
 414         { }
 415 };
 416
 417 /* l3_main_1 -> l3_main_3 */
 418 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 419         .master         = &omap44xx_l3_main_1_hwmod,
 420         .slave          = &omap44xx_l3_main_3_hwmod,
 421         .clk            = "l3_div_ck",
 422         .addr           = omap44xx_l3_main_3_addrs,
 423         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 424 };
 425
 426 /* l3_main_2 -> l3_main_3 */
 427 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 428         .master         = &omap44xx_l3_main_2_hwmod,
 429         .slave          = &omap44xx_l3_main_3_hwmod,
 430         .clk            = "l3_div_ck",
 431         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 432 };
 433
 434 /* l4_cfg -> l3_main_3 */
 435 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 436         .master         = &omap44xx_l4_cfg_hwmod,
 437         .slave          = &omap44xx_l3_main_3_hwmod,
 438         .clk            = "l4_div_ck",
 439         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 440 };
 441
 442 /* l3_main_3 slave ports */
 443 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 444         &omap44xx_l3_main_1__l3_main_3,
 445         &omap44xx_l3_main_2__l3_main_3,
 446         &omap44xx_l4_cfg__l3_main_3,
 447 };
 448
 449 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 450         .name           = "l3_main_3",
 451         .class          = &omap44xx_l3_hwmod_class,
 452         .slaves         = omap44xx_l3_main_3_slaves,
 453         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 454         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 455 };
 456
 457 /*
 458  * 'l4' class
 459  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 460  */
 461 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 462         .name   = "l4",
 463 };
 464
 465 /* l4_abe interface data */
 466 /* aess -> l4_abe */
 467 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 468         .master         = &omap44xx_aess_hwmod,
 469         .slave          = &omap44xx_l4_abe_hwmod,
 470         .clk            = "ocp_abe_iclk",
 471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 472 };
 473
 474 /* dsp -> l4_abe */
 475 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 476         .master         = &omap44xx_dsp_hwmod,
 477         .slave          = &omap44xx_l4_abe_hwmod,
 478         .clk            = "ocp_abe_iclk",
 479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 480 };
 481
 482 /* l3_main_1 -> l4_abe */
 483 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 484         .master         = &omap44xx_l3_main_1_hwmod,
 485         .slave          = &omap44xx_l4_abe_hwmod,
 486         .clk            = "l3_div_ck",
 487         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 488 };
 489
 490 /* mpu -> l4_abe */
 491 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 492         .master         = &omap44xx_mpu_hwmod,
 493         .slave          = &omap44xx_l4_abe_hwmod,
 494         .clk            = "ocp_abe_iclk",
 495         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 496 };
 497
 498 /* l4_abe slave ports */
 499 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 500         &omap44xx_aess__l4_abe,
 501         &omap44xx_dsp__l4_abe,
 502         &omap44xx_l3_main_1__l4_abe,
 503         &omap44xx_mpu__l4_abe,
 504 };
 505
 506 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 507         .name           = "l4_abe",
 508         .class          = &omap44xx_l4_hwmod_class,
 509         .slaves         = omap44xx_l4_abe_slaves,
 510         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 511         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 512 };
 513
 514 /* l4_cfg interface data */
 515 /* l3_main_1 -> l4_cfg */
 516 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 517         .master         = &omap44xx_l3_main_1_hwmod,
 518         .slave          = &omap44xx_l4_cfg_hwmod,
 519         .clk            = "l3_div_ck",
 520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 521 };
 522
 523 /* l4_cfg slave ports */
 524 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 525         &omap44xx_l3_main_1__l4_cfg,
 526 };
 527
 528 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 529         .name           = "l4_cfg",
 530         .class          = &omap44xx_l4_hwmod_class,
 531         .slaves         = omap44xx_l4_cfg_slaves,
 532         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 533         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 534 };
 535
 536 /* l4_per interface data */
 537 /* l3_main_2 -> l4_per */
 538 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 539         .master         = &omap44xx_l3_main_2_hwmod,
 540         .slave          = &omap44xx_l4_per_hwmod,
 541         .clk            = "l3_div_ck",
 542         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 543 };
 544
 545 /* l4_per slave ports */
 546 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 547         &omap44xx_l3_main_2__l4_per,
 548 };
 549
 550 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 551         .name           = "l4_per",
 552         .class          = &omap44xx_l4_hwmod_class,
 553         .slaves         = omap44xx_l4_per_slaves,
 554         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 555         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 556 };
 557
 558 /* l4_wkup interface data */
 559 /* l4_cfg -> l4_wkup */
 560 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 561         .master         = &omap44xx_l4_cfg_hwmod,
 562         .slave          = &omap44xx_l4_wkup_hwmod,
 563         .clk            = "l4_div_ck",
 564         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 565 };
 566
 567 /* l4_wkup slave ports */
 568 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 569         &omap44xx_l4_cfg__l4_wkup,
 570 };
 571
 572 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 573         .name           = "l4_wkup",
 574         .class          = &omap44xx_l4_hwmod_class,
 575         .slaves         = omap44xx_l4_wkup_slaves,
 576         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 577         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 578 };
 579
 580 /*
 581  * 'mpu_bus' class
 582  * instance(s): mpu_private
 583  */
 584 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 585         .name   = "mpu_bus",
 586 };
 587
 588 /* mpu_private interface data */
 589 /* mpu -> mpu_private */
 590 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 591         .master         = &omap44xx_mpu_hwmod,
 592         .slave          = &omap44xx_mpu_private_hwmod,
 593         .clk            = "l3_div_ck",
 594         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 595 };
 596
 597 /* mpu_private slave ports */
 598 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 599         &omap44xx_mpu__mpu_private,
 600 };
 601
 602 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 603         .name           = "mpu_private",
 604         .class          = &omap44xx_mpu_bus_hwmod_class,
 605         .slaves         = omap44xx_mpu_private_slaves,
 606         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 607         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 608 };
 609
 610 /*
 611  * Modules omap_hwmod structures
 612  *
 613  * The following IPs are excluded for the moment because:
 614  * - They do not need an explicit SW control using omap_hwmod API.
 615  * - They still need to be validated with the driver
 616  *   properly adapted to omap_hwmod / omap_device
 617  *
 618  *  c2c
 619  *  c2c_target_fw
 620  *  cm_core
 621  *  cm_core_aon
 622  *  ctrl_module_core
 623  *  ctrl_module_pad_core
 624  *  ctrl_module_pad_wkup
 625  *  ctrl_module_wkup
 626  *  debugss
 627  *  efuse_ctrl_cust
 628  *  efuse_ctrl_std
 629  *  elm
 630  *  emif1
 631  *  emif2
 632  *  fdif
 633  *  gpmc
 634  *  gpu
 635  *  hdq1w
 636  *  hsi
 637  *  ocmc_ram
 638  *  ocp2scp_usb_phy
 639  *  ocp_wp_noc
 640  *  prcm_mpu
 641  *  prm
 642  *  scrm
 643  *  sl2if
 644  *  slimbus1
 645  *  slimbus2
 646  *  usb_host_fs
 647  *  usb_host_hs
 648  *  usb_phy_cm
 649  *  usb_tll_hs
 650  *  usim
 651  */
 652
 653 /*
 654  * 'aess' class
 655  * audio engine sub system
 656  */
 657
 658 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 659         .rev_offs       = 0x0000,
 660         .sysc_offs      = 0x0010,
 661         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 662         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 663                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 664         .sysc_fields    = &omap_hwmod_sysc_type2,
 665 };
 666
 667 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 668         .name   = "aess",
 669         .sysc   = &omap44xx_aess_sysc,
 670 };
 671
 672 /* aess */
 673 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 674         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 675         { .irq = -1 }
 676 };
 677
 678 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 679         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 680         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 681         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 682         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 683         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 684         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 685         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 686         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 687 };
 688
 689 /* aess master ports */
 690 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 691         &omap44xx_aess__l4_abe,
 692 };
 693
 694 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 695         {
 696                 .pa_start       = 0x401f1000,
 697                 .pa_end         = 0x401f13ff,
 698                 .flags          = ADDR_TYPE_RT
 699         },
 700         { }
 701 };
 702
 703 /* l4_abe -> aess */
 704 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 705         .master         = &omap44xx_l4_abe_hwmod,
 706         .slave          = &omap44xx_aess_hwmod,
 707         .clk            = "ocp_abe_iclk",
 708         .addr           = omap44xx_aess_addrs,
 709         .user           = OCP_USER_MPU,
 710 };
 711
 712 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 713         {
 714                 .pa_start       = 0x490f1000,
 715                 .pa_end         = 0x490f13ff,
 716                 .flags          = ADDR_TYPE_RT
 717         },
 718         { }
 719 };
 720
 721 /* l4_abe -> aess (dma) */
 722 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 723         .master         = &omap44xx_l4_abe_hwmod,
 724         .slave          = &omap44xx_aess_hwmod,
 725         .clk            = "ocp_abe_iclk",
 726         .addr           = omap44xx_aess_dma_addrs,
 727         .user           = OCP_USER_SDMA,
 728 };
 729
 730 /* aess slave ports */
 731 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 732         &omap44xx_l4_abe__aess,
 733         &omap44xx_l4_abe__aess_dma,
 734 };
 735
 736 static struct omap_hwmod omap44xx_aess_hwmod = {
 737         .name           = "aess",
 738         .class          = &omap44xx_aess_hwmod_class,
 739         .mpu_irqs       = omap44xx_aess_irqs,
 740         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 741         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
 742         .main_clk       = "aess_fck",
 743         .prcm           = {
 744                 .omap4 = {
 745                         .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 746                 },
 747         },
 748         .slaves         = omap44xx_aess_slaves,
 749         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 750         .masters        = omap44xx_aess_masters,
 751         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 752         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 753 };
 754
 755 /*
 756  * 'bandgap' class
 757  * bangap reference for ldo regulators
 758  */
 759
 760 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 761         .name   = "bandgap",
 762 };
 763
 764 /* bandgap */
 765 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 766         { .role = "fclk", .clk = "bandgap_fclk" },
 767 };
 768
 769 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 770         .name           = "bandgap",
 771         .class          = &omap44xx_bandgap_hwmod_class,
 772         .prcm           = {
 773                 .omap4 = {
 774                         .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 775                 },
 776         },
 777         .opt_clks       = bandgap_opt_clks,
 778         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 779         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 780 };
 781
 782 /*
 783  * 'counter' class
 784  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 785  */
 786
 787 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 788         .rev_offs       = 0x0000,
 789         .sysc_offs      = 0x0004,
 790         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 791         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 792                            SIDLE_SMART_WKUP),
 793         .sysc_fields    = &omap_hwmod_sysc_type1,
 794 };
 795
 796 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 797         .name   = "counter",
 798         .sysc   = &omap44xx_counter_sysc,
 799 };
 800
 801 /* counter_32k */
 802 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 803 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 804         {
 805                 .pa_start       = 0x4a304000,
 806                 .pa_end         = 0x4a30401f,
 807                 .flags          = ADDR_TYPE_RT
 808         },
 809         { }
 810 };
 811
 812 /* l4_wkup -> counter_32k */
 813 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 814         .master         = &omap44xx_l4_wkup_hwmod,
 815         .slave          = &omap44xx_counter_32k_hwmod,
 816         .clk            = "l4_wkup_clk_mux_ck",
 817         .addr           = omap44xx_counter_32k_addrs,
 818         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 819 };
 820
 821 /* counter_32k slave ports */
 822 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 823         &omap44xx_l4_wkup__counter_32k,
 824 };
 825
 826 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 827         .name           = "counter_32k",
 828         .class          = &omap44xx_counter_hwmod_class,
 829         .flags          = HWMOD_SWSUP_SIDLE,
 830         .main_clk       = "sys_32k_ck",
 831         .prcm           = {
 832                 .omap4 = {
 833                         .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
 834                 },
 835         },
 836         .slaves         = omap44xx_counter_32k_slaves,
 837         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 838         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 839 };
 840
 841 /*
 842  * 'dma' class
 843  * dma controller for data exchange between memory to memory (i.e. internal or
 844  * external memory) and gp peripherals to memory or memory to gp peripherals
 845  */
 846
 847 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 848         .rev_offs       = 0x0000,
 849         .sysc_offs      = 0x002c,
 850         .syss_offs      = 0x0028,
 851         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 852                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 853                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 854                            SYSS_HAS_RESET_STATUS),
 855         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 856                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 857         .sysc_fields    = &omap_hwmod_sysc_type1,
 858 };
 859
 860 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 861         .name   = "dma",
 862         .sysc   = &omap44xx_dma_sysc,
 863 };
 864
 865 /* dma dev_attr */
 866 static struct omap_dma_dev_attr dma_dev_attr = {
 867         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 868                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 869         .lch_count      = 32,
 870 };
 871
 872 /* dma_system */
 873 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 874         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 875         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 876         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 877         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 878         { .irq = -1 }
 879 };
 880
 881 /* dma_system master ports */
 882 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 883         &omap44xx_dma_system__l3_main_2,
 884 };
 885
 886 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 887         {
 888                 .pa_start       = 0x4a056000,
 889                 .pa_end         = 0x4a056fff,
 890                 .flags          = ADDR_TYPE_RT
 891         },
 892         { }
 893 };
 894
 895 /* l4_cfg -> dma_system */
 896 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 897         .master         = &omap44xx_l4_cfg_hwmod,
 898         .slave          = &omap44xx_dma_system_hwmod,
 899         .clk            = "l4_div_ck",
 900         .addr           = omap44xx_dma_system_addrs,
 901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 902 };
 903
 904 /* dma_system slave ports */
 905 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 906         &omap44xx_l4_cfg__dma_system,
 907 };
 908
 909 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 910         .name           = "dma_system",
 911         .class          = &omap44xx_dma_hwmod_class,
 912         .mpu_irqs       = omap44xx_dma_system_irqs,
 913         .main_clk       = "l3_div_ck",
 914         .prcm = {
 915                 .omap4 = {
 916                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
 917                 },
 918         },
 919         .dev_attr       = &dma_dev_attr,
 920         .slaves         = omap44xx_dma_system_slaves,
 921         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 922         .masters        = omap44xx_dma_system_masters,
 923         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 924         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 925 };
 926
 927 /*
 928  * 'dmic' class
 929  * digital microphone controller
 930  */
 931
 932 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 933         .rev_offs       = 0x0000,
 934         .sysc_offs      = 0x0010,
 935         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 936                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 937         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 938                            SIDLE_SMART_WKUP),
 939         .sysc_fields    = &omap_hwmod_sysc_type2,
 940 };
 941
 942 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 943         .name   = "dmic",
 944         .sysc   = &omap44xx_dmic_sysc,
 945 };
 946
 947 /* dmic */
 948 static struct omap_hwmod omap44xx_dmic_hwmod;
 949 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 950         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 951         { .irq = -1 }
 952 };
 953
 954 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 955         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 956 };
 957
 958 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
 959         {
 960                 .pa_start       = 0x4012e000,
 961                 .pa_end         = 0x4012e07f,
 962                 .flags          = ADDR_TYPE_RT
 963         },
 964         { }
 965 };
 966
 967 /* l4_abe -> dmic */
 968 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
 969         .master         = &omap44xx_l4_abe_hwmod,
 970         .slave          = &omap44xx_dmic_hwmod,
 971         .clk            = "ocp_abe_iclk",
 972         .addr           = omap44xx_dmic_addrs,
 973         .user           = OCP_USER_MPU,
 974 };
 975
 976 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
 977         {
 978                 .pa_start       = 0x4902e000,
 979                 .pa_end         = 0x4902e07f,
 980                 .flags          = ADDR_TYPE_RT
 981         },
 982         { }
 983 };
 984
 985 /* l4_abe -> dmic (dma) */
 986 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
 987         .master         = &omap44xx_l4_abe_hwmod,
 988         .slave          = &omap44xx_dmic_hwmod,
 989         .clk            = "ocp_abe_iclk",
 990         .addr           = omap44xx_dmic_dma_addrs,
 991         .user           = OCP_USER_SDMA,
 992 };
 993
 994 /* dmic slave ports */
 995 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
 996         &omap44xx_l4_abe__dmic,
 997         &omap44xx_l4_abe__dmic_dma,
 998 };
 999
1000 static struct omap_hwmod omap44xx_dmic_hwmod = {
1001         .name           = "dmic",
1002         .class          = &omap44xx_dmic_hwmod_class,
1003         .mpu_irqs       = omap44xx_dmic_irqs,
1004         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1005         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
1006         .main_clk       = "dmic_fck",
1007         .prcm           = {
1008                 .omap4 = {
1009                         .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1010                 },
1011         },
1012         .slaves         = omap44xx_dmic_slaves,
1013         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1014         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1015 };
1016
1017 /*
1018  * 'dsp' class
1019  * dsp sub-system
1020  */
1021
1022 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1023         .name   = "dsp",
1024 };
1025
1026 /* dsp */
1027 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1028         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1029         { .irq = -1 }
1030 };
1031
1032 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1033         { .name = "mmu_cache", .rst_shift = 1 },
1034 };
1035
1036 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1037         { .name = "dsp", .rst_shift = 0 },
1038 };
1039
1040 /* dsp -> iva */
1041 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1042         .master         = &omap44xx_dsp_hwmod,
1043         .slave          = &omap44xx_iva_hwmod,
1044         .clk            = "dpll_iva_m5x2_ck",
1045 };
1046
1047 /* dsp master ports */
1048 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1049         &omap44xx_dsp__l3_main_1,
1050         &omap44xx_dsp__l4_abe,
1051         &omap44xx_dsp__iva,
1052 };
1053
1054 /* l4_cfg -> dsp */
1055 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1056         .master         = &omap44xx_l4_cfg_hwmod,
1057         .slave          = &omap44xx_dsp_hwmod,
1058         .clk            = "l4_div_ck",
1059         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1060 };
1061
1062 /* dsp slave ports */
1063 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1064         &omap44xx_l4_cfg__dsp,
1065 };
1066
1067 /* Pseudo hwmod for reset control purpose only */
1068 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1069         .name           = "dsp_c0",
1070         .class          = &omap44xx_dsp_hwmod_class,
1071         .flags          = HWMOD_INIT_NO_RESET,
1072         .rst_lines      = omap44xx_dsp_c0_resets,
1073         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1074         .prcm = {
1075                 .omap4 = {
1076                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1077                 },
1078         },
1079         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1080 };
1081
1082 static struct omap_hwmod omap44xx_dsp_hwmod = {
1083         .name           = "dsp",
1084         .class          = &omap44xx_dsp_hwmod_class,
1085         .mpu_irqs       = omap44xx_dsp_irqs,
1086         .rst_lines      = omap44xx_dsp_resets,
1087         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1088         .main_clk       = "dsp_fck",
1089         .prcm = {
1090                 .omap4 = {
1091                         .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1092                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1093                 },
1094         },
1095         .slaves         = omap44xx_dsp_slaves,
1096         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1097         .masters        = omap44xx_dsp_masters,
1098         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1099         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1100 };
1101
1102 /*
1103  * 'dss' class
1104  * display sub-system
1105  */
1106
1107 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1108         .rev_offs       = 0x0000,
1109         .syss_offs      = 0x0014,
1110         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1111 };
1112
1113 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1114         .name   = "dss",
1115         .sysc   = &omap44xx_dss_sysc,
1116 };
1117
1118 /* dss */
1119 /* dss master ports */
1120 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1121         &omap44xx_dss__l3_main_1,
1122 };
1123
1124 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1125         {
1126                 .pa_start       = 0x58000000,
1127                 .pa_end         = 0x5800007f,
1128                 .flags          = ADDR_TYPE_RT
1129         },
1130         { }
1131 };
1132
1133 /* l3_main_2 -> dss */
1134 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1135         .master         = &omap44xx_l3_main_2_hwmod,
1136         .slave          = &omap44xx_dss_hwmod,
1137         .clk            = "l3_div_ck",
1138         .addr           = omap44xx_dss_dma_addrs,
1139         .user           = OCP_USER_SDMA,
1140 };
1141
1142 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1143         {
1144                 .pa_start       = 0x48040000,
1145                 .pa_end         = 0x4804007f,
1146                 .flags          = ADDR_TYPE_RT
1147         },
1148         { }
1149 };
1150
1151 /* l4_per -> dss */
1152 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1153         .master         = &omap44xx_l4_per_hwmod,
1154         .slave          = &omap44xx_dss_hwmod,
1155         .clk            = "l4_div_ck",
1156         .addr           = omap44xx_dss_addrs,
1157         .user           = OCP_USER_MPU,
1158 };
1159
1160 /* dss slave ports */
1161 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1162         &omap44xx_l3_main_2__dss,
1163         &omap44xx_l4_per__dss,
1164 };
1165
1166 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1167         { .role = "sys_clk", .clk = "dss_sys_clk" },
1168         { .role = "tv_clk", .clk = "dss_tv_clk" },
1169         { .role = "dss_clk", .clk = "dss_dss_clk" },
1170         { .role = "video_clk", .clk = "dss_48mhz_clk" },
1171 };
1172
1173 static struct omap_hwmod omap44xx_dss_hwmod = {
1174         .name           = "dss_core",
1175         .class          = &omap44xx_dss_hwmod_class,
1176         .main_clk       = "dss_fck",
1177         .prcm = {
1178                 .omap4 = {
1179                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1180                 },
1181         },
1182         .opt_clks       = dss_opt_clks,
1183         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1184         .slaves         = omap44xx_dss_slaves,
1185         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1186         .masters        = omap44xx_dss_masters,
1187         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1188         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1189 };
1190
1191 /*
1192  * 'dispc' class
1193  * display controller
1194  */
1195
1196 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1197         .rev_offs       = 0x0000,
1198         .sysc_offs      = 0x0010,
1199         .syss_offs      = 0x0014,
1200         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1201                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1202                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1203                            SYSS_HAS_RESET_STATUS),
1204         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1205                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1206         .sysc_fields    = &omap_hwmod_sysc_type1,
1207 };
1208
1209 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1210         .name   = "dispc",
1211         .sysc   = &omap44xx_dispc_sysc,
1212 };
1213
1214 /* dss_dispc */
1215 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1216 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1217         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1218         { .irq = -1 }
1219 };
1220
1221 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1222         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1223 };
1224
1225 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1226         {
1227                 .pa_start       = 0x58001000,
1228                 .pa_end         = 0x58001fff,
1229                 .flags          = ADDR_TYPE_RT
1230         },
1231         { }
1232 };
1233
1234 /* l3_main_2 -> dss_dispc */
1235 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1236         .master         = &omap44xx_l3_main_2_hwmod,
1237         .slave          = &omap44xx_dss_dispc_hwmod,
1238         .clk            = "l3_div_ck",
1239         .addr           = omap44xx_dss_dispc_dma_addrs,
1240         .user           = OCP_USER_SDMA,
1241 };
1242
1243 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1244         {
1245                 .pa_start       = 0x48041000,
1246                 .pa_end         = 0x48041fff,
1247                 .flags          = ADDR_TYPE_RT
1248         },
1249         { }
1250 };
1251
1252 /* l4_per -> dss_dispc */
1253 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1254         .master         = &omap44xx_l4_per_hwmod,
1255         .slave          = &omap44xx_dss_dispc_hwmod,
1256         .clk            = "l4_div_ck",
1257         .addr           = omap44xx_dss_dispc_addrs,
1258         .user           = OCP_USER_MPU,
1259 };
1260
1261 /* dss_dispc slave ports */
1262 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1263         &omap44xx_l3_main_2__dss_dispc,
1264         &omap44xx_l4_per__dss_dispc,
1265 };
1266
1267 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1268         .name           = "dss_dispc",
1269         .class          = &omap44xx_dispc_hwmod_class,
1270         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1271         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1272         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
1273         .main_clk       = "dss_fck",
1274         .prcm = {
1275                 .omap4 = {
1276                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1277                 },
1278         },
1279         .slaves         = omap44xx_dss_dispc_slaves,
1280         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1281         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1282 };
1283
1284 /*
1285  * 'dsi' class
1286  * display serial interface controller
1287  */
1288
1289 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1290         .rev_offs       = 0x0000,
1291         .sysc_offs      = 0x0010,
1292         .syss_offs      = 0x0014,
1293         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1294                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1295                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1296         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1297         .sysc_fields    = &omap_hwmod_sysc_type1,
1298 };
1299
1300 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1301         .name   = "dsi",
1302         .sysc   = &omap44xx_dsi_sysc,
1303 };
1304
1305 /* dss_dsi1 */
1306 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1307 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1308         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1309         { .irq = -1 }
1310 };
1311
1312 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1313         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1314 };
1315
1316 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1317         {
1318                 .pa_start       = 0x58004000,
1319                 .pa_end         = 0x580041ff,
1320                 .flags          = ADDR_TYPE_RT
1321         },
1322         { }
1323 };
1324
1325 /* l3_main_2 -> dss_dsi1 */
1326 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1327         .master         = &omap44xx_l3_main_2_hwmod,
1328         .slave          = &omap44xx_dss_dsi1_hwmod,
1329         .clk            = "l3_div_ck",
1330         .addr           = omap44xx_dss_dsi1_dma_addrs,
1331         .user           = OCP_USER_SDMA,
1332 };
1333
1334 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1335         {
1336                 .pa_start       = 0x48044000,
1337                 .pa_end         = 0x480441ff,
1338                 .flags          = ADDR_TYPE_RT
1339         },
1340         { }
1341 };
1342
1343 /* l4_per -> dss_dsi1 */
1344 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1345         .master         = &omap44xx_l4_per_hwmod,
1346         .slave          = &omap44xx_dss_dsi1_hwmod,
1347         .clk            = "l4_div_ck",
1348         .addr           = omap44xx_dss_dsi1_addrs,
1349         .user           = OCP_USER_MPU,
1350 };
1351
1352 /* dss_dsi1 slave ports */
1353 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1354         &omap44xx_l3_main_2__dss_dsi1,
1355         &omap44xx_l4_per__dss_dsi1,
1356 };
1357
1358 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1359         .name           = "dss_dsi1",
1360         .class          = &omap44xx_dsi_hwmod_class,
1361         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1362         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1363         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
1364         .main_clk       = "dss_fck",
1365         .prcm = {
1366                 .omap4 = {
1367                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1368                 },
1369         },
1370         .slaves         = omap44xx_dss_dsi1_slaves,
1371         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1372         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1373 };
1374
1375 /* dss_dsi2 */
1376 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1377 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1378         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1379         { .irq = -1 }
1380 };
1381
1382 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1383         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1384 };
1385
1386 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1387         {
1388                 .pa_start       = 0x58005000,
1389                 .pa_end         = 0x580051ff,
1390                 .flags          = ADDR_TYPE_RT
1391         },
1392         { }
1393 };
1394
1395 /* l3_main_2 -> dss_dsi2 */
1396 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1397         .master         = &omap44xx_l3_main_2_hwmod,
1398         .slave          = &omap44xx_dss_dsi2_hwmod,
1399         .clk            = "l3_div_ck",
1400         .addr           = omap44xx_dss_dsi2_dma_addrs,
1401         .user           = OCP_USER_SDMA,
1402 };
1403
1404 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1405         {
1406                 .pa_start       = 0x48045000,
1407                 .pa_end         = 0x480451ff,
1408                 .flags          = ADDR_TYPE_RT
1409         },
1410         { }
1411 };
1412
1413 /* l4_per -> dss_dsi2 */
1414 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1415         .master         = &omap44xx_l4_per_hwmod,
1416         .slave          = &omap44xx_dss_dsi2_hwmod,
1417         .clk            = "l4_div_ck",
1418         .addr           = omap44xx_dss_dsi2_addrs,
1419         .user           = OCP_USER_MPU,
1420 };
1421
1422 /* dss_dsi2 slave ports */
1423 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1424         &omap44xx_l3_main_2__dss_dsi2,
1425         &omap44xx_l4_per__dss_dsi2,
1426 };
1427
1428 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1429         .name           = "dss_dsi2",
1430         .class          = &omap44xx_dsi_hwmod_class,
1431         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1432         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1433         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
1434         .main_clk       = "dss_fck",
1435         .prcm = {
1436                 .omap4 = {
1437                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1438                 },
1439         },
1440         .slaves         = omap44xx_dss_dsi2_slaves,
1441         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1442         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1443 };
1444
1445 /*
1446  * 'hdmi' class
1447  * hdmi controller
1448  */
1449
1450 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1451         .rev_offs       = 0x0000,
1452         .sysc_offs      = 0x0010,
1453         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1454                            SYSC_HAS_SOFTRESET),
1455         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1456                            SIDLE_SMART_WKUP),
1457         .sysc_fields    = &omap_hwmod_sysc_type2,
1458 };
1459
1460 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1461         .name   = "hdmi",
1462         .sysc   = &omap44xx_hdmi_sysc,
1463 };
1464
1465 /* dss_hdmi */
1466 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1467 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1468         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1469         { .irq = -1 }
1470 };
1471
1472 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1473         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1474 };
1475
1476 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1477         {
1478                 .pa_start       = 0x58006000,
1479                 .pa_end         = 0x58006fff,
1480                 .flags          = ADDR_TYPE_RT
1481         },
1482         { }
1483 };
1484
1485 /* l3_main_2 -> dss_hdmi */
1486 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1487         .master         = &omap44xx_l3_main_2_hwmod,
1488         .slave          = &omap44xx_dss_hdmi_hwmod,
1489         .clk            = "l3_div_ck",
1490         .addr           = omap44xx_dss_hdmi_dma_addrs,
1491         .user           = OCP_USER_SDMA,
1492 };
1493
1494 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1495         {
1496                 .pa_start       = 0x48046000,
1497                 .pa_end         = 0x48046fff,
1498                 .flags          = ADDR_TYPE_RT
1499         },
1500         { }
1501 };
1502
1503 /* l4_per -> dss_hdmi */
1504 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1505         .master         = &omap44xx_l4_per_hwmod,
1506         .slave          = &omap44xx_dss_hdmi_hwmod,
1507         .clk            = "l4_div_ck",
1508         .addr           = omap44xx_dss_hdmi_addrs,
1509         .user           = OCP_USER_MPU,
1510 };
1511
1512 /* dss_hdmi slave ports */
1513 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1514         &omap44xx_l3_main_2__dss_hdmi,
1515         &omap44xx_l4_per__dss_hdmi,
1516 };
1517
1518 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1519         .name           = "dss_hdmi",
1520         .class          = &omap44xx_hdmi_hwmod_class,
1521         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1522         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1523         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
1524         .main_clk       = "dss_fck",
1525         .prcm = {
1526                 .omap4 = {
1527                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1528                 },
1529         },
1530         .slaves         = omap44xx_dss_hdmi_slaves,
1531         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1532         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1533 };
1534
1535 /*
1536  * 'rfbi' class
1537  * remote frame buffer interface
1538  */
1539
1540 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1541         .rev_offs       = 0x0000,
1542         .sysc_offs      = 0x0010,
1543         .syss_offs      = 0x0014,
1544         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1545                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1546         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1547         .sysc_fields    = &omap_hwmod_sysc_type1,
1548 };
1549
1550 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1551         .name   = "rfbi",
1552         .sysc   = &omap44xx_rfbi_sysc,
1553 };
1554
1555 /* dss_rfbi */
1556 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1557 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1558         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1559 };
1560
1561 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1562         {
1563                 .pa_start       = 0x58002000,
1564                 .pa_end         = 0x580020ff,
1565                 .flags          = ADDR_TYPE_RT
1566         },
1567         { }
1568 };
1569
1570 /* l3_main_2 -> dss_rfbi */
1571 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1572         .master         = &omap44xx_l3_main_2_hwmod,
1573         .slave          = &omap44xx_dss_rfbi_hwmod,
1574         .clk            = "l3_div_ck",
1575         .addr           = omap44xx_dss_rfbi_dma_addrs,
1576         .user           = OCP_USER_SDMA,
1577 };
1578
1579 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1580         {
1581                 .pa_start       = 0x48042000,
1582                 .pa_end         = 0x480420ff,
1583                 .flags          = ADDR_TYPE_RT
1584         },
1585         { }
1586 };
1587
1588 /* l4_per -> dss_rfbi */
1589 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1590         .master         = &omap44xx_l4_per_hwmod,
1591         .slave          = &omap44xx_dss_rfbi_hwmod,
1592         .clk            = "l4_div_ck",
1593         .addr           = omap44xx_dss_rfbi_addrs,
1594         .user           = OCP_USER_MPU,
1595 };
1596
1597 /* dss_rfbi slave ports */
1598 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1599         &omap44xx_l3_main_2__dss_rfbi,
1600         &omap44xx_l4_per__dss_rfbi,
1601 };
1602
1603 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1604         .name           = "dss_rfbi",
1605         .class          = &omap44xx_rfbi_hwmod_class,
1606         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1607         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
1608         .main_clk       = "dss_fck",
1609         .prcm = {
1610                 .omap4 = {
1611                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1612                 },
1613         },
1614         .slaves         = omap44xx_dss_rfbi_slaves,
1615         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1616         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1617 };
1618
1619 /*
1620  * 'venc' class
1621  * video encoder
1622  */
1623
1624 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1625         .name   = "venc",
1626 };
1627
1628 /* dss_venc */
1629 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1630 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1631         {
1632                 .pa_start       = 0x58003000,
1633                 .pa_end         = 0x580030ff,
1634                 .flags          = ADDR_TYPE_RT
1635         },
1636         { }
1637 };
1638
1639 /* l3_main_2 -> dss_venc */
1640 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1641         .master         = &omap44xx_l3_main_2_hwmod,
1642         .slave          = &omap44xx_dss_venc_hwmod,
1643         .clk            = "l3_div_ck",
1644         .addr           = omap44xx_dss_venc_dma_addrs,
1645         .user           = OCP_USER_SDMA,
1646 };
1647
1648 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1649         {
1650                 .pa_start       = 0x48043000,
1651                 .pa_end         = 0x480430ff,
1652                 .flags          = ADDR_TYPE_RT
1653         },
1654         { }
1655 };
1656
1657 /* l4_per -> dss_venc */
1658 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1659         .master         = &omap44xx_l4_per_hwmod,
1660         .slave          = &omap44xx_dss_venc_hwmod,
1661         .clk            = "l4_div_ck",
1662         .addr           = omap44xx_dss_venc_addrs,
1663         .user           = OCP_USER_MPU,
1664 };
1665
1666 /* dss_venc slave ports */
1667 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1668         &omap44xx_l3_main_2__dss_venc,
1669         &omap44xx_l4_per__dss_venc,
1670 };
1671
1672 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1673         .name           = "dss_venc",
1674         .class          = &omap44xx_venc_hwmod_class,
1675         .main_clk       = "dss_fck",
1676         .prcm = {
1677                 .omap4 = {
1678                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1679                 },
1680         },
1681         .slaves         = omap44xx_dss_venc_slaves,
1682         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1683         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1684 };
1685
1686 /*
1687  * 'gpio' class
1688  * general purpose io module
1689  */
1690
1691 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1692         .rev_offs       = 0x0000,
1693         .sysc_offs      = 0x0010,
1694         .syss_offs      = 0x0114,
1695         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1696                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1697                            SYSS_HAS_RESET_STATUS),
1698         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1699                            SIDLE_SMART_WKUP),
1700         .sysc_fields    = &omap_hwmod_sysc_type1,
1701 };
1702
1703 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1704         .name   = "gpio",
1705         .sysc   = &omap44xx_gpio_sysc,
1706         .rev    = 2,
1707 };
1708
1709 /* gpio dev_attr */
1710 static struct omap_gpio_dev_attr gpio_dev_attr = {
1711         .bank_width     = 32,
1712         .dbck_flag      = true,
1713 };
1714
1715 /* gpio1 */
1716 static struct omap_hwmod omap44xx_gpio1_hwmod;
1717 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1718         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1719         { .irq = -1 }
1720 };
1721
1722 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1723         {
1724                 .pa_start       = 0x4a310000,
1725                 .pa_end         = 0x4a3101ff,
1726                 .flags          = ADDR_TYPE_RT
1727         },
1728         { }
1729 };
1730
1731 /* l4_wkup -> gpio1 */
1732 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1733         .master         = &omap44xx_l4_wkup_hwmod,
1734         .slave          = &omap44xx_gpio1_hwmod,
1735         .clk            = "l4_wkup_clk_mux_ck",
1736         .addr           = omap44xx_gpio1_addrs,
1737         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1738 };
1739
1740 /* gpio1 slave ports */
1741 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1742         &omap44xx_l4_wkup__gpio1,
1743 };
1744
1745 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1746         { .role = "dbclk", .clk = "gpio1_dbclk" },
1747 };
1748
1749 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1750         .name           = "gpio1",
1751         .class          = &omap44xx_gpio_hwmod_class,
1752         .mpu_irqs       = omap44xx_gpio1_irqs,
1753         .main_clk       = "gpio1_ick",
1754         .prcm = {
1755                 .omap4 = {
1756                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1757                 },
1758         },
1759         .opt_clks       = gpio1_opt_clks,
1760         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1761         .dev_attr       = &gpio_dev_attr,
1762         .slaves         = omap44xx_gpio1_slaves,
1763         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1764         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1765 };
1766
1767 /* gpio2 */
1768 static struct omap_hwmod omap44xx_gpio2_hwmod;
1769 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1770         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1771         { .irq = -1 }
1772 };
1773
1774 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1775         {
1776                 .pa_start       = 0x48055000,
1777                 .pa_end         = 0x480551ff,
1778                 .flags          = ADDR_TYPE_RT
1779         },
1780         { }
1781 };
1782
1783 /* l4_per -> gpio2 */
1784 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1785         .master         = &omap44xx_l4_per_hwmod,
1786         .slave          = &omap44xx_gpio2_hwmod,
1787         .clk            = "l4_div_ck",
1788         .addr           = omap44xx_gpio2_addrs,
1789         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1790 };
1791
1792 /* gpio2 slave ports */
1793 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1794         &omap44xx_l4_per__gpio2,
1795 };
1796
1797 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1798         { .role = "dbclk", .clk = "gpio2_dbclk" },
1799 };
1800
1801 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1802         .name           = "gpio2",
1803         .class          = &omap44xx_gpio_hwmod_class,
1804         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1805         .mpu_irqs       = omap44xx_gpio2_irqs,
1806         .main_clk       = "gpio2_ick",
1807         .prcm = {
1808                 .omap4 = {
1809                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1810                 },
1811         },
1812         .opt_clks       = gpio2_opt_clks,
1813         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1814         .dev_attr       = &gpio_dev_attr,
1815         .slaves         = omap44xx_gpio2_slaves,
1816         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1817         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1818 };
1819
1820 /* gpio3 */
1821 static struct omap_hwmod omap44xx_gpio3_hwmod;
1822 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1823         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1824         { .irq = -1 }
1825 };
1826
1827 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1828         {
1829                 .pa_start       = 0x48057000,
1830                 .pa_end         = 0x480571ff,
1831                 .flags          = ADDR_TYPE_RT
1832         },
1833         { }
1834 };
1835
1836 /* l4_per -> gpio3 */
1837 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1838         .master         = &omap44xx_l4_per_hwmod,
1839         .slave          = &omap44xx_gpio3_hwmod,
1840         .clk            = "l4_div_ck",
1841         .addr           = omap44xx_gpio3_addrs,
1842         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1843 };
1844
1845 /* gpio3 slave ports */
1846 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1847         &omap44xx_l4_per__gpio3,
1848 };
1849
1850 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1851         { .role = "dbclk", .clk = "gpio3_dbclk" },
1852 };
1853
1854 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1855         .name           = "gpio3",
1856         .class          = &omap44xx_gpio_hwmod_class,
1857         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1858         .mpu_irqs       = omap44xx_gpio3_irqs,
1859         .main_clk       = "gpio3_ick",
1860         .prcm = {
1861                 .omap4 = {
1862                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1863                 },
1864         },
1865         .opt_clks       = gpio3_opt_clks,
1866         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1867         .dev_attr       = &gpio_dev_attr,
1868         .slaves         = omap44xx_gpio3_slaves,
1869         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1870         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1871 };
1872
1873 /* gpio4 */
1874 static struct omap_hwmod omap44xx_gpio4_hwmod;
1875 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1876         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1877         { .irq = -1 }
1878 };
1879
1880 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1881         {
1882                 .pa_start       = 0x48059000,
1883                 .pa_end         = 0x480591ff,
1884                 .flags          = ADDR_TYPE_RT
1885         },
1886         { }
1887 };
1888
1889 /* l4_per -> gpio4 */
1890 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1891         .master         = &omap44xx_l4_per_hwmod,
1892         .slave          = &omap44xx_gpio4_hwmod,
1893         .clk            = "l4_div_ck",
1894         .addr           = omap44xx_gpio4_addrs,
1895         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1896 };
1897
1898 /* gpio4 slave ports */
1899 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1900         &omap44xx_l4_per__gpio4,
1901 };
1902
1903 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1904         { .role = "dbclk", .clk = "gpio4_dbclk" },
1905 };
1906
1907 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1908         .name           = "gpio4",
1909         .class          = &omap44xx_gpio_hwmod_class,
1910         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1911         .mpu_irqs       = omap44xx_gpio4_irqs,
1912         .main_clk       = "gpio4_ick",
1913         .prcm = {
1914                 .omap4 = {
1915                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1916                 },
1917         },
1918         .opt_clks       = gpio4_opt_clks,
1919         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1920         .dev_attr       = &gpio_dev_attr,
1921         .slaves         = omap44xx_gpio4_slaves,
1922         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
1923         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1924 };
1925
1926 /* gpio5 */
1927 static struct omap_hwmod omap44xx_gpio5_hwmod;
1928 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1929         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1930         { .irq = -1 }
1931 };
1932
1933 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1934         {
1935                 .pa_start       = 0x4805b000,
1936                 .pa_end         = 0x4805b1ff,
1937                 .flags          = ADDR_TYPE_RT
1938         },
1939         { }
1940 };
1941
1942 /* l4_per -> gpio5 */
1943 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1944         .master         = &omap44xx_l4_per_hwmod,
1945         .slave          = &omap44xx_gpio5_hwmod,
1946         .clk            = "l4_div_ck",
1947         .addr           = omap44xx_gpio5_addrs,
1948         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1949 };
1950
1951 /* gpio5 slave ports */
1952 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1953         &omap44xx_l4_per__gpio5,
1954 };
1955
1956 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1957         { .role = "dbclk", .clk = "gpio5_dbclk" },
1958 };
1959
1960 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1961         .name           = "gpio5",
1962         .class          = &omap44xx_gpio_hwmod_class,
1963         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1964         .mpu_irqs       = omap44xx_gpio5_irqs,
1965         .main_clk       = "gpio5_ick",
1966         .prcm = {
1967                 .omap4 = {
1968                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1969                 },
1970         },
1971         .opt_clks       = gpio5_opt_clks,
1972         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1973         .dev_attr       = &gpio_dev_attr,
1974         .slaves         = omap44xx_gpio5_slaves,
1975         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
1976         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1977 };
1978
1979 /* gpio6 */
1980 static struct omap_hwmod omap44xx_gpio6_hwmod;
1981 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1982         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1983         { .irq = -1 }
1984 };
1985
1986 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1987         {
1988                 .pa_start       = 0x4805d000,
1989                 .pa_end         = 0x4805d1ff,
1990                 .flags          = ADDR_TYPE_RT
1991         },
1992         { }
1993 };
1994
1995 /* l4_per -> gpio6 */
1996 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1997         .master         = &omap44xx_l4_per_hwmod,
1998         .slave          = &omap44xx_gpio6_hwmod,
1999         .clk            = "l4_div_ck",
2000         .addr           = omap44xx_gpio6_addrs,
2001         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2002 };
2003
2004 /* gpio6 slave ports */
2005 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2006         &omap44xx_l4_per__gpio6,
2007 };
2008
2009 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2010         { .role = "dbclk", .clk = "gpio6_dbclk" },
2011 };
2012
2013 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2014         .name           = "gpio6",
2015         .class          = &omap44xx_gpio_hwmod_class,
2016         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2017         .mpu_irqs       = omap44xx_gpio6_irqs,
2018         .main_clk       = "gpio6_ick",
2019         .prcm = {
2020                 .omap4 = {
2021                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
2022                 },
2023         },
2024         .opt_clks       = gpio6_opt_clks,
2025         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2026         .dev_attr       = &gpio_dev_attr,
2027         .slaves         = omap44xx_gpio6_slaves,
2028         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2029         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2030 };
2031
2032 /*
2033  * 'hsi' class
2034  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2035  * serial if)
2036  */
2037
2038 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2039         .rev_offs       = 0x0000,
2040         .sysc_offs      = 0x0010,
2041         .syss_offs      = 0x0014,
2042         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2043                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2044                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2045         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2046                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2047                            MSTANDBY_SMART),
2048         .sysc_fields    = &omap_hwmod_sysc_type1,
2049 };
2050
2051 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2052         .name   = "hsi",
2053         .sysc   = &omap44xx_hsi_sysc,
2054 };
2055
2056 /* hsi */
2057 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2058         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2059         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2060         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2061         { .irq = -1 }
2062 };
2063
2064 /* hsi master ports */
2065 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2066         &omap44xx_hsi__l3_main_2,
2067 };
2068
2069 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2070         {
2071                 .pa_start       = 0x4a058000,
2072                 .pa_end         = 0x4a05bfff,
2073                 .flags          = ADDR_TYPE_RT
2074         },
2075         { }
2076 };
2077
2078 /* l4_cfg -> hsi */
2079 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2080         .master         = &omap44xx_l4_cfg_hwmod,
2081         .slave          = &omap44xx_hsi_hwmod,
2082         .clk            = "l4_div_ck",
2083         .addr           = omap44xx_hsi_addrs,
2084         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2085 };
2086
2087 /* hsi slave ports */
2088 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2089         &omap44xx_l4_cfg__hsi,
2090 };
2091
2092 static struct omap_hwmod omap44xx_hsi_hwmod = {
2093         .name           = "hsi",
2094         .class          = &omap44xx_hsi_hwmod_class,
2095         .mpu_irqs       = omap44xx_hsi_irqs,
2096         .main_clk       = "hsi_fck",
2097         .prcm           = {
2098                 .omap4 = {
2099                         .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2100                 },
2101         },
2102         .slaves         = omap44xx_hsi_slaves,
2103         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2104         .masters        = omap44xx_hsi_masters,
2105         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2106         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2107 };
2108
2109 /*
2110  * 'i2c' class
2111  * multimaster high-speed i2c controller
2112  */
2113
2114 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2115         .sysc_offs      = 0x0010,
2116         .syss_offs      = 0x0090,
2117         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2118                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2119                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2120         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2121                            SIDLE_SMART_WKUP),
2122         .sysc_fields    = &omap_hwmod_sysc_type1,
2123 };
2124
2125 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2126         .name   = "i2c",
2127         .sysc   = &omap44xx_i2c_sysc,
2128 };
2129
2130 /* i2c1 */
2131 static struct omap_hwmod omap44xx_i2c1_hwmod;
2132 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2133         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2134         { .irq = -1 }
2135 };
2136
2137 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2138         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2139         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2140 };
2141
2142 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2143         {
2144                 .pa_start       = 0x48070000,
2145                 .pa_end         = 0x480700ff,
2146                 .flags          = ADDR_TYPE_RT
2147         },
2148         { }
2149 };
2150
2151 /* l4_per -> i2c1 */
2152 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2153         .master         = &omap44xx_l4_per_hwmod,
2154         .slave          = &omap44xx_i2c1_hwmod,
2155         .clk            = "l4_div_ck",
2156         .addr           = omap44xx_i2c1_addrs,
2157         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2158 };
2159
2160 /* i2c1 slave ports */
2161 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2162         &omap44xx_l4_per__i2c1,
2163 };
2164
2165 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2166         .name           = "i2c1",
2167         .class          = &omap44xx_i2c_hwmod_class,
2168         .flags          = HWMOD_INIT_NO_RESET,
2169         .mpu_irqs       = omap44xx_i2c1_irqs,
2170         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2171         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
2172         .main_clk       = "i2c1_fck",
2173         .prcm = {
2174                 .omap4 = {
2175                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
2176                 },
2177         },
2178         .slaves         = omap44xx_i2c1_slaves,
2179         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2180         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2181 };
2182
2183 /* i2c2 */
2184 static struct omap_hwmod omap44xx_i2c2_hwmod;
2185 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2186         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2187         { .irq = -1 }
2188 };
2189
2190 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2191         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2192         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2193 };
2194
2195 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2196         {
2197                 .pa_start       = 0x48072000,
2198                 .pa_end         = 0x480720ff,
2199                 .flags          = ADDR_TYPE_RT
2200         },
2201         { }
2202 };
2203
2204 /* l4_per -> i2c2 */
2205 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2206         .master         = &omap44xx_l4_per_hwmod,
2207         .slave          = &omap44xx_i2c2_hwmod,
2208         .clk            = "l4_div_ck",
2209         .addr           = omap44xx_i2c2_addrs,
2210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2211 };
2212
2213 /* i2c2 slave ports */
2214 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2215         &omap44xx_l4_per__i2c2,
2216 };
2217
2218 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2219         .name           = "i2c2",
2220         .class          = &omap44xx_i2c_hwmod_class,
2221         .flags          = HWMOD_INIT_NO_RESET,
2222         .mpu_irqs       = omap44xx_i2c2_irqs,
2223         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2224         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
2225         .main_clk       = "i2c2_fck",
2226         .prcm = {
2227                 .omap4 = {
2228                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
2229                 },
2230         },
2231         .slaves         = omap44xx_i2c2_slaves,
2232         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2233         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2234 };
2235
2236 /* i2c3 */
2237 static struct omap_hwmod omap44xx_i2c3_hwmod;
2238 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2239         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2240         { .irq = -1 }
2241 };
2242
2243 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2244         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2245         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2246 };
2247
2248 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2249         {
2250                 .pa_start       = 0x48060000,
2251                 .pa_end         = 0x480600ff,
2252                 .flags          = ADDR_TYPE_RT
2253         },
2254         { }
2255 };
2256
2257 /* l4_per -> i2c3 */
2258 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2259         .master         = &omap44xx_l4_per_hwmod,
2260         .slave          = &omap44xx_i2c3_hwmod,
2261         .clk            = "l4_div_ck",
2262         .addr           = omap44xx_i2c3_addrs,
2263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2264 };
2265
2266 /* i2c3 slave ports */
2267 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2268         &omap44xx_l4_per__i2c3,
2269 };
2270
2271 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2272         .name           = "i2c3",
2273         .class          = &omap44xx_i2c_hwmod_class,
2274         .flags          = HWMOD_INIT_NO_RESET,
2275         .mpu_irqs       = omap44xx_i2c3_irqs,
2276         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2277         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
2278         .main_clk       = "i2c3_fck",
2279         .prcm = {
2280                 .omap4 = {
2281                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
2282                 },
2283         },
2284         .slaves         = omap44xx_i2c3_slaves,
2285         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2286         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2287 };
2288
2289 /* i2c4 */
2290 static struct omap_hwmod omap44xx_i2c4_hwmod;
2291 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2292         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2293         { .irq = -1 }
2294 };
2295
2296 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2297         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2298         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2299 };
2300
2301 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2302         {
2303                 .pa_start       = 0x48350000,
2304                 .pa_end         = 0x483500ff,
2305                 .flags          = ADDR_TYPE_RT
2306         },
2307         { }
2308 };
2309
2310 /* l4_per -> i2c4 */
2311 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2312         .master         = &omap44xx_l4_per_hwmod,
2313         .slave          = &omap44xx_i2c4_hwmod,
2314         .clk            = "l4_div_ck",
2315         .addr           = omap44xx_i2c4_addrs,
2316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2317 };
2318
2319 /* i2c4 slave ports */
2320 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2321         &omap44xx_l4_per__i2c4,
2322 };
2323
2324 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2325         .name           = "i2c4",
2326         .class          = &omap44xx_i2c_hwmod_class,
2327         .flags          = HWMOD_INIT_NO_RESET,
2328         .mpu_irqs       = omap44xx_i2c4_irqs,
2329         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2330         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
2331         .main_clk       = "i2c4_fck",
2332         .prcm = {
2333                 .omap4 = {
2334                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
2335                 },
2336         },
2337         .slaves         = omap44xx_i2c4_slaves,
2338         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2339         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2340 };
2341
2342 /*
2343  * 'ipu' class
2344  * imaging processor unit
2345  */
2346
2347 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2348         .name   = "ipu",
2349 };
2350
2351 /* ipu */
2352 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2353         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2354         { .irq = -1 }
2355 };
2356
2357 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2358         { .name = "cpu0", .rst_shift = 0 },
2359 };
2360
2361 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2362         { .name = "cpu1", .rst_shift = 1 },
2363 };
2364
2365 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2366         { .name = "mmu_cache", .rst_shift = 2 },
2367 };
2368
2369 /* ipu master ports */
2370 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2371         &omap44xx_ipu__l3_main_2,
2372 };
2373
2374 /* l3_main_2 -> ipu */
2375 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2376         .master         = &omap44xx_l3_main_2_hwmod,
2377         .slave          = &omap44xx_ipu_hwmod,
2378         .clk            = "l3_div_ck",
2379         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2380 };
2381
2382 /* ipu slave ports */
2383 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2384         &omap44xx_l3_main_2__ipu,
2385 };
2386
2387 /* Pseudo hwmod for reset control purpose only */
2388 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2389         .name           = "ipu_c0",
2390         .class          = &omap44xx_ipu_hwmod_class,
2391         .flags          = HWMOD_INIT_NO_RESET,
2392         .rst_lines      = omap44xx_ipu_c0_resets,
2393         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2394         .prcm           = {
2395                 .omap4 = {
2396                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2397                 },
2398         },
2399         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2400 };
2401
2402 /* Pseudo hwmod for reset control purpose only */
2403 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2404         .name           = "ipu_c1",
2405         .class          = &omap44xx_ipu_hwmod_class,
2406         .flags          = HWMOD_INIT_NO_RESET,
2407         .rst_lines      = omap44xx_ipu_c1_resets,
2408         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2409         .prcm           = {
2410                 .omap4 = {
2411                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2412                 },
2413         },
2414         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2415 };
2416
2417 static struct omap_hwmod omap44xx_ipu_hwmod = {
2418         .name           = "ipu",
2419         .class          = &omap44xx_ipu_hwmod_class,
2420         .mpu_irqs       = omap44xx_ipu_irqs,
2421         .rst_lines      = omap44xx_ipu_resets,
2422         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2423         .main_clk       = "ipu_fck",
2424         .prcm           = {
2425                 .omap4 = {
2426                         .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2427                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2428                 },
2429         },
2430         .slaves         = omap44xx_ipu_slaves,
2431         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2432         .masters        = omap44xx_ipu_masters,
2433         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2434         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2435 };
2436
2437 /*
2438  * 'iss' class
2439  * external images sensor pixel data processor
2440  */
2441
2442 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2443         .rev_offs       = 0x0000,
2444         .sysc_offs      = 0x0010,
2445         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2446                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2447         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2448                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2449                            MSTANDBY_SMART),
2450         .sysc_fields    = &omap_hwmod_sysc_type2,
2451 };
2452
2453 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2454         .name   = "iss",
2455         .sysc   = &omap44xx_iss_sysc,
2456 };
2457
2458 /* iss */
2459 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2460         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2461         { .irq = -1 }
2462 };
2463
2464 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2465         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2466         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2467         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2468         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2469 };
2470
2471 /* iss master ports */
2472 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2473         &omap44xx_iss__l3_main_2,
2474 };
2475
2476 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2477         {
2478                 .pa_start       = 0x52000000,
2479                 .pa_end         = 0x520000ff,
2480                 .flags          = ADDR_TYPE_RT
2481         },
2482         { }
2483 };
2484
2485 /* l3_main_2 -> iss */
2486 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2487         .master         = &omap44xx_l3_main_2_hwmod,
2488         .slave          = &omap44xx_iss_hwmod,
2489         .clk            = "l3_div_ck",
2490         .addr           = omap44xx_iss_addrs,
2491         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2492 };
2493
2494 /* iss slave ports */
2495 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2496         &omap44xx_l3_main_2__iss,
2497 };
2498
2499 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2500         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2501 };
2502
2503 static struct omap_hwmod omap44xx_iss_hwmod = {
2504         .name           = "iss",
2505         .class          = &omap44xx_iss_hwmod_class,
2506         .mpu_irqs       = omap44xx_iss_irqs,
2507         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2508         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
2509         .main_clk       = "iss_fck",
2510         .prcm           = {
2511                 .omap4 = {
2512                         .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2513                 },
2514         },
2515         .opt_clks       = iss_opt_clks,
2516         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2517         .slaves         = omap44xx_iss_slaves,
2518         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2519         .masters        = omap44xx_iss_masters,
2520         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2521         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2522 };
2523
2524 /*
2525  * 'iva' class
2526  * multi-standard video encoder/decoder hardware accelerator
2527  */
2528
2529 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2530         .name   = "iva",
2531 };
2532
2533 /* iva */
2534 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2535         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2536         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2537         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2538         { .irq = -1 }
2539 };
2540
2541 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2542         { .name = "logic", .rst_shift = 2 },
2543 };
2544
2545 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2546         { .name = "seq0", .rst_shift = 0 },
2547 };
2548
2549 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2550         { .name = "seq1", .rst_shift = 1 },
2551 };
2552
2553 /* iva master ports */
2554 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2555         &omap44xx_iva__l3_main_2,
2556         &omap44xx_iva__l3_instr,
2557 };
2558
2559 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2560         {
2561                 .pa_start       = 0x5a000000,
2562                 .pa_end         = 0x5a07ffff,
2563                 .flags          = ADDR_TYPE_RT
2564         },
2565         { }
2566 };
2567
2568 /* l3_main_2 -> iva */
2569 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2570         .master         = &omap44xx_l3_main_2_hwmod,
2571         .slave          = &omap44xx_iva_hwmod,
2572         .clk            = "l3_div_ck",
2573         .addr           = omap44xx_iva_addrs,
2574         .user           = OCP_USER_MPU,
2575 };
2576
2577 /* iva slave ports */
2578 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2579         &omap44xx_dsp__iva,
2580         &omap44xx_l3_main_2__iva,
2581 };
2582
2583 /* Pseudo hwmod for reset control purpose only */
2584 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2585         .name           = "iva_seq0",
2586         .class          = &omap44xx_iva_hwmod_class,
2587         .flags          = HWMOD_INIT_NO_RESET,
2588         .rst_lines      = omap44xx_iva_seq0_resets,
2589         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2590         .prcm = {
2591                 .omap4 = {
2592                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2593                 },
2594         },
2595         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2596 };
2597
2598 /* Pseudo hwmod for reset control purpose only */
2599 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2600         .name           = "iva_seq1",
2601         .class          = &omap44xx_iva_hwmod_class,
2602         .flags          = HWMOD_INIT_NO_RESET,
2603         .rst_lines      = omap44xx_iva_seq1_resets,
2604         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2605         .prcm = {
2606                 .omap4 = {
2607                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2608                 },
2609         },
2610         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2611 };
2612
2613 static struct omap_hwmod omap44xx_iva_hwmod = {
2614         .name           = "iva",
2615         .class          = &omap44xx_iva_hwmod_class,
2616         .mpu_irqs       = omap44xx_iva_irqs,
2617         .rst_lines      = omap44xx_iva_resets,
2618         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2619         .main_clk       = "iva_fck",
2620         .prcm = {
2621                 .omap4 = {
2622                         .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2623                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2624                 },
2625         },
2626         .slaves         = omap44xx_iva_slaves,
2627         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2628         .masters        = omap44xx_iva_masters,
2629         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2630         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2631 };
2632
2633 /*
2634  * 'kbd' class
2635  * keyboard controller
2636  */
2637
2638 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2639         .rev_offs       = 0x0000,
2640         .sysc_offs      = 0x0010,
2641         .syss_offs      = 0x0014,
2642         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2643                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2644                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2645                            SYSS_HAS_RESET_STATUS),
2646         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2647         .sysc_fields    = &omap_hwmod_sysc_type1,
2648 };
2649
2650 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2651         .name   = "kbd",
2652         .sysc   = &omap44xx_kbd_sysc,
2653 };
2654
2655 /* kbd */
2656 static struct omap_hwmod omap44xx_kbd_hwmod;
2657 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2658         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2659         { .irq = -1 }
2660 };
2661
2662 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2663         {
2664                 .pa_start       = 0x4a31c000,
2665                 .pa_end         = 0x4a31c07f,
2666                 .flags          = ADDR_TYPE_RT
2667         },
2668         { }
2669 };
2670
2671 /* l4_wkup -> kbd */
2672 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2673         .master         = &omap44xx_l4_wkup_hwmod,
2674         .slave          = &omap44xx_kbd_hwmod,
2675         .clk            = "l4_wkup_clk_mux_ck",
2676         .addr           = omap44xx_kbd_addrs,
2677         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2678 };
2679
2680 /* kbd slave ports */
2681 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2682         &omap44xx_l4_wkup__kbd,
2683 };
2684
2685 static struct omap_hwmod omap44xx_kbd_hwmod = {
2686         .name           = "kbd",
2687         .class          = &omap44xx_kbd_hwmod_class,
2688         .mpu_irqs       = omap44xx_kbd_irqs,
2689         .main_clk       = "kbd_fck",
2690         .prcm           = {
2691                 .omap4 = {
2692                         .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2693                 },
2694         },
2695         .slaves         = omap44xx_kbd_slaves,
2696         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2697         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2698 };
2699
2700 /*
2701  * 'mailbox' class
2702  * mailbox module allowing communication between the on-chip processors using a
2703  * queued mailbox-interrupt mechanism.
2704  */
2705
2706 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2707         .rev_offs       = 0x0000,
2708         .sysc_offs      = 0x0010,
2709         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2710                            SYSC_HAS_SOFTRESET),
2711         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2712         .sysc_fields    = &omap_hwmod_sysc_type2,
2713 };
2714
2715 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2716         .name   = "mailbox",
2717         .sysc   = &omap44xx_mailbox_sysc,
2718 };
2719
2720 /* mailbox */
2721 static struct omap_hwmod omap44xx_mailbox_hwmod;
2722 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2723         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2724         { .irq = -1 }
2725 };
2726
2727 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2728         {
2729                 .pa_start       = 0x4a0f4000,
2730                 .pa_end         = 0x4a0f41ff,
2731                 .flags          = ADDR_TYPE_RT
2732         },
2733         { }
2734 };
2735
2736 /* l4_cfg -> mailbox */
2737 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2738         .master         = &omap44xx_l4_cfg_hwmod,
2739         .slave          = &omap44xx_mailbox_hwmod,
2740         .clk            = "l4_div_ck",
2741         .addr           = omap44xx_mailbox_addrs,
2742         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2743 };
2744
2745 /* mailbox slave ports */
2746 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2747         &omap44xx_l4_cfg__mailbox,
2748 };
2749
2750 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2751         .name           = "mailbox",
2752         .class          = &omap44xx_mailbox_hwmod_class,
2753         .mpu_irqs       = omap44xx_mailbox_irqs,
2754         .prcm           = {
2755                 .omap4 = {
2756                         .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2757                 },
2758         },
2759         .slaves         = omap44xx_mailbox_slaves,
2760         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2761         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2762 };
2763
2764 /*
2765  * 'mcbsp' class
2766  * multi channel buffered serial port controller
2767  */
2768
2769 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2770         .sysc_offs      = 0x008c,
2771         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2772                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2773         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2774         .sysc_fields    = &omap_hwmod_sysc_type1,
2775 };
2776
2777 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2778         .name   = "mcbsp",
2779         .sysc   = &omap44xx_mcbsp_sysc,
2780         .rev    = MCBSP_CONFIG_TYPE4,
2781 };
2782
2783 /* mcbsp1 */
2784 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2785 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2786         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2787         { .irq = -1 }
2788 };
2789
2790 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2791         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2792         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2793 };
2794
2795 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2796         {
2797                 .name           = "mpu",
2798                 .pa_start       = 0x40122000,
2799                 .pa_end         = 0x401220ff,
2800                 .flags          = ADDR_TYPE_RT
2801         },
2802         { }
2803 };
2804
2805 /* l4_abe -> mcbsp1 */
2806 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2807         .master         = &omap44xx_l4_abe_hwmod,
2808         .slave          = &omap44xx_mcbsp1_hwmod,
2809         .clk            = "ocp_abe_iclk",
2810         .addr           = omap44xx_mcbsp1_addrs,
2811         .user           = OCP_USER_MPU,
2812 };
2813
2814 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2815         {
2816                 .name           = "dma",
2817                 .pa_start       = 0x49022000,
2818                 .pa_end         = 0x490220ff,
2819                 .flags          = ADDR_TYPE_RT
2820         },
2821         { }
2822 };
2823
2824 /* l4_abe -> mcbsp1 (dma) */
2825 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2826         .master         = &omap44xx_l4_abe_hwmod,
2827         .slave          = &omap44xx_mcbsp1_hwmod,
2828         .clk            = "ocp_abe_iclk",
2829         .addr           = omap44xx_mcbsp1_dma_addrs,
2830         .user           = OCP_USER_SDMA,
2831 };
2832
2833 /* mcbsp1 slave ports */
2834 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2835         &omap44xx_l4_abe__mcbsp1,
2836         &omap44xx_l4_abe__mcbsp1_dma,
2837 };
2838
2839 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2840         .name           = "mcbsp1",
2841         .class          = &omap44xx_mcbsp_hwmod_class,
2842         .mpu_irqs       = omap44xx_mcbsp1_irqs,
2843         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
2844         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
2845         .main_clk       = "mcbsp1_fck",
2846         .prcm = {
2847                 .omap4 = {
2848                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2849                 },
2850         },
2851         .slaves         = omap44xx_mcbsp1_slaves,
2852         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2853         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2854 };
2855
2856 /* mcbsp2 */
2857 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2858 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2859         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2860         { .irq = -1 }
2861 };
2862
2863 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2864         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2865         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2866 };
2867
2868 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2869         {
2870                 .name           = "mpu",
2871                 .pa_start       = 0x40124000,
2872                 .pa_end         = 0x401240ff,
2873                 .flags          = ADDR_TYPE_RT
2874         },
2875         { }
2876 };
2877
2878 /* l4_abe -> mcbsp2 */
2879 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2880         .master         = &omap44xx_l4_abe_hwmod,
2881         .slave          = &omap44xx_mcbsp2_hwmod,
2882         .clk            = "ocp_abe_iclk",
2883         .addr           = omap44xx_mcbsp2_addrs,
2884         .user           = OCP_USER_MPU,
2885 };
2886
2887 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2888         {
2889                 .name           = "dma",
2890                 .pa_start       = 0x49024000,
2891                 .pa_end         = 0x490240ff,
2892                 .flags          = ADDR_TYPE_RT
2893         },
2894         { }
2895 };
2896
2897 /* l4_abe -> mcbsp2 (dma) */
2898 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2899         .master         = &omap44xx_l4_abe_hwmod,
2900         .slave          = &omap44xx_mcbsp2_hwmod,
2901         .clk            = "ocp_abe_iclk",
2902         .addr           = omap44xx_mcbsp2_dma_addrs,
2903         .user           = OCP_USER_SDMA,
2904 };
2905
2906 /* mcbsp2 slave ports */
2907 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2908         &omap44xx_l4_abe__mcbsp2,
2909         &omap44xx_l4_abe__mcbsp2_dma,
2910 };
2911
2912 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2913         .name           = "mcbsp2",
2914         .class          = &omap44xx_mcbsp_hwmod_class,
2915         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2916         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2917         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
2918         .main_clk       = "mcbsp2_fck",
2919         .prcm = {
2920                 .omap4 = {
2921                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2922                 },
2923         },
2924         .slaves         = omap44xx_mcbsp2_slaves,
2925         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
2926         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2927 };
2928
2929 /* mcbsp3 */
2930 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2931 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2932         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2933         { .irq = -1 }
2934 };
2935
2936 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2937         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2938         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2939 };
2940
2941 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2942         {
2943                 .name           = "mpu",
2944                 .pa_start       = 0x40126000,
2945                 .pa_end         = 0x401260ff,
2946                 .flags          = ADDR_TYPE_RT
2947         },
2948         { }
2949 };
2950
2951 /* l4_abe -> mcbsp3 */
2952 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2953         .master         = &omap44xx_l4_abe_hwmod,
2954         .slave          = &omap44xx_mcbsp3_hwmod,
2955         .clk            = "ocp_abe_iclk",
2956         .addr           = omap44xx_mcbsp3_addrs,
2957         .user           = OCP_USER_MPU,
2958 };
2959
2960 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2961         {
2962                 .name           = "dma",
2963                 .pa_start       = 0x49026000,
2964                 .pa_end         = 0x490260ff,
2965                 .flags          = ADDR_TYPE_RT
2966         },
2967         { }
2968 };
2969
2970 /* l4_abe -> mcbsp3 (dma) */
2971 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
2972         .master         = &omap44xx_l4_abe_hwmod,
2973         .slave          = &omap44xx_mcbsp3_hwmod,
2974         .clk            = "ocp_abe_iclk",
2975         .addr           = omap44xx_mcbsp3_dma_addrs,
2976         .user           = OCP_USER_SDMA,
2977 };
2978
2979 /* mcbsp3 slave ports */
2980 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
2981         &omap44xx_l4_abe__mcbsp3,
2982         &omap44xx_l4_abe__mcbsp3_dma,
2983 };
2984
2985 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2986         .name           = "mcbsp3",
2987         .class          = &omap44xx_mcbsp_hwmod_class,
2988         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2989         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2990         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
2991         .main_clk       = "mcbsp3_fck",
2992         .prcm = {
2993                 .omap4 = {
2994                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2995                 },
2996         },
2997         .slaves         = omap44xx_mcbsp3_slaves,
2998         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
2999         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3000 };
3001
3002 /* mcbsp4 */
3003 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3004 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3005         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3006         { .irq = -1 }
3007 };
3008
3009 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3010         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3011         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3012 };
3013
3014 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3015         {
3016                 .pa_start       = 0x48096000,
3017                 .pa_end         = 0x480960ff,
3018                 .flags          = ADDR_TYPE_RT
3019         },
3020         { }
3021 };
3022
3023 /* l4_per -> mcbsp4 */
3024 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3025         .master         = &omap44xx_l4_per_hwmod,
3026         .slave          = &omap44xx_mcbsp4_hwmod,
3027         .clk            = "l4_div_ck",
3028         .addr           = omap44xx_mcbsp4_addrs,
3029         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3030 };
3031
3032 /* mcbsp4 slave ports */
3033 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3034         &omap44xx_l4_per__mcbsp4,
3035 };
3036
3037 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3038         .name           = "mcbsp4",
3039         .class          = &omap44xx_mcbsp_hwmod_class,
3040         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3041         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3042         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
3043         .main_clk       = "mcbsp4_fck",
3044         .prcm = {
3045                 .omap4 = {
3046                         .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3047                 },
3048         },
3049         .slaves         = omap44xx_mcbsp4_slaves,
3050         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3051         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3052 };
3053
3054 /*
3055  * 'mcpdm' class
3056  * multi channel pdm controller (proprietary interface with phoenix power
3057  * ic)
3058  */
3059
3060 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3061         .rev_offs       = 0x0000,
3062         .sysc_offs      = 0x0010,
3063         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3064                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3065         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3066                            SIDLE_SMART_WKUP),
3067         .sysc_fields    = &omap_hwmod_sysc_type2,
3068 };
3069
3070 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3071         .name   = "mcpdm",
3072         .sysc   = &omap44xx_mcpdm_sysc,
3073 };
3074
3075 /* mcpdm */
3076 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3077 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3078         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3079         { .irq = -1 }
3080 };
3081
3082 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3083         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3084         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3085 };
3086
3087 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3088         {
3089                 .pa_start       = 0x40132000,
3090                 .pa_end         = 0x4013207f,
3091                 .flags          = ADDR_TYPE_RT
3092         },
3093         { }
3094 };
3095
3096 /* l4_abe -> mcpdm */
3097 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3098         .master         = &omap44xx_l4_abe_hwmod,
3099         .slave          = &omap44xx_mcpdm_hwmod,
3100         .clk            = "ocp_abe_iclk",
3101         .addr           = omap44xx_mcpdm_addrs,
3102         .user           = OCP_USER_MPU,
3103 };
3104
3105 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3106         {
3107                 .pa_start       = 0x49032000,
3108                 .pa_end         = 0x4903207f,
3109                 .flags          = ADDR_TYPE_RT
3110         },
3111         { }
3112 };
3113
3114 /* l4_abe -> mcpdm (dma) */
3115 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3116         .master         = &omap44xx_l4_abe_hwmod,
3117         .slave          = &omap44xx_mcpdm_hwmod,
3118         .clk            = "ocp_abe_iclk",
3119         .addr           = omap44xx_mcpdm_dma_addrs,
3120         .user           = OCP_USER_SDMA,
3121 };
3122
3123 /* mcpdm slave ports */
3124 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3125         &omap44xx_l4_abe__mcpdm,
3126         &omap44xx_l4_abe__mcpdm_dma,
3127 };
3128
3129 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3130         .name           = "mcpdm",
3131         .class          = &omap44xx_mcpdm_hwmod_class,
3132         .mpu_irqs       = omap44xx_mcpdm_irqs,
3133         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3134         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
3135         .main_clk       = "mcpdm_fck",
3136         .prcm           = {
3137                 .omap4 = {
3138                         .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3139                 },
3140         },
3141         .slaves         = omap44xx_mcpdm_slaves,
3142         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3143         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3144 };
3145
3146 /*
3147  * 'mcspi' class
3148  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3149  * bus
3150  */
3151
3152 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3153         .rev_offs       = 0x0000,
3154         .sysc_offs      = 0x0010,
3155         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3156                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3157         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3158                            SIDLE_SMART_WKUP),
3159         .sysc_fields    = &omap_hwmod_sysc_type2,
3160 };
3161
3162 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3163         .name   = "mcspi",
3164         .sysc   = &omap44xx_mcspi_sysc,
3165         .rev    = OMAP4_MCSPI_REV,
3166 };
3167
3168 /* mcspi1 */
3169 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3170 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3171         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3172         { .irq = -1 }
3173 };
3174
3175 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3176         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3177         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3178         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3179         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3180         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3181         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3182         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3183         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3184 };
3185
3186 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3187         {
3188                 .pa_start       = 0x48098000,
3189                 .pa_end         = 0x480981ff,
3190                 .flags          = ADDR_TYPE_RT
3191         },
3192         { }
3193 };
3194
3195 /* l4_per -> mcspi1 */
3196 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3197         .master         = &omap44xx_l4_per_hwmod,
3198         .slave          = &omap44xx_mcspi1_hwmod,
3199         .clk            = "l4_div_ck",
3200         .addr           = omap44xx_mcspi1_addrs,
3201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3202 };
3203
3204 /* mcspi1 slave ports */
3205 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3206         &omap44xx_l4_per__mcspi1,
3207 };
3208
3209 /* mcspi1 dev_attr */
3210 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3211         .num_chipselect = 4,
3212 };
3213
3214 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3215         .name           = "mcspi1",
3216         .class          = &omap44xx_mcspi_hwmod_class,
3217         .mpu_irqs       = omap44xx_mcspi1_irqs,
3218         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3219         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
3220         .main_clk       = "mcspi1_fck",
3221         .prcm = {
3222                 .omap4 = {
3223                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3224                 },
3225         },
3226         .dev_attr       = &mcspi1_dev_attr,
3227         .slaves         = omap44xx_mcspi1_slaves,
3228         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3229         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3230 };
3231
3232 /* mcspi2 */
3233 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3234 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3235         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3236         { .irq = -1 }
3237 };
3238
3239 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3240         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3241         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3242         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3243         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3244 };
3245
3246 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3247         {
3248                 .pa_start       = 0x4809a000,
3249                 .pa_end         = 0x4809a1ff,
3250                 .flags          = ADDR_TYPE_RT
3251         },
3252         { }
3253 };
3254
3255 /* l4_per -> mcspi2 */
3256 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3257         .master         = &omap44xx_l4_per_hwmod,
3258         .slave          = &omap44xx_mcspi2_hwmod,
3259         .clk            = "l4_div_ck",
3260         .addr           = omap44xx_mcspi2_addrs,
3261         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3262 };
3263
3264 /* mcspi2 slave ports */
3265 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3266         &omap44xx_l4_per__mcspi2,
3267 };
3268
3269 /* mcspi2 dev_attr */
3270 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3271         .num_chipselect = 2,
3272 };
3273
3274 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3275         .name           = "mcspi2",
3276         .class          = &omap44xx_mcspi_hwmod_class,
3277         .mpu_irqs       = omap44xx_mcspi2_irqs,
3278         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3279         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
3280         .main_clk       = "mcspi2_fck",
3281         .prcm = {
3282                 .omap4 = {
3283                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3284                 },
3285         },
3286         .dev_attr       = &mcspi2_dev_attr,
3287         .slaves         = omap44xx_mcspi2_slaves,
3288         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3289         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3290 };
3291
3292 /* mcspi3 */
3293 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3294 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3295         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3296         { .irq = -1 }
3297 };
3298
3299 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3300         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3301         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3302         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3303         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3304 };
3305
3306 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3307         {
3308                 .pa_start       = 0x480b8000,
3309                 .pa_end         = 0x480b81ff,
3310                 .flags          = ADDR_TYPE_RT
3311         },
3312         { }
3313 };
3314
3315 /* l4_per -> mcspi3 */
3316 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3317         .master         = &omap44xx_l4_per_hwmod,
3318         .slave          = &omap44xx_mcspi3_hwmod,
3319         .clk            = "l4_div_ck",
3320         .addr           = omap44xx_mcspi3_addrs,
3321         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3322 };
3323
3324 /* mcspi3 slave ports */
3325 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3326         &omap44xx_l4_per__mcspi3,
3327 };
3328
3329 /* mcspi3 dev_attr */
3330 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3331         .num_chipselect = 2,
3332 };
3333
3334 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3335         .name           = "mcspi3",
3336         .class          = &omap44xx_mcspi_hwmod_class,
3337         .mpu_irqs       = omap44xx_mcspi3_irqs,
3338         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3339         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
3340         .main_clk       = "mcspi3_fck",
3341         .prcm = {
3342                 .omap4 = {
3343                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3344                 },
3345         },
3346         .dev_attr       = &mcspi3_dev_attr,
3347         .slaves         = omap44xx_mcspi3_slaves,
3348         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3349         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3350 };
3351
3352 /* mcspi4 */
3353 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3354 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3355         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3356         { .irq = -1 }
3357 };
3358
3359 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3360         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3361         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3362 };
3363
3364 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3365         {
3366                 .pa_start       = 0x480ba000,
3367                 .pa_end         = 0x480ba1ff,
3368                 .flags          = ADDR_TYPE_RT
3369         },
3370         { }
3371 };
3372
3373 /* l4_per -> mcspi4 */
3374 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3375         .master         = &omap44xx_l4_per_hwmod,
3376         .slave          = &omap44xx_mcspi4_hwmod,
3377         .clk            = "l4_div_ck",
3378         .addr           = omap44xx_mcspi4_addrs,
3379         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3380 };
3381
3382 /* mcspi4 slave ports */
3383 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3384         &omap44xx_l4_per__mcspi4,
3385 };
3386
3387 /* mcspi4 dev_attr */
3388 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3389         .num_chipselect = 1,
3390 };
3391
3392 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3393         .name           = "mcspi4",
3394         .class          = &omap44xx_mcspi_hwmod_class,
3395         .mpu_irqs       = omap44xx_mcspi4_irqs,
3396         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3397         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
3398         .main_clk       = "mcspi4_fck",
3399         .prcm = {
3400                 .omap4 = {
3401                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3402                 },
3403         },
3404         .dev_attr       = &mcspi4_dev_attr,
3405         .slaves         = omap44xx_mcspi4_slaves,
3406         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3407         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3408 };
3409
3410 /*
3411  * 'mmc' class
3412  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3413  */
3414
3415 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3416         .rev_offs       = 0x0000,
3417         .sysc_offs      = 0x0010,
3418         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3419                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3420                            SYSC_HAS_SOFTRESET),
3421         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3422                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3423                            MSTANDBY_SMART),
3424         .sysc_fields    = &omap_hwmod_sysc_type2,
3425 };
3426
3427 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3428         .name   = "mmc",
3429         .sysc   = &omap44xx_mmc_sysc,
3430 };
3431
3432 /* mmc1 */
3433
3434 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3435         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3436         { .irq = -1 }
3437 };
3438
3439 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3440         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3441         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3442 };
3443
3444 /* mmc1 master ports */
3445 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3446         &omap44xx_mmc1__l3_main_1,
3447 };
3448
3449 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3450         {
3451                 .pa_start       = 0x4809c000,
3452                 .pa_end         = 0x4809c3ff,
3453                 .flags          = ADDR_TYPE_RT
3454         },
3455         { }
3456 };
3457
3458 /* l4_per -> mmc1 */
3459 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3460         .master         = &omap44xx_l4_per_hwmod,
3461         .slave          = &omap44xx_mmc1_hwmod,
3462         .clk            = "l4_div_ck",
3463         .addr           = omap44xx_mmc1_addrs,
3464         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3465 };
3466
3467 /* mmc1 slave ports */
3468 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3469         &omap44xx_l4_per__mmc1,
3470 };
3471
3472 /* mmc1 dev_attr */
3473 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3474         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3475 };
3476
3477 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3478         .name           = "mmc1",
3479         .class          = &omap44xx_mmc_hwmod_class,
3480         .mpu_irqs       = omap44xx_mmc1_irqs,
3481         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3482         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
3483         .main_clk       = "mmc1_fck",
3484         .prcm           = {
3485                 .omap4 = {
3486                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3487                 },
3488         },
3489         .dev_attr       = &mmc1_dev_attr,
3490         .slaves         = omap44xx_mmc1_slaves,
3491         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3492         .masters        = omap44xx_mmc1_masters,
3493         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3494         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3495 };
3496
3497 /* mmc2 */
3498 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3499         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3500         { .irq = -1 }
3501 };
3502
3503 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3504         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3505         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3506 };
3507
3508 /* mmc2 master ports */
3509 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3510         &omap44xx_mmc2__l3_main_1,
3511 };
3512
3513 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3514         {
3515                 .pa_start       = 0x480b4000,
3516                 .pa_end         = 0x480b43ff,
3517                 .flags          = ADDR_TYPE_RT
3518         },
3519         { }
3520 };
3521
3522 /* l4_per -> mmc2 */
3523 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3524         .master         = &omap44xx_l4_per_hwmod,
3525         .slave          = &omap44xx_mmc2_hwmod,
3526         .clk            = "l4_div_ck",
3527         .addr           = omap44xx_mmc2_addrs,
3528         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3529 };
3530
3531 /* mmc2 slave ports */
3532 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3533         &omap44xx_l4_per__mmc2,
3534 };
3535
3536 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3537         .name           = "mmc2",
3538         .class          = &omap44xx_mmc_hwmod_class,
3539         .mpu_irqs       = omap44xx_mmc2_irqs,
3540         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3541         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
3542         .main_clk       = "mmc2_fck",
3543         .prcm           = {
3544                 .omap4 = {
3545                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3546                 },
3547         },
3548         .slaves         = omap44xx_mmc2_slaves,
3549         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3550         .masters        = omap44xx_mmc2_masters,
3551         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3552         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3553 };
3554
3555 /* mmc3 */
3556 static struct omap_hwmod omap44xx_mmc3_hwmod;
3557 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3558         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3559         { .irq = -1 }
3560 };
3561
3562 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3563         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3564         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3565 };
3566
3567 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3568         {
3569                 .pa_start       = 0x480ad000,
3570                 .pa_end         = 0x480ad3ff,
3571                 .flags          = ADDR_TYPE_RT
3572         },
3573         { }
3574 };
3575
3576 /* l4_per -> mmc3 */
3577 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3578         .master         = &omap44xx_l4_per_hwmod,
3579         .slave          = &omap44xx_mmc3_hwmod,
3580         .clk            = "l4_div_ck",
3581         .addr           = omap44xx_mmc3_addrs,
3582         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3583 };
3584
3585 /* mmc3 slave ports */
3586 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3587         &omap44xx_l4_per__mmc3,
3588 };
3589
3590 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3591         .name           = "mmc3",
3592         .class          = &omap44xx_mmc_hwmod_class,
3593         .mpu_irqs       = omap44xx_mmc3_irqs,
3594         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3595         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
3596         .main_clk       = "mmc3_fck",
3597         .prcm           = {
3598                 .omap4 = {
3599                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3600                 },
3601         },
3602         .slaves         = omap44xx_mmc3_slaves,
3603         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3604         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3605 };
3606
3607 /* mmc4 */
3608 static struct omap_hwmod omap44xx_mmc4_hwmod;
3609 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3610         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3611         { .irq = -1 }
3612 };
3613
3614 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3615         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3616         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3617 };
3618
3619 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3620         {
3621                 .pa_start       = 0x480d1000,
3622                 .pa_end         = 0x480d13ff,
3623                 .flags          = ADDR_TYPE_RT
3624         },
3625         { }
3626 };
3627
3628 /* l4_per -> mmc4 */
3629 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3630         .master         = &omap44xx_l4_per_hwmod,
3631         .slave          = &omap44xx_mmc4_hwmod,
3632         .clk            = "l4_div_ck",
3633         .addr           = omap44xx_mmc4_addrs,
3634         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3635 };
3636
3637 /* mmc4 slave ports */
3638 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3639         &omap44xx_l4_per__mmc4,
3640 };
3641
3642 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3643         .name           = "mmc4",
3644         .class          = &omap44xx_mmc_hwmod_class,
3645         .mpu_irqs       = omap44xx_mmc4_irqs,
3646
3647         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3648         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
3649         .main_clk       = "mmc4_fck",
3650         .prcm           = {
3651                 .omap4 = {
3652                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3653                 },
3654         },
3655         .slaves         = omap44xx_mmc4_slaves,
3656         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3657         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3658 };
3659
3660 /* mmc5 */
3661 static struct omap_hwmod omap44xx_mmc5_hwmod;
3662 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3663         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3664         { .irq = -1 }
3665 };
3666
3667 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3668         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3669         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3670 };
3671
3672 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3673         {
3674                 .pa_start       = 0x480d5000,
3675                 .pa_end         = 0x480d53ff,
3676                 .flags          = ADDR_TYPE_RT
3677         },
3678         { }
3679 };
3680
3681 /* l4_per -> mmc5 */
3682 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3683         .master         = &omap44xx_l4_per_hwmod,
3684         .slave          = &omap44xx_mmc5_hwmod,
3685         .clk            = "l4_div_ck",
3686         .addr           = omap44xx_mmc5_addrs,
3687         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3688 };
3689
3690 /* mmc5 slave ports */
3691 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3692         &omap44xx_l4_per__mmc5,
3693 };
3694
3695 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3696         .name           = "mmc5",
3697         .class          = &omap44xx_mmc_hwmod_class,
3698         .mpu_irqs       = omap44xx_mmc5_irqs,
3699         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3700         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
3701         .main_clk       = "mmc5_fck",
3702         .prcm           = {
3703                 .omap4 = {
3704                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3705                 },
3706         },
3707         .slaves         = omap44xx_mmc5_slaves,
3708         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3709         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3710 };
3711
3712 /*
3713  * 'mpu' class
3714  * mpu sub-system
3715  */
3716
3717 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3718         .name   = "mpu",
3719 };
3720
3721 /* mpu */
3722 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3723         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3724         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3725         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3726         { .irq = -1 }
3727 };
3728
3729 /* mpu master ports */
3730 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3731         &omap44xx_mpu__l3_main_1,
3732         &omap44xx_mpu__l4_abe,
3733         &omap44xx_mpu__dmm,
3734 };
3735
3736 static struct omap_hwmod omap44xx_mpu_hwmod = {
3737         .name           = "mpu",
3738         .class          = &omap44xx_mpu_hwmod_class,
3739         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
3740         .mpu_irqs       = omap44xx_mpu_irqs,
3741         .main_clk       = "dpll_mpu_m2_ck",
3742         .prcm = {
3743                 .omap4 = {
3744                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
3745                 },
3746         },
3747         .masters        = omap44xx_mpu_masters,
3748         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3749         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3750 };
3751
3752 /*
3753  * 'smartreflex' class
3754  * smartreflex module (monitor silicon performance and outputs a measure of
3755  * performance error)
3756  */
3757
3758 /* The IP is not compliant to type1 / type2 scheme */
3759 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3760         .sidle_shift    = 24,
3761         .enwkup_shift   = 26,
3762 };
3763
3764 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3765         .sysc_offs      = 0x0038,
3766         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3767         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3768                            SIDLE_SMART_WKUP),
3769         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3770 };
3771
3772 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3773         .name   = "smartreflex",
3774         .sysc   = &omap44xx_smartreflex_sysc,
3775         .rev    = 2,
3776 };
3777
3778 /* smartreflex_core */
3779 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3780 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3781         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3782         { .irq = -1 }
3783 };
3784
3785 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3786         {
3787                 .pa_start       = 0x4a0dd000,
3788                 .pa_end         = 0x4a0dd03f,
3789                 .flags          = ADDR_TYPE_RT
3790         },
3791         { }
3792 };
3793
3794 /* l4_cfg -> smartreflex_core */
3795 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3796         .master         = &omap44xx_l4_cfg_hwmod,
3797         .slave          = &omap44xx_smartreflex_core_hwmod,
3798         .clk            = "l4_div_ck",
3799         .addr           = omap44xx_smartreflex_core_addrs,
3800         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3801 };
3802
3803 /* smartreflex_core slave ports */
3804 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3805         &omap44xx_l4_cfg__smartreflex_core,
3806 };
3807
3808 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3809         .name           = "smartreflex_core",
3810         .class          = &omap44xx_smartreflex_hwmod_class,
3811         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
3812
3813         .main_clk       = "smartreflex_core_fck",
3814         .vdd_name       = "core",
3815         .prcm = {
3816                 .omap4 = {
3817                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3818                 },
3819         },
3820         .slaves         = omap44xx_smartreflex_core_slaves,
3821         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3822         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3823 };
3824
3825 /* smartreflex_iva */
3826 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3827 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3828         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3829         { .irq = -1 }
3830 };
3831
3832 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3833         {
3834                 .pa_start       = 0x4a0db000,
3835                 .pa_end         = 0x4a0db03f,
3836                 .flags          = ADDR_TYPE_RT
3837         },
3838         { }
3839 };
3840
3841 /* l4_cfg -> smartreflex_iva */
3842 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3843         .master         = &omap44xx_l4_cfg_hwmod,
3844         .slave          = &omap44xx_smartreflex_iva_hwmod,
3845         .clk            = "l4_div_ck",
3846         .addr           = omap44xx_smartreflex_iva_addrs,
3847         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3848 };
3849
3850 /* smartreflex_iva slave ports */
3851 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3852         &omap44xx_l4_cfg__smartreflex_iva,
3853 };
3854
3855 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3856         .name           = "smartreflex_iva",
3857         .class          = &omap44xx_smartreflex_hwmod_class,
3858         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3859         .main_clk       = "smartreflex_iva_fck",
3860         .vdd_name       = "iva",
3861         .prcm = {
3862                 .omap4 = {
3863                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3864                 },
3865         },
3866         .slaves         = omap44xx_smartreflex_iva_slaves,
3867         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3868         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3869 };
3870
3871 /* smartreflex_mpu */
3872 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3873 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3874         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3875         { .irq = -1 }
3876 };
3877
3878 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3879         {
3880                 .pa_start       = 0x4a0d9000,
3881                 .pa_end         = 0x4a0d903f,
3882                 .flags          = ADDR_TYPE_RT
3883         },
3884         { }
3885 };
3886
3887 /* l4_cfg -> smartreflex_mpu */
3888 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3889         .master         = &omap44xx_l4_cfg_hwmod,
3890         .slave          = &omap44xx_smartreflex_mpu_hwmod,
3891         .clk            = "l4_div_ck",
3892         .addr           = omap44xx_smartreflex_mpu_addrs,
3893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3894 };
3895
3896 /* smartreflex_mpu slave ports */
3897 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
3898         &omap44xx_l4_cfg__smartreflex_mpu,
3899 };
3900
3901 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3902         .name           = "smartreflex_mpu",
3903         .class          = &omap44xx_smartreflex_hwmod_class,
3904         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3905         .main_clk       = "smartreflex_mpu_fck",
3906         .vdd_name       = "mpu",
3907         .prcm = {
3908                 .omap4 = {
3909                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
3910                 },
3911         },
3912         .slaves         = omap44xx_smartreflex_mpu_slaves,
3913         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
3914         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3915 };
3916
3917 /*
3918  * 'spinlock' class
3919  * spinlock provides hardware assistance for synchronizing the processes
3920  * running on multiple processors
3921  */
3922
3923 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3924         .rev_offs       = 0x0000,
3925         .sysc_offs      = 0x0010,
3926         .syss_offs      = 0x0014,
3927         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3928                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3929                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3930         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3931                            SIDLE_SMART_WKUP),
3932         .sysc_fields    = &omap_hwmod_sysc_type1,
3933 };
3934
3935 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3936         .name   = "spinlock",
3937         .sysc   = &omap44xx_spinlock_sysc,
3938 };
3939
3940 /* spinlock */
3941 static struct omap_hwmod omap44xx_spinlock_hwmod;
3942 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3943         {
3944                 .pa_start       = 0x4a0f6000,
3945                 .pa_end         = 0x4a0f6fff,
3946                 .flags          = ADDR_TYPE_RT
3947         },
3948         { }
3949 };
3950
3951 /* l4_cfg -> spinlock */
3952 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3953         .master         = &omap44xx_l4_cfg_hwmod,
3954         .slave          = &omap44xx_spinlock_hwmod,
3955         .clk            = "l4_div_ck",
3956         .addr           = omap44xx_spinlock_addrs,
3957         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3958 };
3959
3960 /* spinlock slave ports */
3961 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
3962         &omap44xx_l4_cfg__spinlock,
3963 };
3964
3965 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3966         .name           = "spinlock",
3967         .class          = &omap44xx_spinlock_hwmod_class,
3968         .prcm = {
3969                 .omap4 = {
3970                         .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
3971                 },
3972         },
3973         .slaves         = omap44xx_spinlock_slaves,
3974         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
3975         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3976 };
3977
3978 /*
3979  * 'timer' class
3980  * general purpose timer module with accurate 1ms tick
3981  * This class contains several variants: ['timer_1ms', 'timer']
3982  */
3983
3984 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3985         .rev_offs       = 0x0000,
3986         .sysc_offs      = 0x0010,
3987         .syss_offs      = 0x0014,
3988         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3989                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3990                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3991                            SYSS_HAS_RESET_STATUS),
3992         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3993         .sysc_fields    = &omap_hwmod_sysc_type1,
3994 };
3995
3996 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3997         .name   = "timer",
3998         .sysc   = &omap44xx_timer_1ms_sysc,
3999 };
4000
4001 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4002         .rev_offs       = 0x0000,
4003         .sysc_offs      = 0x0010,
4004         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4005                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4006         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4007                            SIDLE_SMART_WKUP),
4008         .sysc_fields    = &omap_hwmod_sysc_type2,
4009 };
4010
4011 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4012         .name   = "timer",
4013         .sysc   = &omap44xx_timer_sysc,
4014 };
4015
4016 /* timer1 */
4017 static struct omap_hwmod omap44xx_timer1_hwmod;
4018 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4019         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4020         { .irq = -1 }
4021 };
4022
4023 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4024         {
4025                 .pa_start       = 0x4a318000,
4026                 .pa_end         = 0x4a31807f,
4027                 .flags          = ADDR_TYPE_RT
4028         },
4029         { }
4030 };
4031
4032 /* l4_wkup -> timer1 */
4033 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4034         .master         = &omap44xx_l4_wkup_hwmod,
4035         .slave          = &omap44xx_timer1_hwmod,
4036         .clk            = "l4_wkup_clk_mux_ck",
4037         .addr           = omap44xx_timer1_addrs,
4038         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4039 };
4040
4041 /* timer1 slave ports */
4042 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4043         &omap44xx_l4_wkup__timer1,
4044 };
4045
4046 static struct omap_hwmod omap44xx_timer1_hwmod = {
4047         .name           = "timer1",
4048         .class          = &omap44xx_timer_1ms_hwmod_class,
4049         .mpu_irqs       = omap44xx_timer1_irqs,
4050         .main_clk       = "timer1_fck",
4051         .prcm = {
4052                 .omap4 = {
4053                         .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
4054                 },
4055         },
4056         .slaves         = omap44xx_timer1_slaves,
4057         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4058         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4059 };
4060
4061 /* timer2 */
4062 static struct omap_hwmod omap44xx_timer2_hwmod;
4063 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4064         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4065         { .irq = -1 }
4066 };
4067
4068 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4069         {
4070                 .pa_start       = 0x48032000,
4071                 .pa_end         = 0x4803207f,
4072                 .flags          = ADDR_TYPE_RT
4073         },
4074         { }
4075 };
4076
4077 /* l4_per -> timer2 */
4078 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4079         .master         = &omap44xx_l4_per_hwmod,
4080         .slave          = &omap44xx_timer2_hwmod,
4081         .clk            = "l4_div_ck",
4082         .addr           = omap44xx_timer2_addrs,
4083         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4084 };
4085
4086 /* timer2 slave ports */
4087 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4088         &omap44xx_l4_per__timer2,
4089 };
4090
4091 static struct omap_hwmod omap44xx_timer2_hwmod = {
4092         .name           = "timer2",
4093         .class          = &omap44xx_timer_1ms_hwmod_class,
4094         .mpu_irqs       = omap44xx_timer2_irqs,
4095         .main_clk       = "timer2_fck",
4096         .prcm = {
4097                 .omap4 = {
4098                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4099                 },
4100         },
4101         .slaves         = omap44xx_timer2_slaves,
4102         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4103         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4104 };
4105
4106 /* timer3 */
4107 static struct omap_hwmod omap44xx_timer3_hwmod;
4108 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4109         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4110         { .irq = -1 }
4111 };
4112
4113 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4114         {
4115                 .pa_start       = 0x48034000,
4116                 .pa_end         = 0x4803407f,
4117                 .flags          = ADDR_TYPE_RT
4118         },
4119         { }
4120 };
4121
4122 /* l4_per -> timer3 */
4123 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4124         .master         = &omap44xx_l4_per_hwmod,
4125         .slave          = &omap44xx_timer3_hwmod,
4126         .clk            = "l4_div_ck",
4127         .addr           = omap44xx_timer3_addrs,
4128         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4129 };
4130
4131 /* timer3 slave ports */
4132 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4133         &omap44xx_l4_per__timer3,
4134 };
4135
4136 static struct omap_hwmod omap44xx_timer3_hwmod = {
4137         .name           = "timer3",
4138         .class          = &omap44xx_timer_hwmod_class,
4139         .mpu_irqs       = omap44xx_timer3_irqs,
4140         .main_clk       = "timer3_fck",
4141         .prcm = {
4142                 .omap4 = {
4143                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4144                 },
4145         },
4146         .slaves         = omap44xx_timer3_slaves,
4147         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4148         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4149 };
4150
4151 /* timer4 */
4152 static struct omap_hwmod omap44xx_timer4_hwmod;
4153 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4154         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4155         { .irq = -1 }
4156 };
4157
4158 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4159         {
4160                 .pa_start       = 0x48036000,
4161                 .pa_end         = 0x4803607f,
4162                 .flags          = ADDR_TYPE_RT
4163         },
4164         { }
4165 };
4166
4167 /* l4_per -> timer4 */
4168 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4169         .master         = &omap44xx_l4_per_hwmod,
4170         .slave          = &omap44xx_timer4_hwmod,
4171         .clk            = "l4_div_ck",
4172         .addr           = omap44xx_timer4_addrs,
4173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4174 };
4175
4176 /* timer4 slave ports */
4177 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4178         &omap44xx_l4_per__timer4,
4179 };
4180
4181 static struct omap_hwmod omap44xx_timer4_hwmod = {
4182         .name           = "timer4",
4183         .class          = &omap44xx_timer_hwmod_class,
4184         .mpu_irqs       = omap44xx_timer4_irqs,
4185         .main_clk       = "timer4_fck",
4186         .prcm = {
4187                 .omap4 = {
4188                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4189                 },
4190         },
4191         .slaves         = omap44xx_timer4_slaves,
4192         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4193         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4194 };
4195
4196 /* timer5 */
4197 static struct omap_hwmod omap44xx_timer5_hwmod;
4198 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4199         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4200         { .irq = -1 }
4201 };
4202
4203 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4204         {
4205                 .pa_start       = 0x40138000,
4206                 .pa_end         = 0x4013807f,
4207                 .flags          = ADDR_TYPE_RT
4208         },
4209         { }
4210 };
4211
4212 /* l4_abe -> timer5 */
4213 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4214         .master         = &omap44xx_l4_abe_hwmod,
4215         .slave          = &omap44xx_timer5_hwmod,
4216         .clk            = "ocp_abe_iclk",
4217         .addr           = omap44xx_timer5_addrs,
4218         .user           = OCP_USER_MPU,
4219 };
4220
4221 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4222         {
4223                 .pa_start       = 0x49038000,
4224                 .pa_end         = 0x4903807f,
4225                 .flags          = ADDR_TYPE_RT
4226         },
4227         { }
4228 };
4229
4230 /* l4_abe -> timer5 (dma) */
4231 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4232         .master         = &omap44xx_l4_abe_hwmod,
4233         .slave          = &omap44xx_timer5_hwmod,
4234         .clk            = "ocp_abe_iclk",
4235         .addr           = omap44xx_timer5_dma_addrs,
4236         .user           = OCP_USER_SDMA,
4237 };
4238
4239 /* timer5 slave ports */
4240 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4241         &omap44xx_l4_abe__timer5,
4242         &omap44xx_l4_abe__timer5_dma,
4243 };
4244
4245 static struct omap_hwmod omap44xx_timer5_hwmod = {
4246         .name           = "timer5",
4247         .class          = &omap44xx_timer_hwmod_class,
4248         .mpu_irqs       = omap44xx_timer5_irqs,
4249         .main_clk       = "timer5_fck",
4250         .prcm = {
4251                 .omap4 = {
4252                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4253                 },
4254         },
4255         .slaves         = omap44xx_timer5_slaves,
4256         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4257         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4258 };
4259
4260 /* timer6 */
4261 static struct omap_hwmod omap44xx_timer6_hwmod;
4262 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4263         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4264         { .irq = -1 }
4265 };
4266
4267 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4268         {
4269                 .pa_start       = 0x4013a000,
4270                 .pa_end         = 0x4013a07f,
4271                 .flags          = ADDR_TYPE_RT
4272         },
4273         { }
4274 };
4275
4276 /* l4_abe -> timer6 */
4277 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4278         .master         = &omap44xx_l4_abe_hwmod,
4279         .slave          = &omap44xx_timer6_hwmod,
4280         .clk            = "ocp_abe_iclk",
4281         .addr           = omap44xx_timer6_addrs,
4282         .user           = OCP_USER_MPU,
4283 };
4284
4285 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4286         {
4287                 .pa_start       = 0x4903a000,
4288                 .pa_end         = 0x4903a07f,
4289                 .flags          = ADDR_TYPE_RT
4290         },
4291         { }
4292 };
4293
4294 /* l4_abe -> timer6 (dma) */
4295 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4296         .master         = &omap44xx_l4_abe_hwmod,
4297         .slave          = &omap44xx_timer6_hwmod,
4298         .clk            = "ocp_abe_iclk",
4299         .addr           = omap44xx_timer6_dma_addrs,
4300         .user           = OCP_USER_SDMA,
4301 };
4302
4303 /* timer6 slave ports */
4304 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4305         &omap44xx_l4_abe__timer6,
4306         &omap44xx_l4_abe__timer6_dma,
4307 };
4308
4309 static struct omap_hwmod omap44xx_timer6_hwmod = {
4310         .name           = "timer6",
4311         .class          = &omap44xx_timer_hwmod_class,
4312         .mpu_irqs       = omap44xx_timer6_irqs,
4313
4314         .main_clk       = "timer6_fck",
4315         .prcm = {
4316                 .omap4 = {
4317                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4318                 },
4319         },
4320         .slaves         = omap44xx_timer6_slaves,
4321         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4322         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4323 };
4324
4325 /* timer7 */
4326 static struct omap_hwmod omap44xx_timer7_hwmod;
4327 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4328         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4329         { .irq = -1 }
4330 };
4331
4332 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4333         {
4334                 .pa_start       = 0x4013c000,
4335                 .pa_end         = 0x4013c07f,
4336                 .flags          = ADDR_TYPE_RT
4337         },
4338         { }
4339 };
4340
4341 /* l4_abe -> timer7 */
4342 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4343         .master         = &omap44xx_l4_abe_hwmod,
4344         .slave          = &omap44xx_timer7_hwmod,
4345         .clk            = "ocp_abe_iclk",
4346         .addr           = omap44xx_timer7_addrs,
4347         .user           = OCP_USER_MPU,
4348 };
4349
4350 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4351         {
4352                 .pa_start       = 0x4903c000,
4353                 .pa_end         = 0x4903c07f,
4354                 .flags          = ADDR_TYPE_RT
4355         },
4356         { }
4357 };
4358
4359 /* l4_abe -> timer7 (dma) */
4360 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4361         .master         = &omap44xx_l4_abe_hwmod,
4362         .slave          = &omap44xx_timer7_hwmod,
4363         .clk            = "ocp_abe_iclk",
4364         .addr           = omap44xx_timer7_dma_addrs,
4365         .user           = OCP_USER_SDMA,
4366 };
4367
4368 /* timer7 slave ports */
4369 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4370         &omap44xx_l4_abe__timer7,
4371         &omap44xx_l4_abe__timer7_dma,
4372 };
4373
4374 static struct omap_hwmod omap44xx_timer7_hwmod = {
4375         .name           = "timer7",
4376         .class          = &omap44xx_timer_hwmod_class,
4377         .mpu_irqs       = omap44xx_timer7_irqs,
4378         .main_clk       = "timer7_fck",
4379         .prcm = {
4380                 .omap4 = {
4381                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4382                 },
4383         },
4384         .slaves         = omap44xx_timer7_slaves,
4385         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4386         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4387 };
4388
4389 /* timer8 */
4390 static struct omap_hwmod omap44xx_timer8_hwmod;
4391 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4392         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4393         { .irq = -1 }
4394 };
4395
4396 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4397         {
4398                 .pa_start       = 0x4013e000,
4399                 .pa_end         = 0x4013e07f,
4400                 .flags          = ADDR_TYPE_RT
4401         },
4402         { }
4403 };
4404
4405 /* l4_abe -> timer8 */
4406 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4407         .master         = &omap44xx_l4_abe_hwmod,
4408         .slave          = &omap44xx_timer8_hwmod,
4409         .clk            = "ocp_abe_iclk",
4410         .addr           = omap44xx_timer8_addrs,
4411         .user           = OCP_USER_MPU,
4412 };
4413
4414 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4415         {
4416                 .pa_start       = 0x4903e000,
4417                 .pa_end         = 0x4903e07f,
4418                 .flags          = ADDR_TYPE_RT
4419         },
4420         { }
4421 };
4422
4423 /* l4_abe -> timer8 (dma) */
4424 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4425         .master         = &omap44xx_l4_abe_hwmod,
4426         .slave          = &omap44xx_timer8_hwmod,
4427         .clk            = "ocp_abe_iclk",
4428         .addr           = omap44xx_timer8_dma_addrs,
4429         .user           = OCP_USER_SDMA,
4430 };
4431
4432 /* timer8 slave ports */
4433 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4434         &omap44xx_l4_abe__timer8,
4435         &omap44xx_l4_abe__timer8_dma,
4436 };
4437
4438 static struct omap_hwmod omap44xx_timer8_hwmod = {
4439         .name           = "timer8",
4440         .class          = &omap44xx_timer_hwmod_class,
4441         .mpu_irqs       = omap44xx_timer8_irqs,
4442         .main_clk       = "timer8_fck",
4443         .prcm = {
4444                 .omap4 = {
4445                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4446                 },
4447         },
4448         .slaves         = omap44xx_timer8_slaves,
4449         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4450         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4451 };
4452
4453 /* timer9 */
4454 static struct omap_hwmod omap44xx_timer9_hwmod;
4455 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4456         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4457         { .irq = -1 }
4458 };
4459
4460 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4461         {
4462                 .pa_start       = 0x4803e000,
4463                 .pa_end         = 0x4803e07f,
4464                 .flags          = ADDR_TYPE_RT
4465         },
4466         { }
4467 };
4468
4469 /* l4_per -> timer9 */
4470 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4471         .master         = &omap44xx_l4_per_hwmod,
4472         .slave          = &omap44xx_timer9_hwmod,
4473         .clk            = "l4_div_ck",
4474         .addr           = omap44xx_timer9_addrs,
4475         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4476 };
4477
4478 /* timer9 slave ports */
4479 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4480         &omap44xx_l4_per__timer9,
4481 };
4482
4483 static struct omap_hwmod omap44xx_timer9_hwmod = {
4484         .name           = "timer9",
4485         .class          = &omap44xx_timer_hwmod_class,
4486         .mpu_irqs       = omap44xx_timer9_irqs,
4487         .main_clk       = "timer9_fck",
4488         .prcm = {
4489                 .omap4 = {
4490                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4491                 },
4492         },
4493         .slaves         = omap44xx_timer9_slaves,
4494         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4495         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4496 };
4497
4498 /* timer10 */
4499 static struct omap_hwmod omap44xx_timer10_hwmod;
4500 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4501         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4502         { .irq = -1 }
4503 };
4504
4505 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4506         {
4507                 .pa_start       = 0x48086000,
4508                 .pa_end         = 0x4808607f,
4509                 .flags          = ADDR_TYPE_RT
4510         },
4511         { }
4512 };
4513
4514 /* l4_per -> timer10 */
4515 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4516         .master         = &omap44xx_l4_per_hwmod,
4517         .slave          = &omap44xx_timer10_hwmod,
4518         .clk            = "l4_div_ck",
4519         .addr           = omap44xx_timer10_addrs,
4520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4521 };
4522
4523 /* timer10 slave ports */
4524 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4525         &omap44xx_l4_per__timer10,
4526 };
4527
4528 static struct omap_hwmod omap44xx_timer10_hwmod = {
4529         .name           = "timer10",
4530         .class          = &omap44xx_timer_1ms_hwmod_class,
4531         .mpu_irqs       = omap44xx_timer10_irqs,
4532         .main_clk       = "timer10_fck",
4533         .prcm = {
4534                 .omap4 = {
4535                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4536                 },
4537         },
4538         .slaves         = omap44xx_timer10_slaves,
4539         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4540         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4541 };
4542
4543 /* timer11 */
4544 static struct omap_hwmod omap44xx_timer11_hwmod;
4545 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4546         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4547         { .irq = -1 }
4548 };
4549
4550 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4551         {
4552                 .pa_start       = 0x48088000,
4553                 .pa_end         = 0x4808807f,
4554                 .flags          = ADDR_TYPE_RT
4555         },
4556         { }
4557 };
4558
4559 /* l4_per -> timer11 */
4560 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4561         .master         = &omap44xx_l4_per_hwmod,
4562         .slave          = &omap44xx_timer11_hwmod,
4563         .clk            = "l4_div_ck",
4564         .addr           = omap44xx_timer11_addrs,
4565         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4566 };
4567
4568 /* timer11 slave ports */
4569 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4570         &omap44xx_l4_per__timer11,
4571 };
4572
4573 static struct omap_hwmod omap44xx_timer11_hwmod = {
4574         .name           = "timer11",
4575         .class          = &omap44xx_timer_hwmod_class,
4576         .mpu_irqs       = omap44xx_timer11_irqs,
4577         .main_clk       = "timer11_fck",
4578         .prcm = {
4579                 .omap4 = {
4580                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4581                 },
4582         },
4583         .slaves         = omap44xx_timer11_slaves,
4584         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4585         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4586 };
4587
4588 /*
4589  * 'uart' class
4590  * universal asynchronous receiver/transmitter (uart)
4591  */
4592
4593 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4594         .rev_offs       = 0x0050,
4595         .sysc_offs      = 0x0054,
4596         .syss_offs      = 0x0058,
4597         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4598                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4599                            SYSS_HAS_RESET_STATUS),
4600         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4601                            SIDLE_SMART_WKUP),
4602         .sysc_fields    = &omap_hwmod_sysc_type1,
4603 };
4604
4605 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4606         .name   = "uart",
4607         .sysc   = &omap44xx_uart_sysc,
4608 };
4609
4610 /* uart1 */
4611 static struct omap_hwmod omap44xx_uart1_hwmod;
4612 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4613         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4614         { .irq = -1 }
4615 };
4616
4617 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4618         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4619         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4620 };
4621
4622 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4623         {
4624                 .pa_start       = 0x4806a000,
4625                 .pa_end         = 0x4806a0ff,
4626                 .flags          = ADDR_TYPE_RT
4627         },
4628         { }
4629 };
4630
4631 /* l4_per -> uart1 */
4632 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4633         .master         = &omap44xx_l4_per_hwmod,
4634         .slave          = &omap44xx_uart1_hwmod,
4635         .clk            = "l4_div_ck",
4636         .addr           = omap44xx_uart1_addrs,
4637         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4638 };
4639
4640 /* uart1 slave ports */
4641 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4642         &omap44xx_l4_per__uart1,
4643 };
4644
4645 static struct omap_hwmod omap44xx_uart1_hwmod = {
4646         .name           = "uart1",
4647         .class          = &omap44xx_uart_hwmod_class,
4648         .mpu_irqs       = omap44xx_uart1_irqs,
4649         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4650         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
4651         .main_clk       = "uart1_fck",
4652         .prcm = {
4653                 .omap4 = {
4654                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
4655                 },
4656         },
4657         .slaves         = omap44xx_uart1_slaves,
4658         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4659         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4660 };
4661
4662 /* uart2 */
4663 static struct omap_hwmod omap44xx_uart2_hwmod;
4664 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4665         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4666         { .irq = -1 }
4667 };
4668
4669 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4670         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4671         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4672 };
4673
4674 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4675         {
4676                 .pa_start       = 0x4806c000,
4677                 .pa_end         = 0x4806c0ff,
4678                 .flags          = ADDR_TYPE_RT
4679         },
4680         { }
4681 };
4682
4683 /* l4_per -> uart2 */
4684 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4685         .master         = &omap44xx_l4_per_hwmod,
4686         .slave          = &omap44xx_uart2_hwmod,
4687         .clk            = "l4_div_ck",
4688         .addr           = omap44xx_uart2_addrs,
4689         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4690 };
4691
4692 /* uart2 slave ports */
4693 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4694         &omap44xx_l4_per__uart2,
4695 };
4696
4697 static struct omap_hwmod omap44xx_uart2_hwmod = {
4698         .name           = "uart2",
4699         .class          = &omap44xx_uart_hwmod_class,
4700         .mpu_irqs       = omap44xx_uart2_irqs,
4701         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4702         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
4703         .main_clk       = "uart2_fck",
4704         .prcm = {
4705                 .omap4 = {
4706                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
4707                 },
4708         },
4709         .slaves         = omap44xx_uart2_slaves,
4710         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4711         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4712 };
4713
4714 /* uart3 */
4715 static struct omap_hwmod omap44xx_uart3_hwmod;
4716 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4717         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4718         { .irq = -1 }
4719 };
4720
4721 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4722         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4723         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4724 };
4725
4726 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4727         {
4728                 .pa_start       = 0x48020000,
4729                 .pa_end         = 0x480200ff,
4730                 .flags          = ADDR_TYPE_RT
4731         },
4732         { }
4733 };
4734
4735 /* l4_per -> uart3 */
4736 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4737         .master         = &omap44xx_l4_per_hwmod,
4738         .slave          = &omap44xx_uart3_hwmod,
4739         .clk            = "l4_div_ck",
4740         .addr           = omap44xx_uart3_addrs,
4741         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4742 };
4743
4744 /* uart3 slave ports */
4745 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4746         &omap44xx_l4_per__uart3,
4747 };
4748
4749 static struct omap_hwmod omap44xx_uart3_hwmod = {
4750         .name           = "uart3",
4751         .class          = &omap44xx_uart_hwmod_class,
4752         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
4753         .mpu_irqs       = omap44xx_uart3_irqs,
4754         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
4755         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
4756         .main_clk       = "uart3_fck",
4757         .prcm = {
4758                 .omap4 = {
4759                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
4760                 },
4761         },
4762         .slaves         = omap44xx_uart3_slaves,
4763         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
4764         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4765 };
4766
4767 /* uart4 */
4768 static struct omap_hwmod omap44xx_uart4_hwmod;
4769 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4770         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4771         { .irq = -1 }
4772 };
4773
4774 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4775         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4776         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4777 };
4778
4779 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4780         {
4781                 .pa_start       = 0x4806e000,
4782                 .pa_end         = 0x4806e0ff,
4783                 .flags          = ADDR_TYPE_RT
4784         },
4785         { }
4786 };
4787
4788 /* l4_per -> uart4 */
4789 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4790         .master         = &omap44xx_l4_per_hwmod,
4791         .slave          = &omap44xx_uart4_hwmod,
4792         .clk            = "l4_div_ck",
4793         .addr           = omap44xx_uart4_addrs,
4794         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4795 };
4796
4797 /* uart4 slave ports */
4798 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4799         &omap44xx_l4_per__uart4,
4800 };
4801
4802 static struct omap_hwmod omap44xx_uart4_hwmod = {
4803         .name           = "uart4",
4804         .class          = &omap44xx_uart_hwmod_class,
4805         .mpu_irqs       = omap44xx_uart4_irqs,
4806         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
4807         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
4808         .main_clk       = "uart4_fck",
4809         .prcm = {
4810                 .omap4 = {
4811                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
4812                 },
4813         },
4814         .slaves         = omap44xx_uart4_slaves,
4815         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
4816         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4817 };
4818
4819 /*
4820  * 'usb_otg_hs' class
4821  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4822  */
4823
4824 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4825         .rev_offs       = 0x0400,
4826         .sysc_offs      = 0x0404,
4827         .syss_offs      = 0x0408,
4828         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4829                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4830                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4831         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4832                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4833                            MSTANDBY_SMART),
4834         .sysc_fields    = &omap_hwmod_sysc_type1,
4835 };
4836
4837 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4838         .name = "usb_otg_hs",
4839         .sysc = &omap44xx_usb_otg_hs_sysc,
4840 };
4841
4842 /* usb_otg_hs */
4843 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4844         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4845         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4846         { .irq = -1 }
4847 };
4848
4849 /* usb_otg_hs master ports */
4850 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4851         &omap44xx_usb_otg_hs__l3_main_2,
4852 };
4853
4854 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4855         {
4856                 .pa_start       = 0x4a0ab000,
4857                 .pa_end         = 0x4a0ab003,
4858                 .flags          = ADDR_TYPE_RT
4859         },
4860         { }
4861 };
4862
4863 /* l4_cfg -> usb_otg_hs */
4864 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4865         .master         = &omap44xx_l4_cfg_hwmod,
4866         .slave          = &omap44xx_usb_otg_hs_hwmod,
4867         .clk            = "l4_div_ck",
4868         .addr           = omap44xx_usb_otg_hs_addrs,
4869         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4870 };
4871
4872 /* usb_otg_hs slave ports */
4873 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4874         &omap44xx_l4_cfg__usb_otg_hs,
4875 };
4876
4877 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4878         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
4879 };
4880
4881 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4882         .name           = "usb_otg_hs",
4883         .class          = &omap44xx_usb_otg_hs_hwmod_class,
4884         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4885         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
4886         .main_clk       = "usb_otg_hs_ick",
4887         .prcm = {
4888                 .omap4 = {
4889                         .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
4890                 },
4891         },
4892         .opt_clks       = usb_otg_hs_opt_clks,
4893         .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
4894         .slaves         = omap44xx_usb_otg_hs_slaves,
4895         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4896         .masters        = omap44xx_usb_otg_hs_masters,
4897         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
4898         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4899 };
4900
4901 /*
4902  * 'wd_timer' class
4903  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
4904  * overflow condition
4905  */
4906
4907 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
4908         .rev_offs       = 0x0000,
4909         .sysc_offs      = 0x0010,
4910         .syss_offs      = 0x0014,
4911         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
4912                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4913         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4914                            SIDLE_SMART_WKUP),
4915         .sysc_fields    = &omap_hwmod_sysc_type1,
4916 };
4917
4918 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4919         .name           = "wd_timer",
4920         .sysc           = &omap44xx_wd_timer_sysc,
4921         .pre_shutdown   = &omap2_wd_timer_disable,
4922 };
4923
4924 /* wd_timer2 */
4925 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4926 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4927         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
4928         { .irq = -1 }
4929 };
4930
4931 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
4932         {
4933                 .pa_start       = 0x4a314000,
4934                 .pa_end         = 0x4a31407f,
4935                 .flags          = ADDR_TYPE_RT
4936         },
4937         { }
4938 };
4939
4940 /* l4_wkup -> wd_timer2 */
4941 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4942         .master         = &omap44xx_l4_wkup_hwmod,
4943         .slave          = &omap44xx_wd_timer2_hwmod,
4944         .clk            = "l4_wkup_clk_mux_ck",
4945         .addr           = omap44xx_wd_timer2_addrs,
4946         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4947 };
4948
4949 /* wd_timer2 slave ports */
4950 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
4951         &omap44xx_l4_wkup__wd_timer2,
4952 };
4953
4954 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4955         .name           = "wd_timer2",
4956         .class          = &omap44xx_wd_timer_hwmod_class,
4957         .mpu_irqs       = omap44xx_wd_timer2_irqs,
4958         .main_clk       = "wd_timer2_fck",
4959         .prcm = {
4960                 .omap4 = {
4961                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
4962                 },
4963         },
4964         .slaves         = omap44xx_wd_timer2_slaves,
4965         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
4966         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4967 };
4968
4969 /* wd_timer3 */
4970 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
4971 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
4972         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
4973         { .irq = -1 }
4974 };
4975
4976 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4977         {
4978                 .pa_start       = 0x40130000,
4979                 .pa_end         = 0x4013007f,
4980                 .flags          = ADDR_TYPE_RT
4981         },
4982         { }
4983 };
4984
4985 /* l4_abe -> wd_timer3 */
4986 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4987         .master         = &omap44xx_l4_abe_hwmod,
4988         .slave          = &omap44xx_wd_timer3_hwmod,
4989         .clk            = "ocp_abe_iclk",
4990         .addr           = omap44xx_wd_timer3_addrs,
4991         .user           = OCP_USER_MPU,
4992 };
4993
4994 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4995         {
4996                 .pa_start       = 0x49030000,
4997                 .pa_end         = 0x4903007f,
4998                 .flags          = ADDR_TYPE_RT
4999         },
5000         { }
5001 };
5002
5003 /* l4_abe -> wd_timer3 (dma) */
5004 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5005         .master         = &omap44xx_l4_abe_hwmod,
5006         .slave          = &omap44xx_wd_timer3_hwmod,
5007         .clk            = "ocp_abe_iclk",
5008         .addr           = omap44xx_wd_timer3_dma_addrs,
5009         .user           = OCP_USER_SDMA,
5010 };
5011
5012 /* wd_timer3 slave ports */
5013 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5014         &omap44xx_l4_abe__wd_timer3,
5015         &omap44xx_l4_abe__wd_timer3_dma,
5016 };
5017
5018 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5019         .name           = "wd_timer3",
5020         .class          = &omap44xx_wd_timer_hwmod_class,
5021         .mpu_irqs       = omap44xx_wd_timer3_irqs,
5022         .main_clk       = "wd_timer3_fck",
5023         .prcm = {
5024                 .omap4 = {
5025                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
5026                 },
5027         },
5028         .slaves         = omap44xx_wd_timer3_slaves,
5029         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5030         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5031 };
5032
5033 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5034
5035         /* dmm class */
5036         &omap44xx_dmm_hwmod,
5037
5038         /* emif_fw class */
5039         &omap44xx_emif_fw_hwmod,
5040
5041         /* l3 class */
5042         &omap44xx_l3_instr_hwmod,
5043         &omap44xx_l3_main_1_hwmod,
5044         &omap44xx_l3_main_2_hwmod,
5045         &omap44xx_l3_main_3_hwmod,
5046
5047         /* l4 class */
5048         &omap44xx_l4_abe_hwmod,
5049         &omap44xx_l4_cfg_hwmod,
5050         &omap44xx_l4_per_hwmod,
5051         &omap44xx_l4_wkup_hwmod,
5052
5053         /* mpu_bus class */
5054         &omap44xx_mpu_private_hwmod,
5055
5056         /* aess class */
5057 /*      &omap44xx_aess_hwmod, */
5058
5059         /* bandgap class */
5060         &omap44xx_bandgap_hwmod,
5061
5062         /* counter class */
5063 /*      &omap44xx_counter_32k_hwmod, */
5064
5065         /* dma class */
5066         &omap44xx_dma_system_hwmod,
5067
5068         /* dmic class */
5069         &omap44xx_dmic_hwmod,
5070
5071         /* dsp class */
5072         &omap44xx_dsp_hwmod,
5073         &omap44xx_dsp_c0_hwmod,
5074
5075         /* dss class */
5076         &omap44xx_dss_hwmod,
5077         &omap44xx_dss_dispc_hwmod,
5078         &omap44xx_dss_dsi1_hwmod,
5079         &omap44xx_dss_dsi2_hwmod,
5080         &omap44xx_dss_hdmi_hwmod,
5081         &omap44xx_dss_rfbi_hwmod,
5082         &omap44xx_dss_venc_hwmod,
5083
5084         /* gpio class */
5085         &omap44xx_gpio1_hwmod,
5086         &omap44xx_gpio2_hwmod,
5087         &omap44xx_gpio3_hwmod,
5088         &omap44xx_gpio4_hwmod,
5089         &omap44xx_gpio5_hwmod,
5090         &omap44xx_gpio6_hwmod,
5091
5092         /* hsi class */
5093 /*      &omap44xx_hsi_hwmod, */
5094
5095         /* i2c class */
5096         &omap44xx_i2c1_hwmod,
5097         &omap44xx_i2c2_hwmod,
5098         &omap44xx_i2c3_hwmod,
5099         &omap44xx_i2c4_hwmod,
5100
5101         /* ipu class */
5102         &omap44xx_ipu_hwmod,
5103         &omap44xx_ipu_c0_hwmod,
5104         &omap44xx_ipu_c1_hwmod,
5105
5106         /* iss class */
5107 /*      &omap44xx_iss_hwmod, */
5108
5109         /* iva class */
5110         &omap44xx_iva_hwmod,
5111         &omap44xx_iva_seq0_hwmod,
5112         &omap44xx_iva_seq1_hwmod,
5113
5114         /* kbd class */
5115         &omap44xx_kbd_hwmod,
5116
5117         /* mailbox class */
5118         &omap44xx_mailbox_hwmod,
5119
5120         /* mcbsp class */
5121         &omap44xx_mcbsp1_hwmod,
5122         &omap44xx_mcbsp2_hwmod,
5123         &omap44xx_mcbsp3_hwmod,
5124         &omap44xx_mcbsp4_hwmod,
5125
5126         /* mcpdm class */
5127 /*      &omap44xx_mcpdm_hwmod, */
5128
5129         /* mcspi class */
5130         &omap44xx_mcspi1_hwmod,
5131         &omap44xx_mcspi2_hwmod,
5132         &omap44xx_mcspi3_hwmod,
5133         &omap44xx_mcspi4_hwmod,
5134
5135         /* mmc class */
5136         &omap44xx_mmc1_hwmod,
5137         &omap44xx_mmc2_hwmod,
5138         &omap44xx_mmc3_hwmod,
5139         &omap44xx_mmc4_hwmod,
5140         &omap44xx_mmc5_hwmod,
5141
5142         /* mpu class */
5143         &omap44xx_mpu_hwmod,
5144
5145         /* smartreflex class */
5146         &omap44xx_smartreflex_core_hwmod,
5147         &omap44xx_smartreflex_iva_hwmod,
5148         &omap44xx_smartreflex_mpu_hwmod,
5149
5150         /* spinlock class */
5151         &omap44xx_spinlock_hwmod,
5152
5153         /* timer class */
5154         &omap44xx_timer1_hwmod,
5155         &omap44xx_timer2_hwmod,
5156         &omap44xx_timer3_hwmod,
5157         &omap44xx_timer4_hwmod,
5158         &omap44xx_timer5_hwmod,
5159         &omap44xx_timer6_hwmod,
5160         &omap44xx_timer7_hwmod,
5161         &omap44xx_timer8_hwmod,
5162         &omap44xx_timer9_hwmod,
5163         &omap44xx_timer10_hwmod,
5164         &omap44xx_timer11_hwmod,
5165
5166         /* uart class */
5167         &omap44xx_uart1_hwmod,
5168         &omap44xx_uart2_hwmod,
5169         &omap44xx_uart3_hwmod,
5170         &omap44xx_uart4_hwmod,
5171
5172         /* usb_otg_hs class */
5173         &omap44xx_usb_otg_hs_hwmod,
5174
5175         /* wd_timer class */
5176         &omap44xx_wd_timer2_hwmod,
5177         &omap44xx_wd_timer3_hwmod,
5178
5179         NULL,
5180 };
5181
5182 int __init omap44xx_hwmod_init(void)
5183 {
5184         return omap_hwmod_register(omap44xx_hwmods);
5185 }
5186