arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/gpio.h>
  26 #include <plat/dma.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/mcbsp.h>
  29 #include <plat/mmc.h>
  30
  31 #include "omap_hwmod_common_data.h"
  32
  33 #include "cm1_44xx.h"
  34 #include "cm2_44xx.h"
  35 #include "prm44xx.h"
  36 #include "prm-regbits-44xx.h"
  37 #include "wd_timer.h"
  38
  39 /* Base offset for all OMAP4 interrupts external to MPUSS */
  40 #define OMAP44XX_IRQ_GIC_START  32
  41
  42 /* Base offset for all OMAP4 dma requests */
  43 #define OMAP44XX_DMA_REQ_START  1
  44
  45 /* Backward references (IPs with Bus Master capability) */
  46 static struct omap_hwmod omap44xx_aess_hwmod;
  47 static struct omap_hwmod omap44xx_dma_system_hwmod;
  48 static struct omap_hwmod omap44xx_dmm_hwmod;
  49 static struct omap_hwmod omap44xx_dsp_hwmod;
  50 static struct omap_hwmod omap44xx_dss_hwmod;
  51 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  52 static struct omap_hwmod omap44xx_hsi_hwmod;
  53 static struct omap_hwmod omap44xx_ipu_hwmod;
  54 static struct omap_hwmod omap44xx_iss_hwmod;
  55 static struct omap_hwmod omap44xx_iva_hwmod;
  56 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  57 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  58 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  59 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  60 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  61 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  62 static struct omap_hwmod omap44xx_l4_per_hwmod;
  63 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  64 static struct omap_hwmod omap44xx_mmc1_hwmod;
  65 static struct omap_hwmod omap44xx_mmc2_hwmod;
  66 static struct omap_hwmod omap44xx_mpu_hwmod;
  67 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  68 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  69
  70 /*
  71  * Interconnects omap_hwmod structures
  72  * hwmods that compose the global OMAP interconnect
  73  */
  74
  75 /*
  76  * 'dmm' class
  77  * instance(s): dmm
  78  */
  79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  80         .name   = "dmm",
  81 };
  82
  83 /* dmm interface data */
  84 /* l3_main_1 -> dmm */
  85 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  86         .master         = &omap44xx_l3_main_1_hwmod,
  87         .slave          = &omap44xx_dmm_hwmod,
  88         .clk            = "l3_div_ck",
  89         .user           = OCP_USER_SDMA,
  90 };
  91
  92 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
  93         {
  94                 .pa_start       = 0x4e000000,
  95                 .pa_end         = 0x4e0007ff,
  96                 .flags          = ADDR_TYPE_RT
  97         },
  98 };
  99
 100 /* mpu -> dmm */
 101 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 102         .master         = &omap44xx_mpu_hwmod,
 103         .slave          = &omap44xx_dmm_hwmod,
 104         .clk            = "l3_div_ck",
 105         .addr           = omap44xx_dmm_addrs,
 106         .addr_cnt       = ARRAY_SIZE(omap44xx_dmm_addrs),
 107         .user           = OCP_USER_MPU,
 108 };
 109
 110 /* dmm slave ports */
 111 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 112         &omap44xx_l3_main_1__dmm,
 113         &omap44xx_mpu__dmm,
 114 };
 115
 116 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
 117         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
 118 };
 119
 120 static struct omap_hwmod omap44xx_dmm_hwmod = {
 121         .name           = "dmm",
 122         .class          = &omap44xx_dmm_hwmod_class,
 123         .slaves         = omap44xx_dmm_slaves,
 124         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 125         .mpu_irqs       = omap44xx_dmm_irqs,
 126         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
 127         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 128 };
 129
 130 /*
 131  * 'emif_fw' class
 132  * instance(s): emif_fw
 133  */
 134 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 135         .name   = "emif_fw",
 136 };
 137
 138 /* emif_fw interface data */
 139 /* dmm -> emif_fw */
 140 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 141         .master         = &omap44xx_dmm_hwmod,
 142         .slave          = &omap44xx_emif_fw_hwmod,
 143         .clk            = "l3_div_ck",
 144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 145 };
 146
 147 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 148         {
 149                 .pa_start       = 0x4a20c000,
 150                 .pa_end         = 0x4a20c0ff,
 151                 .flags          = ADDR_TYPE_RT
 152         },
 153 };
 154
 155 /* l4_cfg -> emif_fw */
 156 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 157         .master         = &omap44xx_l4_cfg_hwmod,
 158         .slave          = &omap44xx_emif_fw_hwmod,
 159         .clk            = "l4_div_ck",
 160         .addr           = omap44xx_emif_fw_addrs,
 161         .addr_cnt       = ARRAY_SIZE(omap44xx_emif_fw_addrs),
 162         .user           = OCP_USER_MPU,
 163 };
 164
 165 /* emif_fw slave ports */
 166 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 167         &omap44xx_dmm__emif_fw,
 168         &omap44xx_l4_cfg__emif_fw,
 169 };
 170
 171 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 172         .name           = "emif_fw",
 173         .class          = &omap44xx_emif_fw_hwmod_class,
 174         .slaves         = omap44xx_emif_fw_slaves,
 175         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 176         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 177 };
 178
 179 /*
 180  * 'l3' class
 181  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 182  */
 183 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 184         .name   = "l3",
 185 };
 186
 187 /* l3_instr interface data */
 188 /* iva -> l3_instr */
 189 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 190         .master         = &omap44xx_iva_hwmod,
 191         .slave          = &omap44xx_l3_instr_hwmod,
 192         .clk            = "l3_div_ck",
 193         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 194 };
 195
 196 /* l3_main_3 -> l3_instr */
 197 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 198         .master         = &omap44xx_l3_main_3_hwmod,
 199         .slave          = &omap44xx_l3_instr_hwmod,
 200         .clk            = "l3_div_ck",
 201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 202 };
 203
 204 /* l3_instr slave ports */
 205 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 206         &omap44xx_iva__l3_instr,
 207         &omap44xx_l3_main_3__l3_instr,
 208 };
 209
 210 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 211         .name           = "l3_instr",
 212         .class          = &omap44xx_l3_hwmod_class,
 213         .slaves         = omap44xx_l3_instr_slaves,
 214         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 215         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 216 };
 217
 218 /* l3_main_1 interface data */
 219 /* dsp -> l3_main_1 */
 220 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 221         .master         = &omap44xx_dsp_hwmod,
 222         .slave          = &omap44xx_l3_main_1_hwmod,
 223         .clk            = "l3_div_ck",
 224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 225 };
 226
 227 /* dss -> l3_main_1 */
 228 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 229         .master         = &omap44xx_dss_hwmod,
 230         .slave          = &omap44xx_l3_main_1_hwmod,
 231         .clk            = "l3_div_ck",
 232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 233 };
 234
 235 /* l3_main_2 -> l3_main_1 */
 236 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 237         .master         = &omap44xx_l3_main_2_hwmod,
 238         .slave          = &omap44xx_l3_main_1_hwmod,
 239         .clk            = "l3_div_ck",
 240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 241 };
 242
 243 /* l4_cfg -> l3_main_1 */
 244 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 245         .master         = &omap44xx_l4_cfg_hwmod,
 246         .slave          = &omap44xx_l3_main_1_hwmod,
 247         .clk            = "l4_div_ck",
 248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 249 };
 250
 251 /* mmc1 -> l3_main_1 */
 252 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 253         .master         = &omap44xx_mmc1_hwmod,
 254         .slave          = &omap44xx_l3_main_1_hwmod,
 255         .clk            = "l3_div_ck",
 256         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 257 };
 258
 259 /* mmc2 -> l3_main_1 */
 260 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 261         .master         = &omap44xx_mmc2_hwmod,
 262         .slave          = &omap44xx_l3_main_1_hwmod,
 263         .clk            = "l3_div_ck",
 264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 265 };
 266
 267 /* mpu -> l3_main_1 */
 268 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 269         .master         = &omap44xx_mpu_hwmod,
 270         .slave          = &omap44xx_l3_main_1_hwmod,
 271         .clk            = "l3_div_ck",
 272         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 273 };
 274
 275 /* l3_main_1 slave ports */
 276 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 277         &omap44xx_dsp__l3_main_1,
 278         &omap44xx_dss__l3_main_1,
 279         &omap44xx_l3_main_2__l3_main_1,
 280         &omap44xx_l4_cfg__l3_main_1,
 281         &omap44xx_mmc1__l3_main_1,
 282         &omap44xx_mmc2__l3_main_1,
 283         &omap44xx_mpu__l3_main_1,
 284 };
 285
 286 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 287         .name           = "l3_main_1",
 288         .class          = &omap44xx_l3_hwmod_class,
 289         .slaves         = omap44xx_l3_main_1_slaves,
 290         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 291         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 292 };
 293
 294 /* l3_main_2 interface data */
 295 /* dma_system -> l3_main_2 */
 296 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 297         .master         = &omap44xx_dma_system_hwmod,
 298         .slave          = &omap44xx_l3_main_2_hwmod,
 299         .clk            = "l3_div_ck",
 300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 301 };
 302
 303 /* hsi -> l3_main_2 */
 304 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 305         .master         = &omap44xx_hsi_hwmod,
 306         .slave          = &omap44xx_l3_main_2_hwmod,
 307         .clk            = "l3_div_ck",
 308         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 309 };
 310
 311 /* ipu -> l3_main_2 */
 312 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 313         .master         = &omap44xx_ipu_hwmod,
 314         .slave          = &omap44xx_l3_main_2_hwmod,
 315         .clk            = "l3_div_ck",
 316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 317 };
 318
 319 /* iss -> l3_main_2 */
 320 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 321         .master         = &omap44xx_iss_hwmod,
 322         .slave          = &omap44xx_l3_main_2_hwmod,
 323         .clk            = "l3_div_ck",
 324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 325 };
 326
 327 /* iva -> l3_main_2 */
 328 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 329         .master         = &omap44xx_iva_hwmod,
 330         .slave          = &omap44xx_l3_main_2_hwmod,
 331         .clk            = "l3_div_ck",
 332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 333 };
 334
 335 /* l3_main_1 -> l3_main_2 */
 336 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 337         .master         = &omap44xx_l3_main_1_hwmod,
 338         .slave          = &omap44xx_l3_main_2_hwmod,
 339         .clk            = "l3_div_ck",
 340         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 341 };
 342
 343 /* l4_cfg -> l3_main_2 */
 344 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 345         .master         = &omap44xx_l4_cfg_hwmod,
 346         .slave          = &omap44xx_l3_main_2_hwmod,
 347         .clk            = "l4_div_ck",
 348         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 349 };
 350
 351 /* usb_otg_hs -> l3_main_2 */
 352 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 353         .master         = &omap44xx_usb_otg_hs_hwmod,
 354         .slave          = &omap44xx_l3_main_2_hwmod,
 355         .clk            = "l3_div_ck",
 356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 357 };
 358
 359 /* l3_main_2 slave ports */
 360 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 361         &omap44xx_dma_system__l3_main_2,
 362         &omap44xx_hsi__l3_main_2,
 363         &omap44xx_ipu__l3_main_2,
 364         &omap44xx_iss__l3_main_2,
 365         &omap44xx_iva__l3_main_2,
 366         &omap44xx_l3_main_1__l3_main_2,
 367         &omap44xx_l4_cfg__l3_main_2,
 368         &omap44xx_usb_otg_hs__l3_main_2,
 369 };
 370
 371 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 372         .name           = "l3_main_2",
 373         .class          = &omap44xx_l3_hwmod_class,
 374         .slaves         = omap44xx_l3_main_2_slaves,
 375         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 376         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 377 };
 378
 379 /* l3_main_3 interface data */
 380 /* l3_main_1 -> l3_main_3 */
 381 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 382         .master         = &omap44xx_l3_main_1_hwmod,
 383         .slave          = &omap44xx_l3_main_3_hwmod,
 384         .clk            = "l3_div_ck",
 385         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 386 };
 387
 388 /* l3_main_2 -> l3_main_3 */
 389 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 390         .master         = &omap44xx_l3_main_2_hwmod,
 391         .slave          = &omap44xx_l3_main_3_hwmod,
 392         .clk            = "l3_div_ck",
 393         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 394 };
 395
 396 /* l4_cfg -> l3_main_3 */
 397 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 398         .master         = &omap44xx_l4_cfg_hwmod,
 399         .slave          = &omap44xx_l3_main_3_hwmod,
 400         .clk            = "l4_div_ck",
 401         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 402 };
 403
 404 /* l3_main_3 slave ports */
 405 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 406         &omap44xx_l3_main_1__l3_main_3,
 407         &omap44xx_l3_main_2__l3_main_3,
 408         &omap44xx_l4_cfg__l3_main_3,
 409 };
 410
 411 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 412         .name           = "l3_main_3",
 413         .class          = &omap44xx_l3_hwmod_class,
 414         .slaves         = omap44xx_l3_main_3_slaves,
 415         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 416         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 417 };
 418
 419 /*
 420  * 'l4' class
 421  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 422  */
 423 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 424         .name   = "l4",
 425 };
 426
 427 /* l4_abe interface data */
 428 /* aess -> l4_abe */
 429 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 430         .master         = &omap44xx_aess_hwmod,
 431         .slave          = &omap44xx_l4_abe_hwmod,
 432         .clk            = "ocp_abe_iclk",
 433         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 434 };
 435
 436 /* dsp -> l4_abe */
 437 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 438         .master         = &omap44xx_dsp_hwmod,
 439         .slave          = &omap44xx_l4_abe_hwmod,
 440         .clk            = "ocp_abe_iclk",
 441         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 442 };
 443
 444 /* l3_main_1 -> l4_abe */
 445 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 446         .master         = &omap44xx_l3_main_1_hwmod,
 447         .slave          = &omap44xx_l4_abe_hwmod,
 448         .clk            = "l3_div_ck",
 449         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 450 };
 451
 452 /* mpu -> l4_abe */
 453 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 454         .master         = &omap44xx_mpu_hwmod,
 455         .slave          = &omap44xx_l4_abe_hwmod,
 456         .clk            = "ocp_abe_iclk",
 457         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 458 };
 459
 460 /* l4_abe slave ports */
 461 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 462         &omap44xx_aess__l4_abe,
 463         &omap44xx_dsp__l4_abe,
 464         &omap44xx_l3_main_1__l4_abe,
 465         &omap44xx_mpu__l4_abe,
 466 };
 467
 468 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 469         .name           = "l4_abe",
 470         .class          = &omap44xx_l4_hwmod_class,
 471         .slaves         = omap44xx_l4_abe_slaves,
 472         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 473         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 474 };
 475
 476 /* l4_cfg interface data */
 477 /* l3_main_1 -> l4_cfg */
 478 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 479         .master         = &omap44xx_l3_main_1_hwmod,
 480         .slave          = &omap44xx_l4_cfg_hwmod,
 481         .clk            = "l3_div_ck",
 482         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 483 };
 484
 485 /* l4_cfg slave ports */
 486 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 487         &omap44xx_l3_main_1__l4_cfg,
 488 };
 489
 490 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 491         .name           = "l4_cfg",
 492         .class          = &omap44xx_l4_hwmod_class,
 493         .slaves         = omap44xx_l4_cfg_slaves,
 494         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 495         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 496 };
 497
 498 /* l4_per interface data */
 499 /* l3_main_2 -> l4_per */
 500 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 501         .master         = &omap44xx_l3_main_2_hwmod,
 502         .slave          = &omap44xx_l4_per_hwmod,
 503         .clk            = "l3_div_ck",
 504         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 505 };
 506
 507 /* l4_per slave ports */
 508 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 509         &omap44xx_l3_main_2__l4_per,
 510 };
 511
 512 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 513         .name           = "l4_per",
 514         .class          = &omap44xx_l4_hwmod_class,
 515         .slaves         = omap44xx_l4_per_slaves,
 516         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 517         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 518 };
 519
 520 /* l4_wkup interface data */
 521 /* l4_cfg -> l4_wkup */
 522 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 523         .master         = &omap44xx_l4_cfg_hwmod,
 524         .slave          = &omap44xx_l4_wkup_hwmod,
 525         .clk            = "l4_div_ck",
 526         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 527 };
 528
 529 /* l4_wkup slave ports */
 530 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 531         &omap44xx_l4_cfg__l4_wkup,
 532 };
 533
 534 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 535         .name           = "l4_wkup",
 536         .class          = &omap44xx_l4_hwmod_class,
 537         .slaves         = omap44xx_l4_wkup_slaves,
 538         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 539         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 540 };
 541
 542 /*
 543  * 'mpu_bus' class
 544  * instance(s): mpu_private
 545  */
 546 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 547         .name   = "mpu_bus",
 548 };
 549
 550 /* mpu_private interface data */
 551 /* mpu -> mpu_private */
 552 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 553         .master         = &omap44xx_mpu_hwmod,
 554         .slave          = &omap44xx_mpu_private_hwmod,
 555         .clk            = "l3_div_ck",
 556         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 557 };
 558
 559 /* mpu_private slave ports */
 560 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 561         &omap44xx_mpu__mpu_private,
 562 };
 563
 564 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 565         .name           = "mpu_private",
 566         .class          = &omap44xx_mpu_bus_hwmod_class,
 567         .slaves         = omap44xx_mpu_private_slaves,
 568         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 569         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 570 };
 571
 572 /*
 573  * Modules omap_hwmod structures
 574  *
 575  * The following IPs are excluded for the moment because:
 576  * - They do not need an explicit SW control using omap_hwmod API.
 577  * - They still need to be validated with the driver
 578  *   properly adapted to omap_hwmod / omap_device
 579  *
 580  *  c2c
 581  *  c2c_target_fw
 582  *  cm_core
 583  *  cm_core_aon
 584  *  ctrl_module_core
 585  *  ctrl_module_pad_core
 586  *  ctrl_module_pad_wkup
 587  *  ctrl_module_wkup
 588  *  debugss
 589  *  efuse_ctrl_cust
 590  *  efuse_ctrl_std
 591  *  elm
 592  *  emif1
 593  *  emif2
 594  *  fdif
 595  *  gpmc
 596  *  gpu
 597  *  hdq1w
 598  *  hsi
 599  *  ocmc_ram
 600  *  ocp2scp_usb_phy
 601  *  ocp_wp_noc
 602  *  prcm_mpu
 603  *  prm
 604  *  scrm
 605  *  sl2if
 606  *  slimbus1
 607  *  slimbus2
 608  *  usb_host_fs
 609  *  usb_host_hs
 610  *  usb_phy_cm
 611  *  usb_tll_hs
 612  *  usim
 613  */
 614
 615 /*
 616  * 'aess' class
 617  * audio engine sub system
 618  */
 619
 620 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 621         .rev_offs       = 0x0000,
 622         .sysc_offs      = 0x0010,
 623         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 624         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 625                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 626         .sysc_fields    = &omap_hwmod_sysc_type2,
 627 };
 628
 629 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 630         .name   = "aess",
 631         .sysc   = &omap44xx_aess_sysc,
 632 };
 633
 634 /* aess */
 635 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 636         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 637 };
 638
 639 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 640         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 641         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 642         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 643         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 644         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 645         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 646         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 647         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 648 };
 649
 650 /* aess master ports */
 651 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 652         &omap44xx_aess__l4_abe,
 653 };
 654
 655 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 656         {
 657                 .pa_start       = 0x401f1000,
 658                 .pa_end         = 0x401f13ff,
 659                 .flags          = ADDR_TYPE_RT
 660         },
 661 };
 662
 663 /* l4_abe -> aess */
 664 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 665         .master         = &omap44xx_l4_abe_hwmod,
 666         .slave          = &omap44xx_aess_hwmod,
 667         .clk            = "ocp_abe_iclk",
 668         .addr           = omap44xx_aess_addrs,
 669         .addr_cnt       = ARRAY_SIZE(omap44xx_aess_addrs),
 670         .user           = OCP_USER_MPU,
 671 };
 672
 673 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 674         {
 675                 .pa_start       = 0x490f1000,
 676                 .pa_end         = 0x490f13ff,
 677                 .flags          = ADDR_TYPE_RT
 678         },
 679 };
 680
 681 /* l4_abe -> aess (dma) */
 682 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 683         .master         = &omap44xx_l4_abe_hwmod,
 684         .slave          = &omap44xx_aess_hwmod,
 685         .clk            = "ocp_abe_iclk",
 686         .addr           = omap44xx_aess_dma_addrs,
 687         .addr_cnt       = ARRAY_SIZE(omap44xx_aess_dma_addrs),
 688         .user           = OCP_USER_SDMA,
 689 };
 690
 691 /* aess slave ports */
 692 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 693         &omap44xx_l4_abe__aess,
 694         &omap44xx_l4_abe__aess_dma,
 695 };
 696
 697 static struct omap_hwmod omap44xx_aess_hwmod = {
 698         .name           = "aess",
 699         .class          = &omap44xx_aess_hwmod_class,
 700         .mpu_irqs       = omap44xx_aess_irqs,
 701         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_aess_irqs),
 702         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 703         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
 704         .main_clk       = "aess_fck",
 705         .prcm           = {
 706                 .omap4 = {
 707                         .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 708                 },
 709         },
 710         .slaves         = omap44xx_aess_slaves,
 711         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 712         .masters        = omap44xx_aess_masters,
 713         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 714         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 715 };
 716
 717 /*
 718  * 'bandgap' class
 719  * bangap reference for ldo regulators
 720  */
 721
 722 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 723         .name   = "bandgap",
 724 };
 725
 726 /* bandgap */
 727 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 728         { .role = "fclk", .clk = "bandgap_fclk" },
 729 };
 730
 731 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 732         .name           = "bandgap",
 733         .class          = &omap44xx_bandgap_hwmod_class,
 734         .prcm           = {
 735                 .omap4 = {
 736                         .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 737                 },
 738         },
 739         .opt_clks       = bandgap_opt_clks,
 740         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 741         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 742 };
 743
 744 /*
 745  * 'counter' class
 746  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 747  */
 748
 749 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 750         .rev_offs       = 0x0000,
 751         .sysc_offs      = 0x0004,
 752         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 753         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 754                            SIDLE_SMART_WKUP),
 755         .sysc_fields    = &omap_hwmod_sysc_type1,
 756 };
 757
 758 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 759         .name   = "counter",
 760         .sysc   = &omap44xx_counter_sysc,
 761 };
 762
 763 /* counter_32k */
 764 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 765 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 766         {
 767                 .pa_start       = 0x4a304000,
 768                 .pa_end         = 0x4a30401f,
 769                 .flags          = ADDR_TYPE_RT
 770         },
 771 };
 772
 773 /* l4_wkup -> counter_32k */
 774 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 775         .master         = &omap44xx_l4_wkup_hwmod,
 776         .slave          = &omap44xx_counter_32k_hwmod,
 777         .clk            = "l4_wkup_clk_mux_ck",
 778         .addr           = omap44xx_counter_32k_addrs,
 779         .addr_cnt       = ARRAY_SIZE(omap44xx_counter_32k_addrs),
 780         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 781 };
 782
 783 /* counter_32k slave ports */
 784 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 785         &omap44xx_l4_wkup__counter_32k,
 786 };
 787
 788 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 789         .name           = "counter_32k",
 790         .class          = &omap44xx_counter_hwmod_class,
 791         .flags          = HWMOD_SWSUP_SIDLE,
 792         .main_clk       = "sys_32k_ck",
 793         .prcm           = {
 794                 .omap4 = {
 795                         .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
 796                 },
 797         },
 798         .slaves         = omap44xx_counter_32k_slaves,
 799         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 800         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 801 };
 802
 803 /*
 804  * 'dma' class
 805  * dma controller for data exchange between memory to memory (i.e. internal or
 806  * external memory) and gp peripherals to memory or memory to gp peripherals
 807  */
 808
 809 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 810         .rev_offs       = 0x0000,
 811         .sysc_offs      = 0x002c,
 812         .syss_offs      = 0x0028,
 813         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 814                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 815                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 816                            SYSS_HAS_RESET_STATUS),
 817         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 818                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 819         .sysc_fields    = &omap_hwmod_sysc_type1,
 820 };
 821
 822 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 823         .name   = "dma",
 824         .sysc   = &omap44xx_dma_sysc,
 825 };
 826
 827 /* dma dev_attr */
 828 static struct omap_dma_dev_attr dma_dev_attr = {
 829         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 830                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 831         .lch_count      = 32,
 832 };
 833
 834 /* dma_system */
 835 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 836         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 837         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 838         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 839         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 840 };
 841
 842 /* dma_system master ports */
 843 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 844         &omap44xx_dma_system__l3_main_2,
 845 };
 846
 847 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 848         {
 849                 .pa_start       = 0x4a056000,
 850                 .pa_end         = 0x4a0560ff,
 851                 .flags          = ADDR_TYPE_RT
 852         },
 853 };
 854
 855 /* l4_cfg -> dma_system */
 856 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 857         .master         = &omap44xx_l4_cfg_hwmod,
 858         .slave          = &omap44xx_dma_system_hwmod,
 859         .clk            = "l4_div_ck",
 860         .addr           = omap44xx_dma_system_addrs,
 861         .addr_cnt       = ARRAY_SIZE(omap44xx_dma_system_addrs),
 862         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 863 };
 864
 865 /* dma_system slave ports */
 866 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 867         &omap44xx_l4_cfg__dma_system,
 868 };
 869
 870 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 871         .name           = "dma_system",
 872         .class          = &omap44xx_dma_hwmod_class,
 873         .mpu_irqs       = omap44xx_dma_system_irqs,
 874         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dma_system_irqs),
 875         .main_clk       = "l3_div_ck",
 876         .prcm = {
 877                 .omap4 = {
 878                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
 879                 },
 880         },
 881         .dev_attr       = &dma_dev_attr,
 882         .slaves         = omap44xx_dma_system_slaves,
 883         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 884         .masters        = omap44xx_dma_system_masters,
 885         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 886         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 887 };
 888
 889 /*
 890  * 'dmic' class
 891  * digital microphone controller
 892  */
 893
 894 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 895         .rev_offs       = 0x0000,
 896         .sysc_offs      = 0x0010,
 897         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 898                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 899         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 900                            SIDLE_SMART_WKUP),
 901         .sysc_fields    = &omap_hwmod_sysc_type2,
 902 };
 903
 904 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 905         .name   = "dmic",
 906         .sysc   = &omap44xx_dmic_sysc,
 907 };
 908
 909 /* dmic */
 910 static struct omap_hwmod omap44xx_dmic_hwmod;
 911 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 912         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 913 };
 914
 915 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 916         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 917 };
 918
 919 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
 920         {
 921                 .pa_start       = 0x4012e000,
 922                 .pa_end         = 0x4012e07f,
 923                 .flags          = ADDR_TYPE_RT
 924         },
 925 };
 926
 927 /* l4_abe -> dmic */
 928 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
 929         .master         = &omap44xx_l4_abe_hwmod,
 930         .slave          = &omap44xx_dmic_hwmod,
 931         .clk            = "ocp_abe_iclk",
 932         .addr           = omap44xx_dmic_addrs,
 933         .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_addrs),
 934         .user           = OCP_USER_MPU,
 935 };
 936
 937 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
 938         {
 939                 .pa_start       = 0x4902e000,
 940                 .pa_end         = 0x4902e07f,
 941                 .flags          = ADDR_TYPE_RT
 942         },
 943 };
 944
 945 /* l4_abe -> dmic (dma) */
 946 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
 947         .master         = &omap44xx_l4_abe_hwmod,
 948         .slave          = &omap44xx_dmic_hwmod,
 949         .clk            = "ocp_abe_iclk",
 950         .addr           = omap44xx_dmic_dma_addrs,
 951         .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
 952         .user           = OCP_USER_SDMA,
 953 };
 954
 955 /* dmic slave ports */
 956 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
 957         &omap44xx_l4_abe__dmic,
 958         &omap44xx_l4_abe__dmic_dma,
 959 };
 960
 961 static struct omap_hwmod omap44xx_dmic_hwmod = {
 962         .name           = "dmic",
 963         .class          = &omap44xx_dmic_hwmod_class,
 964         .mpu_irqs       = omap44xx_dmic_irqs,
 965         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmic_irqs),
 966         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 967         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
 968         .main_clk       = "dmic_fck",
 969         .prcm           = {
 970                 .omap4 = {
 971                         .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
 972                 },
 973         },
 974         .slaves         = omap44xx_dmic_slaves,
 975         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
 976         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 977 };
 978
 979 /*
 980  * 'dsp' class
 981  * dsp sub-system
 982  */
 983
 984 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 985         .name   = "dsp",
 986 };
 987
 988 /* dsp */
 989 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 990         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 991 };
 992
 993 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 994         { .name = "mmu_cache", .rst_shift = 1 },
 995 };
 996
 997 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
 998         { .name = "dsp", .rst_shift = 0 },
 999 };
1000
1001 /* dsp -> iva */
1002 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1003         .master         = &omap44xx_dsp_hwmod,
1004         .slave          = &omap44xx_iva_hwmod,
1005         .clk            = "dpll_iva_m5x2_ck",
1006 };
1007
1008 /* dsp master ports */
1009 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1010         &omap44xx_dsp__l3_main_1,
1011         &omap44xx_dsp__l4_abe,
1012         &omap44xx_dsp__iva,
1013 };
1014
1015 /* l4_cfg -> dsp */
1016 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1017         .master         = &omap44xx_l4_cfg_hwmod,
1018         .slave          = &omap44xx_dsp_hwmod,
1019         .clk            = "l4_div_ck",
1020         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1021 };
1022
1023 /* dsp slave ports */
1024 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1025         &omap44xx_l4_cfg__dsp,
1026 };
1027
1028 /* Pseudo hwmod for reset control purpose only */
1029 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1030         .name           = "dsp_c0",
1031         .class          = &omap44xx_dsp_hwmod_class,
1032         .flags          = HWMOD_INIT_NO_RESET,
1033         .rst_lines      = omap44xx_dsp_c0_resets,
1034         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1035         .prcm = {
1036                 .omap4 = {
1037                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1038                 },
1039         },
1040         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1041 };
1042
1043 static struct omap_hwmod omap44xx_dsp_hwmod = {
1044         .name           = "dsp",
1045         .class          = &omap44xx_dsp_hwmod_class,
1046         .mpu_irqs       = omap44xx_dsp_irqs,
1047         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dsp_irqs),
1048         .rst_lines      = omap44xx_dsp_resets,
1049         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1050         .main_clk       = "dsp_fck",
1051         .prcm = {
1052                 .omap4 = {
1053                         .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1054                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1055                 },
1056         },
1057         .slaves         = omap44xx_dsp_slaves,
1058         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1059         .masters        = omap44xx_dsp_masters,
1060         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1061         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1062 };
1063
1064 /*
1065  * 'dss' class
1066  * display sub-system
1067  */
1068
1069 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1070         .rev_offs       = 0x0000,
1071         .syss_offs      = 0x0014,
1072         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1073 };
1074
1075 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1076         .name   = "dss",
1077         .sysc   = &omap44xx_dss_sysc,
1078 };
1079
1080 /* dss */
1081 /* dss master ports */
1082 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1083         &omap44xx_dss__l3_main_1,
1084 };
1085
1086 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1087         {
1088                 .pa_start       = 0x58000000,
1089                 .pa_end         = 0x5800007f,
1090                 .flags          = ADDR_TYPE_RT
1091         },
1092 };
1093
1094 /* l3_main_2 -> dss */
1095 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1096         .master         = &omap44xx_l3_main_2_hwmod,
1097         .slave          = &omap44xx_dss_hwmod,
1098         .clk            = "l3_div_ck",
1099         .addr           = omap44xx_dss_dma_addrs,
1100         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dma_addrs),
1101         .user           = OCP_USER_SDMA,
1102 };
1103
1104 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1105         {
1106                 .pa_start       = 0x48040000,
1107                 .pa_end         = 0x4804007f,
1108                 .flags          = ADDR_TYPE_RT
1109         },
1110 };
1111
1112 /* l4_per -> dss */
1113 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1114         .master         = &omap44xx_l4_per_hwmod,
1115         .slave          = &omap44xx_dss_hwmod,
1116         .clk            = "l4_div_ck",
1117         .addr           = omap44xx_dss_addrs,
1118         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_addrs),
1119         .user           = OCP_USER_MPU,
1120 };
1121
1122 /* dss slave ports */
1123 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1124         &omap44xx_l3_main_2__dss,
1125         &omap44xx_l4_per__dss,
1126 };
1127
1128 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1129         { .role = "sys_clk", .clk = "dss_sys_clk" },
1130         { .role = "tv_clk", .clk = "dss_tv_clk" },
1131         { .role = "dss_clk", .clk = "dss_dss_clk" },
1132         { .role = "video_clk", .clk = "dss_48mhz_clk" },
1133 };
1134
1135 static struct omap_hwmod omap44xx_dss_hwmod = {
1136         .name           = "dss_core",
1137         .class          = &omap44xx_dss_hwmod_class,
1138         .main_clk       = "dss_fck",
1139         .prcm = {
1140                 .omap4 = {
1141                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1142                 },
1143         },
1144         .opt_clks       = dss_opt_clks,
1145         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1146         .slaves         = omap44xx_dss_slaves,
1147         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1148         .masters        = omap44xx_dss_masters,
1149         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1150         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1151 };
1152
1153 /*
1154  * 'dispc' class
1155  * display controller
1156  */
1157
1158 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1159         .rev_offs       = 0x0000,
1160         .sysc_offs      = 0x0010,
1161         .syss_offs      = 0x0014,
1162         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1163                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1164                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1165                            SYSS_HAS_RESET_STATUS),
1166         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1167                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1168         .sysc_fields    = &omap_hwmod_sysc_type1,
1169 };
1170
1171 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1172         .name   = "dispc",
1173         .sysc   = &omap44xx_dispc_sysc,
1174 };
1175
1176 /* dss_dispc */
1177 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1178 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1179         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1180 };
1181
1182 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1183         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1184 };
1185
1186 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1187         {
1188                 .pa_start       = 0x58001000,
1189                 .pa_end         = 0x58001fff,
1190                 .flags          = ADDR_TYPE_RT
1191         },
1192 };
1193
1194 /* l3_main_2 -> dss_dispc */
1195 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1196         .master         = &omap44xx_l3_main_2_hwmod,
1197         .slave          = &omap44xx_dss_dispc_hwmod,
1198         .clk            = "l3_div_ck",
1199         .addr           = omap44xx_dss_dispc_dma_addrs,
1200         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
1201         .user           = OCP_USER_SDMA,
1202 };
1203
1204 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1205         {
1206                 .pa_start       = 0x48041000,
1207                 .pa_end         = 0x48041fff,
1208                 .flags          = ADDR_TYPE_RT
1209         },
1210 };
1211
1212 /* l4_per -> dss_dispc */
1213 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1214         .master         = &omap44xx_l4_per_hwmod,
1215         .slave          = &omap44xx_dss_dispc_hwmod,
1216         .clk            = "l4_div_ck",
1217         .addr           = omap44xx_dss_dispc_addrs,
1218         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
1219         .user           = OCP_USER_MPU,
1220 };
1221
1222 /* dss_dispc slave ports */
1223 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1224         &omap44xx_l3_main_2__dss_dispc,
1225         &omap44xx_l4_per__dss_dispc,
1226 };
1227
1228 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1229         .name           = "dss_dispc",
1230         .class          = &omap44xx_dispc_hwmod_class,
1231         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1232         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
1233         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1234         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
1235         .main_clk       = "dss_fck",
1236         .prcm = {
1237                 .omap4 = {
1238                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1239                 },
1240         },
1241         .slaves         = omap44xx_dss_dispc_slaves,
1242         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1243         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1244 };
1245
1246 /*
1247  * 'dsi' class
1248  * display serial interface controller
1249  */
1250
1251 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1252         .rev_offs       = 0x0000,
1253         .sysc_offs      = 0x0010,
1254         .syss_offs      = 0x0014,
1255         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1256                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1257                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1258         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1259         .sysc_fields    = &omap_hwmod_sysc_type1,
1260 };
1261
1262 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1263         .name   = "dsi",
1264         .sysc   = &omap44xx_dsi_sysc,
1265 };
1266
1267 /* dss_dsi1 */
1268 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1269 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1270         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1271 };
1272
1273 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1274         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1275 };
1276
1277 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1278         {
1279                 .pa_start       = 0x58004000,
1280                 .pa_end         = 0x580041ff,
1281                 .flags          = ADDR_TYPE_RT
1282         },
1283 };
1284
1285 /* l3_main_2 -> dss_dsi1 */
1286 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1287         .master         = &omap44xx_l3_main_2_hwmod,
1288         .slave          = &omap44xx_dss_dsi1_hwmod,
1289         .clk            = "l3_div_ck",
1290         .addr           = omap44xx_dss_dsi1_dma_addrs,
1291         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
1292         .user           = OCP_USER_SDMA,
1293 };
1294
1295 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1296         {
1297                 .pa_start       = 0x48044000,
1298                 .pa_end         = 0x480441ff,
1299                 .flags          = ADDR_TYPE_RT
1300         },
1301 };
1302
1303 /* l4_per -> dss_dsi1 */
1304 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1305         .master         = &omap44xx_l4_per_hwmod,
1306         .slave          = &omap44xx_dss_dsi1_hwmod,
1307         .clk            = "l4_div_ck",
1308         .addr           = omap44xx_dss_dsi1_addrs,
1309         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
1310         .user           = OCP_USER_MPU,
1311 };
1312
1313 /* dss_dsi1 slave ports */
1314 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1315         &omap44xx_l3_main_2__dss_dsi1,
1316         &omap44xx_l4_per__dss_dsi1,
1317 };
1318
1319 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1320         .name           = "dss_dsi1",
1321         .class          = &omap44xx_dsi_hwmod_class,
1322         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1323         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
1324         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1325         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
1326         .main_clk       = "dss_fck",
1327         .prcm = {
1328                 .omap4 = {
1329                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1330                 },
1331         },
1332         .slaves         = omap44xx_dss_dsi1_slaves,
1333         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1334         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1335 };
1336
1337 /* dss_dsi2 */
1338 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1339 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1340         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1341 };
1342
1343 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1344         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1345 };
1346
1347 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1348         {
1349                 .pa_start       = 0x58005000,
1350                 .pa_end         = 0x580051ff,
1351                 .flags          = ADDR_TYPE_RT
1352         },
1353 };
1354
1355 /* l3_main_2 -> dss_dsi2 */
1356 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1357         .master         = &omap44xx_l3_main_2_hwmod,
1358         .slave          = &omap44xx_dss_dsi2_hwmod,
1359         .clk            = "l3_div_ck",
1360         .addr           = omap44xx_dss_dsi2_dma_addrs,
1361         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
1362         .user           = OCP_USER_SDMA,
1363 };
1364
1365 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1366         {
1367                 .pa_start       = 0x48045000,
1368                 .pa_end         = 0x480451ff,
1369                 .flags          = ADDR_TYPE_RT
1370         },
1371 };
1372
1373 /* l4_per -> dss_dsi2 */
1374 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1375         .master         = &omap44xx_l4_per_hwmod,
1376         .slave          = &omap44xx_dss_dsi2_hwmod,
1377         .clk            = "l4_div_ck",
1378         .addr           = omap44xx_dss_dsi2_addrs,
1379         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
1380         .user           = OCP_USER_MPU,
1381 };
1382
1383 /* dss_dsi2 slave ports */
1384 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1385         &omap44xx_l3_main_2__dss_dsi2,
1386         &omap44xx_l4_per__dss_dsi2,
1387 };
1388
1389 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1390         .name           = "dss_dsi2",
1391         .class          = &omap44xx_dsi_hwmod_class,
1392         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1393         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
1394         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1395         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
1396         .main_clk       = "dss_fck",
1397         .prcm = {
1398                 .omap4 = {
1399                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1400                 },
1401         },
1402         .slaves         = omap44xx_dss_dsi2_slaves,
1403         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1404         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1405 };
1406
1407 /*
1408  * 'hdmi' class
1409  * hdmi controller
1410  */
1411
1412 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1413         .rev_offs       = 0x0000,
1414         .sysc_offs      = 0x0010,
1415         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1416                            SYSC_HAS_SOFTRESET),
1417         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1418                            SIDLE_SMART_WKUP),
1419         .sysc_fields    = &omap_hwmod_sysc_type2,
1420 };
1421
1422 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1423         .name   = "hdmi",
1424         .sysc   = &omap44xx_hdmi_sysc,
1425 };
1426
1427 /* dss_hdmi */
1428 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1429 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1430         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1431 };
1432
1433 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1434         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1435 };
1436
1437 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1438         {
1439                 .pa_start       = 0x58006000,
1440                 .pa_end         = 0x58006fff,
1441                 .flags          = ADDR_TYPE_RT
1442         },
1443 };
1444
1445 /* l3_main_2 -> dss_hdmi */
1446 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1447         .master         = &omap44xx_l3_main_2_hwmod,
1448         .slave          = &omap44xx_dss_hdmi_hwmod,
1449         .clk            = "l3_div_ck",
1450         .addr           = omap44xx_dss_hdmi_dma_addrs,
1451         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
1452         .user           = OCP_USER_SDMA,
1453 };
1454
1455 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1456         {
1457                 .pa_start       = 0x48046000,
1458                 .pa_end         = 0x48046fff,
1459                 .flags          = ADDR_TYPE_RT
1460         },
1461 };
1462
1463 /* l4_per -> dss_hdmi */
1464 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1465         .master         = &omap44xx_l4_per_hwmod,
1466         .slave          = &omap44xx_dss_hdmi_hwmod,
1467         .clk            = "l4_div_ck",
1468         .addr           = omap44xx_dss_hdmi_addrs,
1469         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
1470         .user           = OCP_USER_MPU,
1471 };
1472
1473 /* dss_hdmi slave ports */
1474 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1475         &omap44xx_l3_main_2__dss_hdmi,
1476         &omap44xx_l4_per__dss_hdmi,
1477 };
1478
1479 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1480         .name           = "dss_hdmi",
1481         .class          = &omap44xx_hdmi_hwmod_class,
1482         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1483         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
1484         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1485         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
1486         .main_clk       = "dss_fck",
1487         .prcm = {
1488                 .omap4 = {
1489                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1490                 },
1491         },
1492         .slaves         = omap44xx_dss_hdmi_slaves,
1493         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1494         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1495 };
1496
1497 /*
1498  * 'rfbi' class
1499  * remote frame buffer interface
1500  */
1501
1502 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1503         .rev_offs       = 0x0000,
1504         .sysc_offs      = 0x0010,
1505         .syss_offs      = 0x0014,
1506         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1507                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1508         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1509         .sysc_fields    = &omap_hwmod_sysc_type1,
1510 };
1511
1512 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1513         .name   = "rfbi",
1514         .sysc   = &omap44xx_rfbi_sysc,
1515 };
1516
1517 /* dss_rfbi */
1518 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1519 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1520         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1521 };
1522
1523 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1524         {
1525                 .pa_start       = 0x58002000,
1526                 .pa_end         = 0x580020ff,
1527                 .flags          = ADDR_TYPE_RT
1528         },
1529 };
1530
1531 /* l3_main_2 -> dss_rfbi */
1532 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1533         .master         = &omap44xx_l3_main_2_hwmod,
1534         .slave          = &omap44xx_dss_rfbi_hwmod,
1535         .clk            = "l3_div_ck",
1536         .addr           = omap44xx_dss_rfbi_dma_addrs,
1537         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
1538         .user           = OCP_USER_SDMA,
1539 };
1540
1541 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1542         {
1543                 .pa_start       = 0x48042000,
1544                 .pa_end         = 0x480420ff,
1545                 .flags          = ADDR_TYPE_RT
1546         },
1547 };
1548
1549 /* l4_per -> dss_rfbi */
1550 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1551         .master         = &omap44xx_l4_per_hwmod,
1552         .slave          = &omap44xx_dss_rfbi_hwmod,
1553         .clk            = "l4_div_ck",
1554         .addr           = omap44xx_dss_rfbi_addrs,
1555         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
1556         .user           = OCP_USER_MPU,
1557 };
1558
1559 /* dss_rfbi slave ports */
1560 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1561         &omap44xx_l3_main_2__dss_rfbi,
1562         &omap44xx_l4_per__dss_rfbi,
1563 };
1564
1565 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1566         .name           = "dss_rfbi",
1567         .class          = &omap44xx_rfbi_hwmod_class,
1568         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1569         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
1570         .main_clk       = "dss_fck",
1571         .prcm = {
1572                 .omap4 = {
1573                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1574                 },
1575         },
1576         .slaves         = omap44xx_dss_rfbi_slaves,
1577         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1578         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1579 };
1580
1581 /*
1582  * 'venc' class
1583  * video encoder
1584  */
1585
1586 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1587         .name   = "venc",
1588 };
1589
1590 /* dss_venc */
1591 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1592 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1593         {
1594                 .pa_start       = 0x58003000,
1595                 .pa_end         = 0x580030ff,
1596                 .flags          = ADDR_TYPE_RT
1597         },
1598 };
1599
1600 /* l3_main_2 -> dss_venc */
1601 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1602         .master         = &omap44xx_l3_main_2_hwmod,
1603         .slave          = &omap44xx_dss_venc_hwmod,
1604         .clk            = "l3_div_ck",
1605         .addr           = omap44xx_dss_venc_dma_addrs,
1606         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
1607         .user           = OCP_USER_SDMA,
1608 };
1609
1610 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1611         {
1612                 .pa_start       = 0x48043000,
1613                 .pa_end         = 0x480430ff,
1614                 .flags          = ADDR_TYPE_RT
1615         },
1616 };
1617
1618 /* l4_per -> dss_venc */
1619 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1620         .master         = &omap44xx_l4_per_hwmod,
1621         .slave          = &omap44xx_dss_venc_hwmod,
1622         .clk            = "l4_div_ck",
1623         .addr           = omap44xx_dss_venc_addrs,
1624         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_addrs),
1625         .user           = OCP_USER_MPU,
1626 };
1627
1628 /* dss_venc slave ports */
1629 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1630         &omap44xx_l3_main_2__dss_venc,
1631         &omap44xx_l4_per__dss_venc,
1632 };
1633
1634 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1635         .name           = "dss_venc",
1636         .class          = &omap44xx_venc_hwmod_class,
1637         .main_clk       = "dss_fck",
1638         .prcm = {
1639                 .omap4 = {
1640                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1641                 },
1642         },
1643         .slaves         = omap44xx_dss_venc_slaves,
1644         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1645         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1646 };
1647
1648 /*
1649  * 'gpio' class
1650  * general purpose io module
1651  */
1652
1653 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1654         .rev_offs       = 0x0000,
1655         .sysc_offs      = 0x0010,
1656         .syss_offs      = 0x0114,
1657         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1658                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1659                            SYSS_HAS_RESET_STATUS),
1660         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1661                            SIDLE_SMART_WKUP),
1662         .sysc_fields    = &omap_hwmod_sysc_type1,
1663 };
1664
1665 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1666         .name   = "gpio",
1667         .sysc   = &omap44xx_gpio_sysc,
1668         .rev    = 2,
1669 };
1670
1671 /* gpio dev_attr */
1672 static struct omap_gpio_dev_attr gpio_dev_attr = {
1673         .bank_width     = 32,
1674         .dbck_flag      = true,
1675 };
1676
1677 /* gpio1 */
1678 static struct omap_hwmod omap44xx_gpio1_hwmod;
1679 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1680         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1681 };
1682
1683 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1684         {
1685                 .pa_start       = 0x4a310000,
1686                 .pa_end         = 0x4a3101ff,
1687                 .flags          = ADDR_TYPE_RT
1688         },
1689 };
1690
1691 /* l4_wkup -> gpio1 */
1692 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1693         .master         = &omap44xx_l4_wkup_hwmod,
1694         .slave          = &omap44xx_gpio1_hwmod,
1695         .clk            = "l4_wkup_clk_mux_ck",
1696         .addr           = omap44xx_gpio1_addrs,
1697         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio1_addrs),
1698         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1699 };
1700
1701 /* gpio1 slave ports */
1702 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1703         &omap44xx_l4_wkup__gpio1,
1704 };
1705
1706 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1707         { .role = "dbclk", .clk = "gpio1_dbclk" },
1708 };
1709
1710 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1711         .name           = "gpio1",
1712         .class          = &omap44xx_gpio_hwmod_class,
1713         .mpu_irqs       = omap44xx_gpio1_irqs,
1714         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio1_irqs),
1715         .main_clk       = "gpio1_ick",
1716         .prcm = {
1717                 .omap4 = {
1718                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1719                 },
1720         },
1721         .opt_clks       = gpio1_opt_clks,
1722         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1723         .dev_attr       = &gpio_dev_attr,
1724         .slaves         = omap44xx_gpio1_slaves,
1725         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1726         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1727 };
1728
1729 /* gpio2 */
1730 static struct omap_hwmod omap44xx_gpio2_hwmod;
1731 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1732         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1733 };
1734
1735 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1736         {
1737                 .pa_start       = 0x48055000,
1738                 .pa_end         = 0x480551ff,
1739                 .flags          = ADDR_TYPE_RT
1740         },
1741 };
1742
1743 /* l4_per -> gpio2 */
1744 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1745         .master         = &omap44xx_l4_per_hwmod,
1746         .slave          = &omap44xx_gpio2_hwmod,
1747         .clk            = "l4_div_ck",
1748         .addr           = omap44xx_gpio2_addrs,
1749         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio2_addrs),
1750         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1751 };
1752
1753 /* gpio2 slave ports */
1754 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1755         &omap44xx_l4_per__gpio2,
1756 };
1757
1758 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1759         { .role = "dbclk", .clk = "gpio2_dbclk" },
1760 };
1761
1762 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1763         .name           = "gpio2",
1764         .class          = &omap44xx_gpio_hwmod_class,
1765         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1766         .mpu_irqs       = omap44xx_gpio2_irqs,
1767         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio2_irqs),
1768         .main_clk       = "gpio2_ick",
1769         .prcm = {
1770                 .omap4 = {
1771                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1772                 },
1773         },
1774         .opt_clks       = gpio2_opt_clks,
1775         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1776         .dev_attr       = &gpio_dev_attr,
1777         .slaves         = omap44xx_gpio2_slaves,
1778         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1779         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1780 };
1781
1782 /* gpio3 */
1783 static struct omap_hwmod omap44xx_gpio3_hwmod;
1784 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1785         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1786 };
1787
1788 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1789         {
1790                 .pa_start       = 0x48057000,
1791                 .pa_end         = 0x480571ff,
1792                 .flags          = ADDR_TYPE_RT
1793         },
1794 };
1795
1796 /* l4_per -> gpio3 */
1797 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1798         .master         = &omap44xx_l4_per_hwmod,
1799         .slave          = &omap44xx_gpio3_hwmod,
1800         .clk            = "l4_div_ck",
1801         .addr           = omap44xx_gpio3_addrs,
1802         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio3_addrs),
1803         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1804 };
1805
1806 /* gpio3 slave ports */
1807 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1808         &omap44xx_l4_per__gpio3,
1809 };
1810
1811 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1812         { .role = "dbclk", .clk = "gpio3_dbclk" },
1813 };
1814
1815 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1816         .name           = "gpio3",
1817         .class          = &omap44xx_gpio_hwmod_class,
1818         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1819         .mpu_irqs       = omap44xx_gpio3_irqs,
1820         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio3_irqs),
1821         .main_clk       = "gpio3_ick",
1822         .prcm = {
1823                 .omap4 = {
1824                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1825                 },
1826         },
1827         .opt_clks       = gpio3_opt_clks,
1828         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1829         .dev_attr       = &gpio_dev_attr,
1830         .slaves         = omap44xx_gpio3_slaves,
1831         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1832         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1833 };
1834
1835 /* gpio4 */
1836 static struct omap_hwmod omap44xx_gpio4_hwmod;
1837 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1838         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1839 };
1840
1841 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1842         {
1843                 .pa_start       = 0x48059000,
1844                 .pa_end         = 0x480591ff,
1845                 .flags          = ADDR_TYPE_RT
1846         },
1847 };
1848
1849 /* l4_per -> gpio4 */
1850 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1851         .master         = &omap44xx_l4_per_hwmod,
1852         .slave          = &omap44xx_gpio4_hwmod,
1853         .clk            = "l4_div_ck",
1854         .addr           = omap44xx_gpio4_addrs,
1855         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio4_addrs),
1856         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1857 };
1858
1859 /* gpio4 slave ports */
1860 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1861         &omap44xx_l4_per__gpio4,
1862 };
1863
1864 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1865         { .role = "dbclk", .clk = "gpio4_dbclk" },
1866 };
1867
1868 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1869         .name           = "gpio4",
1870         .class          = &omap44xx_gpio_hwmod_class,
1871         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1872         .mpu_irqs       = omap44xx_gpio4_irqs,
1873         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio4_irqs),
1874         .main_clk       = "gpio4_ick",
1875         .prcm = {
1876                 .omap4 = {
1877                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1878                 },
1879         },
1880         .opt_clks       = gpio4_opt_clks,
1881         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1882         .dev_attr       = &gpio_dev_attr,
1883         .slaves         = omap44xx_gpio4_slaves,
1884         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
1885         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1886 };
1887
1888 /* gpio5 */
1889 static struct omap_hwmod omap44xx_gpio5_hwmod;
1890 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1891         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1892 };
1893
1894 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1895         {
1896                 .pa_start       = 0x4805b000,
1897                 .pa_end         = 0x4805b1ff,
1898                 .flags          = ADDR_TYPE_RT
1899         },
1900 };
1901
1902 /* l4_per -> gpio5 */
1903 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1904         .master         = &omap44xx_l4_per_hwmod,
1905         .slave          = &omap44xx_gpio5_hwmod,
1906         .clk            = "l4_div_ck",
1907         .addr           = omap44xx_gpio5_addrs,
1908         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio5_addrs),
1909         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1910 };
1911
1912 /* gpio5 slave ports */
1913 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1914         &omap44xx_l4_per__gpio5,
1915 };
1916
1917 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1918         { .role = "dbclk", .clk = "gpio5_dbclk" },
1919 };
1920
1921 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1922         .name           = "gpio5",
1923         .class          = &omap44xx_gpio_hwmod_class,
1924         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1925         .mpu_irqs       = omap44xx_gpio5_irqs,
1926         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio5_irqs),
1927         .main_clk       = "gpio5_ick",
1928         .prcm = {
1929                 .omap4 = {
1930                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1931                 },
1932         },
1933         .opt_clks       = gpio5_opt_clks,
1934         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1935         .dev_attr       = &gpio_dev_attr,
1936         .slaves         = omap44xx_gpio5_slaves,
1937         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
1938         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1939 };
1940
1941 /* gpio6 */
1942 static struct omap_hwmod omap44xx_gpio6_hwmod;
1943 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1944         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1945 };
1946
1947 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1948         {
1949                 .pa_start       = 0x4805d000,
1950                 .pa_end         = 0x4805d1ff,
1951                 .flags          = ADDR_TYPE_RT
1952         },
1953 };
1954
1955 /* l4_per -> gpio6 */
1956 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1957         .master         = &omap44xx_l4_per_hwmod,
1958         .slave          = &omap44xx_gpio6_hwmod,
1959         .clk            = "l4_div_ck",
1960         .addr           = omap44xx_gpio6_addrs,
1961         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio6_addrs),
1962         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1963 };
1964
1965 /* gpio6 slave ports */
1966 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1967         &omap44xx_l4_per__gpio6,
1968 };
1969
1970 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1971         { .role = "dbclk", .clk = "gpio6_dbclk" },
1972 };
1973
1974 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1975         .name           = "gpio6",
1976         .class          = &omap44xx_gpio_hwmod_class,
1977         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1978         .mpu_irqs       = omap44xx_gpio6_irqs,
1979         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio6_irqs),
1980         .main_clk       = "gpio6_ick",
1981         .prcm = {
1982                 .omap4 = {
1983                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1984                 },
1985         },
1986         .opt_clks       = gpio6_opt_clks,
1987         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1988         .dev_attr       = &gpio_dev_attr,
1989         .slaves         = omap44xx_gpio6_slaves,
1990         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
1991         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1992 };
1993
1994 /*
1995  * 'hsi' class
1996  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1997  * serial if)
1998  */
1999
2000 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2001         .rev_offs       = 0x0000,
2002         .sysc_offs      = 0x0010,
2003         .syss_offs      = 0x0014,
2004         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2005                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2006                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2007         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2008                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2009                            MSTANDBY_SMART),
2010         .sysc_fields    = &omap_hwmod_sysc_type1,
2011 };
2012
2013 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2014         .name   = "hsi",
2015         .sysc   = &omap44xx_hsi_sysc,
2016 };
2017
2018 /* hsi */
2019 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2020         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2021         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2022         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2023 };
2024
2025 /* hsi master ports */
2026 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2027         &omap44xx_hsi__l3_main_2,
2028 };
2029
2030 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2031         {
2032                 .pa_start       = 0x4a058000,
2033                 .pa_end         = 0x4a05bfff,
2034                 .flags          = ADDR_TYPE_RT
2035         },
2036 };
2037
2038 /* l4_cfg -> hsi */
2039 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2040         .master         = &omap44xx_l4_cfg_hwmod,
2041         .slave          = &omap44xx_hsi_hwmod,
2042         .clk            = "l4_div_ck",
2043         .addr           = omap44xx_hsi_addrs,
2044         .addr_cnt       = ARRAY_SIZE(omap44xx_hsi_addrs),
2045         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2046 };
2047
2048 /* hsi slave ports */
2049 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2050         &omap44xx_l4_cfg__hsi,
2051 };
2052
2053 static struct omap_hwmod omap44xx_hsi_hwmod = {
2054         .name           = "hsi",
2055         .class          = &omap44xx_hsi_hwmod_class,
2056         .mpu_irqs       = omap44xx_hsi_irqs,
2057         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_hsi_irqs),
2058         .main_clk       = "hsi_fck",
2059         .prcm           = {
2060                 .omap4 = {
2061                         .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2062                 },
2063         },
2064         .slaves         = omap44xx_hsi_slaves,
2065         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2066         .masters        = omap44xx_hsi_masters,
2067         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2068         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2069 };
2070
2071 /*
2072  * 'i2c' class
2073  * multimaster high-speed i2c controller
2074  */
2075
2076 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2077         .sysc_offs      = 0x0010,
2078         .syss_offs      = 0x0090,
2079         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2080                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2081                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2082         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2083                            SIDLE_SMART_WKUP),
2084         .sysc_fields    = &omap_hwmod_sysc_type1,
2085 };
2086
2087 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2088         .name   = "i2c",
2089         .sysc   = &omap44xx_i2c_sysc,
2090 };
2091
2092 /* i2c1 */
2093 static struct omap_hwmod omap44xx_i2c1_hwmod;
2094 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2095         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2096 };
2097
2098 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2099         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2100         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2101 };
2102
2103 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2104         {
2105                 .pa_start       = 0x48070000,
2106                 .pa_end         = 0x480700ff,
2107                 .flags          = ADDR_TYPE_RT
2108         },
2109 };
2110
2111 /* l4_per -> i2c1 */
2112 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2113         .master         = &omap44xx_l4_per_hwmod,
2114         .slave          = &omap44xx_i2c1_hwmod,
2115         .clk            = "l4_div_ck",
2116         .addr           = omap44xx_i2c1_addrs,
2117         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c1_addrs),
2118         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2119 };
2120
2121 /* i2c1 slave ports */
2122 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2123         &omap44xx_l4_per__i2c1,
2124 };
2125
2126 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2127         .name           = "i2c1",
2128         .class          = &omap44xx_i2c_hwmod_class,
2129         .flags          = HWMOD_INIT_NO_RESET,
2130         .mpu_irqs       = omap44xx_i2c1_irqs,
2131         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c1_irqs),
2132         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2133         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
2134         .main_clk       = "i2c1_fck",
2135         .prcm = {
2136                 .omap4 = {
2137                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
2138                 },
2139         },
2140         .slaves         = omap44xx_i2c1_slaves,
2141         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2142         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2143 };
2144
2145 /* i2c2 */
2146 static struct omap_hwmod omap44xx_i2c2_hwmod;
2147 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2148         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2149 };
2150
2151 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2152         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2153         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2154 };
2155
2156 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2157         {
2158                 .pa_start       = 0x48072000,
2159                 .pa_end         = 0x480720ff,
2160                 .flags          = ADDR_TYPE_RT
2161         },
2162 };
2163
2164 /* l4_per -> i2c2 */
2165 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2166         .master         = &omap44xx_l4_per_hwmod,
2167         .slave          = &omap44xx_i2c2_hwmod,
2168         .clk            = "l4_div_ck",
2169         .addr           = omap44xx_i2c2_addrs,
2170         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c2_addrs),
2171         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2172 };
2173
2174 /* i2c2 slave ports */
2175 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2176         &omap44xx_l4_per__i2c2,
2177 };
2178
2179 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2180         .name           = "i2c2",
2181         .class          = &omap44xx_i2c_hwmod_class,
2182         .flags          = HWMOD_INIT_NO_RESET,
2183         .mpu_irqs       = omap44xx_i2c2_irqs,
2184         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c2_irqs),
2185         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2186         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
2187         .main_clk       = "i2c2_fck",
2188         .prcm = {
2189                 .omap4 = {
2190                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
2191                 },
2192         },
2193         .slaves         = omap44xx_i2c2_slaves,
2194         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2195         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2196 };
2197
2198 /* i2c3 */
2199 static struct omap_hwmod omap44xx_i2c3_hwmod;
2200 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2201         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2202 };
2203
2204 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2205         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2206         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2207 };
2208
2209 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2210         {
2211                 .pa_start       = 0x48060000,
2212                 .pa_end         = 0x480600ff,
2213                 .flags          = ADDR_TYPE_RT
2214         },
2215 };
2216
2217 /* l4_per -> i2c3 */
2218 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2219         .master         = &omap44xx_l4_per_hwmod,
2220         .slave          = &omap44xx_i2c3_hwmod,
2221         .clk            = "l4_div_ck",
2222         .addr           = omap44xx_i2c3_addrs,
2223         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c3_addrs),
2224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2225 };
2226
2227 /* i2c3 slave ports */
2228 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2229         &omap44xx_l4_per__i2c3,
2230 };
2231
2232 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2233         .name           = "i2c3",
2234         .class          = &omap44xx_i2c_hwmod_class,
2235         .flags          = HWMOD_INIT_NO_RESET,
2236         .mpu_irqs       = omap44xx_i2c3_irqs,
2237         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c3_irqs),
2238         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2239         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
2240         .main_clk       = "i2c3_fck",
2241         .prcm = {
2242                 .omap4 = {
2243                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
2244                 },
2245         },
2246         .slaves         = omap44xx_i2c3_slaves,
2247         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2248         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2249 };
2250
2251 /* i2c4 */
2252 static struct omap_hwmod omap44xx_i2c4_hwmod;
2253 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2254         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2255 };
2256
2257 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2258         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2259         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2260 };
2261
2262 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2263         {
2264                 .pa_start       = 0x48350000,
2265                 .pa_end         = 0x483500ff,
2266                 .flags          = ADDR_TYPE_RT
2267         },
2268 };
2269
2270 /* l4_per -> i2c4 */
2271 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2272         .master         = &omap44xx_l4_per_hwmod,
2273         .slave          = &omap44xx_i2c4_hwmod,
2274         .clk            = "l4_div_ck",
2275         .addr           = omap44xx_i2c4_addrs,
2276         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c4_addrs),
2277         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2278 };
2279
2280 /* i2c4 slave ports */
2281 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2282         &omap44xx_l4_per__i2c4,
2283 };
2284
2285 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2286         .name           = "i2c4",
2287         .class          = &omap44xx_i2c_hwmod_class,
2288         .flags          = HWMOD_INIT_NO_RESET,
2289         .mpu_irqs       = omap44xx_i2c4_irqs,
2290         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c4_irqs),
2291         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2292         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
2293         .main_clk       = "i2c4_fck",
2294         .prcm = {
2295                 .omap4 = {
2296                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
2297                 },
2298         },
2299         .slaves         = omap44xx_i2c4_slaves,
2300         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2301         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2302 };
2303
2304 /*
2305  * 'ipu' class
2306  * imaging processor unit
2307  */
2308
2309 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2310         .name   = "ipu",
2311 };
2312
2313 /* ipu */
2314 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2315         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2316 };
2317
2318 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2319         { .name = "cpu0", .rst_shift = 0 },
2320 };
2321
2322 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2323         { .name = "cpu1", .rst_shift = 1 },
2324 };
2325
2326 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2327         { .name = "mmu_cache", .rst_shift = 2 },
2328 };
2329
2330 /* ipu master ports */
2331 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2332         &omap44xx_ipu__l3_main_2,
2333 };
2334
2335 /* l3_main_2 -> ipu */
2336 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2337         .master         = &omap44xx_l3_main_2_hwmod,
2338         .slave          = &omap44xx_ipu_hwmod,
2339         .clk            = "l3_div_ck",
2340         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2341 };
2342
2343 /* ipu slave ports */
2344 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2345         &omap44xx_l3_main_2__ipu,
2346 };
2347
2348 /* Pseudo hwmod for reset control purpose only */
2349 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2350         .name           = "ipu_c0",
2351         .class          = &omap44xx_ipu_hwmod_class,
2352         .flags          = HWMOD_INIT_NO_RESET,
2353         .rst_lines      = omap44xx_ipu_c0_resets,
2354         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2355         .prcm           = {
2356                 .omap4 = {
2357                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2358                 },
2359         },
2360         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2361 };
2362
2363 /* Pseudo hwmod for reset control purpose only */
2364 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2365         .name           = "ipu_c1",
2366         .class          = &omap44xx_ipu_hwmod_class,
2367         .flags          = HWMOD_INIT_NO_RESET,
2368         .rst_lines      = omap44xx_ipu_c1_resets,
2369         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2370         .prcm           = {
2371                 .omap4 = {
2372                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2373                 },
2374         },
2375         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2376 };
2377
2378 static struct omap_hwmod omap44xx_ipu_hwmod = {
2379         .name           = "ipu",
2380         .class          = &omap44xx_ipu_hwmod_class,
2381         .mpu_irqs       = omap44xx_ipu_irqs,
2382         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_ipu_irqs),
2383         .rst_lines      = omap44xx_ipu_resets,
2384         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2385         .main_clk       = "ipu_fck",
2386         .prcm           = {
2387                 .omap4 = {
2388                         .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2389                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2390                 },
2391         },
2392         .slaves         = omap44xx_ipu_slaves,
2393         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2394         .masters        = omap44xx_ipu_masters,
2395         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2396         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2397 };
2398
2399 /*
2400  * 'iss' class
2401  * external images sensor pixel data processor
2402  */
2403
2404 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2405         .rev_offs       = 0x0000,
2406         .sysc_offs      = 0x0010,
2407         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2408                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2409         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2410                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2411                            MSTANDBY_SMART),
2412         .sysc_fields    = &omap_hwmod_sysc_type2,
2413 };
2414
2415 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2416         .name   = "iss",
2417         .sysc   = &omap44xx_iss_sysc,
2418 };
2419
2420 /* iss */
2421 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2422         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2423 };
2424
2425 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2426         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2427         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2428         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2429         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2430 };
2431
2432 /* iss master ports */
2433 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2434         &omap44xx_iss__l3_main_2,
2435 };
2436
2437 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2438         {
2439                 .pa_start       = 0x52000000,
2440                 .pa_end         = 0x520000ff,
2441                 .flags          = ADDR_TYPE_RT
2442         },
2443 };
2444
2445 /* l3_main_2 -> iss */
2446 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2447         .master         = &omap44xx_l3_main_2_hwmod,
2448         .slave          = &omap44xx_iss_hwmod,
2449         .clk            = "l3_div_ck",
2450         .addr           = omap44xx_iss_addrs,
2451         .addr_cnt       = ARRAY_SIZE(omap44xx_iss_addrs),
2452         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2453 };
2454
2455 /* iss slave ports */
2456 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2457         &omap44xx_l3_main_2__iss,
2458 };
2459
2460 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2461         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2462 };
2463
2464 static struct omap_hwmod omap44xx_iss_hwmod = {
2465         .name           = "iss",
2466         .class          = &omap44xx_iss_hwmod_class,
2467         .mpu_irqs       = omap44xx_iss_irqs,
2468         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iss_irqs),
2469         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2470         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
2471         .main_clk       = "iss_fck",
2472         .prcm           = {
2473                 .omap4 = {
2474                         .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2475                 },
2476         },
2477         .opt_clks       = iss_opt_clks,
2478         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2479         .slaves         = omap44xx_iss_slaves,
2480         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2481         .masters        = omap44xx_iss_masters,
2482         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2483         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2484 };
2485
2486 /*
2487  * 'iva' class
2488  * multi-standard video encoder/decoder hardware accelerator
2489  */
2490
2491 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2492         .name   = "iva",
2493 };
2494
2495 /* iva */
2496 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2497         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2498         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2499         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2500 };
2501
2502 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2503         { .name = "logic", .rst_shift = 2 },
2504 };
2505
2506 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2507         { .name = "seq0", .rst_shift = 0 },
2508 };
2509
2510 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2511         { .name = "seq1", .rst_shift = 1 },
2512 };
2513
2514 /* iva master ports */
2515 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2516         &omap44xx_iva__l3_main_2,
2517         &omap44xx_iva__l3_instr,
2518 };
2519
2520 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2521         {
2522                 .pa_start       = 0x5a000000,
2523                 .pa_end         = 0x5a07ffff,
2524                 .flags          = ADDR_TYPE_RT
2525         },
2526 };
2527
2528 /* l3_main_2 -> iva */
2529 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2530         .master         = &omap44xx_l3_main_2_hwmod,
2531         .slave          = &omap44xx_iva_hwmod,
2532         .clk            = "l3_div_ck",
2533         .addr           = omap44xx_iva_addrs,
2534         .addr_cnt       = ARRAY_SIZE(omap44xx_iva_addrs),
2535         .user           = OCP_USER_MPU,
2536 };
2537
2538 /* iva slave ports */
2539 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2540         &omap44xx_dsp__iva,
2541         &omap44xx_l3_main_2__iva,
2542 };
2543
2544 /* Pseudo hwmod for reset control purpose only */
2545 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2546         .name           = "iva_seq0",
2547         .class          = &omap44xx_iva_hwmod_class,
2548         .flags          = HWMOD_INIT_NO_RESET,
2549         .rst_lines      = omap44xx_iva_seq0_resets,
2550         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2551         .prcm = {
2552                 .omap4 = {
2553                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2554                 },
2555         },
2556         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2557 };
2558
2559 /* Pseudo hwmod for reset control purpose only */
2560 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2561         .name           = "iva_seq1",
2562         .class          = &omap44xx_iva_hwmod_class,
2563         .flags          = HWMOD_INIT_NO_RESET,
2564         .rst_lines      = omap44xx_iva_seq1_resets,
2565         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2566         .prcm = {
2567                 .omap4 = {
2568                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2569                 },
2570         },
2571         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2572 };
2573
2574 static struct omap_hwmod omap44xx_iva_hwmod = {
2575         .name           = "iva",
2576         .class          = &omap44xx_iva_hwmod_class,
2577         .mpu_irqs       = omap44xx_iva_irqs,
2578         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iva_irqs),
2579         .rst_lines      = omap44xx_iva_resets,
2580         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2581         .main_clk       = "iva_fck",
2582         .prcm = {
2583                 .omap4 = {
2584                         .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2585                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2586                 },
2587         },
2588         .slaves         = omap44xx_iva_slaves,
2589         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2590         .masters        = omap44xx_iva_masters,
2591         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2592         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2593 };
2594
2595 /*
2596  * 'kbd' class
2597  * keyboard controller
2598  */
2599
2600 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2601         .rev_offs       = 0x0000,
2602         .sysc_offs      = 0x0010,
2603         .syss_offs      = 0x0014,
2604         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2605                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2606                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2607                            SYSS_HAS_RESET_STATUS),
2608         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2609         .sysc_fields    = &omap_hwmod_sysc_type1,
2610 };
2611
2612 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2613         .name   = "kbd",
2614         .sysc   = &omap44xx_kbd_sysc,
2615 };
2616
2617 /* kbd */
2618 static struct omap_hwmod omap44xx_kbd_hwmod;
2619 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2620         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2621 };
2622
2623 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2624         {
2625                 .pa_start       = 0x4a31c000,
2626                 .pa_end         = 0x4a31c07f,
2627                 .flags          = ADDR_TYPE_RT
2628         },
2629 };
2630
2631 /* l4_wkup -> kbd */
2632 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2633         .master         = &omap44xx_l4_wkup_hwmod,
2634         .slave          = &omap44xx_kbd_hwmod,
2635         .clk            = "l4_wkup_clk_mux_ck",
2636         .addr           = omap44xx_kbd_addrs,
2637         .addr_cnt       = ARRAY_SIZE(omap44xx_kbd_addrs),
2638         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2639 };
2640
2641 /* kbd slave ports */
2642 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2643         &omap44xx_l4_wkup__kbd,
2644 };
2645
2646 static struct omap_hwmod omap44xx_kbd_hwmod = {
2647         .name           = "kbd",
2648         .class          = &omap44xx_kbd_hwmod_class,
2649         .mpu_irqs       = omap44xx_kbd_irqs,
2650         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_kbd_irqs),
2651         .main_clk       = "kbd_fck",
2652         .prcm           = {
2653                 .omap4 = {
2654                         .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2655                 },
2656         },
2657         .slaves         = omap44xx_kbd_slaves,
2658         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2659         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2660 };
2661
2662 /*
2663  * 'mailbox' class
2664  * mailbox module allowing communication between the on-chip processors using a
2665  * queued mailbox-interrupt mechanism.
2666  */
2667
2668 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2669         .rev_offs       = 0x0000,
2670         .sysc_offs      = 0x0010,
2671         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2672                            SYSC_HAS_SOFTRESET),
2673         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2674         .sysc_fields    = &omap_hwmod_sysc_type2,
2675 };
2676
2677 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2678         .name   = "mailbox",
2679         .sysc   = &omap44xx_mailbox_sysc,
2680 };
2681
2682 /* mailbox */
2683 static struct omap_hwmod omap44xx_mailbox_hwmod;
2684 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2685         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2686 };
2687
2688 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2689         {
2690                 .pa_start       = 0x4a0f4000,
2691                 .pa_end         = 0x4a0f41ff,
2692                 .flags          = ADDR_TYPE_RT
2693         },
2694 };
2695
2696 /* l4_cfg -> mailbox */
2697 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2698         .master         = &omap44xx_l4_cfg_hwmod,
2699         .slave          = &omap44xx_mailbox_hwmod,
2700         .clk            = "l4_div_ck",
2701         .addr           = omap44xx_mailbox_addrs,
2702         .addr_cnt       = ARRAY_SIZE(omap44xx_mailbox_addrs),
2703         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2704 };
2705
2706 /* mailbox slave ports */
2707 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2708         &omap44xx_l4_cfg__mailbox,
2709 };
2710
2711 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2712         .name           = "mailbox",
2713         .class          = &omap44xx_mailbox_hwmod_class,
2714         .mpu_irqs       = omap44xx_mailbox_irqs,
2715         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mailbox_irqs),
2716         .prcm           = {
2717                 .omap4 = {
2718                         .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2719                 },
2720         },
2721         .slaves         = omap44xx_mailbox_slaves,
2722         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2723         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2724 };
2725
2726 /*
2727  * 'mcbsp' class
2728  * multi channel buffered serial port controller
2729  */
2730
2731 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2732         .sysc_offs      = 0x008c,
2733         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2734                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2735         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2736         .sysc_fields    = &omap_hwmod_sysc_type1,
2737 };
2738
2739 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2740         .name   = "mcbsp",
2741         .sysc   = &omap44xx_mcbsp_sysc,
2742         .rev    = MCBSP_CONFIG_TYPE4,
2743 };
2744
2745 /* mcbsp1 */
2746 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2747 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2748         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2749 };
2750
2751 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2752         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2753         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2754 };
2755
2756 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2757         {
2758                 .name           = "mpu",
2759                 .pa_start       = 0x40122000,
2760                 .pa_end         = 0x401220ff,
2761                 .flags          = ADDR_TYPE_RT
2762         },
2763 };
2764
2765 /* l4_abe -> mcbsp1 */
2766 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2767         .master         = &omap44xx_l4_abe_hwmod,
2768         .slave          = &omap44xx_mcbsp1_hwmod,
2769         .clk            = "ocp_abe_iclk",
2770         .addr           = omap44xx_mcbsp1_addrs,
2771         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
2772         .user           = OCP_USER_MPU,
2773 };
2774
2775 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2776         {
2777                 .name           = "dma",
2778                 .pa_start       = 0x49022000,
2779                 .pa_end         = 0x490220ff,
2780                 .flags          = ADDR_TYPE_RT
2781         },
2782 };
2783
2784 /* l4_abe -> mcbsp1 (dma) */
2785 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2786         .master         = &omap44xx_l4_abe_hwmod,
2787         .slave          = &omap44xx_mcbsp1_hwmod,
2788         .clk            = "ocp_abe_iclk",
2789         .addr           = omap44xx_mcbsp1_dma_addrs,
2790         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
2791         .user           = OCP_USER_SDMA,
2792 };
2793
2794 /* mcbsp1 slave ports */
2795 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2796         &omap44xx_l4_abe__mcbsp1,
2797         &omap44xx_l4_abe__mcbsp1_dma,
2798 };
2799
2800 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2801         .name           = "mcbsp1",
2802         .class          = &omap44xx_mcbsp_hwmod_class,
2803         .mpu_irqs       = omap44xx_mcbsp1_irqs,
2804         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
2805         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
2806         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
2807         .main_clk       = "mcbsp1_fck",
2808         .prcm = {
2809                 .omap4 = {
2810                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2811                 },
2812         },
2813         .slaves         = omap44xx_mcbsp1_slaves,
2814         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2815         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2816 };
2817
2818 /* mcbsp2 */
2819 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2820 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2821         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2822 };
2823
2824 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2825         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2826         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2827 };
2828
2829 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2830         {
2831                 .name           = "mpu",
2832                 .pa_start       = 0x40124000,
2833                 .pa_end         = 0x401240ff,
2834                 .flags          = ADDR_TYPE_RT
2835         },
2836 };
2837
2838 /* l4_abe -> mcbsp2 */
2839 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2840         .master         = &omap44xx_l4_abe_hwmod,
2841         .slave          = &omap44xx_mcbsp2_hwmod,
2842         .clk            = "ocp_abe_iclk",
2843         .addr           = omap44xx_mcbsp2_addrs,
2844         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
2845         .user           = OCP_USER_MPU,
2846 };
2847
2848 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2849         {
2850                 .name           = "dma",
2851                 .pa_start       = 0x49024000,
2852                 .pa_end         = 0x490240ff,
2853                 .flags          = ADDR_TYPE_RT
2854         },
2855 };
2856
2857 /* l4_abe -> mcbsp2 (dma) */
2858 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2859         .master         = &omap44xx_l4_abe_hwmod,
2860         .slave          = &omap44xx_mcbsp2_hwmod,
2861         .clk            = "ocp_abe_iclk",
2862         .addr           = omap44xx_mcbsp2_dma_addrs,
2863         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
2864         .user           = OCP_USER_SDMA,
2865 };
2866
2867 /* mcbsp2 slave ports */
2868 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2869         &omap44xx_l4_abe__mcbsp2,
2870         &omap44xx_l4_abe__mcbsp2_dma,
2871 };
2872
2873 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2874         .name           = "mcbsp2",
2875         .class          = &omap44xx_mcbsp_hwmod_class,
2876         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2877         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
2878         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2879         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
2880         .main_clk       = "mcbsp2_fck",
2881         .prcm = {
2882                 .omap4 = {
2883                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2884                 },
2885         },
2886         .slaves         = omap44xx_mcbsp2_slaves,
2887         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
2888         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2889 };
2890
2891 /* mcbsp3 */
2892 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2893 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2894         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2895 };
2896
2897 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2898         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2899         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2900 };
2901
2902 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2903         {
2904                 .name           = "mpu",
2905                 .pa_start       = 0x40126000,
2906                 .pa_end         = 0x401260ff,
2907                 .flags          = ADDR_TYPE_RT
2908         },
2909 };
2910
2911 /* l4_abe -> mcbsp3 */
2912 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2913         .master         = &omap44xx_l4_abe_hwmod,
2914         .slave          = &omap44xx_mcbsp3_hwmod,
2915         .clk            = "ocp_abe_iclk",
2916         .addr           = omap44xx_mcbsp3_addrs,
2917         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
2918         .user           = OCP_USER_MPU,
2919 };
2920
2921 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2922         {
2923                 .name           = "dma",
2924                 .pa_start       = 0x49026000,
2925                 .pa_end         = 0x490260ff,
2926                 .flags          = ADDR_TYPE_RT
2927         },
2928 };
2929
2930 /* l4_abe -> mcbsp3 (dma) */
2931 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
2932         .master         = &omap44xx_l4_abe_hwmod,
2933         .slave          = &omap44xx_mcbsp3_hwmod,
2934         .clk            = "ocp_abe_iclk",
2935         .addr           = omap44xx_mcbsp3_dma_addrs,
2936         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
2937         .user           = OCP_USER_SDMA,
2938 };
2939
2940 /* mcbsp3 slave ports */
2941 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
2942         &omap44xx_l4_abe__mcbsp3,
2943         &omap44xx_l4_abe__mcbsp3_dma,
2944 };
2945
2946 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2947         .name           = "mcbsp3",
2948         .class          = &omap44xx_mcbsp_hwmod_class,
2949         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2950         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
2951         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2952         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
2953         .main_clk       = "mcbsp3_fck",
2954         .prcm = {
2955                 .omap4 = {
2956                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2957                 },
2958         },
2959         .slaves         = omap44xx_mcbsp3_slaves,
2960         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
2961         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2962 };
2963
2964 /* mcbsp4 */
2965 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
2966 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2967         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
2968 };
2969
2970 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2971         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2972         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2973 };
2974
2975 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
2976         {
2977                 .pa_start       = 0x48096000,
2978                 .pa_end         = 0x480960ff,
2979                 .flags          = ADDR_TYPE_RT
2980         },
2981 };
2982
2983 /* l4_per -> mcbsp4 */
2984 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
2985         .master         = &omap44xx_l4_per_hwmod,
2986         .slave          = &omap44xx_mcbsp4_hwmod,
2987         .clk            = "l4_div_ck",
2988         .addr           = omap44xx_mcbsp4_addrs,
2989         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
2990         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2991 };
2992
2993 /* mcbsp4 slave ports */
2994 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
2995         &omap44xx_l4_per__mcbsp4,
2996 };
2997
2998 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2999         .name           = "mcbsp4",
3000         .class          = &omap44xx_mcbsp_hwmod_class,
3001         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3002         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
3003         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3004         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
3005         .main_clk       = "mcbsp4_fck",
3006         .prcm = {
3007                 .omap4 = {
3008                         .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3009                 },
3010         },
3011         .slaves         = omap44xx_mcbsp4_slaves,
3012         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3013         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3014 };
3015
3016 /*
3017  * 'mcpdm' class
3018  * multi channel pdm controller (proprietary interface with phoenix power
3019  * ic)
3020  */
3021
3022 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3023         .rev_offs       = 0x0000,
3024         .sysc_offs      = 0x0010,
3025         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3026                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3027         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3028                            SIDLE_SMART_WKUP),
3029         .sysc_fields    = &omap_hwmod_sysc_type2,
3030 };
3031
3032 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3033         .name   = "mcpdm",
3034         .sysc   = &omap44xx_mcpdm_sysc,
3035 };
3036
3037 /* mcpdm */
3038 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3039 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3040         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3041 };
3042
3043 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3044         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3045         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3046 };
3047
3048 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3049         {
3050                 .pa_start       = 0x40132000,
3051                 .pa_end         = 0x4013207f,
3052                 .flags          = ADDR_TYPE_RT
3053         },
3054 };
3055
3056 /* l4_abe -> mcpdm */
3057 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3058         .master         = &omap44xx_l4_abe_hwmod,
3059         .slave          = &omap44xx_mcpdm_hwmod,
3060         .clk            = "ocp_abe_iclk",
3061         .addr           = omap44xx_mcpdm_addrs,
3062         .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_addrs),
3063         .user           = OCP_USER_MPU,
3064 };
3065
3066 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3067         {
3068                 .pa_start       = 0x49032000,
3069                 .pa_end         = 0x4903207f,
3070                 .flags          = ADDR_TYPE_RT
3071         },
3072 };
3073
3074 /* l4_abe -> mcpdm (dma) */
3075 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3076         .master         = &omap44xx_l4_abe_hwmod,
3077         .slave          = &omap44xx_mcpdm_hwmod,
3078         .clk            = "ocp_abe_iclk",
3079         .addr           = omap44xx_mcpdm_dma_addrs,
3080         .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
3081         .user           = OCP_USER_SDMA,
3082 };
3083
3084 /* mcpdm slave ports */
3085 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3086         &omap44xx_l4_abe__mcpdm,
3087         &omap44xx_l4_abe__mcpdm_dma,
3088 };
3089
3090 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3091         .name           = "mcpdm",
3092         .class          = &omap44xx_mcpdm_hwmod_class,
3093         .mpu_irqs       = omap44xx_mcpdm_irqs,
3094         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcpdm_irqs),
3095         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3096         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
3097         .main_clk       = "mcpdm_fck",
3098         .prcm           = {
3099                 .omap4 = {
3100                         .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3101                 },
3102         },
3103         .slaves         = omap44xx_mcpdm_slaves,
3104         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3105         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3106 };
3107
3108 /*
3109  * 'mcspi' class
3110  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3111  * bus
3112  */
3113
3114 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3115         .rev_offs       = 0x0000,
3116         .sysc_offs      = 0x0010,
3117         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3118                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3119         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3120                            SIDLE_SMART_WKUP),
3121         .sysc_fields    = &omap_hwmod_sysc_type2,
3122 };
3123
3124 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3125         .name   = "mcspi",
3126         .sysc   = &omap44xx_mcspi_sysc,
3127         .rev    = OMAP4_MCSPI_REV,
3128 };
3129
3130 /* mcspi1 */
3131 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3132 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3133         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3134 };
3135
3136 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3137         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3138         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3139         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3140         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3141         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3142         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3143         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3144         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3145 };
3146
3147 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3148         {
3149                 .pa_start       = 0x48098000,
3150                 .pa_end         = 0x480981ff,
3151                 .flags          = ADDR_TYPE_RT
3152         },
3153 };
3154
3155 /* l4_per -> mcspi1 */
3156 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3157         .master         = &omap44xx_l4_per_hwmod,
3158         .slave          = &omap44xx_mcspi1_hwmod,
3159         .clk            = "l4_div_ck",
3160         .addr           = omap44xx_mcspi1_addrs,
3161         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi1_addrs),
3162         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3163 };
3164
3165 /* mcspi1 slave ports */
3166 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3167         &omap44xx_l4_per__mcspi1,
3168 };
3169
3170 /* mcspi1 dev_attr */
3171 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3172         .num_chipselect = 4,
3173 };
3174
3175 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3176         .name           = "mcspi1",
3177         .class          = &omap44xx_mcspi_hwmod_class,
3178         .mpu_irqs       = omap44xx_mcspi1_irqs,
3179         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi1_irqs),
3180         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3181         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
3182         .main_clk       = "mcspi1_fck",
3183         .prcm = {
3184                 .omap4 = {
3185                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3186                 },
3187         },
3188         .dev_attr       = &mcspi1_dev_attr,
3189         .slaves         = omap44xx_mcspi1_slaves,
3190         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3191         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3192 };
3193
3194 /* mcspi2 */
3195 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3196 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3197         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3198 };
3199
3200 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3201         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3202         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3203         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3204         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3205 };
3206
3207 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3208         {
3209                 .pa_start       = 0x4809a000,
3210                 .pa_end         = 0x4809a1ff,
3211                 .flags          = ADDR_TYPE_RT
3212         },
3213 };
3214
3215 /* l4_per -> mcspi2 */
3216 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3217         .master         = &omap44xx_l4_per_hwmod,
3218         .slave          = &omap44xx_mcspi2_hwmod,
3219         .clk            = "l4_div_ck",
3220         .addr           = omap44xx_mcspi2_addrs,
3221         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi2_addrs),
3222         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3223 };
3224
3225 /* mcspi2 slave ports */
3226 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3227         &omap44xx_l4_per__mcspi2,
3228 };
3229
3230 /* mcspi2 dev_attr */
3231 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3232         .num_chipselect = 2,
3233 };
3234
3235 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3236         .name           = "mcspi2",
3237         .class          = &omap44xx_mcspi_hwmod_class,
3238         .mpu_irqs       = omap44xx_mcspi2_irqs,
3239         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi2_irqs),
3240         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3241         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
3242         .main_clk       = "mcspi2_fck",
3243         .prcm = {
3244                 .omap4 = {
3245                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3246                 },
3247         },
3248         .dev_attr       = &mcspi2_dev_attr,
3249         .slaves         = omap44xx_mcspi2_slaves,
3250         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3251         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3252 };
3253
3254 /* mcspi3 */
3255 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3256 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3257         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3258 };
3259
3260 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3261         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3262         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3263         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3264         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3265 };
3266
3267 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3268         {
3269                 .pa_start       = 0x480b8000,
3270                 .pa_end         = 0x480b81ff,
3271                 .flags          = ADDR_TYPE_RT
3272         },
3273 };
3274
3275 /* l4_per -> mcspi3 */
3276 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3277         .master         = &omap44xx_l4_per_hwmod,
3278         .slave          = &omap44xx_mcspi3_hwmod,
3279         .clk            = "l4_div_ck",
3280         .addr           = omap44xx_mcspi3_addrs,
3281         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi3_addrs),
3282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3283 };
3284
3285 /* mcspi3 slave ports */
3286 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3287         &omap44xx_l4_per__mcspi3,
3288 };
3289
3290 /* mcspi3 dev_attr */
3291 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3292         .num_chipselect = 2,
3293 };
3294
3295 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3296         .name           = "mcspi3",
3297         .class          = &omap44xx_mcspi_hwmod_class,
3298         .mpu_irqs       = omap44xx_mcspi3_irqs,
3299         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi3_irqs),
3300         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3301         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
3302         .main_clk       = "mcspi3_fck",
3303         .prcm = {
3304                 .omap4 = {
3305                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3306                 },
3307         },
3308         .dev_attr       = &mcspi3_dev_attr,
3309         .slaves         = omap44xx_mcspi3_slaves,
3310         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3311         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3312 };
3313
3314 /* mcspi4 */
3315 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3316 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3317         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3318 };
3319
3320 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3321         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3322         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3323 };
3324
3325 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3326         {
3327                 .pa_start       = 0x480ba000,
3328                 .pa_end         = 0x480ba1ff,
3329                 .flags          = ADDR_TYPE_RT
3330         },
3331 };
3332
3333 /* l4_per -> mcspi4 */
3334 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3335         .master         = &omap44xx_l4_per_hwmod,
3336         .slave          = &omap44xx_mcspi4_hwmod,
3337         .clk            = "l4_div_ck",
3338         .addr           = omap44xx_mcspi4_addrs,
3339         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi4_addrs),
3340         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3341 };
3342
3343 /* mcspi4 slave ports */
3344 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3345         &omap44xx_l4_per__mcspi4,
3346 };
3347
3348 /* mcspi4 dev_attr */
3349 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3350         .num_chipselect = 1,
3351 };
3352
3353 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3354         .name           = "mcspi4",
3355         .class          = &omap44xx_mcspi_hwmod_class,
3356         .mpu_irqs       = omap44xx_mcspi4_irqs,
3357         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi4_irqs),
3358         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3359         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
3360         .main_clk       = "mcspi4_fck",
3361         .prcm = {
3362                 .omap4 = {
3363                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3364                 },
3365         },
3366         .dev_attr       = &mcspi4_dev_attr,
3367         .slaves         = omap44xx_mcspi4_slaves,
3368         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3369         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3370 };
3371
3372 /*
3373  * 'mmc' class
3374  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3375  */
3376
3377 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3378         .rev_offs       = 0x0000,
3379         .sysc_offs      = 0x0010,
3380         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3381                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3382                            SYSC_HAS_SOFTRESET),
3383         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3384                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3385                            MSTANDBY_SMART),
3386         .sysc_fields    = &omap_hwmod_sysc_type2,
3387 };
3388
3389 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3390         .name   = "mmc",
3391         .sysc   = &omap44xx_mmc_sysc,
3392 };
3393
3394 /* mmc1 */
3395
3396 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3397         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3398 };
3399
3400 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3401         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3402         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3403 };
3404
3405 /* mmc1 master ports */
3406 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3407         &omap44xx_mmc1__l3_main_1,
3408 };
3409
3410 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3411         {
3412                 .pa_start       = 0x4809c000,
3413                 .pa_end         = 0x4809c3ff,
3414                 .flags          = ADDR_TYPE_RT
3415         },
3416 };
3417
3418 /* l4_per -> mmc1 */
3419 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3420         .master         = &omap44xx_l4_per_hwmod,
3421         .slave          = &omap44xx_mmc1_hwmod,
3422         .clk            = "l4_div_ck",
3423         .addr           = omap44xx_mmc1_addrs,
3424         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc1_addrs),
3425         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3426 };
3427
3428 /* mmc1 slave ports */
3429 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3430         &omap44xx_l4_per__mmc1,
3431 };
3432
3433 /* mmc1 dev_attr */
3434 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3435         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3436 };
3437
3438 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3439         .name           = "mmc1",
3440         .class          = &omap44xx_mmc_hwmod_class,
3441         .mpu_irqs       = omap44xx_mmc1_irqs,
3442         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc1_irqs),
3443         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3444         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
3445         .main_clk       = "mmc1_fck",
3446         .prcm           = {
3447                 .omap4 = {
3448                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3449                 },
3450         },
3451         .dev_attr       = &mmc1_dev_attr,
3452         .slaves         = omap44xx_mmc1_slaves,
3453         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3454         .masters        = omap44xx_mmc1_masters,
3455         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3456         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3457 };
3458
3459 /* mmc2 */
3460 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3461         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3462 };
3463
3464 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3465         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3466         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3467 };
3468
3469 /* mmc2 master ports */
3470 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3471         &omap44xx_mmc2__l3_main_1,
3472 };
3473
3474 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3475         {
3476                 .pa_start       = 0x480b4000,
3477                 .pa_end         = 0x480b43ff,
3478                 .flags          = ADDR_TYPE_RT
3479         },
3480 };
3481
3482 /* l4_per -> mmc2 */
3483 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3484         .master         = &omap44xx_l4_per_hwmod,
3485         .slave          = &omap44xx_mmc2_hwmod,
3486         .clk            = "l4_div_ck",
3487         .addr           = omap44xx_mmc2_addrs,
3488         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc2_addrs),
3489         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3490 };
3491
3492 /* mmc2 slave ports */
3493 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3494         &omap44xx_l4_per__mmc2,
3495 };
3496
3497 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3498         .name           = "mmc2",
3499         .class          = &omap44xx_mmc_hwmod_class,
3500         .mpu_irqs       = omap44xx_mmc2_irqs,
3501         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc2_irqs),
3502         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3503         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
3504         .main_clk       = "mmc2_fck",
3505         .prcm           = {
3506                 .omap4 = {
3507                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3508                 },
3509         },
3510         .slaves         = omap44xx_mmc2_slaves,
3511         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3512         .masters        = omap44xx_mmc2_masters,
3513         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3514         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3515 };
3516
3517 /* mmc3 */
3518 static struct omap_hwmod omap44xx_mmc3_hwmod;
3519 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3520         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3521 };
3522
3523 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3524         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3525         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3526 };
3527
3528 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3529         {
3530                 .pa_start       = 0x480ad000,
3531                 .pa_end         = 0x480ad3ff,
3532                 .flags          = ADDR_TYPE_RT
3533         },
3534 };
3535
3536 /* l4_per -> mmc3 */
3537 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3538         .master         = &omap44xx_l4_per_hwmod,
3539         .slave          = &omap44xx_mmc3_hwmod,
3540         .clk            = "l4_div_ck",
3541         .addr           = omap44xx_mmc3_addrs,
3542         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc3_addrs),
3543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3544 };
3545
3546 /* mmc3 slave ports */
3547 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3548         &omap44xx_l4_per__mmc3,
3549 };
3550
3551 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3552         .name           = "mmc3",
3553         .class          = &omap44xx_mmc_hwmod_class,
3554         .mpu_irqs       = omap44xx_mmc3_irqs,
3555         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc3_irqs),
3556         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3557         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
3558         .main_clk       = "mmc3_fck",
3559         .prcm           = {
3560                 .omap4 = {
3561                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3562                 },
3563         },
3564         .slaves         = omap44xx_mmc3_slaves,
3565         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3566         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3567 };
3568
3569 /* mmc4 */
3570 static struct omap_hwmod omap44xx_mmc4_hwmod;
3571 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3572         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3573 };
3574
3575 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3576         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3577         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3578 };
3579
3580 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3581         {
3582                 .pa_start       = 0x480d1000,
3583                 .pa_end         = 0x480d13ff,
3584                 .flags          = ADDR_TYPE_RT
3585         },
3586 };
3587
3588 /* l4_per -> mmc4 */
3589 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3590         .master         = &omap44xx_l4_per_hwmod,
3591         .slave          = &omap44xx_mmc4_hwmod,
3592         .clk            = "l4_div_ck",
3593         .addr           = omap44xx_mmc4_addrs,
3594         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc4_addrs),
3595         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3596 };
3597
3598 /* mmc4 slave ports */
3599 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3600         &omap44xx_l4_per__mmc4,
3601 };
3602
3603 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3604         .name           = "mmc4",
3605         .class          = &omap44xx_mmc_hwmod_class,
3606         .mpu_irqs       = omap44xx_mmc4_irqs,
3607         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc4_irqs),
3608         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3609         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
3610         .main_clk       = "mmc4_fck",
3611         .prcm           = {
3612                 .omap4 = {
3613                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3614                 },
3615         },
3616         .slaves         = omap44xx_mmc4_slaves,
3617         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3618         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3619 };
3620
3621 /* mmc5 */
3622 static struct omap_hwmod omap44xx_mmc5_hwmod;
3623 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3624         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3625 };
3626
3627 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3628         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3629         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3630 };
3631
3632 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3633         {
3634                 .pa_start       = 0x480d5000,
3635                 .pa_end         = 0x480d53ff,
3636                 .flags          = ADDR_TYPE_RT
3637         },
3638 };
3639
3640 /* l4_per -> mmc5 */
3641 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3642         .master         = &omap44xx_l4_per_hwmod,
3643         .slave          = &omap44xx_mmc5_hwmod,
3644         .clk            = "l4_div_ck",
3645         .addr           = omap44xx_mmc5_addrs,
3646         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc5_addrs),
3647         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3648 };
3649
3650 /* mmc5 slave ports */
3651 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3652         &omap44xx_l4_per__mmc5,
3653 };
3654
3655 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3656         .name           = "mmc5",
3657         .class          = &omap44xx_mmc_hwmod_class,
3658         .mpu_irqs       = omap44xx_mmc5_irqs,
3659         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc5_irqs),
3660         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3661         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
3662         .main_clk       = "mmc5_fck",
3663         .prcm           = {
3664                 .omap4 = {
3665                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3666                 },
3667         },
3668         .slaves         = omap44xx_mmc5_slaves,
3669         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3670         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3671 };
3672
3673 /*
3674  * 'mpu' class
3675  * mpu sub-system
3676  */
3677
3678 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3679         .name   = "mpu",
3680 };
3681
3682 /* mpu */
3683 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3684         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3685         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3686         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3687 };
3688
3689 /* mpu master ports */
3690 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3691         &omap44xx_mpu__l3_main_1,
3692         &omap44xx_mpu__l4_abe,
3693         &omap44xx_mpu__dmm,
3694 };
3695
3696 static struct omap_hwmod omap44xx_mpu_hwmod = {
3697         .name           = "mpu",
3698         .class          = &omap44xx_mpu_hwmod_class,
3699         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
3700         .mpu_irqs       = omap44xx_mpu_irqs,
3701         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
3702         .main_clk       = "dpll_mpu_m2_ck",
3703         .prcm = {
3704                 .omap4 = {
3705                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
3706                 },
3707         },
3708         .masters        = omap44xx_mpu_masters,
3709         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3710         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3711 };
3712
3713 /*
3714  * 'smartreflex' class
3715  * smartreflex module (monitor silicon performance and outputs a measure of
3716  * performance error)
3717  */
3718
3719 /* The IP is not compliant to type1 / type2 scheme */
3720 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3721         .sidle_shift    = 24,
3722         .enwkup_shift   = 26,
3723 };
3724
3725 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3726         .sysc_offs      = 0x0038,
3727         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3728         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3729                            SIDLE_SMART_WKUP),
3730         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3731 };
3732
3733 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3734         .name   = "smartreflex",
3735         .sysc   = &omap44xx_smartreflex_sysc,
3736         .rev    = 2,
3737 };
3738
3739 /* smartreflex_core */
3740 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3741 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3742         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3743 };
3744
3745 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3746         {
3747                 .pa_start       = 0x4a0dd000,
3748                 .pa_end         = 0x4a0dd03f,
3749                 .flags          = ADDR_TYPE_RT
3750         },
3751 };
3752
3753 /* l4_cfg -> smartreflex_core */
3754 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3755         .master         = &omap44xx_l4_cfg_hwmod,
3756         .slave          = &omap44xx_smartreflex_core_hwmod,
3757         .clk            = "l4_div_ck",
3758         .addr           = omap44xx_smartreflex_core_addrs,
3759         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
3760         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3761 };
3762
3763 /* smartreflex_core slave ports */
3764 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3765         &omap44xx_l4_cfg__smartreflex_core,
3766 };
3767
3768 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3769         .name           = "smartreflex_core",
3770         .class          = &omap44xx_smartreflex_hwmod_class,
3771         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
3772         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
3773         .main_clk       = "smartreflex_core_fck",
3774         .vdd_name       = "core",
3775         .prcm = {
3776                 .omap4 = {
3777                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3778                 },
3779         },
3780         .slaves         = omap44xx_smartreflex_core_slaves,
3781         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3782         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3783 };
3784
3785 /* smartreflex_iva */
3786 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3787 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3788         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3789 };
3790
3791 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3792         {
3793                 .pa_start       = 0x4a0db000,
3794                 .pa_end         = 0x4a0db03f,
3795                 .flags          = ADDR_TYPE_RT
3796         },
3797 };
3798
3799 /* l4_cfg -> smartreflex_iva */
3800 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3801         .master         = &omap44xx_l4_cfg_hwmod,
3802         .slave          = &omap44xx_smartreflex_iva_hwmod,
3803         .clk            = "l4_div_ck",
3804         .addr           = omap44xx_smartreflex_iva_addrs,
3805         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
3806         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3807 };
3808
3809 /* smartreflex_iva slave ports */
3810 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3811         &omap44xx_l4_cfg__smartreflex_iva,
3812 };
3813
3814 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3815         .name           = "smartreflex_iva",
3816         .class          = &omap44xx_smartreflex_hwmod_class,
3817         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3818         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
3819         .main_clk       = "smartreflex_iva_fck",
3820         .vdd_name       = "iva",
3821         .prcm = {
3822                 .omap4 = {
3823                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3824                 },
3825         },
3826         .slaves         = omap44xx_smartreflex_iva_slaves,
3827         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3828         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3829 };
3830
3831 /* smartreflex_mpu */
3832 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3833 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3834         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3835 };
3836
3837 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3838         {
3839                 .pa_start       = 0x4a0d9000,
3840                 .pa_end         = 0x4a0d903f,
3841                 .flags          = ADDR_TYPE_RT
3842         },
3843 };
3844
3845 /* l4_cfg -> smartreflex_mpu */
3846 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3847         .master         = &omap44xx_l4_cfg_hwmod,
3848         .slave          = &omap44xx_smartreflex_mpu_hwmod,
3849         .clk            = "l4_div_ck",
3850         .addr           = omap44xx_smartreflex_mpu_addrs,
3851         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
3852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3853 };
3854
3855 /* smartreflex_mpu slave ports */
3856 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
3857         &omap44xx_l4_cfg__smartreflex_mpu,
3858 };
3859
3860 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3861         .name           = "smartreflex_mpu",
3862         .class          = &omap44xx_smartreflex_hwmod_class,
3863         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3864         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
3865         .main_clk       = "smartreflex_mpu_fck",
3866         .vdd_name       = "mpu",
3867         .prcm = {
3868                 .omap4 = {
3869                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
3870                 },
3871         },
3872         .slaves         = omap44xx_smartreflex_mpu_slaves,
3873         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
3874         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3875 };
3876
3877 /*
3878  * 'spinlock' class
3879  * spinlock provides hardware assistance for synchronizing the processes
3880  * running on multiple processors
3881  */
3882
3883 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3884         .rev_offs       = 0x0000,
3885         .sysc_offs      = 0x0010,
3886         .syss_offs      = 0x0014,
3887         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3888                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3889                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3890         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3891                            SIDLE_SMART_WKUP),
3892         .sysc_fields    = &omap_hwmod_sysc_type1,
3893 };
3894
3895 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3896         .name   = "spinlock",
3897         .sysc   = &omap44xx_spinlock_sysc,
3898 };
3899
3900 /* spinlock */
3901 static struct omap_hwmod omap44xx_spinlock_hwmod;
3902 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3903         {
3904                 .pa_start       = 0x4a0f6000,
3905                 .pa_end         = 0x4a0f6fff,
3906                 .flags          = ADDR_TYPE_RT
3907         },
3908 };
3909
3910 /* l4_cfg -> spinlock */
3911 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3912         .master         = &omap44xx_l4_cfg_hwmod,
3913         .slave          = &omap44xx_spinlock_hwmod,
3914         .clk            = "l4_div_ck",
3915         .addr           = omap44xx_spinlock_addrs,
3916         .addr_cnt       = ARRAY_SIZE(omap44xx_spinlock_addrs),
3917         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3918 };
3919
3920 /* spinlock slave ports */
3921 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
3922         &omap44xx_l4_cfg__spinlock,
3923 };
3924
3925 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3926         .name           = "spinlock",
3927         .class          = &omap44xx_spinlock_hwmod_class,
3928         .prcm = {
3929                 .omap4 = {
3930                         .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
3931                 },
3932         },
3933         .slaves         = omap44xx_spinlock_slaves,
3934         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
3935         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3936 };
3937
3938 /*
3939  * 'timer' class
3940  * general purpose timer module with accurate 1ms tick
3941  * This class contains several variants: ['timer_1ms', 'timer']
3942  */
3943
3944 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3945         .rev_offs       = 0x0000,
3946         .sysc_offs      = 0x0010,
3947         .syss_offs      = 0x0014,
3948         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3949                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3950                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3951                            SYSS_HAS_RESET_STATUS),
3952         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3953         .sysc_fields    = &omap_hwmod_sysc_type1,
3954 };
3955
3956 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3957         .name   = "timer",
3958         .sysc   = &omap44xx_timer_1ms_sysc,
3959 };
3960
3961 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3962         .rev_offs       = 0x0000,
3963         .sysc_offs      = 0x0010,
3964         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3965                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3966         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3967                            SIDLE_SMART_WKUP),
3968         .sysc_fields    = &omap_hwmod_sysc_type2,
3969 };
3970
3971 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3972         .name   = "timer",
3973         .sysc   = &omap44xx_timer_sysc,
3974 };
3975
3976 /* timer1 */
3977 static struct omap_hwmod omap44xx_timer1_hwmod;
3978 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3979         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3980 };
3981
3982 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
3983         {
3984                 .pa_start       = 0x4a318000,
3985                 .pa_end         = 0x4a31807f,
3986                 .flags          = ADDR_TYPE_RT
3987         },
3988 };
3989
3990 /* l4_wkup -> timer1 */
3991 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
3992         .master         = &omap44xx_l4_wkup_hwmod,
3993         .slave          = &omap44xx_timer1_hwmod,
3994         .clk            = "l4_wkup_clk_mux_ck",
3995         .addr           = omap44xx_timer1_addrs,
3996         .addr_cnt       = ARRAY_SIZE(omap44xx_timer1_addrs),
3997         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3998 };
3999
4000 /* timer1 slave ports */
4001 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4002         &omap44xx_l4_wkup__timer1,
4003 };
4004
4005 static struct omap_hwmod omap44xx_timer1_hwmod = {
4006         .name           = "timer1",
4007         .class          = &omap44xx_timer_1ms_hwmod_class,
4008         .mpu_irqs       = omap44xx_timer1_irqs,
4009         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer1_irqs),
4010         .main_clk       = "timer1_fck",
4011         .prcm = {
4012                 .omap4 = {
4013                         .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
4014                 },
4015         },
4016         .slaves         = omap44xx_timer1_slaves,
4017         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4018         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4019 };
4020
4021 /* timer2 */
4022 static struct omap_hwmod omap44xx_timer2_hwmod;
4023 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4024         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4025 };
4026
4027 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4028         {
4029                 .pa_start       = 0x48032000,
4030                 .pa_end         = 0x4803207f,
4031                 .flags          = ADDR_TYPE_RT
4032         },
4033 };
4034
4035 /* l4_per -> timer2 */
4036 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4037         .master         = &omap44xx_l4_per_hwmod,
4038         .slave          = &omap44xx_timer2_hwmod,
4039         .clk            = "l4_div_ck",
4040         .addr           = omap44xx_timer2_addrs,
4041         .addr_cnt       = ARRAY_SIZE(omap44xx_timer2_addrs),
4042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4043 };
4044
4045 /* timer2 slave ports */
4046 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4047         &omap44xx_l4_per__timer2,
4048 };
4049
4050 static struct omap_hwmod omap44xx_timer2_hwmod = {
4051         .name           = "timer2",
4052         .class          = &omap44xx_timer_1ms_hwmod_class,
4053         .mpu_irqs       = omap44xx_timer2_irqs,
4054         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer2_irqs),
4055         .main_clk       = "timer2_fck",
4056         .prcm = {
4057                 .omap4 = {
4058                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4059                 },
4060         },
4061         .slaves         = omap44xx_timer2_slaves,
4062         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4063         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4064 };
4065
4066 /* timer3 */
4067 static struct omap_hwmod omap44xx_timer3_hwmod;
4068 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4069         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4070 };
4071
4072 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4073         {
4074                 .pa_start       = 0x48034000,
4075                 .pa_end         = 0x4803407f,
4076                 .flags          = ADDR_TYPE_RT
4077         },
4078 };
4079
4080 /* l4_per -> timer3 */
4081 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4082         .master         = &omap44xx_l4_per_hwmod,
4083         .slave          = &omap44xx_timer3_hwmod,
4084         .clk            = "l4_div_ck",
4085         .addr           = omap44xx_timer3_addrs,
4086         .addr_cnt       = ARRAY_SIZE(omap44xx_timer3_addrs),
4087         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4088 };
4089
4090 /* timer3 slave ports */
4091 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4092         &omap44xx_l4_per__timer3,
4093 };
4094
4095 static struct omap_hwmod omap44xx_timer3_hwmod = {
4096         .name           = "timer3",
4097         .class          = &omap44xx_timer_hwmod_class,
4098         .mpu_irqs       = omap44xx_timer3_irqs,
4099         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer3_irqs),
4100         .main_clk       = "timer3_fck",
4101         .prcm = {
4102                 .omap4 = {
4103                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4104                 },
4105         },
4106         .slaves         = omap44xx_timer3_slaves,
4107         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4108         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4109 };
4110
4111 /* timer4 */
4112 static struct omap_hwmod omap44xx_timer4_hwmod;
4113 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4114         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4115 };
4116
4117 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4118         {
4119                 .pa_start       = 0x48036000,
4120                 .pa_end         = 0x4803607f,
4121                 .flags          = ADDR_TYPE_RT
4122         },
4123 };
4124
4125 /* l4_per -> timer4 */
4126 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4127         .master         = &omap44xx_l4_per_hwmod,
4128         .slave          = &omap44xx_timer4_hwmod,
4129         .clk            = "l4_div_ck",
4130         .addr           = omap44xx_timer4_addrs,
4131         .addr_cnt       = ARRAY_SIZE(omap44xx_timer4_addrs),
4132         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4133 };
4134
4135 /* timer4 slave ports */
4136 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4137         &omap44xx_l4_per__timer4,
4138 };
4139
4140 static struct omap_hwmod omap44xx_timer4_hwmod = {
4141         .name           = "timer4",
4142         .class          = &omap44xx_timer_hwmod_class,
4143         .mpu_irqs       = omap44xx_timer4_irqs,
4144         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer4_irqs),
4145         .main_clk       = "timer4_fck",
4146         .prcm = {
4147                 .omap4 = {
4148                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4149                 },
4150         },
4151         .slaves         = omap44xx_timer4_slaves,
4152         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4153         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4154 };
4155
4156 /* timer5 */
4157 static struct omap_hwmod omap44xx_timer5_hwmod;
4158 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4159         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4160 };
4161
4162 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4163         {
4164                 .pa_start       = 0x40138000,
4165                 .pa_end         = 0x4013807f,
4166                 .flags          = ADDR_TYPE_RT
4167         },
4168 };
4169
4170 /* l4_abe -> timer5 */
4171 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4172         .master         = &omap44xx_l4_abe_hwmod,
4173         .slave          = &omap44xx_timer5_hwmod,
4174         .clk            = "ocp_abe_iclk",
4175         .addr           = omap44xx_timer5_addrs,
4176         .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_addrs),
4177         .user           = OCP_USER_MPU,
4178 };
4179
4180 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4181         {
4182                 .pa_start       = 0x49038000,
4183                 .pa_end         = 0x4903807f,
4184                 .flags          = ADDR_TYPE_RT
4185         },
4186 };
4187
4188 /* l4_abe -> timer5 (dma) */
4189 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4190         .master         = &omap44xx_l4_abe_hwmod,
4191         .slave          = &omap44xx_timer5_hwmod,
4192         .clk            = "ocp_abe_iclk",
4193         .addr           = omap44xx_timer5_dma_addrs,
4194         .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
4195         .user           = OCP_USER_SDMA,
4196 };
4197
4198 /* timer5 slave ports */
4199 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4200         &omap44xx_l4_abe__timer5,
4201         &omap44xx_l4_abe__timer5_dma,
4202 };
4203
4204 static struct omap_hwmod omap44xx_timer5_hwmod = {
4205         .name           = "timer5",
4206         .class          = &omap44xx_timer_hwmod_class,
4207         .mpu_irqs       = omap44xx_timer5_irqs,
4208         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer5_irqs),
4209         .main_clk       = "timer5_fck",
4210         .prcm = {
4211                 .omap4 = {
4212                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4213                 },
4214         },
4215         .slaves         = omap44xx_timer5_slaves,
4216         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4217         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4218 };
4219
4220 /* timer6 */
4221 static struct omap_hwmod omap44xx_timer6_hwmod;
4222 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4223         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4224 };
4225
4226 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4227         {
4228                 .pa_start       = 0x4013a000,
4229                 .pa_end         = 0x4013a07f,
4230                 .flags          = ADDR_TYPE_RT
4231         },
4232 };
4233
4234 /* l4_abe -> timer6 */
4235 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4236         .master         = &omap44xx_l4_abe_hwmod,
4237         .slave          = &omap44xx_timer6_hwmod,
4238         .clk            = "ocp_abe_iclk",
4239         .addr           = omap44xx_timer6_addrs,
4240         .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_addrs),
4241         .user           = OCP_USER_MPU,
4242 };
4243
4244 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4245         {
4246                 .pa_start       = 0x4903a000,
4247                 .pa_end         = 0x4903a07f,
4248                 .flags          = ADDR_TYPE_RT
4249         },
4250 };
4251
4252 /* l4_abe -> timer6 (dma) */
4253 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4254         .master         = &omap44xx_l4_abe_hwmod,
4255         .slave          = &omap44xx_timer6_hwmod,
4256         .clk            = "ocp_abe_iclk",
4257         .addr           = omap44xx_timer6_dma_addrs,
4258         .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
4259         .user           = OCP_USER_SDMA,
4260 };
4261
4262 /* timer6 slave ports */
4263 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4264         &omap44xx_l4_abe__timer6,
4265         &omap44xx_l4_abe__timer6_dma,
4266 };
4267
4268 static struct omap_hwmod omap44xx_timer6_hwmod = {
4269         .name           = "timer6",
4270         .class          = &omap44xx_timer_hwmod_class,
4271         .mpu_irqs       = omap44xx_timer6_irqs,
4272         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer6_irqs),
4273         .main_clk       = "timer6_fck",
4274         .prcm = {
4275                 .omap4 = {
4276                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4277                 },
4278         },
4279         .slaves         = omap44xx_timer6_slaves,
4280         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4281         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4282 };
4283
4284 /* timer7 */
4285 static struct omap_hwmod omap44xx_timer7_hwmod;
4286 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4287         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4288 };
4289
4290 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4291         {
4292                 .pa_start       = 0x4013c000,
4293                 .pa_end         = 0x4013c07f,
4294                 .flags          = ADDR_TYPE_RT
4295         },
4296 };
4297
4298 /* l4_abe -> timer7 */
4299 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4300         .master         = &omap44xx_l4_abe_hwmod,
4301         .slave          = &omap44xx_timer7_hwmod,
4302         .clk            = "ocp_abe_iclk",
4303         .addr           = omap44xx_timer7_addrs,
4304         .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_addrs),
4305         .user           = OCP_USER_MPU,
4306 };
4307
4308 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4309         {
4310                 .pa_start       = 0x4903c000,
4311                 .pa_end         = 0x4903c07f,
4312                 .flags          = ADDR_TYPE_RT
4313         },
4314 };
4315
4316 /* l4_abe -> timer7 (dma) */
4317 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4318         .master         = &omap44xx_l4_abe_hwmod,
4319         .slave          = &omap44xx_timer7_hwmod,
4320         .clk            = "ocp_abe_iclk",
4321         .addr           = omap44xx_timer7_dma_addrs,
4322         .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
4323         .user           = OCP_USER_SDMA,
4324 };
4325
4326 /* timer7 slave ports */
4327 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4328         &omap44xx_l4_abe__timer7,
4329         &omap44xx_l4_abe__timer7_dma,
4330 };
4331
4332 static struct omap_hwmod omap44xx_timer7_hwmod = {
4333         .name           = "timer7",
4334         .class          = &omap44xx_timer_hwmod_class,
4335         .mpu_irqs       = omap44xx_timer7_irqs,
4336         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer7_irqs),
4337         .main_clk       = "timer7_fck",
4338         .prcm = {
4339                 .omap4 = {
4340                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4341                 },
4342         },
4343         .slaves         = omap44xx_timer7_slaves,
4344         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4345         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4346 };
4347
4348 /* timer8 */
4349 static struct omap_hwmod omap44xx_timer8_hwmod;
4350 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4351         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4352 };
4353
4354 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4355         {
4356                 .pa_start       = 0x4013e000,
4357                 .pa_end         = 0x4013e07f,
4358                 .flags          = ADDR_TYPE_RT
4359         },
4360 };
4361
4362 /* l4_abe -> timer8 */
4363 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4364         .master         = &omap44xx_l4_abe_hwmod,
4365         .slave          = &omap44xx_timer8_hwmod,
4366         .clk            = "ocp_abe_iclk",
4367         .addr           = omap44xx_timer8_addrs,
4368         .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_addrs),
4369         .user           = OCP_USER_MPU,
4370 };
4371
4372 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4373         {
4374                 .pa_start       = 0x4903e000,
4375                 .pa_end         = 0x4903e07f,
4376                 .flags          = ADDR_TYPE_RT
4377         },
4378 };
4379
4380 /* l4_abe -> timer8 (dma) */
4381 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4382         .master         = &omap44xx_l4_abe_hwmod,
4383         .slave          = &omap44xx_timer8_hwmod,
4384         .clk            = "ocp_abe_iclk",
4385         .addr           = omap44xx_timer8_dma_addrs,
4386         .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
4387         .user           = OCP_USER_SDMA,
4388 };
4389
4390 /* timer8 slave ports */
4391 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4392         &omap44xx_l4_abe__timer8,
4393         &omap44xx_l4_abe__timer8_dma,
4394 };
4395
4396 static struct omap_hwmod omap44xx_timer8_hwmod = {
4397         .name           = "timer8",
4398         .class          = &omap44xx_timer_hwmod_class,
4399         .mpu_irqs       = omap44xx_timer8_irqs,
4400         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer8_irqs),
4401         .main_clk       = "timer8_fck",
4402         .prcm = {
4403                 .omap4 = {
4404                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4405                 },
4406         },
4407         .slaves         = omap44xx_timer8_slaves,
4408         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4409         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4410 };
4411
4412 /* timer9 */
4413 static struct omap_hwmod omap44xx_timer9_hwmod;
4414 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4415         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4416 };
4417
4418 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4419         {
4420                 .pa_start       = 0x4803e000,
4421                 .pa_end         = 0x4803e07f,
4422                 .flags          = ADDR_TYPE_RT
4423         },
4424 };
4425
4426 /* l4_per -> timer9 */
4427 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4428         .master         = &omap44xx_l4_per_hwmod,
4429         .slave          = &omap44xx_timer9_hwmod,
4430         .clk            = "l4_div_ck",
4431         .addr           = omap44xx_timer9_addrs,
4432         .addr_cnt       = ARRAY_SIZE(omap44xx_timer9_addrs),
4433         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4434 };
4435
4436 /* timer9 slave ports */
4437 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4438         &omap44xx_l4_per__timer9,
4439 };
4440
4441 static struct omap_hwmod omap44xx_timer9_hwmod = {
4442         .name           = "timer9",
4443         .class          = &omap44xx_timer_hwmod_class,
4444         .mpu_irqs       = omap44xx_timer9_irqs,
4445         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer9_irqs),
4446         .main_clk       = "timer9_fck",
4447         .prcm = {
4448                 .omap4 = {
4449                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4450                 },
4451         },
4452         .slaves         = omap44xx_timer9_slaves,
4453         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4454         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4455 };
4456
4457 /* timer10 */
4458 static struct omap_hwmod omap44xx_timer10_hwmod;
4459 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4460         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4461 };
4462
4463 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4464         {
4465                 .pa_start       = 0x48086000,
4466                 .pa_end         = 0x4808607f,
4467                 .flags          = ADDR_TYPE_RT
4468         },
4469 };
4470
4471 /* l4_per -> timer10 */
4472 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4473         .master         = &omap44xx_l4_per_hwmod,
4474         .slave          = &omap44xx_timer10_hwmod,
4475         .clk            = "l4_div_ck",
4476         .addr           = omap44xx_timer10_addrs,
4477         .addr_cnt       = ARRAY_SIZE(omap44xx_timer10_addrs),
4478         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4479 };
4480
4481 /* timer10 slave ports */
4482 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4483         &omap44xx_l4_per__timer10,
4484 };
4485
4486 static struct omap_hwmod omap44xx_timer10_hwmod = {
4487         .name           = "timer10",
4488         .class          = &omap44xx_timer_1ms_hwmod_class,
4489         .mpu_irqs       = omap44xx_timer10_irqs,
4490         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer10_irqs),
4491         .main_clk       = "timer10_fck",
4492         .prcm = {
4493                 .omap4 = {
4494                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4495                 },
4496         },
4497         .slaves         = omap44xx_timer10_slaves,
4498         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4499         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4500 };
4501
4502 /* timer11 */
4503 static struct omap_hwmod omap44xx_timer11_hwmod;
4504 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4505         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4506 };
4507
4508 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4509         {
4510                 .pa_start       = 0x48088000,
4511                 .pa_end         = 0x4808807f,
4512                 .flags          = ADDR_TYPE_RT
4513         },
4514 };
4515
4516 /* l4_per -> timer11 */
4517 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4518         .master         = &omap44xx_l4_per_hwmod,
4519         .slave          = &omap44xx_timer11_hwmod,
4520         .clk            = "l4_div_ck",
4521         .addr           = omap44xx_timer11_addrs,
4522         .addr_cnt       = ARRAY_SIZE(omap44xx_timer11_addrs),
4523         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4524 };
4525
4526 /* timer11 slave ports */
4527 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4528         &omap44xx_l4_per__timer11,
4529 };
4530
4531 static struct omap_hwmod omap44xx_timer11_hwmod = {
4532         .name           = "timer11",
4533         .class          = &omap44xx_timer_hwmod_class,
4534         .mpu_irqs       = omap44xx_timer11_irqs,
4535         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer11_irqs),
4536         .main_clk       = "timer11_fck",
4537         .prcm = {
4538                 .omap4 = {
4539                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4540                 },
4541         },
4542         .slaves         = omap44xx_timer11_slaves,
4543         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4544         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4545 };
4546
4547 /*
4548  * 'uart' class
4549  * universal asynchronous receiver/transmitter (uart)
4550  */
4551
4552 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4553         .rev_offs       = 0x0050,
4554         .sysc_offs      = 0x0054,
4555         .syss_offs      = 0x0058,
4556         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4557                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4558                            SYSS_HAS_RESET_STATUS),
4559         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4560                            SIDLE_SMART_WKUP),
4561         .sysc_fields    = &omap_hwmod_sysc_type1,
4562 };
4563
4564 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4565         .name   = "uart",
4566         .sysc   = &omap44xx_uart_sysc,
4567 };
4568
4569 /* uart1 */
4570 static struct omap_hwmod omap44xx_uart1_hwmod;
4571 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4572         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4573 };
4574
4575 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4576         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4577         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4578 };
4579
4580 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4581         {
4582                 .pa_start       = 0x4806a000,
4583                 .pa_end         = 0x4806a0ff,
4584                 .flags          = ADDR_TYPE_RT
4585         },
4586 };
4587
4588 /* l4_per -> uart1 */
4589 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4590         .master         = &omap44xx_l4_per_hwmod,
4591         .slave          = &omap44xx_uart1_hwmod,
4592         .clk            = "l4_div_ck",
4593         .addr           = omap44xx_uart1_addrs,
4594         .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
4595         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4596 };
4597
4598 /* uart1 slave ports */
4599 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4600         &omap44xx_l4_per__uart1,
4601 };
4602
4603 static struct omap_hwmod omap44xx_uart1_hwmod = {
4604         .name           = "uart1",
4605         .class          = &omap44xx_uart_hwmod_class,
4606         .mpu_irqs       = omap44xx_uart1_irqs,
4607         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
4608         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4609         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
4610         .main_clk       = "uart1_fck",
4611         .prcm = {
4612                 .omap4 = {
4613                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
4614                 },
4615         },
4616         .slaves         = omap44xx_uart1_slaves,
4617         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4618         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4619 };
4620
4621 /* uart2 */
4622 static struct omap_hwmod omap44xx_uart2_hwmod;
4623 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4624         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4625 };
4626
4627 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4628         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4629         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4630 };
4631
4632 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4633         {
4634                 .pa_start       = 0x4806c000,
4635                 .pa_end         = 0x4806c0ff,
4636                 .flags          = ADDR_TYPE_RT
4637         },
4638 };
4639
4640 /* l4_per -> uart2 */
4641 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4642         .master         = &omap44xx_l4_per_hwmod,
4643         .slave          = &omap44xx_uart2_hwmod,
4644         .clk            = "l4_div_ck",
4645         .addr           = omap44xx_uart2_addrs,
4646         .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
4647         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4648 };
4649
4650 /* uart2 slave ports */
4651 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4652         &omap44xx_l4_per__uart2,
4653 };
4654
4655 static struct omap_hwmod omap44xx_uart2_hwmod = {
4656         .name           = "uart2",
4657         .class          = &omap44xx_uart_hwmod_class,
4658         .mpu_irqs       = omap44xx_uart2_irqs,
4659         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
4660         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4661         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
4662         .main_clk       = "uart2_fck",
4663         .prcm = {
4664                 .omap4 = {
4665                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
4666                 },
4667         },
4668         .slaves         = omap44xx_uart2_slaves,
4669         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4670         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4671 };
4672
4673 /* uart3 */
4674 static struct omap_hwmod omap44xx_uart3_hwmod;
4675 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4676         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4677 };
4678
4679 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4680         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4681         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4682 };
4683
4684 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4685         {
4686                 .pa_start       = 0x48020000,
4687                 .pa_end         = 0x480200ff,
4688                 .flags          = ADDR_TYPE_RT
4689         },
4690 };
4691
4692 /* l4_per -> uart3 */
4693 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4694         .master         = &omap44xx_l4_per_hwmod,
4695         .slave          = &omap44xx_uart3_hwmod,
4696         .clk            = "l4_div_ck",
4697         .addr           = omap44xx_uart3_addrs,
4698         .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
4699         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4700 };
4701
4702 /* uart3 slave ports */
4703 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4704         &omap44xx_l4_per__uart3,
4705 };
4706
4707 static struct omap_hwmod omap44xx_uart3_hwmod = {
4708         .name           = "uart3",
4709         .class          = &omap44xx_uart_hwmod_class,
4710         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
4711         .mpu_irqs       = omap44xx_uart3_irqs,
4712         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
4713         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
4714         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
4715         .main_clk       = "uart3_fck",
4716         .prcm = {
4717                 .omap4 = {
4718                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
4719                 },
4720         },
4721         .slaves         = omap44xx_uart3_slaves,
4722         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
4723         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4724 };
4725
4726 /* uart4 */
4727 static struct omap_hwmod omap44xx_uart4_hwmod;
4728 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4729         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4730 };
4731
4732 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4733         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4734         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4735 };
4736
4737 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4738         {
4739                 .pa_start       = 0x4806e000,
4740                 .pa_end         = 0x4806e0ff,
4741                 .flags          = ADDR_TYPE_RT
4742         },
4743 };
4744
4745 /* l4_per -> uart4 */
4746 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4747         .master         = &omap44xx_l4_per_hwmod,
4748         .slave          = &omap44xx_uart4_hwmod,
4749         .clk            = "l4_div_ck",
4750         .addr           = omap44xx_uart4_addrs,
4751         .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
4752         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4753 };
4754
4755 /* uart4 slave ports */
4756 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4757         &omap44xx_l4_per__uart4,
4758 };
4759
4760 static struct omap_hwmod omap44xx_uart4_hwmod = {
4761         .name           = "uart4",
4762         .class          = &omap44xx_uart_hwmod_class,
4763         .mpu_irqs       = omap44xx_uart4_irqs,
4764         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
4765         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
4766         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
4767         .main_clk       = "uart4_fck",
4768         .prcm = {
4769                 .omap4 = {
4770                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
4771                 },
4772         },
4773         .slaves         = omap44xx_uart4_slaves,
4774         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
4775         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4776 };
4777
4778 /*
4779  * 'usb_otg_hs' class
4780  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4781  */
4782
4783 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4784         .rev_offs       = 0x0400,
4785         .sysc_offs      = 0x0404,
4786         .syss_offs      = 0x0408,
4787         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4788                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4789                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4790         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4791                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4792                            MSTANDBY_SMART),
4793         .sysc_fields    = &omap_hwmod_sysc_type1,
4794 };
4795
4796 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4797         .name = "usb_otg_hs",
4798         .sysc = &omap44xx_usb_otg_hs_sysc,
4799 };
4800
4801 /* usb_otg_hs */
4802 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4803         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4804         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4805 };
4806
4807 /* usb_otg_hs master ports */
4808 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4809         &omap44xx_usb_otg_hs__l3_main_2,
4810 };
4811
4812 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4813         {
4814                 .pa_start       = 0x4a0ab000,
4815                 .pa_end         = 0x4a0ab003,
4816                 .flags          = ADDR_TYPE_RT
4817         },
4818 };
4819
4820 /* l4_cfg -> usb_otg_hs */
4821 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4822         .master         = &omap44xx_l4_cfg_hwmod,
4823         .slave          = &omap44xx_usb_otg_hs_hwmod,
4824         .clk            = "l4_div_ck",
4825         .addr           = omap44xx_usb_otg_hs_addrs,
4826         .addr_cnt       = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
4827         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4828 };
4829
4830 /* usb_otg_hs slave ports */
4831 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4832         &omap44xx_l4_cfg__usb_otg_hs,
4833 };
4834
4835 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4836         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
4837 };
4838
4839 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4840         .name           = "usb_otg_hs",
4841         .class          = &omap44xx_usb_otg_hs_hwmod_class,
4842         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4843         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
4844         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
4845         .main_clk       = "usb_otg_hs_ick",
4846         .prcm = {
4847                 .omap4 = {
4848                         .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
4849                 },
4850         },
4851         .opt_clks       = usb_otg_hs_opt_clks,
4852         .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
4853         .slaves         = omap44xx_usb_otg_hs_slaves,
4854         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4855         .masters        = omap44xx_usb_otg_hs_masters,
4856         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
4857         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4858 };
4859
4860 /*
4861  * 'wd_timer' class
4862  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
4863  * overflow condition
4864  */
4865
4866 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
4867         .rev_offs       = 0x0000,
4868         .sysc_offs      = 0x0010,
4869         .syss_offs      = 0x0014,
4870         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
4871                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4872         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4873                            SIDLE_SMART_WKUP),
4874         .sysc_fields    = &omap_hwmod_sysc_type1,
4875 };
4876
4877 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4878         .name           = "wd_timer",
4879         .sysc           = &omap44xx_wd_timer_sysc,
4880         .pre_shutdown   = &omap2_wd_timer_disable,
4881 };
4882
4883 /* wd_timer2 */
4884 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4885 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4886         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
4887 };
4888
4889 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
4890         {
4891                 .pa_start       = 0x4a314000,
4892                 .pa_end         = 0x4a31407f,
4893                 .flags          = ADDR_TYPE_RT
4894         },
4895 };
4896
4897 /* l4_wkup -> wd_timer2 */
4898 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4899         .master         = &omap44xx_l4_wkup_hwmod,
4900         .slave          = &omap44xx_wd_timer2_hwmod,
4901         .clk            = "l4_wkup_clk_mux_ck",
4902         .addr           = omap44xx_wd_timer2_addrs,
4903         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
4904         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4905 };
4906
4907 /* wd_timer2 slave ports */
4908 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
4909         &omap44xx_l4_wkup__wd_timer2,
4910 };
4911
4912 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4913         .name           = "wd_timer2",
4914         .class          = &omap44xx_wd_timer_hwmod_class,
4915         .mpu_irqs       = omap44xx_wd_timer2_irqs,
4916         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
4917         .main_clk       = "wd_timer2_fck",
4918         .prcm = {
4919                 .omap4 = {
4920                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
4921                 },
4922         },
4923         .slaves         = omap44xx_wd_timer2_slaves,
4924         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
4925         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4926 };
4927
4928 /* wd_timer3 */
4929 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
4930 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
4931         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
4932 };
4933
4934 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4935         {
4936                 .pa_start       = 0x40130000,
4937                 .pa_end         = 0x4013007f,
4938                 .flags          = ADDR_TYPE_RT
4939         },
4940 };
4941
4942 /* l4_abe -> wd_timer3 */
4943 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4944         .master         = &omap44xx_l4_abe_hwmod,
4945         .slave          = &omap44xx_wd_timer3_hwmod,
4946         .clk            = "ocp_abe_iclk",
4947         .addr           = omap44xx_wd_timer3_addrs,
4948         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
4949         .user           = OCP_USER_MPU,
4950 };
4951
4952 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4953         {
4954                 .pa_start       = 0x49030000,
4955                 .pa_end         = 0x4903007f,
4956                 .flags          = ADDR_TYPE_RT
4957         },
4958 };
4959
4960 /* l4_abe -> wd_timer3 (dma) */
4961 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4962         .master         = &omap44xx_l4_abe_hwmod,
4963         .slave          = &omap44xx_wd_timer3_hwmod,
4964         .clk            = "ocp_abe_iclk",
4965         .addr           = omap44xx_wd_timer3_dma_addrs,
4966         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
4967         .user           = OCP_USER_SDMA,
4968 };
4969
4970 /* wd_timer3 slave ports */
4971 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
4972         &omap44xx_l4_abe__wd_timer3,
4973         &omap44xx_l4_abe__wd_timer3_dma,
4974 };
4975
4976 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
4977         .name           = "wd_timer3",
4978         .class          = &omap44xx_wd_timer_hwmod_class,
4979         .mpu_irqs       = omap44xx_wd_timer3_irqs,
4980         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
4981         .main_clk       = "wd_timer3_fck",
4982         .prcm = {
4983                 .omap4 = {
4984                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
4985                 },
4986         },
4987         .slaves         = omap44xx_wd_timer3_slaves,
4988         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
4989         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4990 };
4991
4992 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
4993
4994         /* dmm class */
4995         &omap44xx_dmm_hwmod,
4996
4997         /* emif_fw class */
4998         &omap44xx_emif_fw_hwmod,
4999
5000         /* l3 class */
5001         &omap44xx_l3_instr_hwmod,
5002         &omap44xx_l3_main_1_hwmod,
5003         &omap44xx_l3_main_2_hwmod,
5004         &omap44xx_l3_main_3_hwmod,
5005
5006         /* l4 class */
5007         &omap44xx_l4_abe_hwmod,
5008         &omap44xx_l4_cfg_hwmod,
5009         &omap44xx_l4_per_hwmod,
5010         &omap44xx_l4_wkup_hwmod,
5011
5012         /* mpu_bus class */
5013         &omap44xx_mpu_private_hwmod,
5014
5015         /* aess class */
5016 /*      &omap44xx_aess_hwmod, */
5017
5018         /* bandgap class */
5019         &omap44xx_bandgap_hwmod,
5020
5021         /* counter class */
5022 /*      &omap44xx_counter_32k_hwmod, */
5023
5024         /* dma class */
5025         &omap44xx_dma_system_hwmod,
5026
5027         /* dmic class */
5028         &omap44xx_dmic_hwmod,
5029
5030         /* dsp class */
5031         &omap44xx_dsp_hwmod,
5032         &omap44xx_dsp_c0_hwmod,
5033
5034         /* dss class */
5035         &omap44xx_dss_hwmod,
5036         &omap44xx_dss_dispc_hwmod,
5037         &omap44xx_dss_dsi1_hwmod,
5038         &omap44xx_dss_dsi2_hwmod,
5039         &omap44xx_dss_hdmi_hwmod,
5040         &omap44xx_dss_rfbi_hwmod,
5041         &omap44xx_dss_venc_hwmod,
5042
5043         /* gpio class */
5044         &omap44xx_gpio1_hwmod,
5045         &omap44xx_gpio2_hwmod,
5046         &omap44xx_gpio3_hwmod,
5047         &omap44xx_gpio4_hwmod,
5048         &omap44xx_gpio5_hwmod,
5049         &omap44xx_gpio6_hwmod,
5050
5051         /* hsi class */
5052 /*      &omap44xx_hsi_hwmod, */
5053
5054         /* i2c class */
5055         &omap44xx_i2c1_hwmod,
5056         &omap44xx_i2c2_hwmod,
5057         &omap44xx_i2c3_hwmod,
5058         &omap44xx_i2c4_hwmod,
5059
5060         /* ipu class */
5061         &omap44xx_ipu_hwmod,
5062         &omap44xx_ipu_c0_hwmod,
5063         &omap44xx_ipu_c1_hwmod,
5064
5065         /* iss class */
5066 /*      &omap44xx_iss_hwmod, */
5067
5068         /* iva class */
5069         &omap44xx_iva_hwmod,
5070         &omap44xx_iva_seq0_hwmod,
5071         &omap44xx_iva_seq1_hwmod,
5072
5073         /* kbd class */
5074 /*      &omap44xx_kbd_hwmod, */
5075
5076         /* mailbox class */
5077         &omap44xx_mailbox_hwmod,
5078
5079         /* mcbsp class */
5080         &omap44xx_mcbsp1_hwmod,
5081         &omap44xx_mcbsp2_hwmod,
5082         &omap44xx_mcbsp3_hwmod,
5083         &omap44xx_mcbsp4_hwmod,
5084
5085         /* mcpdm class */
5086 /*      &omap44xx_mcpdm_hwmod, */
5087
5088         /* mcspi class */
5089         &omap44xx_mcspi1_hwmod,
5090         &omap44xx_mcspi2_hwmod,
5091         &omap44xx_mcspi3_hwmod,
5092         &omap44xx_mcspi4_hwmod,
5093
5094         /* mmc class */
5095         &omap44xx_mmc1_hwmod,
5096         &omap44xx_mmc2_hwmod,
5097         &omap44xx_mmc3_hwmod,
5098         &omap44xx_mmc4_hwmod,
5099         &omap44xx_mmc5_hwmod,
5100
5101         /* mpu class */
5102         &omap44xx_mpu_hwmod,
5103
5104         /* smartreflex class */
5105         &omap44xx_smartreflex_core_hwmod,
5106         &omap44xx_smartreflex_iva_hwmod,
5107         &omap44xx_smartreflex_mpu_hwmod,
5108
5109         /* spinlock class */
5110         &omap44xx_spinlock_hwmod,
5111
5112         /* timer class */
5113         &omap44xx_timer1_hwmod,
5114         &omap44xx_timer2_hwmod,
5115         &omap44xx_timer3_hwmod,
5116         &omap44xx_timer4_hwmod,
5117         &omap44xx_timer5_hwmod,
5118         &omap44xx_timer6_hwmod,
5119         &omap44xx_timer7_hwmod,
5120         &omap44xx_timer8_hwmod,
5121         &omap44xx_timer9_hwmod,
5122         &omap44xx_timer10_hwmod,
5123         &omap44xx_timer11_hwmod,
5124
5125         /* uart class */
5126         &omap44xx_uart1_hwmod,
5127         &omap44xx_uart2_hwmod,
5128         &omap44xx_uart3_hwmod,
5129         &omap44xx_uart4_hwmod,
5130
5131         /* usb_otg_hs class */
5132         &omap44xx_usb_otg_hs_hwmod,
5133
5134         /* wd_timer class */
5135         &omap44xx_wd_timer2_hwmod,
5136         &omap44xx_wd_timer3_hwmod,
5137
5138         NULL,
5139 };
5140
5141 int __init omap44xx_hwmod_init(void)
5142 {
5143         return omap_hwmod_register(omap44xx_hwmods);
5144 }
5145