Linux 3.2-rc2
[pandora-kernel.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
1 /*
2  * Hardware modules present on the OMAP44xx chips
3  *
4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
5  * Copyright (C) 2009-2010 Nokia Corporation
6  *
7  * Paul Walmsley
8  * Benoit Cousson
9  *
10  * This file is automatically generated from the OMAP hardware databases.
11  * We respectfully ask that any modifications to this file be coordinated
12  * with the public linux-omap@vger.kernel.org mailing list and the
13  * authors above to ensure that the autogeneration scripts are kept
14  * up-to-date with the file contents.
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License version 2 as
18  * published by the Free Software Foundation.
19  */
20
21 #include <linux/io.h>
22
23 #include <plat/omap_hwmod.h>
24 #include <plat/cpu.h>
25 #include <plat/i2c.h>
26 #include <plat/gpio.h>
27 #include <plat/dma.h>
28 #include <plat/mcspi.h>
29 #include <plat/mcbsp.h>
30 #include <plat/mmc.h>
31 #include <plat/i2c.h>
32 #include <plat/dmtimer.h>
33
34 #include "omap_hwmod_common_data.h"
35
36 #include "cm1_44xx.h"
37 #include "cm2_44xx.h"
38 #include "prm44xx.h"
39 #include "prm-regbits-44xx.h"
40 #include "wd_timer.h"
41
42 /* Base offset for all OMAP4 interrupts external to MPUSS */
43 #define OMAP44XX_IRQ_GIC_START  32
44
45 /* Base offset for all OMAP4 dma requests */
46 #define OMAP44XX_DMA_REQ_START  1
47
48 /* Backward references (IPs with Bus Master capability) */
49 static struct omap_hwmod omap44xx_aess_hwmod;
50 static struct omap_hwmod omap44xx_dma_system_hwmod;
51 static struct omap_hwmod omap44xx_dmm_hwmod;
52 static struct omap_hwmod omap44xx_dsp_hwmod;
53 static struct omap_hwmod omap44xx_dss_hwmod;
54 static struct omap_hwmod omap44xx_emif_fw_hwmod;
55 static struct omap_hwmod omap44xx_hsi_hwmod;
56 static struct omap_hwmod omap44xx_ipu_hwmod;
57 static struct omap_hwmod omap44xx_iss_hwmod;
58 static struct omap_hwmod omap44xx_iva_hwmod;
59 static struct omap_hwmod omap44xx_l3_instr_hwmod;
60 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
61 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
62 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
63 static struct omap_hwmod omap44xx_l4_abe_hwmod;
64 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
65 static struct omap_hwmod omap44xx_l4_per_hwmod;
66 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
67 static struct omap_hwmod omap44xx_mmc1_hwmod;
68 static struct omap_hwmod omap44xx_mmc2_hwmod;
69 static struct omap_hwmod omap44xx_mpu_hwmod;
70 static struct omap_hwmod omap44xx_mpu_private_hwmod;
71 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
72
73 /*
74  * Interconnects omap_hwmod structures
75  * hwmods that compose the global OMAP interconnect
76  */
77
78 /*
79  * 'dmm' class
80  * instance(s): dmm
81  */
82 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
83         .name   = "dmm",
84 };
85
86 /* dmm */
87 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
88         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
89         { .irq = -1 }
90 };
91
92 /* l3_main_1 -> dmm */
93 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
94         .master         = &omap44xx_l3_main_1_hwmod,
95         .slave          = &omap44xx_dmm_hwmod,
96         .clk            = "l3_div_ck",
97         .user           = OCP_USER_SDMA,
98 };
99
100 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
101         {
102                 .pa_start       = 0x4e000000,
103                 .pa_end         = 0x4e0007ff,
104                 .flags          = ADDR_TYPE_RT
105         },
106         { }
107 };
108
109 /* mpu -> dmm */
110 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
111         .master         = &omap44xx_mpu_hwmod,
112         .slave          = &omap44xx_dmm_hwmod,
113         .clk            = "l3_div_ck",
114         .addr           = omap44xx_dmm_addrs,
115         .user           = OCP_USER_MPU,
116 };
117
118 /* dmm slave ports */
119 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
120         &omap44xx_l3_main_1__dmm,
121         &omap44xx_mpu__dmm,
122 };
123
124 static struct omap_hwmod omap44xx_dmm_hwmod = {
125         .name           = "dmm",
126         .class          = &omap44xx_dmm_hwmod_class,
127         .clkdm_name     = "l3_emif_clkdm",
128         .prcm = {
129                 .omap4 = {
130                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
131                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
132                 },
133         },
134         .slaves         = omap44xx_dmm_slaves,
135         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
136         .mpu_irqs       = omap44xx_dmm_irqs,
137 };
138
139 /*
140  * 'emif_fw' class
141  * instance(s): emif_fw
142  */
143 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
144         .name   = "emif_fw",
145 };
146
147 /* emif_fw */
148 /* dmm -> emif_fw */
149 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
150         .master         = &omap44xx_dmm_hwmod,
151         .slave          = &omap44xx_emif_fw_hwmod,
152         .clk            = "l3_div_ck",
153         .user           = OCP_USER_MPU | OCP_USER_SDMA,
154 };
155
156 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
157         {
158                 .pa_start       = 0x4a20c000,
159                 .pa_end         = 0x4a20c0ff,
160                 .flags          = ADDR_TYPE_RT
161         },
162         { }
163 };
164
165 /* l4_cfg -> emif_fw */
166 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
167         .master         = &omap44xx_l4_cfg_hwmod,
168         .slave          = &omap44xx_emif_fw_hwmod,
169         .clk            = "l4_div_ck",
170         .addr           = omap44xx_emif_fw_addrs,
171         .user           = OCP_USER_MPU,
172 };
173
174 /* emif_fw slave ports */
175 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
176         &omap44xx_dmm__emif_fw,
177         &omap44xx_l4_cfg__emif_fw,
178 };
179
180 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
181         .name           = "emif_fw",
182         .class          = &omap44xx_emif_fw_hwmod_class,
183         .clkdm_name     = "l3_emif_clkdm",
184         .prcm = {
185                 .omap4 = {
186                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
187                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
188                 },
189         },
190         .slaves         = omap44xx_emif_fw_slaves,
191         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
192 };
193
194 /*
195  * 'l3' class
196  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
197  */
198 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
199         .name   = "l3",
200 };
201
202 /* l3_instr */
203 /* iva -> l3_instr */
204 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
205         .master         = &omap44xx_iva_hwmod,
206         .slave          = &omap44xx_l3_instr_hwmod,
207         .clk            = "l3_div_ck",
208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
209 };
210
211 /* l3_main_3 -> l3_instr */
212 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
213         .master         = &omap44xx_l3_main_3_hwmod,
214         .slave          = &omap44xx_l3_instr_hwmod,
215         .clk            = "l3_div_ck",
216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
217 };
218
219 /* l3_instr slave ports */
220 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
221         &omap44xx_iva__l3_instr,
222         &omap44xx_l3_main_3__l3_instr,
223 };
224
225 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
226         .name           = "l3_instr",
227         .class          = &omap44xx_l3_hwmod_class,
228         .clkdm_name     = "l3_instr_clkdm",
229         .prcm = {
230                 .omap4 = {
231                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
232                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
233                         .modulemode   = MODULEMODE_HWCTRL,
234                 },
235         },
236         .slaves         = omap44xx_l3_instr_slaves,
237         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
238 };
239
240 /* l3_main_1 */
241 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
242         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
243         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
244         { .irq = -1 }
245 };
246
247 /* dsp -> l3_main_1 */
248 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
249         .master         = &omap44xx_dsp_hwmod,
250         .slave          = &omap44xx_l3_main_1_hwmod,
251         .clk            = "l3_div_ck",
252         .user           = OCP_USER_MPU | OCP_USER_SDMA,
253 };
254
255 /* dss -> l3_main_1 */
256 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
257         .master         = &omap44xx_dss_hwmod,
258         .slave          = &omap44xx_l3_main_1_hwmod,
259         .clk            = "l3_div_ck",
260         .user           = OCP_USER_MPU | OCP_USER_SDMA,
261 };
262
263 /* l3_main_2 -> l3_main_1 */
264 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
265         .master         = &omap44xx_l3_main_2_hwmod,
266         .slave          = &omap44xx_l3_main_1_hwmod,
267         .clk            = "l3_div_ck",
268         .user           = OCP_USER_MPU | OCP_USER_SDMA,
269 };
270
271 /* l4_cfg -> l3_main_1 */
272 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
273         .master         = &omap44xx_l4_cfg_hwmod,
274         .slave          = &omap44xx_l3_main_1_hwmod,
275         .clk            = "l4_div_ck",
276         .user           = OCP_USER_MPU | OCP_USER_SDMA,
277 };
278
279 /* mmc1 -> l3_main_1 */
280 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
281         .master         = &omap44xx_mmc1_hwmod,
282         .slave          = &omap44xx_l3_main_1_hwmod,
283         .clk            = "l3_div_ck",
284         .user           = OCP_USER_MPU | OCP_USER_SDMA,
285 };
286
287 /* mmc2 -> l3_main_1 */
288 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
289         .master         = &omap44xx_mmc2_hwmod,
290         .slave          = &omap44xx_l3_main_1_hwmod,
291         .clk            = "l3_div_ck",
292         .user           = OCP_USER_MPU | OCP_USER_SDMA,
293 };
294
295 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
296         {
297                 .pa_start       = 0x44000000,
298                 .pa_end         = 0x44000fff,
299                 .flags          = ADDR_TYPE_RT
300         },
301         { }
302 };
303
304 /* mpu -> l3_main_1 */
305 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
306         .master         = &omap44xx_mpu_hwmod,
307         .slave          = &omap44xx_l3_main_1_hwmod,
308         .clk            = "l3_div_ck",
309         .addr           = omap44xx_l3_main_1_addrs,
310         .user           = OCP_USER_MPU,
311 };
312
313 /* l3_main_1 slave ports */
314 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
315         &omap44xx_dsp__l3_main_1,
316         &omap44xx_dss__l3_main_1,
317         &omap44xx_l3_main_2__l3_main_1,
318         &omap44xx_l4_cfg__l3_main_1,
319         &omap44xx_mmc1__l3_main_1,
320         &omap44xx_mmc2__l3_main_1,
321         &omap44xx_mpu__l3_main_1,
322 };
323
324 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
325         .name           = "l3_main_1",
326         .class          = &omap44xx_l3_hwmod_class,
327         .clkdm_name     = "l3_1_clkdm",
328         .mpu_irqs       = omap44xx_l3_main_1_irqs,
329         .prcm = {
330                 .omap4 = {
331                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
332                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
333                 },
334         },
335         .slaves         = omap44xx_l3_main_1_slaves,
336         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
337 };
338
339 /* l3_main_2 */
340 /* dma_system -> l3_main_2 */
341 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
342         .master         = &omap44xx_dma_system_hwmod,
343         .slave          = &omap44xx_l3_main_2_hwmod,
344         .clk            = "l3_div_ck",
345         .user           = OCP_USER_MPU | OCP_USER_SDMA,
346 };
347
348 /* hsi -> l3_main_2 */
349 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
350         .master         = &omap44xx_hsi_hwmod,
351         .slave          = &omap44xx_l3_main_2_hwmod,
352         .clk            = "l3_div_ck",
353         .user           = OCP_USER_MPU | OCP_USER_SDMA,
354 };
355
356 /* ipu -> l3_main_2 */
357 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
358         .master         = &omap44xx_ipu_hwmod,
359         .slave          = &omap44xx_l3_main_2_hwmod,
360         .clk            = "l3_div_ck",
361         .user           = OCP_USER_MPU | OCP_USER_SDMA,
362 };
363
364 /* iss -> l3_main_2 */
365 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
366         .master         = &omap44xx_iss_hwmod,
367         .slave          = &omap44xx_l3_main_2_hwmod,
368         .clk            = "l3_div_ck",
369         .user           = OCP_USER_MPU | OCP_USER_SDMA,
370 };
371
372 /* iva -> l3_main_2 */
373 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
374         .master         = &omap44xx_iva_hwmod,
375         .slave          = &omap44xx_l3_main_2_hwmod,
376         .clk            = "l3_div_ck",
377         .user           = OCP_USER_MPU | OCP_USER_SDMA,
378 };
379
380 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
381         {
382                 .pa_start       = 0x44800000,
383                 .pa_end         = 0x44801fff,
384                 .flags          = ADDR_TYPE_RT
385         },
386         { }
387 };
388
389 /* l3_main_1 -> l3_main_2 */
390 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
391         .master         = &omap44xx_l3_main_1_hwmod,
392         .slave          = &omap44xx_l3_main_2_hwmod,
393         .clk            = "l3_div_ck",
394         .addr           = omap44xx_l3_main_2_addrs,
395         .user           = OCP_USER_MPU,
396 };
397
398 /* l4_cfg -> l3_main_2 */
399 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
400         .master         = &omap44xx_l4_cfg_hwmod,
401         .slave          = &omap44xx_l3_main_2_hwmod,
402         .clk            = "l4_div_ck",
403         .user           = OCP_USER_MPU | OCP_USER_SDMA,
404 };
405
406 /* usb_otg_hs -> l3_main_2 */
407 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
408         .master         = &omap44xx_usb_otg_hs_hwmod,
409         .slave          = &omap44xx_l3_main_2_hwmod,
410         .clk            = "l3_div_ck",
411         .user           = OCP_USER_MPU | OCP_USER_SDMA,
412 };
413
414 /* l3_main_2 slave ports */
415 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
416         &omap44xx_dma_system__l3_main_2,
417         &omap44xx_hsi__l3_main_2,
418         &omap44xx_ipu__l3_main_2,
419         &omap44xx_iss__l3_main_2,
420         &omap44xx_iva__l3_main_2,
421         &omap44xx_l3_main_1__l3_main_2,
422         &omap44xx_l4_cfg__l3_main_2,
423         &omap44xx_usb_otg_hs__l3_main_2,
424 };
425
426 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
427         .name           = "l3_main_2",
428         .class          = &omap44xx_l3_hwmod_class,
429         .clkdm_name     = "l3_2_clkdm",
430         .prcm = {
431                 .omap4 = {
432                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
433                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
434                 },
435         },
436         .slaves         = omap44xx_l3_main_2_slaves,
437         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
438 };
439
440 /* l3_main_3 */
441 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
442         {
443                 .pa_start       = 0x45000000,
444                 .pa_end         = 0x45000fff,
445                 .flags          = ADDR_TYPE_RT
446         },
447         { }
448 };
449
450 /* l3_main_1 -> l3_main_3 */
451 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
452         .master         = &omap44xx_l3_main_1_hwmod,
453         .slave          = &omap44xx_l3_main_3_hwmod,
454         .clk            = "l3_div_ck",
455         .addr           = omap44xx_l3_main_3_addrs,
456         .user           = OCP_USER_MPU,
457 };
458
459 /* l3_main_2 -> l3_main_3 */
460 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
461         .master         = &omap44xx_l3_main_2_hwmod,
462         .slave          = &omap44xx_l3_main_3_hwmod,
463         .clk            = "l3_div_ck",
464         .user           = OCP_USER_MPU | OCP_USER_SDMA,
465 };
466
467 /* l4_cfg -> l3_main_3 */
468 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
469         .master         = &omap44xx_l4_cfg_hwmod,
470         .slave          = &omap44xx_l3_main_3_hwmod,
471         .clk            = "l4_div_ck",
472         .user           = OCP_USER_MPU | OCP_USER_SDMA,
473 };
474
475 /* l3_main_3 slave ports */
476 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
477         &omap44xx_l3_main_1__l3_main_3,
478         &omap44xx_l3_main_2__l3_main_3,
479         &omap44xx_l4_cfg__l3_main_3,
480 };
481
482 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
483         .name           = "l3_main_3",
484         .class          = &omap44xx_l3_hwmod_class,
485         .clkdm_name     = "l3_instr_clkdm",
486         .prcm = {
487                 .omap4 = {
488                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
489                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
490                         .modulemode   = MODULEMODE_HWCTRL,
491                 },
492         },
493         .slaves         = omap44xx_l3_main_3_slaves,
494         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
495 };
496
497 /*
498  * 'l4' class
499  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
500  */
501 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
502         .name   = "l4",
503 };
504
505 /* l4_abe */
506 /* aess -> l4_abe */
507 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
508         .master         = &omap44xx_aess_hwmod,
509         .slave          = &omap44xx_l4_abe_hwmod,
510         .clk            = "ocp_abe_iclk",
511         .user           = OCP_USER_MPU | OCP_USER_SDMA,
512 };
513
514 /* dsp -> l4_abe */
515 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
516         .master         = &omap44xx_dsp_hwmod,
517         .slave          = &omap44xx_l4_abe_hwmod,
518         .clk            = "ocp_abe_iclk",
519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
520 };
521
522 /* l3_main_1 -> l4_abe */
523 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
524         .master         = &omap44xx_l3_main_1_hwmod,
525         .slave          = &omap44xx_l4_abe_hwmod,
526         .clk            = "l3_div_ck",
527         .user           = OCP_USER_MPU | OCP_USER_SDMA,
528 };
529
530 /* mpu -> l4_abe */
531 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
532         .master         = &omap44xx_mpu_hwmod,
533         .slave          = &omap44xx_l4_abe_hwmod,
534         .clk            = "ocp_abe_iclk",
535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
536 };
537
538 /* l4_abe slave ports */
539 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
540         &omap44xx_aess__l4_abe,
541         &omap44xx_dsp__l4_abe,
542         &omap44xx_l3_main_1__l4_abe,
543         &omap44xx_mpu__l4_abe,
544 };
545
546 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
547         .name           = "l4_abe",
548         .class          = &omap44xx_l4_hwmod_class,
549         .clkdm_name     = "abe_clkdm",
550         .prcm = {
551                 .omap4 = {
552                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
553                 },
554         },
555         .slaves         = omap44xx_l4_abe_slaves,
556         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
557 };
558
559 /* l4_cfg */
560 /* l3_main_1 -> l4_cfg */
561 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
562         .master         = &omap44xx_l3_main_1_hwmod,
563         .slave          = &omap44xx_l4_cfg_hwmod,
564         .clk            = "l3_div_ck",
565         .user           = OCP_USER_MPU | OCP_USER_SDMA,
566 };
567
568 /* l4_cfg slave ports */
569 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
570         &omap44xx_l3_main_1__l4_cfg,
571 };
572
573 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
574         .name           = "l4_cfg",
575         .class          = &omap44xx_l4_hwmod_class,
576         .clkdm_name     = "l4_cfg_clkdm",
577         .prcm = {
578                 .omap4 = {
579                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
580                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
581                 },
582         },
583         .slaves         = omap44xx_l4_cfg_slaves,
584         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
585 };
586
587 /* l4_per */
588 /* l3_main_2 -> l4_per */
589 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
590         .master         = &omap44xx_l3_main_2_hwmod,
591         .slave          = &omap44xx_l4_per_hwmod,
592         .clk            = "l3_div_ck",
593         .user           = OCP_USER_MPU | OCP_USER_SDMA,
594 };
595
596 /* l4_per slave ports */
597 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
598         &omap44xx_l3_main_2__l4_per,
599 };
600
601 static struct omap_hwmod omap44xx_l4_per_hwmod = {
602         .name           = "l4_per",
603         .class          = &omap44xx_l4_hwmod_class,
604         .clkdm_name     = "l4_per_clkdm",
605         .prcm = {
606                 .omap4 = {
607                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
608                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
609                 },
610         },
611         .slaves         = omap44xx_l4_per_slaves,
612         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
613 };
614
615 /* l4_wkup */
616 /* l4_cfg -> l4_wkup */
617 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
618         .master         = &omap44xx_l4_cfg_hwmod,
619         .slave          = &omap44xx_l4_wkup_hwmod,
620         .clk            = "l4_div_ck",
621         .user           = OCP_USER_MPU | OCP_USER_SDMA,
622 };
623
624 /* l4_wkup slave ports */
625 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
626         &omap44xx_l4_cfg__l4_wkup,
627 };
628
629 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
630         .name           = "l4_wkup",
631         .class          = &omap44xx_l4_hwmod_class,
632         .clkdm_name     = "l4_wkup_clkdm",
633         .prcm = {
634                 .omap4 = {
635                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
636                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
637                 },
638         },
639         .slaves         = omap44xx_l4_wkup_slaves,
640         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
641 };
642
643 /*
644  * 'mpu_bus' class
645  * instance(s): mpu_private
646  */
647 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
648         .name   = "mpu_bus",
649 };
650
651 /* mpu_private */
652 /* mpu -> mpu_private */
653 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
654         .master         = &omap44xx_mpu_hwmod,
655         .slave          = &omap44xx_mpu_private_hwmod,
656         .clk            = "l3_div_ck",
657         .user           = OCP_USER_MPU | OCP_USER_SDMA,
658 };
659
660 /* mpu_private slave ports */
661 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
662         &omap44xx_mpu__mpu_private,
663 };
664
665 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
666         .name           = "mpu_private",
667         .class          = &omap44xx_mpu_bus_hwmod_class,
668         .clkdm_name     = "mpuss_clkdm",
669         .slaves         = omap44xx_mpu_private_slaves,
670         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
671 };
672
673 /*
674  * Modules omap_hwmod structures
675  *
676  * The following IPs are excluded for the moment because:
677  * - They do not need an explicit SW control using omap_hwmod API.
678  * - They still need to be validated with the driver
679  *   properly adapted to omap_hwmod / omap_device
680  *
681  *  c2c
682  *  c2c_target_fw
683  *  cm_core
684  *  cm_core_aon
685  *  ctrl_module_core
686  *  ctrl_module_pad_core
687  *  ctrl_module_pad_wkup
688  *  ctrl_module_wkup
689  *  debugss
690  *  efuse_ctrl_cust
691  *  efuse_ctrl_std
692  *  elm
693  *  emif1
694  *  emif2
695  *  fdif
696  *  gpmc
697  *  gpu
698  *  hdq1w
699  *  mcasp
700  *  mpu_c0
701  *  mpu_c1
702  *  ocmc_ram
703  *  ocp2scp_usb_phy
704  *  ocp_wp_noc
705  *  prcm_mpu
706  *  prm
707  *  scrm
708  *  sl2if
709  *  slimbus1
710  *  slimbus2
711  *  usb_host_fs
712  *  usb_host_hs
713  *  usb_phy_cm
714  *  usb_tll_hs
715  *  usim
716  */
717
718 /*
719  * 'aess' class
720  * audio engine sub system
721  */
722
723 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
724         .rev_offs       = 0x0000,
725         .sysc_offs      = 0x0010,
726         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
727         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
728                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
729                            MSTANDBY_SMART_WKUP),
730         .sysc_fields    = &omap_hwmod_sysc_type2,
731 };
732
733 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
734         .name   = "aess",
735         .sysc   = &omap44xx_aess_sysc,
736 };
737
738 /* aess */
739 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
740         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
741         { .irq = -1 }
742 };
743
744 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
745         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
746         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
747         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
748         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
749         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
750         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
751         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
752         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
753         { .dma_req = -1 }
754 };
755
756 /* aess master ports */
757 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
758         &omap44xx_aess__l4_abe,
759 };
760
761 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
762         {
763                 .pa_start       = 0x401f1000,
764                 .pa_end         = 0x401f13ff,
765                 .flags          = ADDR_TYPE_RT
766         },
767         { }
768 };
769
770 /* l4_abe -> aess */
771 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
772         .master         = &omap44xx_l4_abe_hwmod,
773         .slave          = &omap44xx_aess_hwmod,
774         .clk            = "ocp_abe_iclk",
775         .addr           = omap44xx_aess_addrs,
776         .user           = OCP_USER_MPU,
777 };
778
779 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
780         {
781                 .pa_start       = 0x490f1000,
782                 .pa_end         = 0x490f13ff,
783                 .flags          = ADDR_TYPE_RT
784         },
785         { }
786 };
787
788 /* l4_abe -> aess (dma) */
789 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
790         .master         = &omap44xx_l4_abe_hwmod,
791         .slave          = &omap44xx_aess_hwmod,
792         .clk            = "ocp_abe_iclk",
793         .addr           = omap44xx_aess_dma_addrs,
794         .user           = OCP_USER_SDMA,
795 };
796
797 /* aess slave ports */
798 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
799         &omap44xx_l4_abe__aess,
800         &omap44xx_l4_abe__aess_dma,
801 };
802
803 static struct omap_hwmod omap44xx_aess_hwmod = {
804         .name           = "aess",
805         .class          = &omap44xx_aess_hwmod_class,
806         .clkdm_name     = "abe_clkdm",
807         .mpu_irqs       = omap44xx_aess_irqs,
808         .sdma_reqs      = omap44xx_aess_sdma_reqs,
809         .main_clk       = "aess_fck",
810         .prcm = {
811                 .omap4 = {
812                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
813                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
814                         .modulemode   = MODULEMODE_SWCTRL,
815                 },
816         },
817         .slaves         = omap44xx_aess_slaves,
818         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
819         .masters        = omap44xx_aess_masters,
820         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
821 };
822
823 /*
824  * 'bandgap' class
825  * bangap reference for ldo regulators
826  */
827
828 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
829         .name   = "bandgap",
830 };
831
832 /* bandgap */
833 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
834         { .role = "fclk", .clk = "bandgap_fclk" },
835 };
836
837 static struct omap_hwmod omap44xx_bandgap_hwmod = {
838         .name           = "bandgap",
839         .class          = &omap44xx_bandgap_hwmod_class,
840         .clkdm_name     = "l4_wkup_clkdm",
841         .prcm = {
842                 .omap4 = {
843                         .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
844                 },
845         },
846         .opt_clks       = bandgap_opt_clks,
847         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
848 };
849
850 /*
851  * 'counter' class
852  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
853  */
854
855 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
856         .rev_offs       = 0x0000,
857         .sysc_offs      = 0x0004,
858         .sysc_flags     = SYSC_HAS_SIDLEMODE,
859         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
860                            SIDLE_SMART_WKUP),
861         .sysc_fields    = &omap_hwmod_sysc_type1,
862 };
863
864 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
865         .name   = "counter",
866         .sysc   = &omap44xx_counter_sysc,
867 };
868
869 /* counter_32k */
870 static struct omap_hwmod omap44xx_counter_32k_hwmod;
871 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
872         {
873                 .pa_start       = 0x4a304000,
874                 .pa_end         = 0x4a30401f,
875                 .flags          = ADDR_TYPE_RT
876         },
877         { }
878 };
879
880 /* l4_wkup -> counter_32k */
881 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
882         .master         = &omap44xx_l4_wkup_hwmod,
883         .slave          = &omap44xx_counter_32k_hwmod,
884         .clk            = "l4_wkup_clk_mux_ck",
885         .addr           = omap44xx_counter_32k_addrs,
886         .user           = OCP_USER_MPU | OCP_USER_SDMA,
887 };
888
889 /* counter_32k slave ports */
890 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
891         &omap44xx_l4_wkup__counter_32k,
892 };
893
894 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
895         .name           = "counter_32k",
896         .class          = &omap44xx_counter_hwmod_class,
897         .clkdm_name     = "l4_wkup_clkdm",
898         .flags          = HWMOD_SWSUP_SIDLE,
899         .main_clk       = "sys_32k_ck",
900         .prcm = {
901                 .omap4 = {
902                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
903                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
904                 },
905         },
906         .slaves         = omap44xx_counter_32k_slaves,
907         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
908 };
909
910 /*
911  * 'dma' class
912  * dma controller for data exchange between memory to memory (i.e. internal or
913  * external memory) and gp peripherals to memory or memory to gp peripherals
914  */
915
916 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
917         .rev_offs       = 0x0000,
918         .sysc_offs      = 0x002c,
919         .syss_offs      = 0x0028,
920         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
921                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
922                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
923                            SYSS_HAS_RESET_STATUS),
924         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
925                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
926         .sysc_fields    = &omap_hwmod_sysc_type1,
927 };
928
929 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
930         .name   = "dma",
931         .sysc   = &omap44xx_dma_sysc,
932 };
933
934 /* dma dev_attr */
935 static struct omap_dma_dev_attr dma_dev_attr = {
936         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
937                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
938         .lch_count      = 32,
939 };
940
941 /* dma_system */
942 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
943         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
944         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
945         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
946         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
947         { .irq = -1 }
948 };
949
950 /* dma_system master ports */
951 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
952         &omap44xx_dma_system__l3_main_2,
953 };
954
955 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
956         {
957                 .pa_start       = 0x4a056000,
958                 .pa_end         = 0x4a056fff,
959                 .flags          = ADDR_TYPE_RT
960         },
961         { }
962 };
963
964 /* l4_cfg -> dma_system */
965 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
966         .master         = &omap44xx_l4_cfg_hwmod,
967         .slave          = &omap44xx_dma_system_hwmod,
968         .clk            = "l4_div_ck",
969         .addr           = omap44xx_dma_system_addrs,
970         .user           = OCP_USER_MPU | OCP_USER_SDMA,
971 };
972
973 /* dma_system slave ports */
974 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
975         &omap44xx_l4_cfg__dma_system,
976 };
977
978 static struct omap_hwmod omap44xx_dma_system_hwmod = {
979         .name           = "dma_system",
980         .class          = &omap44xx_dma_hwmod_class,
981         .clkdm_name     = "l3_dma_clkdm",
982         .mpu_irqs       = omap44xx_dma_system_irqs,
983         .main_clk       = "l3_div_ck",
984         .prcm = {
985                 .omap4 = {
986                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
987                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
988                 },
989         },
990         .dev_attr       = &dma_dev_attr,
991         .slaves         = omap44xx_dma_system_slaves,
992         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
993         .masters        = omap44xx_dma_system_masters,
994         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
995 };
996
997 /*
998  * 'dmic' class
999  * digital microphone controller
1000  */
1001
1002 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1003         .rev_offs       = 0x0000,
1004         .sysc_offs      = 0x0010,
1005         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1006                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1007         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1008                            SIDLE_SMART_WKUP),
1009         .sysc_fields    = &omap_hwmod_sysc_type2,
1010 };
1011
1012 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1013         .name   = "dmic",
1014         .sysc   = &omap44xx_dmic_sysc,
1015 };
1016
1017 /* dmic */
1018 static struct omap_hwmod omap44xx_dmic_hwmod;
1019 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1020         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1021         { .irq = -1 }
1022 };
1023
1024 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1025         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1026         { .dma_req = -1 }
1027 };
1028
1029 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1030         {
1031                 .pa_start       = 0x4012e000,
1032                 .pa_end         = 0x4012e07f,
1033                 .flags          = ADDR_TYPE_RT
1034         },
1035         { }
1036 };
1037
1038 /* l4_abe -> dmic */
1039 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1040         .master         = &omap44xx_l4_abe_hwmod,
1041         .slave          = &omap44xx_dmic_hwmod,
1042         .clk            = "ocp_abe_iclk",
1043         .addr           = omap44xx_dmic_addrs,
1044         .user           = OCP_USER_MPU,
1045 };
1046
1047 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1048         {
1049                 .pa_start       = 0x4902e000,
1050                 .pa_end         = 0x4902e07f,
1051                 .flags          = ADDR_TYPE_RT
1052         },
1053         { }
1054 };
1055
1056 /* l4_abe -> dmic (dma) */
1057 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1058         .master         = &omap44xx_l4_abe_hwmod,
1059         .slave          = &omap44xx_dmic_hwmod,
1060         .clk            = "ocp_abe_iclk",
1061         .addr           = omap44xx_dmic_dma_addrs,
1062         .user           = OCP_USER_SDMA,
1063 };
1064
1065 /* dmic slave ports */
1066 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1067         &omap44xx_l4_abe__dmic,
1068         &omap44xx_l4_abe__dmic_dma,
1069 };
1070
1071 static struct omap_hwmod omap44xx_dmic_hwmod = {
1072         .name           = "dmic",
1073         .class          = &omap44xx_dmic_hwmod_class,
1074         .clkdm_name     = "abe_clkdm",
1075         .mpu_irqs       = omap44xx_dmic_irqs,
1076         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1077         .main_clk       = "dmic_fck",
1078         .prcm = {
1079                 .omap4 = {
1080                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1081                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1082                         .modulemode   = MODULEMODE_SWCTRL,
1083                 },
1084         },
1085         .slaves         = omap44xx_dmic_slaves,
1086         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1087 };
1088
1089 /*
1090  * 'dsp' class
1091  * dsp sub-system
1092  */
1093
1094 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1095         .name   = "dsp",
1096 };
1097
1098 /* dsp */
1099 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1100         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1101         { .irq = -1 }
1102 };
1103
1104 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1105         { .name = "mmu_cache", .rst_shift = 1 },
1106 };
1107
1108 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1109         { .name = "dsp", .rst_shift = 0 },
1110 };
1111
1112 /* dsp -> iva */
1113 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1114         .master         = &omap44xx_dsp_hwmod,
1115         .slave          = &omap44xx_iva_hwmod,
1116         .clk            = "dpll_iva_m5x2_ck",
1117 };
1118
1119 /* dsp master ports */
1120 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1121         &omap44xx_dsp__l3_main_1,
1122         &omap44xx_dsp__l4_abe,
1123         &omap44xx_dsp__iva,
1124 };
1125
1126 /* l4_cfg -> dsp */
1127 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1128         .master         = &omap44xx_l4_cfg_hwmod,
1129         .slave          = &omap44xx_dsp_hwmod,
1130         .clk            = "l4_div_ck",
1131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1132 };
1133
1134 /* dsp slave ports */
1135 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1136         &omap44xx_l4_cfg__dsp,
1137 };
1138
1139 /* Pseudo hwmod for reset control purpose only */
1140 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1141         .name           = "dsp_c0",
1142         .class          = &omap44xx_dsp_hwmod_class,
1143         .clkdm_name     = "tesla_clkdm",
1144         .flags          = HWMOD_INIT_NO_RESET,
1145         .rst_lines      = omap44xx_dsp_c0_resets,
1146         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1147         .prcm = {
1148                 .omap4 = {
1149                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1150                 },
1151         },
1152 };
1153
1154 static struct omap_hwmod omap44xx_dsp_hwmod = {
1155         .name           = "dsp",
1156         .class          = &omap44xx_dsp_hwmod_class,
1157         .clkdm_name     = "tesla_clkdm",
1158         .mpu_irqs       = omap44xx_dsp_irqs,
1159         .rst_lines      = omap44xx_dsp_resets,
1160         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1161         .main_clk       = "dsp_fck",
1162         .prcm = {
1163                 .omap4 = {
1164                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1165                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1166                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1167                         .modulemode   = MODULEMODE_HWCTRL,
1168                 },
1169         },
1170         .slaves         = omap44xx_dsp_slaves,
1171         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1172         .masters        = omap44xx_dsp_masters,
1173         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1174 };
1175
1176 /*
1177  * 'dss' class
1178  * display sub-system
1179  */
1180
1181 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1182         .rev_offs       = 0x0000,
1183         .syss_offs      = 0x0014,
1184         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1185 };
1186
1187 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1188         .name   = "dss",
1189         .sysc   = &omap44xx_dss_sysc,
1190 };
1191
1192 /* dss */
1193 /* dss master ports */
1194 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1195         &omap44xx_dss__l3_main_1,
1196 };
1197
1198 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1199         {
1200                 .pa_start       = 0x58000000,
1201                 .pa_end         = 0x5800007f,
1202                 .flags          = ADDR_TYPE_RT
1203         },
1204         { }
1205 };
1206
1207 /* l3_main_2 -> dss */
1208 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1209         .master         = &omap44xx_l3_main_2_hwmod,
1210         .slave          = &omap44xx_dss_hwmod,
1211         .clk            = "dss_fck",
1212         .addr           = omap44xx_dss_dma_addrs,
1213         .user           = OCP_USER_SDMA,
1214 };
1215
1216 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1217         {
1218                 .pa_start       = 0x48040000,
1219                 .pa_end         = 0x4804007f,
1220                 .flags          = ADDR_TYPE_RT
1221         },
1222         { }
1223 };
1224
1225 /* l4_per -> dss */
1226 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1227         .master         = &omap44xx_l4_per_hwmod,
1228         .slave          = &omap44xx_dss_hwmod,
1229         .clk            = "l4_div_ck",
1230         .addr           = omap44xx_dss_addrs,
1231         .user           = OCP_USER_MPU,
1232 };
1233
1234 /* dss slave ports */
1235 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1236         &omap44xx_l3_main_2__dss,
1237         &omap44xx_l4_per__dss,
1238 };
1239
1240 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1241         { .role = "sys_clk", .clk = "dss_sys_clk" },
1242         { .role = "tv_clk", .clk = "dss_tv_clk" },
1243         { .role = "dss_clk", .clk = "dss_dss_clk" },
1244         { .role = "video_clk", .clk = "dss_48mhz_clk" },
1245 };
1246
1247 static struct omap_hwmod omap44xx_dss_hwmod = {
1248         .name           = "dss_core",
1249         .class          = &omap44xx_dss_hwmod_class,
1250         .clkdm_name     = "l3_dss_clkdm",
1251         .main_clk       = "dss_dss_clk",
1252         .prcm = {
1253                 .omap4 = {
1254                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1255                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1256                 },
1257         },
1258         .opt_clks       = dss_opt_clks,
1259         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1260         .slaves         = omap44xx_dss_slaves,
1261         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1262         .masters        = omap44xx_dss_masters,
1263         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1264 };
1265
1266 /*
1267  * 'dispc' class
1268  * display controller
1269  */
1270
1271 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1272         .rev_offs       = 0x0000,
1273         .sysc_offs      = 0x0010,
1274         .syss_offs      = 0x0014,
1275         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1276                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1277                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1278                            SYSS_HAS_RESET_STATUS),
1279         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1280                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1281         .sysc_fields    = &omap_hwmod_sysc_type1,
1282 };
1283
1284 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1285         .name   = "dispc",
1286         .sysc   = &omap44xx_dispc_sysc,
1287 };
1288
1289 /* dss_dispc */
1290 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1291 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1292         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1293         { .irq = -1 }
1294 };
1295
1296 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1297         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1298         { .dma_req = -1 }
1299 };
1300
1301 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1302         {
1303                 .pa_start       = 0x58001000,
1304                 .pa_end         = 0x58001fff,
1305                 .flags          = ADDR_TYPE_RT
1306         },
1307         { }
1308 };
1309
1310 /* l3_main_2 -> dss_dispc */
1311 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1312         .master         = &omap44xx_l3_main_2_hwmod,
1313         .slave          = &omap44xx_dss_dispc_hwmod,
1314         .clk            = "dss_fck",
1315         .addr           = omap44xx_dss_dispc_dma_addrs,
1316         .user           = OCP_USER_SDMA,
1317 };
1318
1319 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1320         {
1321                 .pa_start       = 0x48041000,
1322                 .pa_end         = 0x48041fff,
1323                 .flags          = ADDR_TYPE_RT
1324         },
1325         { }
1326 };
1327
1328 /* l4_per -> dss_dispc */
1329 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1330         .master         = &omap44xx_l4_per_hwmod,
1331         .slave          = &omap44xx_dss_dispc_hwmod,
1332         .clk            = "l4_div_ck",
1333         .addr           = omap44xx_dss_dispc_addrs,
1334         .user           = OCP_USER_MPU,
1335 };
1336
1337 /* dss_dispc slave ports */
1338 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1339         &omap44xx_l3_main_2__dss_dispc,
1340         &omap44xx_l4_per__dss_dispc,
1341 };
1342
1343 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1344         { .role = "sys_clk", .clk = "dss_sys_clk" },
1345         { .role = "tv_clk", .clk = "dss_tv_clk" },
1346         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1347 };
1348
1349 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1350         .name           = "dss_dispc",
1351         .class          = &omap44xx_dispc_hwmod_class,
1352         .clkdm_name     = "l3_dss_clkdm",
1353         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1354         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1355         .main_clk       = "dss_dss_clk",
1356         .prcm = {
1357                 .omap4 = {
1358                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1359                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1360                 },
1361         },
1362         .opt_clks       = dss_dispc_opt_clks,
1363         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
1364         .slaves         = omap44xx_dss_dispc_slaves,
1365         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1366 };
1367
1368 /*
1369  * 'dsi' class
1370  * display serial interface controller
1371  */
1372
1373 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1374         .rev_offs       = 0x0000,
1375         .sysc_offs      = 0x0010,
1376         .syss_offs      = 0x0014,
1377         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1378                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1379                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1380         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1381         .sysc_fields    = &omap_hwmod_sysc_type1,
1382 };
1383
1384 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1385         .name   = "dsi",
1386         .sysc   = &omap44xx_dsi_sysc,
1387 };
1388
1389 /* dss_dsi1 */
1390 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1391 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1392         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1393         { .irq = -1 }
1394 };
1395
1396 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1397         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1398         { .dma_req = -1 }
1399 };
1400
1401 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1402         {
1403                 .pa_start       = 0x58004000,
1404                 .pa_end         = 0x580041ff,
1405                 .flags          = ADDR_TYPE_RT
1406         },
1407         { }
1408 };
1409
1410 /* l3_main_2 -> dss_dsi1 */
1411 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1412         .master         = &omap44xx_l3_main_2_hwmod,
1413         .slave          = &omap44xx_dss_dsi1_hwmod,
1414         .clk            = "dss_fck",
1415         .addr           = omap44xx_dss_dsi1_dma_addrs,
1416         .user           = OCP_USER_SDMA,
1417 };
1418
1419 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1420         {
1421                 .pa_start       = 0x48044000,
1422                 .pa_end         = 0x480441ff,
1423                 .flags          = ADDR_TYPE_RT
1424         },
1425         { }
1426 };
1427
1428 /* l4_per -> dss_dsi1 */
1429 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1430         .master         = &omap44xx_l4_per_hwmod,
1431         .slave          = &omap44xx_dss_dsi1_hwmod,
1432         .clk            = "l4_div_ck",
1433         .addr           = omap44xx_dss_dsi1_addrs,
1434         .user           = OCP_USER_MPU,
1435 };
1436
1437 /* dss_dsi1 slave ports */
1438 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1439         &omap44xx_l3_main_2__dss_dsi1,
1440         &omap44xx_l4_per__dss_dsi1,
1441 };
1442
1443 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1444         { .role = "sys_clk", .clk = "dss_sys_clk" },
1445 };
1446
1447 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1448         .name           = "dss_dsi1",
1449         .class          = &omap44xx_dsi_hwmod_class,
1450         .clkdm_name     = "l3_dss_clkdm",
1451         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1452         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1453         .main_clk       = "dss_dss_clk",
1454         .prcm = {
1455                 .omap4 = {
1456                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1457                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1458                 },
1459         },
1460         .opt_clks       = dss_dsi1_opt_clks,
1461         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1462         .slaves         = omap44xx_dss_dsi1_slaves,
1463         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1464 };
1465
1466 /* dss_dsi2 */
1467 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1468 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1469         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1470         { .irq = -1 }
1471 };
1472
1473 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1474         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1475         { .dma_req = -1 }
1476 };
1477
1478 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1479         {
1480                 .pa_start       = 0x58005000,
1481                 .pa_end         = 0x580051ff,
1482                 .flags          = ADDR_TYPE_RT
1483         },
1484         { }
1485 };
1486
1487 /* l3_main_2 -> dss_dsi2 */
1488 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1489         .master         = &omap44xx_l3_main_2_hwmod,
1490         .slave          = &omap44xx_dss_dsi2_hwmod,
1491         .clk            = "dss_fck",
1492         .addr           = omap44xx_dss_dsi2_dma_addrs,
1493         .user           = OCP_USER_SDMA,
1494 };
1495
1496 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1497         {
1498                 .pa_start       = 0x48045000,
1499                 .pa_end         = 0x480451ff,
1500                 .flags          = ADDR_TYPE_RT
1501         },
1502         { }
1503 };
1504
1505 /* l4_per -> dss_dsi2 */
1506 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1507         .master         = &omap44xx_l4_per_hwmod,
1508         .slave          = &omap44xx_dss_dsi2_hwmod,
1509         .clk            = "l4_div_ck",
1510         .addr           = omap44xx_dss_dsi2_addrs,
1511         .user           = OCP_USER_MPU,
1512 };
1513
1514 /* dss_dsi2 slave ports */
1515 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1516         &omap44xx_l3_main_2__dss_dsi2,
1517         &omap44xx_l4_per__dss_dsi2,
1518 };
1519
1520 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1521         { .role = "sys_clk", .clk = "dss_sys_clk" },
1522 };
1523
1524 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1525         .name           = "dss_dsi2",
1526         .class          = &omap44xx_dsi_hwmod_class,
1527         .clkdm_name     = "l3_dss_clkdm",
1528         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1529         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1530         .main_clk       = "dss_dss_clk",
1531         .prcm = {
1532                 .omap4 = {
1533                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1534                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1535                 },
1536         },
1537         .opt_clks       = dss_dsi2_opt_clks,
1538         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
1539         .slaves         = omap44xx_dss_dsi2_slaves,
1540         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1541 };
1542
1543 /*
1544  * 'hdmi' class
1545  * hdmi controller
1546  */
1547
1548 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1549         .rev_offs       = 0x0000,
1550         .sysc_offs      = 0x0010,
1551         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1552                            SYSC_HAS_SOFTRESET),
1553         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1554                            SIDLE_SMART_WKUP),
1555         .sysc_fields    = &omap_hwmod_sysc_type2,
1556 };
1557
1558 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1559         .name   = "hdmi",
1560         .sysc   = &omap44xx_hdmi_sysc,
1561 };
1562
1563 /* dss_hdmi */
1564 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1565 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1566         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1567         { .irq = -1 }
1568 };
1569
1570 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1571         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1572         { .dma_req = -1 }
1573 };
1574
1575 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1576         {
1577                 .pa_start       = 0x58006000,
1578                 .pa_end         = 0x58006fff,
1579                 .flags          = ADDR_TYPE_RT
1580         },
1581         { }
1582 };
1583
1584 /* l3_main_2 -> dss_hdmi */
1585 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1586         .master         = &omap44xx_l3_main_2_hwmod,
1587         .slave          = &omap44xx_dss_hdmi_hwmod,
1588         .clk            = "dss_fck",
1589         .addr           = omap44xx_dss_hdmi_dma_addrs,
1590         .user           = OCP_USER_SDMA,
1591 };
1592
1593 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1594         {
1595                 .pa_start       = 0x48046000,
1596                 .pa_end         = 0x48046fff,
1597                 .flags          = ADDR_TYPE_RT
1598         },
1599         { }
1600 };
1601
1602 /* l4_per -> dss_hdmi */
1603 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1604         .master         = &omap44xx_l4_per_hwmod,
1605         .slave          = &omap44xx_dss_hdmi_hwmod,
1606         .clk            = "l4_div_ck",
1607         .addr           = omap44xx_dss_hdmi_addrs,
1608         .user           = OCP_USER_MPU,
1609 };
1610
1611 /* dss_hdmi slave ports */
1612 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1613         &omap44xx_l3_main_2__dss_hdmi,
1614         &omap44xx_l4_per__dss_hdmi,
1615 };
1616
1617 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1618         { .role = "sys_clk", .clk = "dss_sys_clk" },
1619 };
1620
1621 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1622         .name           = "dss_hdmi",
1623         .class          = &omap44xx_hdmi_hwmod_class,
1624         .clkdm_name     = "l3_dss_clkdm",
1625         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1626         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1627         .main_clk       = "dss_dss_clk",
1628         .prcm = {
1629                 .omap4 = {
1630                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1631                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1632                 },
1633         },
1634         .opt_clks       = dss_hdmi_opt_clks,
1635         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
1636         .slaves         = omap44xx_dss_hdmi_slaves,
1637         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1638 };
1639
1640 /*
1641  * 'rfbi' class
1642  * remote frame buffer interface
1643  */
1644
1645 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1646         .rev_offs       = 0x0000,
1647         .sysc_offs      = 0x0010,
1648         .syss_offs      = 0x0014,
1649         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1650                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1651         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1652         .sysc_fields    = &omap_hwmod_sysc_type1,
1653 };
1654
1655 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1656         .name   = "rfbi",
1657         .sysc   = &omap44xx_rfbi_sysc,
1658 };
1659
1660 /* dss_rfbi */
1661 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1662 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1663         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1664         { .dma_req = -1 }
1665 };
1666
1667 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1668         {
1669                 .pa_start       = 0x58002000,
1670                 .pa_end         = 0x580020ff,
1671                 .flags          = ADDR_TYPE_RT
1672         },
1673         { }
1674 };
1675
1676 /* l3_main_2 -> dss_rfbi */
1677 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1678         .master         = &omap44xx_l3_main_2_hwmod,
1679         .slave          = &omap44xx_dss_rfbi_hwmod,
1680         .clk            = "dss_fck",
1681         .addr           = omap44xx_dss_rfbi_dma_addrs,
1682         .user           = OCP_USER_SDMA,
1683 };
1684
1685 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1686         {
1687                 .pa_start       = 0x48042000,
1688                 .pa_end         = 0x480420ff,
1689                 .flags          = ADDR_TYPE_RT
1690         },
1691         { }
1692 };
1693
1694 /* l4_per -> dss_rfbi */
1695 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1696         .master         = &omap44xx_l4_per_hwmod,
1697         .slave          = &omap44xx_dss_rfbi_hwmod,
1698         .clk            = "l4_div_ck",
1699         .addr           = omap44xx_dss_rfbi_addrs,
1700         .user           = OCP_USER_MPU,
1701 };
1702
1703 /* dss_rfbi slave ports */
1704 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1705         &omap44xx_l3_main_2__dss_rfbi,
1706         &omap44xx_l4_per__dss_rfbi,
1707 };
1708
1709 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1710         { .role = "ick", .clk = "dss_fck" },
1711 };
1712
1713 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1714         .name           = "dss_rfbi",
1715         .class          = &omap44xx_rfbi_hwmod_class,
1716         .clkdm_name     = "l3_dss_clkdm",
1717         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1718         .main_clk       = "dss_dss_clk",
1719         .prcm = {
1720                 .omap4 = {
1721                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1722                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1723                 },
1724         },
1725         .opt_clks       = dss_rfbi_opt_clks,
1726         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1727         .slaves         = omap44xx_dss_rfbi_slaves,
1728         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1729 };
1730
1731 /*
1732  * 'venc' class
1733  * video encoder
1734  */
1735
1736 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1737         .name   = "venc",
1738 };
1739
1740 /* dss_venc */
1741 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1742 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1743         {
1744                 .pa_start       = 0x58003000,
1745                 .pa_end         = 0x580030ff,
1746                 .flags          = ADDR_TYPE_RT
1747         },
1748         { }
1749 };
1750
1751 /* l3_main_2 -> dss_venc */
1752 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1753         .master         = &omap44xx_l3_main_2_hwmod,
1754         .slave          = &omap44xx_dss_venc_hwmod,
1755         .clk            = "dss_fck",
1756         .addr           = omap44xx_dss_venc_dma_addrs,
1757         .user           = OCP_USER_SDMA,
1758 };
1759
1760 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1761         {
1762                 .pa_start       = 0x48043000,
1763                 .pa_end         = 0x480430ff,
1764                 .flags          = ADDR_TYPE_RT
1765         },
1766         { }
1767 };
1768
1769 /* l4_per -> dss_venc */
1770 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1771         .master         = &omap44xx_l4_per_hwmod,
1772         .slave          = &omap44xx_dss_venc_hwmod,
1773         .clk            = "l4_div_ck",
1774         .addr           = omap44xx_dss_venc_addrs,
1775         .user           = OCP_USER_MPU,
1776 };
1777
1778 /* dss_venc slave ports */
1779 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1780         &omap44xx_l3_main_2__dss_venc,
1781         &omap44xx_l4_per__dss_venc,
1782 };
1783
1784 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1785         .name           = "dss_venc",
1786         .class          = &omap44xx_venc_hwmod_class,
1787         .clkdm_name     = "l3_dss_clkdm",
1788         .main_clk       = "dss_dss_clk",
1789         .prcm = {
1790                 .omap4 = {
1791                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1792                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1793                 },
1794         },
1795         .slaves         = omap44xx_dss_venc_slaves,
1796         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1797 };
1798
1799 /*
1800  * 'gpio' class
1801  * general purpose io module
1802  */
1803
1804 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1805         .rev_offs       = 0x0000,
1806         .sysc_offs      = 0x0010,
1807         .syss_offs      = 0x0114,
1808         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1809                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1810                            SYSS_HAS_RESET_STATUS),
1811         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1812                            SIDLE_SMART_WKUP),
1813         .sysc_fields    = &omap_hwmod_sysc_type1,
1814 };
1815
1816 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1817         .name   = "gpio",
1818         .sysc   = &omap44xx_gpio_sysc,
1819         .rev    = 2,
1820 };
1821
1822 /* gpio dev_attr */
1823 static struct omap_gpio_dev_attr gpio_dev_attr = {
1824         .bank_width     = 32,
1825         .dbck_flag      = true,
1826 };
1827
1828 /* gpio1 */
1829 static struct omap_hwmod omap44xx_gpio1_hwmod;
1830 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1831         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1832         { .irq = -1 }
1833 };
1834
1835 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1836         {
1837                 .pa_start       = 0x4a310000,
1838                 .pa_end         = 0x4a3101ff,
1839                 .flags          = ADDR_TYPE_RT
1840         },
1841         { }
1842 };
1843
1844 /* l4_wkup -> gpio1 */
1845 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1846         .master         = &omap44xx_l4_wkup_hwmod,
1847         .slave          = &omap44xx_gpio1_hwmod,
1848         .clk            = "l4_wkup_clk_mux_ck",
1849         .addr           = omap44xx_gpio1_addrs,
1850         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1851 };
1852
1853 /* gpio1 slave ports */
1854 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1855         &omap44xx_l4_wkup__gpio1,
1856 };
1857
1858 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1859         { .role = "dbclk", .clk = "gpio1_dbclk" },
1860 };
1861
1862 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1863         .name           = "gpio1",
1864         .class          = &omap44xx_gpio_hwmod_class,
1865         .clkdm_name     = "l4_wkup_clkdm",
1866         .mpu_irqs       = omap44xx_gpio1_irqs,
1867         .main_clk       = "gpio1_ick",
1868         .prcm = {
1869                 .omap4 = {
1870                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1871                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1872                         .modulemode   = MODULEMODE_HWCTRL,
1873                 },
1874         },
1875         .opt_clks       = gpio1_opt_clks,
1876         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1877         .dev_attr       = &gpio_dev_attr,
1878         .slaves         = omap44xx_gpio1_slaves,
1879         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1880 };
1881
1882 /* gpio2 */
1883 static struct omap_hwmod omap44xx_gpio2_hwmod;
1884 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1885         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1886         { .irq = -1 }
1887 };
1888
1889 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1890         {
1891                 .pa_start       = 0x48055000,
1892                 .pa_end         = 0x480551ff,
1893                 .flags          = ADDR_TYPE_RT
1894         },
1895         { }
1896 };
1897
1898 /* l4_per -> gpio2 */
1899 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1900         .master         = &omap44xx_l4_per_hwmod,
1901         .slave          = &omap44xx_gpio2_hwmod,
1902         .clk            = "l4_div_ck",
1903         .addr           = omap44xx_gpio2_addrs,
1904         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1905 };
1906
1907 /* gpio2 slave ports */
1908 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1909         &omap44xx_l4_per__gpio2,
1910 };
1911
1912 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1913         { .role = "dbclk", .clk = "gpio2_dbclk" },
1914 };
1915
1916 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1917         .name           = "gpio2",
1918         .class          = &omap44xx_gpio_hwmod_class,
1919         .clkdm_name     = "l4_per_clkdm",
1920         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1921         .mpu_irqs       = omap44xx_gpio2_irqs,
1922         .main_clk       = "gpio2_ick",
1923         .prcm = {
1924                 .omap4 = {
1925                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1926                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1927                         .modulemode   = MODULEMODE_HWCTRL,
1928                 },
1929         },
1930         .opt_clks       = gpio2_opt_clks,
1931         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1932         .dev_attr       = &gpio_dev_attr,
1933         .slaves         = omap44xx_gpio2_slaves,
1934         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1935 };
1936
1937 /* gpio3 */
1938 static struct omap_hwmod omap44xx_gpio3_hwmod;
1939 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1940         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1941         { .irq = -1 }
1942 };
1943
1944 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1945         {
1946                 .pa_start       = 0x48057000,
1947                 .pa_end         = 0x480571ff,
1948                 .flags          = ADDR_TYPE_RT
1949         },
1950         { }
1951 };
1952
1953 /* l4_per -> gpio3 */
1954 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1955         .master         = &omap44xx_l4_per_hwmod,
1956         .slave          = &omap44xx_gpio3_hwmod,
1957         .clk            = "l4_div_ck",
1958         .addr           = omap44xx_gpio3_addrs,
1959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1960 };
1961
1962 /* gpio3 slave ports */
1963 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1964         &omap44xx_l4_per__gpio3,
1965 };
1966
1967 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1968         { .role = "dbclk", .clk = "gpio3_dbclk" },
1969 };
1970
1971 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1972         .name           = "gpio3",
1973         .class          = &omap44xx_gpio_hwmod_class,
1974         .clkdm_name     = "l4_per_clkdm",
1975         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1976         .mpu_irqs       = omap44xx_gpio3_irqs,
1977         .main_clk       = "gpio3_ick",
1978         .prcm = {
1979                 .omap4 = {
1980                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1981                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1982                         .modulemode   = MODULEMODE_HWCTRL,
1983                 },
1984         },
1985         .opt_clks       = gpio3_opt_clks,
1986         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1987         .dev_attr       = &gpio_dev_attr,
1988         .slaves         = omap44xx_gpio3_slaves,
1989         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1990 };
1991
1992 /* gpio4 */
1993 static struct omap_hwmod omap44xx_gpio4_hwmod;
1994 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1995         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1996         { .irq = -1 }
1997 };
1998
1999 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2000         {
2001                 .pa_start       = 0x48059000,
2002                 .pa_end         = 0x480591ff,
2003                 .flags          = ADDR_TYPE_RT
2004         },
2005         { }
2006 };
2007
2008 /* l4_per -> gpio4 */
2009 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2010         .master         = &omap44xx_l4_per_hwmod,
2011         .slave          = &omap44xx_gpio4_hwmod,
2012         .clk            = "l4_div_ck",
2013         .addr           = omap44xx_gpio4_addrs,
2014         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2015 };
2016
2017 /* gpio4 slave ports */
2018 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2019         &omap44xx_l4_per__gpio4,
2020 };
2021
2022 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2023         { .role = "dbclk", .clk = "gpio4_dbclk" },
2024 };
2025
2026 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2027         .name           = "gpio4",
2028         .class          = &omap44xx_gpio_hwmod_class,
2029         .clkdm_name     = "l4_per_clkdm",
2030         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2031         .mpu_irqs       = omap44xx_gpio4_irqs,
2032         .main_clk       = "gpio4_ick",
2033         .prcm = {
2034                 .omap4 = {
2035                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2036                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2037                         .modulemode   = MODULEMODE_HWCTRL,
2038                 },
2039         },
2040         .opt_clks       = gpio4_opt_clks,
2041         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2042         .dev_attr       = &gpio_dev_attr,
2043         .slaves         = omap44xx_gpio4_slaves,
2044         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
2045 };
2046
2047 /* gpio5 */
2048 static struct omap_hwmod omap44xx_gpio5_hwmod;
2049 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2050         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2051         { .irq = -1 }
2052 };
2053
2054 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2055         {
2056                 .pa_start       = 0x4805b000,
2057                 .pa_end         = 0x4805b1ff,
2058                 .flags          = ADDR_TYPE_RT
2059         },
2060         { }
2061 };
2062
2063 /* l4_per -> gpio5 */
2064 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2065         .master         = &omap44xx_l4_per_hwmod,
2066         .slave          = &omap44xx_gpio5_hwmod,
2067         .clk            = "l4_div_ck",
2068         .addr           = omap44xx_gpio5_addrs,
2069         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2070 };
2071
2072 /* gpio5 slave ports */
2073 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2074         &omap44xx_l4_per__gpio5,
2075 };
2076
2077 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2078         { .role = "dbclk", .clk = "gpio5_dbclk" },
2079 };
2080
2081 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2082         .name           = "gpio5",
2083         .class          = &omap44xx_gpio_hwmod_class,
2084         .clkdm_name     = "l4_per_clkdm",
2085         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2086         .mpu_irqs       = omap44xx_gpio5_irqs,
2087         .main_clk       = "gpio5_ick",
2088         .prcm = {
2089                 .omap4 = {
2090                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2091                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2092                         .modulemode   = MODULEMODE_HWCTRL,
2093                 },
2094         },
2095         .opt_clks       = gpio5_opt_clks,
2096         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2097         .dev_attr       = &gpio_dev_attr,
2098         .slaves         = omap44xx_gpio5_slaves,
2099         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
2100 };
2101
2102 /* gpio6 */
2103 static struct omap_hwmod omap44xx_gpio6_hwmod;
2104 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2105         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2106         { .irq = -1 }
2107 };
2108
2109 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2110         {
2111                 .pa_start       = 0x4805d000,
2112                 .pa_end         = 0x4805d1ff,
2113                 .flags          = ADDR_TYPE_RT
2114         },
2115         { }
2116 };
2117
2118 /* l4_per -> gpio6 */
2119 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2120         .master         = &omap44xx_l4_per_hwmod,
2121         .slave          = &omap44xx_gpio6_hwmod,
2122         .clk            = "l4_div_ck",
2123         .addr           = omap44xx_gpio6_addrs,
2124         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2125 };
2126
2127 /* gpio6 slave ports */
2128 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2129         &omap44xx_l4_per__gpio6,
2130 };
2131
2132 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2133         { .role = "dbclk", .clk = "gpio6_dbclk" },
2134 };
2135
2136 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2137         .name           = "gpio6",
2138         .class          = &omap44xx_gpio_hwmod_class,
2139         .clkdm_name     = "l4_per_clkdm",
2140         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2141         .mpu_irqs       = omap44xx_gpio6_irqs,
2142         .main_clk       = "gpio6_ick",
2143         .prcm = {
2144                 .omap4 = {
2145                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2146                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2147                         .modulemode   = MODULEMODE_HWCTRL,
2148                 },
2149         },
2150         .opt_clks       = gpio6_opt_clks,
2151         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2152         .dev_attr       = &gpio_dev_attr,
2153         .slaves         = omap44xx_gpio6_slaves,
2154         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2155 };
2156
2157 /*
2158  * 'hsi' class
2159  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2160  * serial if)
2161  */
2162
2163 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2164         .rev_offs       = 0x0000,
2165         .sysc_offs      = 0x0010,
2166         .syss_offs      = 0x0014,
2167         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2168                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2169                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2170         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2171                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2172                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2173         .sysc_fields    = &omap_hwmod_sysc_type1,
2174 };
2175
2176 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2177         .name   = "hsi",
2178         .sysc   = &omap44xx_hsi_sysc,
2179 };
2180
2181 /* hsi */
2182 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2183         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2184         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2185         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2186         { .irq = -1 }
2187 };
2188
2189 /* hsi master ports */
2190 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2191         &omap44xx_hsi__l3_main_2,
2192 };
2193
2194 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2195         {
2196                 .pa_start       = 0x4a058000,
2197                 .pa_end         = 0x4a05bfff,
2198                 .flags          = ADDR_TYPE_RT
2199         },
2200         { }
2201 };
2202
2203 /* l4_cfg -> hsi */
2204 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2205         .master         = &omap44xx_l4_cfg_hwmod,
2206         .slave          = &omap44xx_hsi_hwmod,
2207         .clk            = "l4_div_ck",
2208         .addr           = omap44xx_hsi_addrs,
2209         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2210 };
2211
2212 /* hsi slave ports */
2213 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2214         &omap44xx_l4_cfg__hsi,
2215 };
2216
2217 static struct omap_hwmod omap44xx_hsi_hwmod = {
2218         .name           = "hsi",
2219         .class          = &omap44xx_hsi_hwmod_class,
2220         .clkdm_name     = "l3_init_clkdm",
2221         .mpu_irqs       = omap44xx_hsi_irqs,
2222         .main_clk       = "hsi_fck",
2223         .prcm = {
2224                 .omap4 = {
2225                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2226                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2227                         .modulemode   = MODULEMODE_HWCTRL,
2228                 },
2229         },
2230         .slaves         = omap44xx_hsi_slaves,
2231         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2232         .masters        = omap44xx_hsi_masters,
2233         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2234 };
2235
2236 /*
2237  * 'i2c' class
2238  * multimaster high-speed i2c controller
2239  */
2240
2241 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2242         .sysc_offs      = 0x0010,
2243         .syss_offs      = 0x0090,
2244         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2245                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2246                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2247         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2248                            SIDLE_SMART_WKUP),
2249         .sysc_fields    = &omap_hwmod_sysc_type1,
2250 };
2251
2252 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2253         .name   = "i2c",
2254         .sysc   = &omap44xx_i2c_sysc,
2255         .rev    = OMAP_I2C_IP_VERSION_2,
2256         .reset  = &omap_i2c_reset,
2257 };
2258
2259 static struct omap_i2c_dev_attr i2c_dev_attr = {
2260         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2261 };
2262
2263 /* i2c1 */
2264 static struct omap_hwmod omap44xx_i2c1_hwmod;
2265 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2266         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2267         { .irq = -1 }
2268 };
2269
2270 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2271         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2272         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2273         { .dma_req = -1 }
2274 };
2275
2276 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2277         {
2278                 .pa_start       = 0x48070000,
2279                 .pa_end         = 0x480700ff,
2280                 .flags          = ADDR_TYPE_RT
2281         },
2282         { }
2283 };
2284
2285 /* l4_per -> i2c1 */
2286 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2287         .master         = &omap44xx_l4_per_hwmod,
2288         .slave          = &omap44xx_i2c1_hwmod,
2289         .clk            = "l4_div_ck",
2290         .addr           = omap44xx_i2c1_addrs,
2291         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2292 };
2293
2294 /* i2c1 slave ports */
2295 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2296         &omap44xx_l4_per__i2c1,
2297 };
2298
2299 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2300         .name           = "i2c1",
2301         .class          = &omap44xx_i2c_hwmod_class,
2302         .clkdm_name     = "l4_per_clkdm",
2303         .flags          = HWMOD_16BIT_REG,
2304         .mpu_irqs       = omap44xx_i2c1_irqs,
2305         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2306         .main_clk       = "i2c1_fck",
2307         .prcm = {
2308                 .omap4 = {
2309                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2310                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2311                         .modulemode   = MODULEMODE_SWCTRL,
2312                 },
2313         },
2314         .slaves         = omap44xx_i2c1_slaves,
2315         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2316         .dev_attr       = &i2c_dev_attr,
2317 };
2318
2319 /* i2c2 */
2320 static struct omap_hwmod omap44xx_i2c2_hwmod;
2321 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2322         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2323         { .irq = -1 }
2324 };
2325
2326 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2327         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2328         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2329         { .dma_req = -1 }
2330 };
2331
2332 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2333         {
2334                 .pa_start       = 0x48072000,
2335                 .pa_end         = 0x480720ff,
2336                 .flags          = ADDR_TYPE_RT
2337         },
2338         { }
2339 };
2340
2341 /* l4_per -> i2c2 */
2342 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2343         .master         = &omap44xx_l4_per_hwmod,
2344         .slave          = &omap44xx_i2c2_hwmod,
2345         .clk            = "l4_div_ck",
2346         .addr           = omap44xx_i2c2_addrs,
2347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2348 };
2349
2350 /* i2c2 slave ports */
2351 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2352         &omap44xx_l4_per__i2c2,
2353 };
2354
2355 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2356         .name           = "i2c2",
2357         .class          = &omap44xx_i2c_hwmod_class,
2358         .clkdm_name     = "l4_per_clkdm",
2359         .flags          = HWMOD_16BIT_REG,
2360         .mpu_irqs       = omap44xx_i2c2_irqs,
2361         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2362         .main_clk       = "i2c2_fck",
2363         .prcm = {
2364                 .omap4 = {
2365                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2366                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2367                         .modulemode   = MODULEMODE_SWCTRL,
2368                 },
2369         },
2370         .slaves         = omap44xx_i2c2_slaves,
2371         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2372         .dev_attr       = &i2c_dev_attr,
2373 };
2374
2375 /* i2c3 */
2376 static struct omap_hwmod omap44xx_i2c3_hwmod;
2377 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2378         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2379         { .irq = -1 }
2380 };
2381
2382 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2383         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2384         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2385         { .dma_req = -1 }
2386 };
2387
2388 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2389         {
2390                 .pa_start       = 0x48060000,
2391                 .pa_end         = 0x480600ff,
2392                 .flags          = ADDR_TYPE_RT
2393         },
2394         { }
2395 };
2396
2397 /* l4_per -> i2c3 */
2398 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2399         .master         = &omap44xx_l4_per_hwmod,
2400         .slave          = &omap44xx_i2c3_hwmod,
2401         .clk            = "l4_div_ck",
2402         .addr           = omap44xx_i2c3_addrs,
2403         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2404 };
2405
2406 /* i2c3 slave ports */
2407 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2408         &omap44xx_l4_per__i2c3,
2409 };
2410
2411 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2412         .name           = "i2c3",
2413         .class          = &omap44xx_i2c_hwmod_class,
2414         .clkdm_name     = "l4_per_clkdm",
2415         .flags          = HWMOD_16BIT_REG,
2416         .mpu_irqs       = omap44xx_i2c3_irqs,
2417         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2418         .main_clk       = "i2c3_fck",
2419         .prcm = {
2420                 .omap4 = {
2421                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2422                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2423                         .modulemode   = MODULEMODE_SWCTRL,
2424                 },
2425         },
2426         .slaves         = omap44xx_i2c3_slaves,
2427         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2428         .dev_attr       = &i2c_dev_attr,
2429 };
2430
2431 /* i2c4 */
2432 static struct omap_hwmod omap44xx_i2c4_hwmod;
2433 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2434         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2435         { .irq = -1 }
2436 };
2437
2438 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2439         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2440         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2441         { .dma_req = -1 }
2442 };
2443
2444 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2445         {
2446                 .pa_start       = 0x48350000,
2447                 .pa_end         = 0x483500ff,
2448                 .flags          = ADDR_TYPE_RT
2449         },
2450         { }
2451 };
2452
2453 /* l4_per -> i2c4 */
2454 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2455         .master         = &omap44xx_l4_per_hwmod,
2456         .slave          = &omap44xx_i2c4_hwmod,
2457         .clk            = "l4_div_ck",
2458         .addr           = omap44xx_i2c4_addrs,
2459         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2460 };
2461
2462 /* i2c4 slave ports */
2463 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2464         &omap44xx_l4_per__i2c4,
2465 };
2466
2467 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2468         .name           = "i2c4",
2469         .class          = &omap44xx_i2c_hwmod_class,
2470         .clkdm_name     = "l4_per_clkdm",
2471         .flags          = HWMOD_16BIT_REG,
2472         .mpu_irqs       = omap44xx_i2c4_irqs,
2473         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2474         .main_clk       = "i2c4_fck",
2475         .prcm = {
2476                 .omap4 = {
2477                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2478                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2479                         .modulemode   = MODULEMODE_SWCTRL,
2480                 },
2481         },
2482         .slaves         = omap44xx_i2c4_slaves,
2483         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2484         .dev_attr       = &i2c_dev_attr,
2485 };
2486
2487 /*
2488  * 'ipu' class
2489  * imaging processor unit
2490  */
2491
2492 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2493         .name   = "ipu",
2494 };
2495
2496 /* ipu */
2497 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2498         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2499         { .irq = -1 }
2500 };
2501
2502 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2503         { .name = "cpu0", .rst_shift = 0 },
2504 };
2505
2506 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2507         { .name = "cpu1", .rst_shift = 1 },
2508 };
2509
2510 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2511         { .name = "mmu_cache", .rst_shift = 2 },
2512 };
2513
2514 /* ipu master ports */
2515 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2516         &omap44xx_ipu__l3_main_2,
2517 };
2518
2519 /* l3_main_2 -> ipu */
2520 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2521         .master         = &omap44xx_l3_main_2_hwmod,
2522         .slave          = &omap44xx_ipu_hwmod,
2523         .clk            = "l3_div_ck",
2524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2525 };
2526
2527 /* ipu slave ports */
2528 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2529         &omap44xx_l3_main_2__ipu,
2530 };
2531
2532 /* Pseudo hwmod for reset control purpose only */
2533 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2534         .name           = "ipu_c0",
2535         .class          = &omap44xx_ipu_hwmod_class,
2536         .clkdm_name     = "ducati_clkdm",
2537         .flags          = HWMOD_INIT_NO_RESET,
2538         .rst_lines      = omap44xx_ipu_c0_resets,
2539         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2540         .prcm = {
2541                 .omap4 = {
2542                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2543                 },
2544         },
2545 };
2546
2547 /* Pseudo hwmod for reset control purpose only */
2548 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2549         .name           = "ipu_c1",
2550         .class          = &omap44xx_ipu_hwmod_class,
2551         .clkdm_name     = "ducati_clkdm",
2552         .flags          = HWMOD_INIT_NO_RESET,
2553         .rst_lines      = omap44xx_ipu_c1_resets,
2554         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2555         .prcm = {
2556                 .omap4 = {
2557                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2558                 },
2559         },
2560 };
2561
2562 static struct omap_hwmod omap44xx_ipu_hwmod = {
2563         .name           = "ipu",
2564         .class          = &omap44xx_ipu_hwmod_class,
2565         .clkdm_name     = "ducati_clkdm",
2566         .mpu_irqs       = omap44xx_ipu_irqs,
2567         .rst_lines      = omap44xx_ipu_resets,
2568         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2569         .main_clk       = "ipu_fck",
2570         .prcm = {
2571                 .omap4 = {
2572                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2573                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2574                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2575                         .modulemode   = MODULEMODE_HWCTRL,
2576                 },
2577         },
2578         .slaves         = omap44xx_ipu_slaves,
2579         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2580         .masters        = omap44xx_ipu_masters,
2581         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2582 };
2583
2584 /*
2585  * 'iss' class
2586  * external images sensor pixel data processor
2587  */
2588
2589 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2590         .rev_offs       = 0x0000,
2591         .sysc_offs      = 0x0010,
2592         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2593                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2594         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2595                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2596                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2597         .sysc_fields    = &omap_hwmod_sysc_type2,
2598 };
2599
2600 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2601         .name   = "iss",
2602         .sysc   = &omap44xx_iss_sysc,
2603 };
2604
2605 /* iss */
2606 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2607         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2608         { .irq = -1 }
2609 };
2610
2611 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2612         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2613         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2614         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2615         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2616         { .dma_req = -1 }
2617 };
2618
2619 /* iss master ports */
2620 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2621         &omap44xx_iss__l3_main_2,
2622 };
2623
2624 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2625         {
2626                 .pa_start       = 0x52000000,
2627                 .pa_end         = 0x520000ff,
2628                 .flags          = ADDR_TYPE_RT
2629         },
2630         { }
2631 };
2632
2633 /* l3_main_2 -> iss */
2634 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2635         .master         = &omap44xx_l3_main_2_hwmod,
2636         .slave          = &omap44xx_iss_hwmod,
2637         .clk            = "l3_div_ck",
2638         .addr           = omap44xx_iss_addrs,
2639         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2640 };
2641
2642 /* iss slave ports */
2643 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2644         &omap44xx_l3_main_2__iss,
2645 };
2646
2647 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2648         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2649 };
2650
2651 static struct omap_hwmod omap44xx_iss_hwmod = {
2652         .name           = "iss",
2653         .class          = &omap44xx_iss_hwmod_class,
2654         .clkdm_name     = "iss_clkdm",
2655         .mpu_irqs       = omap44xx_iss_irqs,
2656         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2657         .main_clk       = "iss_fck",
2658         .prcm = {
2659                 .omap4 = {
2660                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2661                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2662                         .modulemode   = MODULEMODE_SWCTRL,
2663                 },
2664         },
2665         .opt_clks       = iss_opt_clks,
2666         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2667         .slaves         = omap44xx_iss_slaves,
2668         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2669         .masters        = omap44xx_iss_masters,
2670         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2671 };
2672
2673 /*
2674  * 'iva' class
2675  * multi-standard video encoder/decoder hardware accelerator
2676  */
2677
2678 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2679         .name   = "iva",
2680 };
2681
2682 /* iva */
2683 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2684         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2685         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2686         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2687         { .irq = -1 }
2688 };
2689
2690 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2691         { .name = "logic", .rst_shift = 2 },
2692 };
2693
2694 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2695         { .name = "seq0", .rst_shift = 0 },
2696 };
2697
2698 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2699         { .name = "seq1", .rst_shift = 1 },
2700 };
2701
2702 /* iva master ports */
2703 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2704         &omap44xx_iva__l3_main_2,
2705         &omap44xx_iva__l3_instr,
2706 };
2707
2708 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2709         {
2710                 .pa_start       = 0x5a000000,
2711                 .pa_end         = 0x5a07ffff,
2712                 .flags          = ADDR_TYPE_RT
2713         },
2714         { }
2715 };
2716
2717 /* l3_main_2 -> iva */
2718 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2719         .master         = &omap44xx_l3_main_2_hwmod,
2720         .slave          = &omap44xx_iva_hwmod,
2721         .clk            = "l3_div_ck",
2722         .addr           = omap44xx_iva_addrs,
2723         .user           = OCP_USER_MPU,
2724 };
2725
2726 /* iva slave ports */
2727 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2728         &omap44xx_dsp__iva,
2729         &omap44xx_l3_main_2__iva,
2730 };
2731
2732 /* Pseudo hwmod for reset control purpose only */
2733 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2734         .name           = "iva_seq0",
2735         .class          = &omap44xx_iva_hwmod_class,
2736         .clkdm_name     = "ivahd_clkdm",
2737         .flags          = HWMOD_INIT_NO_RESET,
2738         .rst_lines      = omap44xx_iva_seq0_resets,
2739         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2740         .prcm = {
2741                 .omap4 = {
2742                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2743                 },
2744         },
2745 };
2746
2747 /* Pseudo hwmod for reset control purpose only */
2748 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2749         .name           = "iva_seq1",
2750         .class          = &omap44xx_iva_hwmod_class,
2751         .clkdm_name     = "ivahd_clkdm",
2752         .flags          = HWMOD_INIT_NO_RESET,
2753         .rst_lines      = omap44xx_iva_seq1_resets,
2754         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2755         .prcm = {
2756                 .omap4 = {
2757                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2758                 },
2759         },
2760 };
2761
2762 static struct omap_hwmod omap44xx_iva_hwmod = {
2763         .name           = "iva",
2764         .class          = &omap44xx_iva_hwmod_class,
2765         .clkdm_name     = "ivahd_clkdm",
2766         .mpu_irqs       = omap44xx_iva_irqs,
2767         .rst_lines      = omap44xx_iva_resets,
2768         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2769         .main_clk       = "iva_fck",
2770         .prcm = {
2771                 .omap4 = {
2772                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2773                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2774                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2775                         .modulemode   = MODULEMODE_HWCTRL,
2776                 },
2777         },
2778         .slaves         = omap44xx_iva_slaves,
2779         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2780         .masters        = omap44xx_iva_masters,
2781         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2782 };
2783
2784 /*
2785  * 'kbd' class
2786  * keyboard controller
2787  */
2788
2789 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2790         .rev_offs       = 0x0000,
2791         .sysc_offs      = 0x0010,
2792         .syss_offs      = 0x0014,
2793         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2794                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2795                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2796                            SYSS_HAS_RESET_STATUS),
2797         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2798         .sysc_fields    = &omap_hwmod_sysc_type1,
2799 };
2800
2801 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2802         .name   = "kbd",
2803         .sysc   = &omap44xx_kbd_sysc,
2804 };
2805
2806 /* kbd */
2807 static struct omap_hwmod omap44xx_kbd_hwmod;
2808 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2809         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2810         { .irq = -1 }
2811 };
2812
2813 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2814         {
2815                 .pa_start       = 0x4a31c000,
2816                 .pa_end         = 0x4a31c07f,
2817                 .flags          = ADDR_TYPE_RT
2818         },
2819         { }
2820 };
2821
2822 /* l4_wkup -> kbd */
2823 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2824         .master         = &omap44xx_l4_wkup_hwmod,
2825         .slave          = &omap44xx_kbd_hwmod,
2826         .clk            = "l4_wkup_clk_mux_ck",
2827         .addr           = omap44xx_kbd_addrs,
2828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2829 };
2830
2831 /* kbd slave ports */
2832 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2833         &omap44xx_l4_wkup__kbd,
2834 };
2835
2836 static struct omap_hwmod omap44xx_kbd_hwmod = {
2837         .name           = "kbd",
2838         .class          = &omap44xx_kbd_hwmod_class,
2839         .clkdm_name     = "l4_wkup_clkdm",
2840         .mpu_irqs       = omap44xx_kbd_irqs,
2841         .main_clk       = "kbd_fck",
2842         .prcm = {
2843                 .omap4 = {
2844                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2845                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2846                         .modulemode   = MODULEMODE_SWCTRL,
2847                 },
2848         },
2849         .slaves         = omap44xx_kbd_slaves,
2850         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2851 };
2852
2853 /*
2854  * 'mailbox' class
2855  * mailbox module allowing communication between the on-chip processors using a
2856  * queued mailbox-interrupt mechanism.
2857  */
2858
2859 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2860         .rev_offs       = 0x0000,
2861         .sysc_offs      = 0x0010,
2862         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2863                            SYSC_HAS_SOFTRESET),
2864         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2865         .sysc_fields    = &omap_hwmod_sysc_type2,
2866 };
2867
2868 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2869         .name   = "mailbox",
2870         .sysc   = &omap44xx_mailbox_sysc,
2871 };
2872
2873 /* mailbox */
2874 static struct omap_hwmod omap44xx_mailbox_hwmod;
2875 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2876         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2877         { .irq = -1 }
2878 };
2879
2880 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2881         {
2882                 .pa_start       = 0x4a0f4000,
2883                 .pa_end         = 0x4a0f41ff,
2884                 .flags          = ADDR_TYPE_RT
2885         },
2886         { }
2887 };
2888
2889 /* l4_cfg -> mailbox */
2890 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2891         .master         = &omap44xx_l4_cfg_hwmod,
2892         .slave          = &omap44xx_mailbox_hwmod,
2893         .clk            = "l4_div_ck",
2894         .addr           = omap44xx_mailbox_addrs,
2895         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2896 };
2897
2898 /* mailbox slave ports */
2899 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2900         &omap44xx_l4_cfg__mailbox,
2901 };
2902
2903 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2904         .name           = "mailbox",
2905         .class          = &omap44xx_mailbox_hwmod_class,
2906         .clkdm_name     = "l4_cfg_clkdm",
2907         .mpu_irqs       = omap44xx_mailbox_irqs,
2908         .prcm = {
2909                 .omap4 = {
2910                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2911                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2912                 },
2913         },
2914         .slaves         = omap44xx_mailbox_slaves,
2915         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2916 };
2917
2918 /*
2919  * 'mcbsp' class
2920  * multi channel buffered serial port controller
2921  */
2922
2923 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2924         .sysc_offs      = 0x008c,
2925         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2926                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2927         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2928         .sysc_fields    = &omap_hwmod_sysc_type1,
2929 };
2930
2931 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2932         .name   = "mcbsp",
2933         .sysc   = &omap44xx_mcbsp_sysc,
2934         .rev    = MCBSP_CONFIG_TYPE4,
2935 };
2936
2937 /* mcbsp1 */
2938 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2939 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2940         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2941         { .irq = -1 }
2942 };
2943
2944 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2945         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2946         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2947         { .dma_req = -1 }
2948 };
2949
2950 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2951         {
2952                 .name           = "mpu",
2953                 .pa_start       = 0x40122000,
2954                 .pa_end         = 0x401220ff,
2955                 .flags          = ADDR_TYPE_RT
2956         },
2957         { }
2958 };
2959
2960 /* l4_abe -> mcbsp1 */
2961 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2962         .master         = &omap44xx_l4_abe_hwmod,
2963         .slave          = &omap44xx_mcbsp1_hwmod,
2964         .clk            = "ocp_abe_iclk",
2965         .addr           = omap44xx_mcbsp1_addrs,
2966         .user           = OCP_USER_MPU,
2967 };
2968
2969 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2970         {
2971                 .name           = "dma",
2972                 .pa_start       = 0x49022000,
2973                 .pa_end         = 0x490220ff,
2974                 .flags          = ADDR_TYPE_RT
2975         },
2976         { }
2977 };
2978
2979 /* l4_abe -> mcbsp1 (dma) */
2980 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2981         .master         = &omap44xx_l4_abe_hwmod,
2982         .slave          = &omap44xx_mcbsp1_hwmod,
2983         .clk            = "ocp_abe_iclk",
2984         .addr           = omap44xx_mcbsp1_dma_addrs,
2985         .user           = OCP_USER_SDMA,
2986 };
2987
2988 /* mcbsp1 slave ports */
2989 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2990         &omap44xx_l4_abe__mcbsp1,
2991         &omap44xx_l4_abe__mcbsp1_dma,
2992 };
2993
2994 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2995         .name           = "mcbsp1",
2996         .class          = &omap44xx_mcbsp_hwmod_class,
2997         .clkdm_name     = "abe_clkdm",
2998         .mpu_irqs       = omap44xx_mcbsp1_irqs,
2999         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
3000         .main_clk       = "mcbsp1_fck",
3001         .prcm = {
3002                 .omap4 = {
3003                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
3004                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
3005                         .modulemode   = MODULEMODE_SWCTRL,
3006                 },
3007         },
3008         .slaves         = omap44xx_mcbsp1_slaves,
3009         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3010 };
3011
3012 /* mcbsp2 */
3013 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3014 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3015         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
3016         { .irq = -1 }
3017 };
3018
3019 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3020         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
3021         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
3022         { .dma_req = -1 }
3023 };
3024
3025 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3026         {
3027                 .name           = "mpu",
3028                 .pa_start       = 0x40124000,
3029                 .pa_end         = 0x401240ff,
3030                 .flags          = ADDR_TYPE_RT
3031         },
3032         { }
3033 };
3034
3035 /* l4_abe -> mcbsp2 */
3036 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3037         .master         = &omap44xx_l4_abe_hwmod,
3038         .slave          = &omap44xx_mcbsp2_hwmod,
3039         .clk            = "ocp_abe_iclk",
3040         .addr           = omap44xx_mcbsp2_addrs,
3041         .user           = OCP_USER_MPU,
3042 };
3043
3044 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3045         {
3046                 .name           = "dma",
3047                 .pa_start       = 0x49024000,
3048                 .pa_end         = 0x490240ff,
3049                 .flags          = ADDR_TYPE_RT
3050         },
3051         { }
3052 };
3053
3054 /* l4_abe -> mcbsp2 (dma) */
3055 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3056         .master         = &omap44xx_l4_abe_hwmod,
3057         .slave          = &omap44xx_mcbsp2_hwmod,
3058         .clk            = "ocp_abe_iclk",
3059         .addr           = omap44xx_mcbsp2_dma_addrs,
3060         .user           = OCP_USER_SDMA,
3061 };
3062
3063 /* mcbsp2 slave ports */
3064 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3065         &omap44xx_l4_abe__mcbsp2,
3066         &omap44xx_l4_abe__mcbsp2_dma,
3067 };
3068
3069 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3070         .name           = "mcbsp2",
3071         .class          = &omap44xx_mcbsp_hwmod_class,
3072         .clkdm_name     = "abe_clkdm",
3073         .mpu_irqs       = omap44xx_mcbsp2_irqs,
3074         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
3075         .main_clk       = "mcbsp2_fck",
3076         .prcm = {
3077                 .omap4 = {
3078                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3079                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,