arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/gpio.h>
  26 #include <plat/dma.h>
  27 #include <plat/mcspi.h>
  28
  29 #include "omap_hwmod_common_data.h"
  30
  31 #include "cm1_44xx.h"
  32 #include "cm2_44xx.h"
  33 #include "prm44xx.h"
  34 #include "prm-regbits-44xx.h"
  35 #include "wd_timer.h"
  36
  37 /* Base offset for all OMAP4 interrupts external to MPUSS */
  38 #define OMAP44XX_IRQ_GIC_START  32
  39
  40 /* Base offset for all OMAP4 dma requests */
  41 #define OMAP44XX_DMA_REQ_START  1
  42
  43 /* Backward references (IPs with Bus Master capability) */
  44 static struct omap_hwmod omap44xx_aess_hwmod;
  45 static struct omap_hwmod omap44xx_dma_system_hwmod;
  46 static struct omap_hwmod omap44xx_dmm_hwmod;
  47 static struct omap_hwmod omap44xx_dsp_hwmod;
  48 static struct omap_hwmod omap44xx_dss_hwmod;
  49 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  50 static struct omap_hwmod omap44xx_hsi_hwmod;
  51 static struct omap_hwmod omap44xx_ipu_hwmod;
  52 static struct omap_hwmod omap44xx_iss_hwmod;
  53 static struct omap_hwmod omap44xx_iva_hwmod;
  54 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  55 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  56 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  57 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  58 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  59 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  60 static struct omap_hwmod omap44xx_l4_per_hwmod;
  61 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  62 static struct omap_hwmod omap44xx_mmc1_hwmod;
  63 static struct omap_hwmod omap44xx_mmc2_hwmod;
  64 static struct omap_hwmod omap44xx_mpu_hwmod;
  65 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  66 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  67
  68 /*
  69  * Interconnects omap_hwmod structures
  70  * hwmods that compose the global OMAP interconnect
  71  */
  72
  73 /*
  74  * 'dmm' class
  75  * instance(s): dmm
  76  */
  77 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  78         .name   = "dmm",
  79 };
  80
  81 /* dmm interface data */
  82 /* l3_main_1 -> dmm */
  83 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  84         .master         = &omap44xx_l3_main_1_hwmod,
  85         .slave          = &omap44xx_dmm_hwmod,
  86         .clk            = "l3_div_ck",
  87         .user           = OCP_USER_SDMA,
  88 };
  89
  90 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
  91         {
  92                 .pa_start       = 0x4e000000,
  93                 .pa_end         = 0x4e0007ff,
  94                 .flags          = ADDR_TYPE_RT
  95         },
  96 };
  97
  98 /* mpu -> dmm */
  99 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 100         .master         = &omap44xx_mpu_hwmod,
 101         .slave          = &omap44xx_dmm_hwmod,
 102         .clk            = "l3_div_ck",
 103         .addr           = omap44xx_dmm_addrs,
 104         .addr_cnt       = ARRAY_SIZE(omap44xx_dmm_addrs),
 105         .user           = OCP_USER_MPU,
 106 };
 107
 108 /* dmm slave ports */
 109 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 110         &omap44xx_l3_main_1__dmm,
 111         &omap44xx_mpu__dmm,
 112 };
 113
 114 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
 115         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
 116 };
 117
 118 static struct omap_hwmod omap44xx_dmm_hwmod = {
 119         .name           = "dmm",
 120         .class          = &omap44xx_dmm_hwmod_class,
 121         .slaves         = omap44xx_dmm_slaves,
 122         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 123         .mpu_irqs       = omap44xx_dmm_irqs,
 124         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
 125         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 126 };
 127
 128 /*
 129  * 'emif_fw' class
 130  * instance(s): emif_fw
 131  */
 132 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 133         .name   = "emif_fw",
 134 };
 135
 136 /* emif_fw interface data */
 137 /* dmm -> emif_fw */
 138 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 139         .master         = &omap44xx_dmm_hwmod,
 140         .slave          = &omap44xx_emif_fw_hwmod,
 141         .clk            = "l3_div_ck",
 142         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 143 };
 144
 145 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 146         {
 147                 .pa_start       = 0x4a20c000,
 148                 .pa_end         = 0x4a20c0ff,
 149                 .flags          = ADDR_TYPE_RT
 150         },
 151 };
 152
 153 /* l4_cfg -> emif_fw */
 154 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 155         .master         = &omap44xx_l4_cfg_hwmod,
 156         .slave          = &omap44xx_emif_fw_hwmod,
 157         .clk            = "l4_div_ck",
 158         .addr           = omap44xx_emif_fw_addrs,
 159         .addr_cnt       = ARRAY_SIZE(omap44xx_emif_fw_addrs),
 160         .user           = OCP_USER_MPU,
 161 };
 162
 163 /* emif_fw slave ports */
 164 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 165         &omap44xx_dmm__emif_fw,
 166         &omap44xx_l4_cfg__emif_fw,
 167 };
 168
 169 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 170         .name           = "emif_fw",
 171         .class          = &omap44xx_emif_fw_hwmod_class,
 172         .slaves         = omap44xx_emif_fw_slaves,
 173         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 174         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 175 };
 176
 177 /*
 178  * 'l3' class
 179  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 180  */
 181 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 182         .name   = "l3",
 183 };
 184
 185 /* l3_instr interface data */
 186 /* iva -> l3_instr */
 187 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 188         .master         = &omap44xx_iva_hwmod,
 189         .slave          = &omap44xx_l3_instr_hwmod,
 190         .clk            = "l3_div_ck",
 191         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 192 };
 193
 194 /* l3_main_3 -> l3_instr */
 195 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 196         .master         = &omap44xx_l3_main_3_hwmod,
 197         .slave          = &omap44xx_l3_instr_hwmod,
 198         .clk            = "l3_div_ck",
 199         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 200 };
 201
 202 /* l3_instr slave ports */
 203 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 204         &omap44xx_iva__l3_instr,
 205         &omap44xx_l3_main_3__l3_instr,
 206 };
 207
 208 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 209         .name           = "l3_instr",
 210         .class          = &omap44xx_l3_hwmod_class,
 211         .slaves         = omap44xx_l3_instr_slaves,
 212         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 213         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 214 };
 215
 216 /* l3_main_1 interface data */
 217 /* dsp -> l3_main_1 */
 218 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 219         .master         = &omap44xx_dsp_hwmod,
 220         .slave          = &omap44xx_l3_main_1_hwmod,
 221         .clk            = "l3_div_ck",
 222         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 223 };
 224
 225 /* dss -> l3_main_1 */
 226 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 227         .master         = &omap44xx_dss_hwmod,
 228         .slave          = &omap44xx_l3_main_1_hwmod,
 229         .clk            = "l3_div_ck",
 230         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 231 };
 232
 233 /* l3_main_2 -> l3_main_1 */
 234 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 235         .master         = &omap44xx_l3_main_2_hwmod,
 236         .slave          = &omap44xx_l3_main_1_hwmod,
 237         .clk            = "l3_div_ck",
 238         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 239 };
 240
 241 /* l4_cfg -> l3_main_1 */
 242 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 243         .master         = &omap44xx_l4_cfg_hwmod,
 244         .slave          = &omap44xx_l3_main_1_hwmod,
 245         .clk            = "l4_div_ck",
 246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 247 };
 248
 249 /* mmc1 -> l3_main_1 */
 250 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 251         .master         = &omap44xx_mmc1_hwmod,
 252         .slave          = &omap44xx_l3_main_1_hwmod,
 253         .clk            = "l3_div_ck",
 254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 255 };
 256
 257 /* mmc2 -> l3_main_1 */
 258 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 259         .master         = &omap44xx_mmc2_hwmod,
 260         .slave          = &omap44xx_l3_main_1_hwmod,
 261         .clk            = "l3_div_ck",
 262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 263 };
 264
 265 /* mpu -> l3_main_1 */
 266 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 267         .master         = &omap44xx_mpu_hwmod,
 268         .slave          = &omap44xx_l3_main_1_hwmod,
 269         .clk            = "l3_div_ck",
 270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 271 };
 272
 273 /* l3_main_1 slave ports */
 274 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 275         &omap44xx_dsp__l3_main_1,
 276         &omap44xx_dss__l3_main_1,
 277         &omap44xx_l3_main_2__l3_main_1,
 278         &omap44xx_l4_cfg__l3_main_1,
 279         &omap44xx_mmc1__l3_main_1,
 280         &omap44xx_mmc2__l3_main_1,
 281         &omap44xx_mpu__l3_main_1,
 282 };
 283
 284 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 285         .name           = "l3_main_1",
 286         .class          = &omap44xx_l3_hwmod_class,
 287         .slaves         = omap44xx_l3_main_1_slaves,
 288         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 289         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 290 };
 291
 292 /* l3_main_2 interface data */
 293 /* dma_system -> l3_main_2 */
 294 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 295         .master         = &omap44xx_dma_system_hwmod,
 296         .slave          = &omap44xx_l3_main_2_hwmod,
 297         .clk            = "l3_div_ck",
 298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 299 };
 300
 301 /* hsi -> l3_main_2 */
 302 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 303         .master         = &omap44xx_hsi_hwmod,
 304         .slave          = &omap44xx_l3_main_2_hwmod,
 305         .clk            = "l3_div_ck",
 306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 307 };
 308
 309 /* ipu -> l3_main_2 */
 310 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 311         .master         = &omap44xx_ipu_hwmod,
 312         .slave          = &omap44xx_l3_main_2_hwmod,
 313         .clk            = "l3_div_ck",
 314         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 315 };
 316
 317 /* iss -> l3_main_2 */
 318 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 319         .master         = &omap44xx_iss_hwmod,
 320         .slave          = &omap44xx_l3_main_2_hwmod,
 321         .clk            = "l3_div_ck",
 322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 323 };
 324
 325 /* iva -> l3_main_2 */
 326 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 327         .master         = &omap44xx_iva_hwmod,
 328         .slave          = &omap44xx_l3_main_2_hwmod,
 329         .clk            = "l3_div_ck",
 330         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 331 };
 332
 333 /* l3_main_1 -> l3_main_2 */
 334 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 335         .master         = &omap44xx_l3_main_1_hwmod,
 336         .slave          = &omap44xx_l3_main_2_hwmod,
 337         .clk            = "l3_div_ck",
 338         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 339 };
 340
 341 /* l4_cfg -> l3_main_2 */
 342 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 343         .master         = &omap44xx_l4_cfg_hwmod,
 344         .slave          = &omap44xx_l3_main_2_hwmod,
 345         .clk            = "l4_div_ck",
 346         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 347 };
 348
 349 /* usb_otg_hs -> l3_main_2 */
 350 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 351         .master         = &omap44xx_usb_otg_hs_hwmod,
 352         .slave          = &omap44xx_l3_main_2_hwmod,
 353         .clk            = "l3_div_ck",
 354         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 355 };
 356
 357 /* l3_main_2 slave ports */
 358 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 359         &omap44xx_dma_system__l3_main_2,
 360         &omap44xx_hsi__l3_main_2,
 361         &omap44xx_ipu__l3_main_2,
 362         &omap44xx_iss__l3_main_2,
 363         &omap44xx_iva__l3_main_2,
 364         &omap44xx_l3_main_1__l3_main_2,
 365         &omap44xx_l4_cfg__l3_main_2,
 366         &omap44xx_usb_otg_hs__l3_main_2,
 367 };
 368
 369 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 370         .name           = "l3_main_2",
 371         .class          = &omap44xx_l3_hwmod_class,
 372         .slaves         = omap44xx_l3_main_2_slaves,
 373         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 374         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 375 };
 376
 377 /* l3_main_3 interface data */
 378 /* l3_main_1 -> l3_main_3 */
 379 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 380         .master         = &omap44xx_l3_main_1_hwmod,
 381         .slave          = &omap44xx_l3_main_3_hwmod,
 382         .clk            = "l3_div_ck",
 383         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 384 };
 385
 386 /* l3_main_2 -> l3_main_3 */
 387 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 388         .master         = &omap44xx_l3_main_2_hwmod,
 389         .slave          = &omap44xx_l3_main_3_hwmod,
 390         .clk            = "l3_div_ck",
 391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 392 };
 393
 394 /* l4_cfg -> l3_main_3 */
 395 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 396         .master         = &omap44xx_l4_cfg_hwmod,
 397         .slave          = &omap44xx_l3_main_3_hwmod,
 398         .clk            = "l4_div_ck",
 399         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 400 };
 401
 402 /* l3_main_3 slave ports */
 403 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 404         &omap44xx_l3_main_1__l3_main_3,
 405         &omap44xx_l3_main_2__l3_main_3,
 406         &omap44xx_l4_cfg__l3_main_3,
 407 };
 408
 409 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 410         .name           = "l3_main_3",
 411         .class          = &omap44xx_l3_hwmod_class,
 412         .slaves         = omap44xx_l3_main_3_slaves,
 413         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 414         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 415 };
 416
 417 /*
 418  * 'l4' class
 419  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 420  */
 421 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 422         .name   = "l4",
 423 };
 424
 425 /* l4_abe interface data */
 426 /* aess -> l4_abe */
 427 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 428         .master         = &omap44xx_aess_hwmod,
 429         .slave          = &omap44xx_l4_abe_hwmod,
 430         .clk            = "ocp_abe_iclk",
 431         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 432 };
 433
 434 /* dsp -> l4_abe */
 435 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 436         .master         = &omap44xx_dsp_hwmod,
 437         .slave          = &omap44xx_l4_abe_hwmod,
 438         .clk            = "ocp_abe_iclk",
 439         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 440 };
 441
 442 /* l3_main_1 -> l4_abe */
 443 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 444         .master         = &omap44xx_l3_main_1_hwmod,
 445         .slave          = &omap44xx_l4_abe_hwmod,
 446         .clk            = "l3_div_ck",
 447         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 448 };
 449
 450 /* mpu -> l4_abe */
 451 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 452         .master         = &omap44xx_mpu_hwmod,
 453         .slave          = &omap44xx_l4_abe_hwmod,
 454         .clk            = "ocp_abe_iclk",
 455         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 456 };
 457
 458 /* l4_abe slave ports */
 459 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 460         &omap44xx_aess__l4_abe,
 461         &omap44xx_dsp__l4_abe,
 462         &omap44xx_l3_main_1__l4_abe,
 463         &omap44xx_mpu__l4_abe,
 464 };
 465
 466 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 467         .name           = "l4_abe",
 468         .class          = &omap44xx_l4_hwmod_class,
 469         .slaves         = omap44xx_l4_abe_slaves,
 470         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 471         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 472 };
 473
 474 /* l4_cfg interface data */
 475 /* l3_main_1 -> l4_cfg */
 476 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 477         .master         = &omap44xx_l3_main_1_hwmod,
 478         .slave          = &omap44xx_l4_cfg_hwmod,
 479         .clk            = "l3_div_ck",
 480         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 481 };
 482
 483 /* l4_cfg slave ports */
 484 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 485         &omap44xx_l3_main_1__l4_cfg,
 486 };
 487
 488 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 489         .name           = "l4_cfg",
 490         .class          = &omap44xx_l4_hwmod_class,
 491         .slaves         = omap44xx_l4_cfg_slaves,
 492         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 493         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 494 };
 495
 496 /* l4_per interface data */
 497 /* l3_main_2 -> l4_per */
 498 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 499         .master         = &omap44xx_l3_main_2_hwmod,
 500         .slave          = &omap44xx_l4_per_hwmod,
 501         .clk            = "l3_div_ck",
 502         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 503 };
 504
 505 /* l4_per slave ports */
 506 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 507         &omap44xx_l3_main_2__l4_per,
 508 };
 509
 510 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 511         .name           = "l4_per",
 512         .class          = &omap44xx_l4_hwmod_class,
 513         .slaves         = omap44xx_l4_per_slaves,
 514         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 515         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 516 };
 517
 518 /* l4_wkup interface data */
 519 /* l4_cfg -> l4_wkup */
 520 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 521         .master         = &omap44xx_l4_cfg_hwmod,
 522         .slave          = &omap44xx_l4_wkup_hwmod,
 523         .clk            = "l4_div_ck",
 524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 525 };
 526
 527 /* l4_wkup slave ports */
 528 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 529         &omap44xx_l4_cfg__l4_wkup,
 530 };
 531
 532 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 533         .name           = "l4_wkup",
 534         .class          = &omap44xx_l4_hwmod_class,
 535         .slaves         = omap44xx_l4_wkup_slaves,
 536         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 537         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 538 };
 539
 540 /*
 541  * 'mpu_bus' class
 542  * instance(s): mpu_private
 543  */
 544 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 545         .name   = "mpu_bus",
 546 };
 547
 548 /* mpu_private interface data */
 549 /* mpu -> mpu_private */
 550 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 551         .master         = &omap44xx_mpu_hwmod,
 552         .slave          = &omap44xx_mpu_private_hwmod,
 553         .clk            = "l3_div_ck",
 554         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 555 };
 556
 557 /* mpu_private slave ports */
 558 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 559         &omap44xx_mpu__mpu_private,
 560 };
 561
 562 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 563         .name           = "mpu_private",
 564         .class          = &omap44xx_mpu_bus_hwmod_class,
 565         .slaves         = omap44xx_mpu_private_slaves,
 566         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 567         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 568 };
 569
 570 /*
 571  * Modules omap_hwmod structures
 572  *
 573  * The following IPs are excluded for the moment because:
 574  * - They do not need an explicit SW control using omap_hwmod API.
 575  * - They still need to be validated with the driver
 576  *   properly adapted to omap_hwmod / omap_device
 577  *
 578  *  c2c
 579  *  c2c_target_fw
 580  *  cm_core
 581  *  cm_core_aon
 582  *  ctrl_module_core
 583  *  ctrl_module_pad_core
 584  *  ctrl_module_pad_wkup
 585  *  ctrl_module_wkup
 586  *  debugss
 587  *  efuse_ctrl_cust
 588  *  efuse_ctrl_std
 589  *  elm
 590  *  emif1
 591  *  emif2
 592  *  fdif
 593  *  gpmc
 594  *  gpu
 595  *  hdq1w
 596  *  hsi
 597  *  ocmc_ram
 598  *  ocp2scp_usb_phy
 599  *  ocp_wp_noc
 600  *  prcm_mpu
 601  *  prm
 602  *  scrm
 603  *  sl2if
 604  *  slimbus1
 605  *  slimbus2
 606  *  usb_host_fs
 607  *  usb_host_hs
 608  *  usb_phy_cm
 609  *  usb_tll_hs
 610  *  usim
 611  */
 612
 613 /*
 614  * 'aess' class
 615  * audio engine sub system
 616  */
 617
 618 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 619         .rev_offs       = 0x0000,
 620         .sysc_offs      = 0x0010,
 621         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 622         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 623                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 624         .sysc_fields    = &omap_hwmod_sysc_type2,
 625 };
 626
 627 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 628         .name   = "aess",
 629         .sysc   = &omap44xx_aess_sysc,
 630 };
 631
 632 /* aess */
 633 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 634         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 635 };
 636
 637 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 638         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 639         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 640         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 641         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 642         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 643         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 644         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 645         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 646 };
 647
 648 /* aess master ports */
 649 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 650         &omap44xx_aess__l4_abe,
 651 };
 652
 653 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 654         {
 655                 .pa_start       = 0x401f1000,
 656                 .pa_end         = 0x401f13ff,
 657                 .flags          = ADDR_TYPE_RT
 658         },
 659 };
 660
 661 /* l4_abe -> aess */
 662 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 663         .master         = &omap44xx_l4_abe_hwmod,
 664         .slave          = &omap44xx_aess_hwmod,
 665         .clk            = "ocp_abe_iclk",
 666         .addr           = omap44xx_aess_addrs,
 667         .addr_cnt       = ARRAY_SIZE(omap44xx_aess_addrs),
 668         .user           = OCP_USER_MPU,
 669 };
 670
 671 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 672         {
 673                 .pa_start       = 0x490f1000,
 674                 .pa_end         = 0x490f13ff,
 675                 .flags          = ADDR_TYPE_RT
 676         },
 677 };
 678
 679 /* l4_abe -> aess (dma) */
 680 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 681         .master         = &omap44xx_l4_abe_hwmod,
 682         .slave          = &omap44xx_aess_hwmod,
 683         .clk            = "ocp_abe_iclk",
 684         .addr           = omap44xx_aess_dma_addrs,
 685         .addr_cnt       = ARRAY_SIZE(omap44xx_aess_dma_addrs),
 686         .user           = OCP_USER_SDMA,
 687 };
 688
 689 /* aess slave ports */
 690 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 691         &omap44xx_l4_abe__aess,
 692         &omap44xx_l4_abe__aess_dma,
 693 };
 694
 695 static struct omap_hwmod omap44xx_aess_hwmod = {
 696         .name           = "aess",
 697         .class          = &omap44xx_aess_hwmod_class,
 698         .mpu_irqs       = omap44xx_aess_irqs,
 699         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_aess_irqs),
 700         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 701         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
 702         .main_clk       = "aess_fck",
 703         .prcm           = {
 704                 .omap4 = {
 705                         .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 706                 },
 707         },
 708         .slaves         = omap44xx_aess_slaves,
 709         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 710         .masters        = omap44xx_aess_masters,
 711         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 712         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 713 };
 714
 715 /*
 716  * 'bandgap' class
 717  * bangap reference for ldo regulators
 718  */
 719
 720 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 721         .name   = "bandgap",
 722 };
 723
 724 /* bandgap */
 725 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 726         { .role = "fclk", .clk = "bandgap_fclk" },
 727 };
 728
 729 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 730         .name           = "bandgap",
 731         .class          = &omap44xx_bandgap_hwmod_class,
 732         .prcm           = {
 733                 .omap4 = {
 734                         .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 735                 },
 736         },
 737         .opt_clks       = bandgap_opt_clks,
 738         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 739         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 740 };
 741
 742 /*
 743  * 'counter' class
 744  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 745  */
 746
 747 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 748         .rev_offs       = 0x0000,
 749         .sysc_offs      = 0x0004,
 750         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 751         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 752                            SIDLE_SMART_WKUP),
 753         .sysc_fields    = &omap_hwmod_sysc_type1,
 754 };
 755
 756 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 757         .name   = "counter",
 758         .sysc   = &omap44xx_counter_sysc,
 759 };
 760
 761 /* counter_32k */
 762 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 763 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 764         {
 765                 .pa_start       = 0x4a304000,
 766                 .pa_end         = 0x4a30401f,
 767                 .flags          = ADDR_TYPE_RT
 768         },
 769 };
 770
 771 /* l4_wkup -> counter_32k */
 772 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 773         .master         = &omap44xx_l4_wkup_hwmod,
 774         .slave          = &omap44xx_counter_32k_hwmod,
 775         .clk            = "l4_wkup_clk_mux_ck",
 776         .addr           = omap44xx_counter_32k_addrs,
 777         .addr_cnt       = ARRAY_SIZE(omap44xx_counter_32k_addrs),
 778         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 779 };
 780
 781 /* counter_32k slave ports */
 782 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 783         &omap44xx_l4_wkup__counter_32k,
 784 };
 785
 786 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 787         .name           = "counter_32k",
 788         .class          = &omap44xx_counter_hwmod_class,
 789         .flags          = HWMOD_SWSUP_SIDLE,
 790         .main_clk       = "sys_32k_ck",
 791         .prcm           = {
 792                 .omap4 = {
 793                         .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
 794                 },
 795         },
 796         .slaves         = omap44xx_counter_32k_slaves,
 797         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 798         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 799 };
 800
 801 /*
 802  * 'dma' class
 803  * dma controller for data exchange between memory to memory (i.e. internal or
 804  * external memory) and gp peripherals to memory or memory to gp peripherals
 805  */
 806
 807 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 808         .rev_offs       = 0x0000,
 809         .sysc_offs      = 0x002c,
 810         .syss_offs      = 0x0028,
 811         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 812                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 813                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 814                            SYSS_HAS_RESET_STATUS),
 815         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 816                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 817         .sysc_fields    = &omap_hwmod_sysc_type1,
 818 };
 819
 820 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 821         .name   = "dma",
 822         .sysc   = &omap44xx_dma_sysc,
 823 };
 824
 825 /* dma dev_attr */
 826 static struct omap_dma_dev_attr dma_dev_attr = {
 827         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 828                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 829         .lch_count      = 32,
 830 };
 831
 832 /* dma_system */
 833 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 834         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 835         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 836         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 837         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 838 };
 839
 840 /* dma_system master ports */
 841 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 842         &omap44xx_dma_system__l3_main_2,
 843 };
 844
 845 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 846         {
 847                 .pa_start       = 0x4a056000,
 848                 .pa_end         = 0x4a0560ff,
 849                 .flags          = ADDR_TYPE_RT
 850         },
 851 };
 852
 853 /* l4_cfg -> dma_system */
 854 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 855         .master         = &omap44xx_l4_cfg_hwmod,
 856         .slave          = &omap44xx_dma_system_hwmod,
 857         .clk            = "l4_div_ck",
 858         .addr           = omap44xx_dma_system_addrs,
 859         .addr_cnt       = ARRAY_SIZE(omap44xx_dma_system_addrs),
 860         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 861 };
 862
 863 /* dma_system slave ports */
 864 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 865         &omap44xx_l4_cfg__dma_system,
 866 };
 867
 868 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 869         .name           = "dma_system",
 870         .class          = &omap44xx_dma_hwmod_class,
 871         .mpu_irqs       = omap44xx_dma_system_irqs,
 872         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dma_system_irqs),
 873         .main_clk       = "l3_div_ck",
 874         .prcm = {
 875                 .omap4 = {
 876                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
 877                 },
 878         },
 879         .dev_attr       = &dma_dev_attr,
 880         .slaves         = omap44xx_dma_system_slaves,
 881         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 882         .masters        = omap44xx_dma_system_masters,
 883         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 884         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 885 };
 886
 887 /*
 888  * 'dmic' class
 889  * digital microphone controller
 890  */
 891
 892 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 893         .rev_offs       = 0x0000,
 894         .sysc_offs      = 0x0010,
 895         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 896                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 897         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 898                            SIDLE_SMART_WKUP),
 899         .sysc_fields    = &omap_hwmod_sysc_type2,
 900 };
 901
 902 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 903         .name   = "dmic",
 904         .sysc   = &omap44xx_dmic_sysc,
 905 };
 906
 907 /* dmic */
 908 static struct omap_hwmod omap44xx_dmic_hwmod;
 909 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 910         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 911 };
 912
 913 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 914         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 915 };
 916
 917 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
 918         {
 919                 .pa_start       = 0x4012e000,
 920                 .pa_end         = 0x4012e07f,
 921                 .flags          = ADDR_TYPE_RT
 922         },
 923 };
 924
 925 /* l4_abe -> dmic */
 926 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
 927         .master         = &omap44xx_l4_abe_hwmod,
 928         .slave          = &omap44xx_dmic_hwmod,
 929         .clk            = "ocp_abe_iclk",
 930         .addr           = omap44xx_dmic_addrs,
 931         .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_addrs),
 932         .user           = OCP_USER_MPU,
 933 };
 934
 935 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
 936         {
 937                 .pa_start       = 0x4902e000,
 938                 .pa_end         = 0x4902e07f,
 939                 .flags          = ADDR_TYPE_RT
 940         },
 941 };
 942
 943 /* l4_abe -> dmic (dma) */
 944 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
 945         .master         = &omap44xx_l4_abe_hwmod,
 946         .slave          = &omap44xx_dmic_hwmod,
 947         .clk            = "ocp_abe_iclk",
 948         .addr           = omap44xx_dmic_dma_addrs,
 949         .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
 950         .user           = OCP_USER_SDMA,
 951 };
 952
 953 /* dmic slave ports */
 954 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
 955         &omap44xx_l4_abe__dmic,
 956         &omap44xx_l4_abe__dmic_dma,
 957 };
 958
 959 static struct omap_hwmod omap44xx_dmic_hwmod = {
 960         .name           = "dmic",
 961         .class          = &omap44xx_dmic_hwmod_class,
 962         .mpu_irqs       = omap44xx_dmic_irqs,
 963         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmic_irqs),
 964         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 965         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
 966         .main_clk       = "dmic_fck",
 967         .prcm           = {
 968                 .omap4 = {
 969                         .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
 970                 },
 971         },
 972         .slaves         = omap44xx_dmic_slaves,
 973         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
 974         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 975 };
 976
 977 /*
 978  * 'dsp' class
 979  * dsp sub-system
 980  */
 981
 982 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 983         .name   = "dsp",
 984 };
 985
 986 /* dsp */
 987 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 988         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 989 };
 990
 991 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 992         { .name = "mmu_cache", .rst_shift = 1 },
 993 };
 994
 995 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
 996         { .name = "dsp", .rst_shift = 0 },
 997 };
 998
 999 /* dsp -> iva */
1000 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1001         .master         = &omap44xx_dsp_hwmod,
1002         .slave          = &omap44xx_iva_hwmod,
1003         .clk            = "dpll_iva_m5x2_ck",
1004 };
1005
1006 /* dsp master ports */
1007 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1008         &omap44xx_dsp__l3_main_1,
1009         &omap44xx_dsp__l4_abe,
1010         &omap44xx_dsp__iva,
1011 };
1012
1013 /* l4_cfg -> dsp */
1014 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1015         .master         = &omap44xx_l4_cfg_hwmod,
1016         .slave          = &omap44xx_dsp_hwmod,
1017         .clk            = "l4_div_ck",
1018         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1019 };
1020
1021 /* dsp slave ports */
1022 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1023         &omap44xx_l4_cfg__dsp,
1024 };
1025
1026 /* Pseudo hwmod for reset control purpose only */
1027 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1028         .name           = "dsp_c0",
1029         .class          = &omap44xx_dsp_hwmod_class,
1030         .flags          = HWMOD_INIT_NO_RESET,
1031         .rst_lines      = omap44xx_dsp_c0_resets,
1032         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1033         .prcm = {
1034                 .omap4 = {
1035                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1036                 },
1037         },
1038         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1039 };
1040
1041 static struct omap_hwmod omap44xx_dsp_hwmod = {
1042         .name           = "dsp",
1043         .class          = &omap44xx_dsp_hwmod_class,
1044         .mpu_irqs       = omap44xx_dsp_irqs,
1045         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dsp_irqs),
1046         .rst_lines      = omap44xx_dsp_resets,
1047         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1048         .main_clk       = "dsp_fck",
1049         .prcm = {
1050                 .omap4 = {
1051                         .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1052                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1053                 },
1054         },
1055         .slaves         = omap44xx_dsp_slaves,
1056         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1057         .masters        = omap44xx_dsp_masters,
1058         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1059         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1060 };
1061
1062 /*
1063  * 'dss' class
1064  * display sub-system
1065  */
1066
1067 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1068         .rev_offs       = 0x0000,
1069         .syss_offs      = 0x0014,
1070         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1071 };
1072
1073 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1074         .name   = "dss",
1075         .sysc   = &omap44xx_dss_sysc,
1076 };
1077
1078 /* dss */
1079 /* dss master ports */
1080 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1081         &omap44xx_dss__l3_main_1,
1082 };
1083
1084 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1085         {
1086                 .pa_start       = 0x58000000,
1087                 .pa_end         = 0x5800007f,
1088                 .flags          = ADDR_TYPE_RT
1089         },
1090 };
1091
1092 /* l3_main_2 -> dss */
1093 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1094         .master         = &omap44xx_l3_main_2_hwmod,
1095         .slave          = &omap44xx_dss_hwmod,
1096         .clk            = "l3_div_ck",
1097         .addr           = omap44xx_dss_dma_addrs,
1098         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dma_addrs),
1099         .user           = OCP_USER_SDMA,
1100 };
1101
1102 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1103         {
1104                 .pa_start       = 0x48040000,
1105                 .pa_end         = 0x4804007f,
1106                 .flags          = ADDR_TYPE_RT
1107         },
1108 };
1109
1110 /* l4_per -> dss */
1111 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1112         .master         = &omap44xx_l4_per_hwmod,
1113         .slave          = &omap44xx_dss_hwmod,
1114         .clk            = "l4_div_ck",
1115         .addr           = omap44xx_dss_addrs,
1116         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_addrs),
1117         .user           = OCP_USER_MPU,
1118 };
1119
1120 /* dss slave ports */
1121 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1122         &omap44xx_l3_main_2__dss,
1123         &omap44xx_l4_per__dss,
1124 };
1125
1126 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1127         { .role = "sys_clk", .clk = "dss_sys_clk" },
1128         { .role = "tv_clk", .clk = "dss_tv_clk" },
1129         { .role = "dss_clk", .clk = "dss_dss_clk" },
1130         { .role = "video_clk", .clk = "dss_48mhz_clk" },
1131 };
1132
1133 static struct omap_hwmod omap44xx_dss_hwmod = {
1134         .name           = "dss_core",
1135         .class          = &omap44xx_dss_hwmod_class,
1136         .main_clk       = "dss_fck",
1137         .prcm = {
1138                 .omap4 = {
1139                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1140                 },
1141         },
1142         .opt_clks       = dss_opt_clks,
1143         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1144         .slaves         = omap44xx_dss_slaves,
1145         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1146         .masters        = omap44xx_dss_masters,
1147         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1148         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1149 };
1150
1151 /*
1152  * 'dispc' class
1153  * display controller
1154  */
1155
1156 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1157         .rev_offs       = 0x0000,
1158         .sysc_offs      = 0x0010,
1159         .syss_offs      = 0x0014,
1160         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1161                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1162                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1163                            SYSS_HAS_RESET_STATUS),
1164         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1165                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1166         .sysc_fields    = &omap_hwmod_sysc_type1,
1167 };
1168
1169 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1170         .name   = "dispc",
1171         .sysc   = &omap44xx_dispc_sysc,
1172 };
1173
1174 /* dss_dispc */
1175 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1176 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1177         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1178 };
1179
1180 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1181         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1182 };
1183
1184 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1185         {
1186                 .pa_start       = 0x58001000,
1187                 .pa_end         = 0x58001fff,
1188                 .flags          = ADDR_TYPE_RT
1189         },
1190 };
1191
1192 /* l3_main_2 -> dss_dispc */
1193 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1194         .master         = &omap44xx_l3_main_2_hwmod,
1195         .slave          = &omap44xx_dss_dispc_hwmod,
1196         .clk            = "l3_div_ck",
1197         .addr           = omap44xx_dss_dispc_dma_addrs,
1198         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
1199         .user           = OCP_USER_SDMA,
1200 };
1201
1202 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1203         {
1204                 .pa_start       = 0x48041000,
1205                 .pa_end         = 0x48041fff,
1206                 .flags          = ADDR_TYPE_RT
1207         },
1208 };
1209
1210 /* l4_per -> dss_dispc */
1211 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1212         .master         = &omap44xx_l4_per_hwmod,
1213         .slave          = &omap44xx_dss_dispc_hwmod,
1214         .clk            = "l4_div_ck",
1215         .addr           = omap44xx_dss_dispc_addrs,
1216         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
1217         .user           = OCP_USER_MPU,
1218 };
1219
1220 /* dss_dispc slave ports */
1221 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1222         &omap44xx_l3_main_2__dss_dispc,
1223         &omap44xx_l4_per__dss_dispc,
1224 };
1225
1226 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1227         .name           = "dss_dispc",
1228         .class          = &omap44xx_dispc_hwmod_class,
1229         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1230         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
1231         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1232         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
1233         .main_clk       = "dss_fck",
1234         .prcm = {
1235                 .omap4 = {
1236                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1237                 },
1238         },
1239         .slaves         = omap44xx_dss_dispc_slaves,
1240         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1241         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1242 };
1243
1244 /*
1245  * 'dsi' class
1246  * display serial interface controller
1247  */
1248
1249 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1250         .rev_offs       = 0x0000,
1251         .sysc_offs      = 0x0010,
1252         .syss_offs      = 0x0014,
1253         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1254                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1255                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1256         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1257         .sysc_fields    = &omap_hwmod_sysc_type1,
1258 };
1259
1260 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1261         .name   = "dsi",
1262         .sysc   = &omap44xx_dsi_sysc,
1263 };
1264
1265 /* dss_dsi1 */
1266 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1267 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1268         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1269 };
1270
1271 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1272         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1273 };
1274
1275 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1276         {
1277                 .pa_start       = 0x58004000,
1278                 .pa_end         = 0x580041ff,
1279                 .flags          = ADDR_TYPE_RT
1280         },
1281 };
1282
1283 /* l3_main_2 -> dss_dsi1 */
1284 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1285         .master         = &omap44xx_l3_main_2_hwmod,
1286         .slave          = &omap44xx_dss_dsi1_hwmod,
1287         .clk            = "l3_div_ck",
1288         .addr           = omap44xx_dss_dsi1_dma_addrs,
1289         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
1290         .user           = OCP_USER_SDMA,
1291 };
1292
1293 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1294         {
1295                 .pa_start       = 0x48044000,
1296                 .pa_end         = 0x480441ff,
1297                 .flags          = ADDR_TYPE_RT
1298         },
1299 };
1300
1301 /* l4_per -> dss_dsi1 */
1302 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1303         .master         = &omap44xx_l4_per_hwmod,
1304         .slave          = &omap44xx_dss_dsi1_hwmod,
1305         .clk            = "l4_div_ck",
1306         .addr           = omap44xx_dss_dsi1_addrs,
1307         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
1308         .user           = OCP_USER_MPU,
1309 };
1310
1311 /* dss_dsi1 slave ports */
1312 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1313         &omap44xx_l3_main_2__dss_dsi1,
1314         &omap44xx_l4_per__dss_dsi1,
1315 };
1316
1317 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1318         .name           = "dss_dsi1",
1319         .class          = &omap44xx_dsi_hwmod_class,
1320         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1321         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
1322         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1323         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
1324         .main_clk       = "dss_fck",
1325         .prcm = {
1326                 .omap4 = {
1327                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1328                 },
1329         },
1330         .slaves         = omap44xx_dss_dsi1_slaves,
1331         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1332         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1333 };
1334
1335 /* dss_dsi2 */
1336 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1337 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1338         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1339 };
1340
1341 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1342         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1343 };
1344
1345 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1346         {
1347                 .pa_start       = 0x58005000,
1348                 .pa_end         = 0x580051ff,
1349                 .flags          = ADDR_TYPE_RT
1350         },
1351 };
1352
1353 /* l3_main_2 -> dss_dsi2 */
1354 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1355         .master         = &omap44xx_l3_main_2_hwmod,
1356         .slave          = &omap44xx_dss_dsi2_hwmod,
1357         .clk            = "l3_div_ck",
1358         .addr           = omap44xx_dss_dsi2_dma_addrs,
1359         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
1360         .user           = OCP_USER_SDMA,
1361 };
1362
1363 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1364         {
1365                 .pa_start       = 0x48045000,
1366                 .pa_end         = 0x480451ff,
1367                 .flags          = ADDR_TYPE_RT
1368         },
1369 };
1370
1371 /* l4_per -> dss_dsi2 */
1372 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1373         .master         = &omap44xx_l4_per_hwmod,
1374         .slave          = &omap44xx_dss_dsi2_hwmod,
1375         .clk            = "l4_div_ck",
1376         .addr           = omap44xx_dss_dsi2_addrs,
1377         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
1378         .user           = OCP_USER_MPU,
1379 };
1380
1381 /* dss_dsi2 slave ports */
1382 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1383         &omap44xx_l3_main_2__dss_dsi2,
1384         &omap44xx_l4_per__dss_dsi2,
1385 };
1386
1387 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1388         .name           = "dss_dsi2",
1389         .class          = &omap44xx_dsi_hwmod_class,
1390         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1391         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
1392         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1393         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
1394         .main_clk       = "dss_fck",
1395         .prcm = {
1396                 .omap4 = {
1397                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1398                 },
1399         },
1400         .slaves         = omap44xx_dss_dsi2_slaves,
1401         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1402         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1403 };
1404
1405 /*
1406  * 'hdmi' class
1407  * hdmi controller
1408  */
1409
1410 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1411         .rev_offs       = 0x0000,
1412         .sysc_offs      = 0x0010,
1413         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1414                            SYSC_HAS_SOFTRESET),
1415         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1416                            SIDLE_SMART_WKUP),
1417         .sysc_fields    = &omap_hwmod_sysc_type2,
1418 };
1419
1420 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1421         .name   = "hdmi",
1422         .sysc   = &omap44xx_hdmi_sysc,
1423 };
1424
1425 /* dss_hdmi */
1426 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1427 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1428         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1429 };
1430
1431 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1432         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1433 };
1434
1435 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1436         {
1437                 .pa_start       = 0x58006000,
1438                 .pa_end         = 0x58006fff,
1439                 .flags          = ADDR_TYPE_RT
1440         },
1441 };
1442
1443 /* l3_main_2 -> dss_hdmi */
1444 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1445         .master         = &omap44xx_l3_main_2_hwmod,
1446         .slave          = &omap44xx_dss_hdmi_hwmod,
1447         .clk            = "l3_div_ck",
1448         .addr           = omap44xx_dss_hdmi_dma_addrs,
1449         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
1450         .user           = OCP_USER_SDMA,
1451 };
1452
1453 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1454         {
1455                 .pa_start       = 0x48046000,
1456                 .pa_end         = 0x48046fff,
1457                 .flags          = ADDR_TYPE_RT
1458         },
1459 };
1460
1461 /* l4_per -> dss_hdmi */
1462 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1463         .master         = &omap44xx_l4_per_hwmod,
1464         .slave          = &omap44xx_dss_hdmi_hwmod,
1465         .clk            = "l4_div_ck",
1466         .addr           = omap44xx_dss_hdmi_addrs,
1467         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
1468         .user           = OCP_USER_MPU,
1469 };
1470
1471 /* dss_hdmi slave ports */
1472 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1473         &omap44xx_l3_main_2__dss_hdmi,
1474         &omap44xx_l4_per__dss_hdmi,
1475 };
1476
1477 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1478         .name           = "dss_hdmi",
1479         .class          = &omap44xx_hdmi_hwmod_class,
1480         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1481         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
1482         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1483         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
1484         .main_clk       = "dss_fck",
1485         .prcm = {
1486                 .omap4 = {
1487                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1488                 },
1489         },
1490         .slaves         = omap44xx_dss_hdmi_slaves,
1491         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1492         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1493 };
1494
1495 /*
1496  * 'rfbi' class
1497  * remote frame buffer interface
1498  */
1499
1500 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1501         .rev_offs       = 0x0000,
1502         .sysc_offs      = 0x0010,
1503         .syss_offs      = 0x0014,
1504         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1505                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1506         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1507         .sysc_fields    = &omap_hwmod_sysc_type1,
1508 };
1509
1510 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1511         .name   = "rfbi",
1512         .sysc   = &omap44xx_rfbi_sysc,
1513 };
1514
1515 /* dss_rfbi */
1516 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1517 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1518         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1519 };
1520
1521 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1522         {
1523                 .pa_start       = 0x58002000,
1524                 .pa_end         = 0x580020ff,
1525                 .flags          = ADDR_TYPE_RT
1526         },
1527 };
1528
1529 /* l3_main_2 -> dss_rfbi */
1530 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1531         .master         = &omap44xx_l3_main_2_hwmod,
1532         .slave          = &omap44xx_dss_rfbi_hwmod,
1533         .clk            = "l3_div_ck",
1534         .addr           = omap44xx_dss_rfbi_dma_addrs,
1535         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
1536         .user           = OCP_USER_SDMA,
1537 };
1538
1539 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1540         {
1541                 .pa_start       = 0x48042000,
1542                 .pa_end         = 0x480420ff,
1543                 .flags          = ADDR_TYPE_RT
1544         },
1545 };
1546
1547 /* l4_per -> dss_rfbi */
1548 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1549         .master         = &omap44xx_l4_per_hwmod,
1550         .slave          = &omap44xx_dss_rfbi_hwmod,
1551         .clk            = "l4_div_ck",
1552         .addr           = omap44xx_dss_rfbi_addrs,
1553         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
1554         .user           = OCP_USER_MPU,
1555 };
1556
1557 /* dss_rfbi slave ports */
1558 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1559         &omap44xx_l3_main_2__dss_rfbi,
1560         &omap44xx_l4_per__dss_rfbi,
1561 };
1562
1563 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1564         .name           = "dss_rfbi",
1565         .class          = &omap44xx_rfbi_hwmod_class,
1566         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1567         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
1568         .main_clk       = "dss_fck",
1569         .prcm = {
1570                 .omap4 = {
1571                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1572                 },
1573         },
1574         .slaves         = omap44xx_dss_rfbi_slaves,
1575         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1576         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1577 };
1578
1579 /*
1580  * 'venc' class
1581  * video encoder
1582  */
1583
1584 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1585         .name   = "venc",
1586 };
1587
1588 /* dss_venc */
1589 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1590 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1591         {
1592                 .pa_start       = 0x58003000,
1593                 .pa_end         = 0x580030ff,
1594                 .flags          = ADDR_TYPE_RT
1595         },
1596 };
1597
1598 /* l3_main_2 -> dss_venc */
1599 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1600         .master         = &omap44xx_l3_main_2_hwmod,
1601         .slave          = &omap44xx_dss_venc_hwmod,
1602         .clk            = "l3_div_ck",
1603         .addr           = omap44xx_dss_venc_dma_addrs,
1604         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
1605         .user           = OCP_USER_SDMA,
1606 };
1607
1608 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1609         {
1610                 .pa_start       = 0x48043000,
1611                 .pa_end         = 0x480430ff,
1612                 .flags          = ADDR_TYPE_RT
1613         },
1614 };
1615
1616 /* l4_per -> dss_venc */
1617 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1618         .master         = &omap44xx_l4_per_hwmod,
1619         .slave          = &omap44xx_dss_venc_hwmod,
1620         .clk            = "l4_div_ck",
1621         .addr           = omap44xx_dss_venc_addrs,
1622         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_addrs),
1623         .user           = OCP_USER_MPU,
1624 };
1625
1626 /* dss_venc slave ports */
1627 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1628         &omap44xx_l3_main_2__dss_venc,
1629         &omap44xx_l4_per__dss_venc,
1630 };
1631
1632 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1633         .name           = "dss_venc",
1634         .class          = &omap44xx_venc_hwmod_class,
1635         .main_clk       = "dss_fck",
1636         .prcm = {
1637                 .omap4 = {
1638                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1639                 },
1640         },
1641         .slaves         = omap44xx_dss_venc_slaves,
1642         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1643         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1644 };
1645
1646 /*
1647  * 'gpio' class
1648  * general purpose io module
1649  */
1650
1651 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1652         .rev_offs       = 0x0000,
1653         .sysc_offs      = 0x0010,
1654         .syss_offs      = 0x0114,
1655         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1656                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1657                            SYSS_HAS_RESET_STATUS),
1658         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1659                            SIDLE_SMART_WKUP),
1660         .sysc_fields    = &omap_hwmod_sysc_type1,
1661 };
1662
1663 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1664         .name   = "gpio",
1665         .sysc   = &omap44xx_gpio_sysc,
1666         .rev    = 2,
1667 };
1668
1669 /* gpio dev_attr */
1670 static struct omap_gpio_dev_attr gpio_dev_attr = {
1671         .bank_width     = 32,
1672         .dbck_flag      = true,
1673 };
1674
1675 /* gpio1 */
1676 static struct omap_hwmod omap44xx_gpio1_hwmod;
1677 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1678         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1679 };
1680
1681 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1682         {
1683                 .pa_start       = 0x4a310000,
1684                 .pa_end         = 0x4a3101ff,
1685                 .flags          = ADDR_TYPE_RT
1686         },
1687 };
1688
1689 /* l4_wkup -> gpio1 */
1690 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1691         .master         = &omap44xx_l4_wkup_hwmod,
1692         .slave          = &omap44xx_gpio1_hwmod,
1693         .clk            = "l4_wkup_clk_mux_ck",
1694         .addr           = omap44xx_gpio1_addrs,
1695         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio1_addrs),
1696         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1697 };
1698
1699 /* gpio1 slave ports */
1700 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1701         &omap44xx_l4_wkup__gpio1,
1702 };
1703
1704 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1705         { .role = "dbclk", .clk = "gpio1_dbclk" },
1706 };
1707
1708 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1709         .name           = "gpio1",
1710         .class          = &omap44xx_gpio_hwmod_class,
1711         .mpu_irqs       = omap44xx_gpio1_irqs,
1712         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio1_irqs),
1713         .main_clk       = "gpio1_ick",
1714         .prcm = {
1715                 .omap4 = {
1716                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1717                 },
1718         },
1719         .opt_clks       = gpio1_opt_clks,
1720         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1721         .dev_attr       = &gpio_dev_attr,
1722         .slaves         = omap44xx_gpio1_slaves,
1723         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1724         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1725 };
1726
1727 /* gpio2 */
1728 static struct omap_hwmod omap44xx_gpio2_hwmod;
1729 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1730         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1731 };
1732
1733 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1734         {
1735                 .pa_start       = 0x48055000,
1736                 .pa_end         = 0x480551ff,
1737                 .flags          = ADDR_TYPE_RT
1738         },
1739 };
1740
1741 /* l4_per -> gpio2 */
1742 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1743         .master         = &omap44xx_l4_per_hwmod,
1744         .slave          = &omap44xx_gpio2_hwmod,
1745         .clk            = "l4_div_ck",
1746         .addr           = omap44xx_gpio2_addrs,
1747         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio2_addrs),
1748         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1749 };
1750
1751 /* gpio2 slave ports */
1752 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1753         &omap44xx_l4_per__gpio2,
1754 };
1755
1756 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1757         { .role = "dbclk", .clk = "gpio2_dbclk" },
1758 };
1759
1760 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1761         .name           = "gpio2",
1762         .class          = &omap44xx_gpio_hwmod_class,
1763         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1764         .mpu_irqs       = omap44xx_gpio2_irqs,
1765         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio2_irqs),
1766         .main_clk       = "gpio2_ick",
1767         .prcm = {
1768                 .omap4 = {
1769                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1770                 },
1771         },
1772         .opt_clks       = gpio2_opt_clks,
1773         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1774         .dev_attr       = &gpio_dev_attr,
1775         .slaves         = omap44xx_gpio2_slaves,
1776         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1777         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1778 };
1779
1780 /* gpio3 */
1781 static struct omap_hwmod omap44xx_gpio3_hwmod;
1782 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1783         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1784 };
1785
1786 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1787         {
1788                 .pa_start       = 0x48057000,
1789                 .pa_end         = 0x480571ff,
1790                 .flags          = ADDR_TYPE_RT
1791         },
1792 };
1793
1794 /* l4_per -> gpio3 */
1795 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1796         .master         = &omap44xx_l4_per_hwmod,
1797         .slave          = &omap44xx_gpio3_hwmod,
1798         .clk            = "l4_div_ck",
1799         .addr           = omap44xx_gpio3_addrs,
1800         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio3_addrs),
1801         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1802 };
1803
1804 /* gpio3 slave ports */
1805 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1806         &omap44xx_l4_per__gpio3,
1807 };
1808
1809 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1810         { .role = "dbclk", .clk = "gpio3_dbclk" },
1811 };
1812
1813 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1814         .name           = "gpio3",
1815         .class          = &omap44xx_gpio_hwmod_class,
1816         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1817         .mpu_irqs       = omap44xx_gpio3_irqs,
1818         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio3_irqs),
1819         .main_clk       = "gpio3_ick",
1820         .prcm = {
1821                 .omap4 = {
1822                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1823                 },
1824         },
1825         .opt_clks       = gpio3_opt_clks,
1826         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1827         .dev_attr       = &gpio_dev_attr,
1828         .slaves         = omap44xx_gpio3_slaves,
1829         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1830         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1831 };
1832
1833 /* gpio4 */
1834 static struct omap_hwmod omap44xx_gpio4_hwmod;
1835 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1836         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1837 };
1838
1839 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1840         {
1841                 .pa_start       = 0x48059000,
1842                 .pa_end         = 0x480591ff,
1843                 .flags          = ADDR_TYPE_RT
1844         },
1845 };
1846
1847 /* l4_per -> gpio4 */
1848 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1849         .master         = &omap44xx_l4_per_hwmod,
1850         .slave          = &omap44xx_gpio4_hwmod,
1851         .clk            = "l4_div_ck",
1852         .addr           = omap44xx_gpio4_addrs,
1853         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio4_addrs),
1854         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1855 };
1856
1857 /* gpio4 slave ports */
1858 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1859         &omap44xx_l4_per__gpio4,
1860 };
1861
1862 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1863         { .role = "dbclk", .clk = "gpio4_dbclk" },
1864 };
1865
1866 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1867         .name           = "gpio4",
1868         .class          = &omap44xx_gpio_hwmod_class,
1869         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1870         .mpu_irqs       = omap44xx_gpio4_irqs,
1871         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio4_irqs),
1872         .main_clk       = "gpio4_ick",
1873         .prcm = {
1874                 .omap4 = {
1875                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1876                 },
1877         },
1878         .opt_clks       = gpio4_opt_clks,
1879         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1880         .dev_attr       = &gpio_dev_attr,
1881         .slaves         = omap44xx_gpio4_slaves,
1882         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
1883         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1884 };
1885
1886 /* gpio5 */
1887 static struct omap_hwmod omap44xx_gpio5_hwmod;
1888 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1889         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1890 };
1891
1892 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1893         {
1894                 .pa_start       = 0x4805b000,
1895                 .pa_end         = 0x4805b1ff,
1896                 .flags          = ADDR_TYPE_RT
1897         },
1898 };
1899
1900 /* l4_per -> gpio5 */
1901 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1902         .master         = &omap44xx_l4_per_hwmod,
1903         .slave          = &omap44xx_gpio5_hwmod,
1904         .clk            = "l4_div_ck",
1905         .addr           = omap44xx_gpio5_addrs,
1906         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio5_addrs),
1907         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1908 };
1909
1910 /* gpio5 slave ports */
1911 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1912         &omap44xx_l4_per__gpio5,
1913 };
1914
1915 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1916         { .role = "dbclk", .clk = "gpio5_dbclk" },
1917 };
1918
1919 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1920         .name           = "gpio5",
1921         .class          = &omap44xx_gpio_hwmod_class,
1922         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1923         .mpu_irqs       = omap44xx_gpio5_irqs,
1924         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio5_irqs),
1925         .main_clk       = "gpio5_ick",
1926         .prcm = {
1927                 .omap4 = {
1928                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1929                 },
1930         },
1931         .opt_clks       = gpio5_opt_clks,
1932         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1933         .dev_attr       = &gpio_dev_attr,
1934         .slaves         = omap44xx_gpio5_slaves,
1935         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
1936         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1937 };
1938
1939 /* gpio6 */
1940 static struct omap_hwmod omap44xx_gpio6_hwmod;
1941 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1942         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1943 };
1944
1945 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1946         {
1947                 .pa_start       = 0x4805d000,
1948                 .pa_end         = 0x4805d1ff,
1949                 .flags          = ADDR_TYPE_RT
1950         },
1951 };
1952
1953 /* l4_per -> gpio6 */
1954 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1955         .master         = &omap44xx_l4_per_hwmod,
1956         .slave          = &omap44xx_gpio6_hwmod,
1957         .clk            = "l4_div_ck",
1958         .addr           = omap44xx_gpio6_addrs,
1959         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio6_addrs),
1960         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1961 };
1962
1963 /* gpio6 slave ports */
1964 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1965         &omap44xx_l4_per__gpio6,
1966 };
1967
1968 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1969         { .role = "dbclk", .clk = "gpio6_dbclk" },
1970 };
1971
1972 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1973         .name           = "gpio6",
1974         .class          = &omap44xx_gpio_hwmod_class,
1975         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1976         .mpu_irqs       = omap44xx_gpio6_irqs,
1977         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio6_irqs),
1978         .main_clk       = "gpio6_ick",
1979         .prcm = {
1980                 .omap4 = {
1981                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1982                 },
1983         },
1984         .opt_clks       = gpio6_opt_clks,
1985         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1986         .dev_attr       = &gpio_dev_attr,
1987         .slaves         = omap44xx_gpio6_slaves,
1988         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
1989         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1990 };
1991
1992 /*
1993  * 'hsi' class
1994  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1995  * serial if)
1996  */
1997
1998 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1999         .rev_offs       = 0x0000,
2000         .sysc_offs      = 0x0010,
2001         .syss_offs      = 0x0014,
2002         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2003                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2004                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2005         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2006                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2007                            MSTANDBY_SMART),
2008         .sysc_fields    = &omap_hwmod_sysc_type1,
2009 };
2010
2011 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2012         .name   = "hsi",
2013         .sysc   = &omap44xx_hsi_sysc,
2014 };
2015
2016 /* hsi */
2017 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2018         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2019         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2020         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2021 };
2022
2023 /* hsi master ports */
2024 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2025         &omap44xx_hsi__l3_main_2,
2026 };
2027
2028 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2029         {
2030                 .pa_start       = 0x4a058000,
2031                 .pa_end         = 0x4a05bfff,
2032                 .flags          = ADDR_TYPE_RT
2033         },
2034 };
2035
2036 /* l4_cfg -> hsi */
2037 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2038         .master         = &omap44xx_l4_cfg_hwmod,
2039         .slave          = &omap44xx_hsi_hwmod,
2040         .clk            = "l4_div_ck",
2041         .addr           = omap44xx_hsi_addrs,
2042         .addr_cnt       = ARRAY_SIZE(omap44xx_hsi_addrs),
2043         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2044 };
2045
2046 /* hsi slave ports */
2047 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2048         &omap44xx_l4_cfg__hsi,
2049 };
2050
2051 static struct omap_hwmod omap44xx_hsi_hwmod = {
2052         .name           = "hsi",
2053         .class          = &omap44xx_hsi_hwmod_class,
2054         .mpu_irqs       = omap44xx_hsi_irqs,
2055         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_hsi_irqs),
2056         .main_clk       = "hsi_fck",
2057         .prcm           = {
2058                 .omap4 = {
2059                         .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2060                 },
2061         },
2062         .slaves         = omap44xx_hsi_slaves,
2063         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2064         .masters        = omap44xx_hsi_masters,
2065         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2066         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2067 };
2068
2069 /*
2070  * 'i2c' class
2071  * multimaster high-speed i2c controller
2072  */
2073
2074 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2075         .sysc_offs      = 0x0010,
2076         .syss_offs      = 0x0090,
2077         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2078                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2079                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2080         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2081                            SIDLE_SMART_WKUP),
2082         .sysc_fields    = &omap_hwmod_sysc_type1,
2083 };
2084
2085 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2086         .name   = "i2c",
2087         .sysc   = &omap44xx_i2c_sysc,
2088 };
2089
2090 /* i2c1 */
2091 static struct omap_hwmod omap44xx_i2c1_hwmod;
2092 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2093         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2094 };
2095
2096 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2097         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2098         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2099 };
2100
2101 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2102         {
2103                 .pa_start       = 0x48070000,
2104                 .pa_end         = 0x480700ff,
2105                 .flags          = ADDR_TYPE_RT
2106         },
2107 };
2108
2109 /* l4_per -> i2c1 */
2110 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2111         .master         = &omap44xx_l4_per_hwmod,
2112         .slave          = &omap44xx_i2c1_hwmod,
2113         .clk            = "l4_div_ck",
2114         .addr           = omap44xx_i2c1_addrs,
2115         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c1_addrs),
2116         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2117 };
2118
2119 /* i2c1 slave ports */
2120 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2121         &omap44xx_l4_per__i2c1,
2122 };
2123
2124 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2125         .name           = "i2c1",
2126         .class          = &omap44xx_i2c_hwmod_class,
2127         .flags          = HWMOD_INIT_NO_RESET,
2128         .mpu_irqs       = omap44xx_i2c1_irqs,
2129         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c1_irqs),
2130         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2131         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
2132         .main_clk       = "i2c1_fck",
2133         .prcm = {
2134                 .omap4 = {
2135                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
2136                 },
2137         },
2138         .slaves         = omap44xx_i2c1_slaves,
2139         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2140         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2141 };
2142
2143 /* i2c2 */
2144 static struct omap_hwmod omap44xx_i2c2_hwmod;
2145 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2146         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2147 };
2148
2149 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2150         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2151         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2152 };
2153
2154 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2155         {
2156                 .pa_start       = 0x48072000,
2157                 .pa_end         = 0x480720ff,
2158                 .flags          = ADDR_TYPE_RT
2159         },
2160 };
2161
2162 /* l4_per -> i2c2 */
2163 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2164         .master         = &omap44xx_l4_per_hwmod,
2165         .slave          = &omap44xx_i2c2_hwmod,
2166         .clk            = "l4_div_ck",
2167         .addr           = omap44xx_i2c2_addrs,
2168         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c2_addrs),
2169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2170 };
2171
2172 /* i2c2 slave ports */
2173 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2174         &omap44xx_l4_per__i2c2,
2175 };
2176
2177 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2178         .name           = "i2c2",
2179         .class          = &omap44xx_i2c_hwmod_class,
2180         .flags          = HWMOD_INIT_NO_RESET,
2181         .mpu_irqs       = omap44xx_i2c2_irqs,
2182         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c2_irqs),
2183         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2184         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
2185         .main_clk       = "i2c2_fck",
2186         .prcm = {
2187                 .omap4 = {
2188                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
2189                 },
2190         },
2191         .slaves         = omap44xx_i2c2_slaves,
2192         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2193         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2194 };
2195
2196 /* i2c3 */
2197 static struct omap_hwmod omap44xx_i2c3_hwmod;
2198 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2199         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2200 };
2201
2202 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2203         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2204         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2205 };
2206
2207 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2208         {
2209                 .pa_start       = 0x48060000,
2210                 .pa_end         = 0x480600ff,
2211                 .flags          = ADDR_TYPE_RT
2212         },
2213 };
2214
2215 /* l4_per -> i2c3 */
2216 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2217         .master         = &omap44xx_l4_per_hwmod,
2218         .slave          = &omap44xx_i2c3_hwmod,
2219         .clk            = "l4_div_ck",
2220         .addr           = omap44xx_i2c3_addrs,
2221         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c3_addrs),
2222         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2223 };
2224
2225 /* i2c3 slave ports */
2226 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2227         &omap44xx_l4_per__i2c3,
2228 };
2229
2230 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2231         .name           = "i2c3",
2232         .class          = &omap44xx_i2c_hwmod_class,
2233         .flags          = HWMOD_INIT_NO_RESET,
2234         .mpu_irqs       = omap44xx_i2c3_irqs,
2235         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c3_irqs),
2236         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2237         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
2238         .main_clk       = "i2c3_fck",
2239         .prcm = {
2240                 .omap4 = {
2241                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
2242                 },
2243         },
2244         .slaves         = omap44xx_i2c3_slaves,
2245         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2246         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2247 };
2248
2249 /* i2c4 */
2250 static struct omap_hwmod omap44xx_i2c4_hwmod;
2251 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2252         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2253 };
2254
2255 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2256         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2257         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2258 };
2259
2260 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2261         {
2262                 .pa_start       = 0x48350000,
2263                 .pa_end         = 0x483500ff,
2264                 .flags          = ADDR_TYPE_RT
2265         },
2266 };
2267
2268 /* l4_per -> i2c4 */
2269 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2270         .master         = &omap44xx_l4_per_hwmod,
2271         .slave          = &omap44xx_i2c4_hwmod,
2272         .clk            = "l4_div_ck",
2273         .addr           = omap44xx_i2c4_addrs,
2274         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c4_addrs),
2275         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2276 };
2277
2278 /* i2c4 slave ports */
2279 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2280         &omap44xx_l4_per__i2c4,
2281 };
2282
2283 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2284         .name           = "i2c4",
2285         .class          = &omap44xx_i2c_hwmod_class,
2286         .flags          = HWMOD_INIT_NO_RESET,
2287         .mpu_irqs       = omap44xx_i2c4_irqs,
2288         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c4_irqs),
2289         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2290         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
2291         .main_clk       = "i2c4_fck",
2292         .prcm = {
2293                 .omap4 = {
2294                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
2295                 },
2296         },
2297         .slaves         = omap44xx_i2c4_slaves,
2298         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2299         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2300 };
2301
2302 /*
2303  * 'ipu' class
2304  * imaging processor unit
2305  */
2306
2307 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2308         .name   = "ipu",
2309 };
2310
2311 /* ipu */
2312 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2313         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2314 };
2315
2316 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2317         { .name = "cpu0", .rst_shift = 0 },
2318 };
2319
2320 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2321         { .name = "cpu1", .rst_shift = 1 },
2322 };
2323
2324 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2325         { .name = "mmu_cache", .rst_shift = 2 },
2326 };
2327
2328 /* ipu master ports */
2329 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2330         &omap44xx_ipu__l3_main_2,
2331 };
2332
2333 /* l3_main_2 -> ipu */
2334 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2335         .master         = &omap44xx_l3_main_2_hwmod,
2336         .slave          = &omap44xx_ipu_hwmod,
2337         .clk            = "l3_div_ck",
2338         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2339 };
2340
2341 /* ipu slave ports */
2342 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2343         &omap44xx_l3_main_2__ipu,
2344 };
2345
2346 /* Pseudo hwmod for reset control purpose only */
2347 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2348         .name           = "ipu_c0",
2349         .class          = &omap44xx_ipu_hwmod_class,
2350         .flags          = HWMOD_INIT_NO_RESET,
2351         .rst_lines      = omap44xx_ipu_c0_resets,
2352         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2353         .prcm           = {
2354                 .omap4 = {
2355                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2356                 },
2357         },
2358         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2359 };
2360
2361 /* Pseudo hwmod for reset control purpose only */
2362 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2363         .name           = "ipu_c1",
2364         .class          = &omap44xx_ipu_hwmod_class,
2365         .flags          = HWMOD_INIT_NO_RESET,
2366         .rst_lines      = omap44xx_ipu_c1_resets,
2367         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2368         .prcm           = {
2369                 .omap4 = {
2370                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2371                 },
2372         },
2373         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2374 };
2375
2376 static struct omap_hwmod omap44xx_ipu_hwmod = {
2377         .name           = "ipu",
2378         .class          = &omap44xx_ipu_hwmod_class,
2379         .mpu_irqs       = omap44xx_ipu_irqs,
2380         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_ipu_irqs),
2381         .rst_lines      = omap44xx_ipu_resets,
2382         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2383         .main_clk       = "ipu_fck",
2384         .prcm           = {
2385                 .omap4 = {
2386                         .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2387                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2388                 },
2389         },
2390         .slaves         = omap44xx_ipu_slaves,
2391         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2392         .masters        = omap44xx_ipu_masters,
2393         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2394         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2395 };
2396
2397 /*
2398  * 'iss' class
2399  * external images sensor pixel data processor
2400  */
2401
2402 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2403         .rev_offs       = 0x0000,
2404         .sysc_offs      = 0x0010,
2405         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2406                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2407         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2408                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2409                            MSTANDBY_SMART),
2410         .sysc_fields    = &omap_hwmod_sysc_type2,
2411 };
2412
2413 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2414         .name   = "iss",
2415         .sysc   = &omap44xx_iss_sysc,
2416 };
2417
2418 /* iss */
2419 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2420         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2421 };
2422
2423 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2424         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2425         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2426         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2427         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2428 };
2429
2430 /* iss master ports */
2431 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2432         &omap44xx_iss__l3_main_2,
2433 };
2434
2435 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2436         {
2437                 .pa_start       = 0x52000000,
2438                 .pa_end         = 0x520000ff,
2439                 .flags          = ADDR_TYPE_RT
2440         },
2441 };
2442
2443 /* l3_main_2 -> iss */
2444 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2445         .master         = &omap44xx_l3_main_2_hwmod,
2446         .slave          = &omap44xx_iss_hwmod,
2447         .clk            = "l3_div_ck",
2448         .addr           = omap44xx_iss_addrs,
2449         .addr_cnt       = ARRAY_SIZE(omap44xx_iss_addrs),
2450         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2451 };
2452
2453 /* iss slave ports */
2454 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2455         &omap44xx_l3_main_2__iss,
2456 };
2457
2458 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2459         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2460 };
2461
2462 static struct omap_hwmod omap44xx_iss_hwmod = {
2463         .name           = "iss",
2464         .class          = &omap44xx_iss_hwmod_class,
2465         .mpu_irqs       = omap44xx_iss_irqs,
2466         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iss_irqs),
2467         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2468         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
2469         .main_clk       = "iss_fck",
2470         .prcm           = {
2471                 .omap4 = {
2472                         .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2473                 },
2474         },
2475         .opt_clks       = iss_opt_clks,
2476         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2477         .slaves         = omap44xx_iss_slaves,
2478         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2479         .masters        = omap44xx_iss_masters,
2480         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2481         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2482 };
2483
2484 /*
2485  * 'iva' class
2486  * multi-standard video encoder/decoder hardware accelerator
2487  */
2488
2489 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2490         .name   = "iva",
2491 };
2492
2493 /* iva */
2494 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2495         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2496         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2497         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2498 };
2499
2500 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2501         { .name = "logic", .rst_shift = 2 },
2502 };
2503
2504 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2505         { .name = "seq0", .rst_shift = 0 },
2506 };
2507
2508 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2509         { .name = "seq1", .rst_shift = 1 },
2510 };
2511
2512 /* iva master ports */
2513 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2514         &omap44xx_iva__l3_main_2,
2515         &omap44xx_iva__l3_instr,
2516 };
2517
2518 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2519         {
2520                 .pa_start       = 0x5a000000,
2521                 .pa_end         = 0x5a07ffff,
2522                 .flags          = ADDR_TYPE_RT
2523         },
2524 };
2525
2526 /* l3_main_2 -> iva */
2527 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2528         .master         = &omap44xx_l3_main_2_hwmod,
2529         .slave          = &omap44xx_iva_hwmod,
2530         .clk            = "l3_div_ck",
2531         .addr           = omap44xx_iva_addrs,
2532         .addr_cnt       = ARRAY_SIZE(omap44xx_iva_addrs),
2533         .user           = OCP_USER_MPU,
2534 };
2535
2536 /* iva slave ports */
2537 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2538         &omap44xx_dsp__iva,
2539         &omap44xx_l3_main_2__iva,
2540 };
2541
2542 /* Pseudo hwmod for reset control purpose only */
2543 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2544         .name           = "iva_seq0",
2545         .class          = &omap44xx_iva_hwmod_class,
2546         .flags          = HWMOD_INIT_NO_RESET,
2547         .rst_lines      = omap44xx_iva_seq0_resets,
2548         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2549         .prcm = {
2550                 .omap4 = {
2551                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2552                 },
2553         },
2554         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2555 };
2556
2557 /* Pseudo hwmod for reset control purpose only */
2558 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2559         .name           = "iva_seq1",
2560         .class          = &omap44xx_iva_hwmod_class,
2561         .flags          = HWMOD_INIT_NO_RESET,
2562         .rst_lines      = omap44xx_iva_seq1_resets,
2563         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2564         .prcm = {
2565                 .omap4 = {
2566                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2567                 },
2568         },
2569         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2570 };
2571
2572 static struct omap_hwmod omap44xx_iva_hwmod = {
2573         .name           = "iva",
2574         .class          = &omap44xx_iva_hwmod_class,
2575         .mpu_irqs       = omap44xx_iva_irqs,
2576         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iva_irqs),
2577         .rst_lines      = omap44xx_iva_resets,
2578         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2579         .main_clk       = "iva_fck",
2580         .prcm = {
2581                 .omap4 = {
2582                         .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2583                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2584                 },
2585         },
2586         .slaves         = omap44xx_iva_slaves,
2587         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2588         .masters        = omap44xx_iva_masters,
2589         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2590         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2591 };
2592
2593 /*
2594  * 'kbd' class
2595  * keyboard controller
2596  */
2597
2598 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2599         .rev_offs       = 0x0000,
2600         .sysc_offs      = 0x0010,
2601         .syss_offs      = 0x0014,
2602         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2603                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2604                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2605                            SYSS_HAS_RESET_STATUS),
2606         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2607         .sysc_fields    = &omap_hwmod_sysc_type1,
2608 };
2609
2610 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2611         .name   = "kbd",
2612         .sysc   = &omap44xx_kbd_sysc,
2613 };
2614
2615 /* kbd */
2616 static struct omap_hwmod omap44xx_kbd_hwmod;
2617 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2618         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2619 };
2620
2621 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2622         {
2623                 .pa_start       = 0x4a31c000,
2624                 .pa_end         = 0x4a31c07f,
2625                 .flags          = ADDR_TYPE_RT
2626         },
2627 };
2628
2629 /* l4_wkup -> kbd */
2630 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2631         .master         = &omap44xx_l4_wkup_hwmod,
2632         .slave          = &omap44xx_kbd_hwmod,
2633         .clk            = "l4_wkup_clk_mux_ck",
2634         .addr           = omap44xx_kbd_addrs,
2635         .addr_cnt       = ARRAY_SIZE(omap44xx_kbd_addrs),
2636         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2637 };
2638
2639 /* kbd slave ports */
2640 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2641         &omap44xx_l4_wkup__kbd,
2642 };
2643
2644 static struct omap_hwmod omap44xx_kbd_hwmod = {
2645         .name           = "kbd",
2646         .class          = &omap44xx_kbd_hwmod_class,
2647         .mpu_irqs       = omap44xx_kbd_irqs,
2648         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_kbd_irqs),
2649         .main_clk       = "kbd_fck",
2650         .prcm           = {
2651                 .omap4 = {
2652                         .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2653                 },
2654         },
2655         .slaves         = omap44xx_kbd_slaves,
2656         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2657         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2658 };
2659
2660 /*
2661  * 'mailbox' class
2662  * mailbox module allowing communication between the on-chip processors using a
2663  * queued mailbox-interrupt mechanism.
2664  */
2665
2666 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2667         .rev_offs       = 0x0000,
2668         .sysc_offs      = 0x0010,
2669         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2670                            SYSC_HAS_SOFTRESET),
2671         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2672         .sysc_fields    = &omap_hwmod_sysc_type2,
2673 };
2674
2675 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2676         .name   = "mailbox",
2677         .sysc   = &omap44xx_mailbox_sysc,
2678 };
2679
2680 /* mailbox */
2681 static struct omap_hwmod omap44xx_mailbox_hwmod;
2682 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2683         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2684 };
2685
2686 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2687         {
2688                 .pa_start       = 0x4a0f4000,
2689                 .pa_end         = 0x4a0f41ff,
2690                 .flags          = ADDR_TYPE_RT
2691         },
2692 };
2693
2694 /* l4_cfg -> mailbox */
2695 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2696         .master         = &omap44xx_l4_cfg_hwmod,
2697         .slave          = &omap44xx_mailbox_hwmod,
2698         .clk            = "l4_div_ck",
2699         .addr           = omap44xx_mailbox_addrs,
2700         .addr_cnt       = ARRAY_SIZE(omap44xx_mailbox_addrs),
2701         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2702 };
2703
2704 /* mailbox slave ports */
2705 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2706         &omap44xx_l4_cfg__mailbox,
2707 };
2708
2709 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2710         .name           = "mailbox",
2711         .class          = &omap44xx_mailbox_hwmod_class,
2712         .mpu_irqs       = omap44xx_mailbox_irqs,
2713         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mailbox_irqs),
2714         .prcm           = {
2715                 .omap4 = {
2716                         .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2717                 },
2718         },
2719         .slaves         = omap44xx_mailbox_slaves,
2720         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2721         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2722 };
2723
2724 /*
2725  * 'mcbsp' class
2726  * multi channel buffered serial port controller
2727  */
2728
2729 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2730         .sysc_offs      = 0x008c,
2731         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2732                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2733         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2734         .sysc_fields    = &omap_hwmod_sysc_type1,
2735 };
2736
2737 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2738         .name   = "mcbsp",
2739         .sysc   = &omap44xx_mcbsp_sysc,
2740 };
2741
2742 /* mcbsp1 */
2743 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2744 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2745         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2746 };
2747
2748 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2749         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2750         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2751 };
2752
2753 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2754         {
2755                 .pa_start       = 0x40122000,
2756                 .pa_end         = 0x401220ff,
2757                 .flags          = ADDR_TYPE_RT
2758         },
2759 };
2760
2761 /* l4_abe -> mcbsp1 */
2762 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2763         .master         = &omap44xx_l4_abe_hwmod,
2764         .slave          = &omap44xx_mcbsp1_hwmod,
2765         .clk            = "ocp_abe_iclk",
2766         .addr           = omap44xx_mcbsp1_addrs,
2767         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
2768         .user           = OCP_USER_MPU,
2769 };
2770
2771 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2772         {
2773                 .pa_start       = 0x49022000,
2774                 .pa_end         = 0x490220ff,
2775                 .flags          = ADDR_TYPE_RT
2776         },
2777 };
2778
2779 /* l4_abe -> mcbsp1 (dma) */
2780 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2781         .master         = &omap44xx_l4_abe_hwmod,
2782         .slave          = &omap44xx_mcbsp1_hwmod,
2783         .clk            = "ocp_abe_iclk",
2784         .addr           = omap44xx_mcbsp1_dma_addrs,
2785         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
2786         .user           = OCP_USER_SDMA,
2787 };
2788
2789 /* mcbsp1 slave ports */
2790 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2791         &omap44xx_l4_abe__mcbsp1,
2792         &omap44xx_l4_abe__mcbsp1_dma,
2793 };
2794
2795 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2796         .name           = "mcbsp1",
2797         .class          = &omap44xx_mcbsp_hwmod_class,
2798         .mpu_irqs       = omap44xx_mcbsp1_irqs,
2799         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
2800         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
2801         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
2802         .main_clk       = "mcbsp1_fck",
2803         .prcm = {
2804                 .omap4 = {
2805                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2806                 },
2807         },
2808         .slaves         = omap44xx_mcbsp1_slaves,
2809         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2810         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2811 };
2812
2813 /* mcbsp2 */
2814 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2815 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2816         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2817 };
2818
2819 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2820         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2821         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2822 };
2823
2824 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2825         {
2826                 .pa_start       = 0x40124000,
2827                 .pa_end         = 0x401240ff,
2828                 .flags          = ADDR_TYPE_RT
2829         },
2830 };
2831
2832 /* l4_abe -> mcbsp2 */
2833 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2834         .master         = &omap44xx_l4_abe_hwmod,
2835         .slave          = &omap44xx_mcbsp2_hwmod,
2836         .clk            = "ocp_abe_iclk",
2837         .addr           = omap44xx_mcbsp2_addrs,
2838         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
2839         .user           = OCP_USER_MPU,
2840 };
2841
2842 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2843         {
2844                 .pa_start       = 0x49024000,
2845                 .pa_end         = 0x490240ff,
2846                 .flags          = ADDR_TYPE_RT
2847         },
2848 };
2849
2850 /* l4_abe -> mcbsp2 (dma) */
2851 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2852         .master         = &omap44xx_l4_abe_hwmod,
2853         .slave          = &omap44xx_mcbsp2_hwmod,
2854         .clk            = "ocp_abe_iclk",
2855         .addr           = omap44xx_mcbsp2_dma_addrs,
2856         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
2857         .user           = OCP_USER_SDMA,
2858 };
2859
2860 /* mcbsp2 slave ports */
2861 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2862         &omap44xx_l4_abe__mcbsp2,
2863         &omap44xx_l4_abe__mcbsp2_dma,
2864 };
2865
2866 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2867         .name           = "mcbsp2",
2868         .class          = &omap44xx_mcbsp_hwmod_class,
2869         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2870         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
2871         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2872         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
2873         .main_clk       = "mcbsp2_fck",
2874         .prcm = {
2875                 .omap4 = {
2876                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2877                 },
2878         },
2879         .slaves         = omap44xx_mcbsp2_slaves,
2880         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
2881         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2882 };
2883
2884 /* mcbsp3 */
2885 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2886 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2887         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2888 };
2889
2890 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2891         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2892         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2893 };
2894
2895 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2896         {
2897                 .pa_start       = 0x40126000,
2898                 .pa_end         = 0x401260ff,
2899                 .flags          = ADDR_TYPE_RT
2900         },
2901 };
2902
2903 /* l4_abe -> mcbsp3 */
2904 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2905         .master         = &omap44xx_l4_abe_hwmod,
2906         .slave          = &omap44xx_mcbsp3_hwmod,
2907         .clk            = "ocp_abe_iclk",
2908         .addr           = omap44xx_mcbsp3_addrs,
2909         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
2910         .user           = OCP_USER_MPU,
2911 };
2912
2913 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2914         {
2915                 .pa_start       = 0x49026000,
2916                 .pa_end         = 0x490260ff,
2917                 .flags          = ADDR_TYPE_RT
2918         },
2919 };
2920
2921 /* l4_abe -> mcbsp3 (dma) */
2922 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
2923         .master         = &omap44xx_l4_abe_hwmod,
2924         .slave          = &omap44xx_mcbsp3_hwmod,
2925         .clk            = "ocp_abe_iclk",
2926         .addr           = omap44xx_mcbsp3_dma_addrs,
2927         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
2928         .user           = OCP_USER_SDMA,
2929 };
2930
2931 /* mcbsp3 slave ports */
2932 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
2933         &omap44xx_l4_abe__mcbsp3,
2934         &omap44xx_l4_abe__mcbsp3_dma,
2935 };
2936
2937 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2938         .name           = "mcbsp3",
2939         .class          = &omap44xx_mcbsp_hwmod_class,
2940         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2941         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
2942         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2943         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
2944         .main_clk       = "mcbsp3_fck",
2945         .prcm = {
2946                 .omap4 = {
2947                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2948                 },
2949         },
2950         .slaves         = omap44xx_mcbsp3_slaves,
2951         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
2952         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2953 };
2954
2955 /* mcbsp4 */
2956 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
2957 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2958         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
2959 };
2960
2961 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2962         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2963         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2964 };
2965
2966 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
2967         {
2968                 .pa_start       = 0x48096000,
2969                 .pa_end         = 0x480960ff,
2970                 .flags          = ADDR_TYPE_RT
2971         },
2972 };
2973
2974 /* l4_per -> mcbsp4 */
2975 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
2976         .master         = &omap44xx_l4_per_hwmod,
2977         .slave          = &omap44xx_mcbsp4_hwmod,
2978         .clk            = "l4_div_ck",
2979         .addr           = omap44xx_mcbsp4_addrs,
2980         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
2981         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2982 };
2983
2984 /* mcbsp4 slave ports */
2985 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
2986         &omap44xx_l4_per__mcbsp4,
2987 };
2988
2989 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2990         .name           = "mcbsp4",
2991         .class          = &omap44xx_mcbsp_hwmod_class,
2992         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2993         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
2994         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2995         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
2996         .main_clk       = "mcbsp4_fck",
2997         .prcm = {
2998                 .omap4 = {
2999                         .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3000                 },
3001         },
3002         .slaves         = omap44xx_mcbsp4_slaves,
3003         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3004         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3005 };
3006
3007 /*
3008  * 'mcpdm' class
3009  * multi channel pdm controller (proprietary interface with phoenix power
3010  * ic)
3011  */
3012
3013 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3014         .rev_offs       = 0x0000,
3015         .sysc_offs      = 0x0010,
3016         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3017                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3018         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3019                            SIDLE_SMART_WKUP),
3020         .sysc_fields    = &omap_hwmod_sysc_type2,
3021 };
3022
3023 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3024         .name   = "mcpdm",
3025         .sysc   = &omap44xx_mcpdm_sysc,
3026 };
3027
3028 /* mcpdm */
3029 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3030 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3031         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3032 };
3033
3034 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3035         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3036         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3037 };
3038
3039 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3040         {
3041                 .pa_start       = 0x40132000,
3042                 .pa_end         = 0x4013207f,
3043                 .flags          = ADDR_TYPE_RT
3044         },
3045 };
3046
3047 /* l4_abe -> mcpdm */
3048 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3049         .master         = &omap44xx_l4_abe_hwmod,
3050         .slave          = &omap44xx_mcpdm_hwmod,
3051         .clk            = "ocp_abe_iclk",
3052         .addr           = omap44xx_mcpdm_addrs,
3053         .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_addrs),
3054         .user           = OCP_USER_MPU,
3055 };
3056
3057 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3058         {
3059                 .pa_start       = 0x49032000,
3060                 .pa_end         = 0x4903207f,
3061                 .flags          = ADDR_TYPE_RT
3062         },
3063 };
3064
3065 /* l4_abe -> mcpdm (dma) */
3066 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3067         .master         = &omap44xx_l4_abe_hwmod,
3068         .slave          = &omap44xx_mcpdm_hwmod,
3069         .clk            = "ocp_abe_iclk",
3070         .addr           = omap44xx_mcpdm_dma_addrs,
3071         .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
3072         .user           = OCP_USER_SDMA,
3073 };
3074
3075 /* mcpdm slave ports */
3076 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3077         &omap44xx_l4_abe__mcpdm,
3078         &omap44xx_l4_abe__mcpdm_dma,
3079 };
3080
3081 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3082         .name           = "mcpdm",
3083         .class          = &omap44xx_mcpdm_hwmod_class,
3084         .mpu_irqs       = omap44xx_mcpdm_irqs,
3085         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcpdm_irqs),
3086         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3087         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
3088         .main_clk       = "mcpdm_fck",
3089         .prcm           = {
3090                 .omap4 = {
3091                         .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3092                 },
3093         },
3094         .slaves         = omap44xx_mcpdm_slaves,
3095         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3096         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3097 };
3098
3099 /*
3100  * 'mcspi' class
3101  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3102  * bus
3103  */
3104
3105 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3106         .rev_offs       = 0x0000,
3107         .sysc_offs      = 0x0010,
3108         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3109                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3110         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3111                            SIDLE_SMART_WKUP),
3112         .sysc_fields    = &omap_hwmod_sysc_type2,
3113 };
3114
3115 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3116         .name   = "mcspi",
3117         .sysc   = &omap44xx_mcspi_sysc,
3118         .rev    = OMAP4_MCSPI_REV,
3119 };
3120
3121 /* mcspi1 */
3122 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3123 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3124         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3125 };
3126
3127 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3128         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3129         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3130         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3131         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3132         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3133         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3134         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3135         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3136 };
3137
3138 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3139         {
3140                 .pa_start       = 0x48098000,
3141                 .pa_end         = 0x480981ff,
3142                 .flags          = ADDR_TYPE_RT
3143         },
3144 };
3145
3146 /* l4_per -> mcspi1 */
3147 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3148         .master         = &omap44xx_l4_per_hwmod,
3149         .slave          = &omap44xx_mcspi1_hwmod,
3150         .clk            = "l4_div_ck",
3151         .addr           = omap44xx_mcspi1_addrs,
3152         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi1_addrs),
3153         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3154 };
3155
3156 /* mcspi1 slave ports */
3157 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3158         &omap44xx_l4_per__mcspi1,
3159 };
3160
3161 /* mcspi1 dev_attr */
3162 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3163         .num_chipselect = 4,
3164 };
3165
3166 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3167         .name           = "mcspi1",
3168         .class          = &omap44xx_mcspi_hwmod_class,
3169         .mpu_irqs       = omap44xx_mcspi1_irqs,
3170         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi1_irqs),
3171         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3172         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
3173         .main_clk       = "mcspi1_fck",
3174         .prcm = {
3175                 .omap4 = {
3176                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3177                 },
3178         },
3179         .dev_attr       = &mcspi1_dev_attr,
3180         .slaves         = omap44xx_mcspi1_slaves,
3181         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3182         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3183 };
3184
3185 /* mcspi2 */
3186 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3187 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3188         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3189 };
3190
3191 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3192         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3193         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3194         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3195         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3196 };
3197
3198 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3199         {
3200                 .pa_start       = 0x4809a000,
3201                 .pa_end         = 0x4809a1ff,
3202                 .flags          = ADDR_TYPE_RT
3203         },
3204 };
3205
3206 /* l4_per -> mcspi2 */
3207 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3208         .master         = &omap44xx_l4_per_hwmod,
3209         .slave          = &omap44xx_mcspi2_hwmod,
3210         .clk            = "l4_div_ck",
3211         .addr           = omap44xx_mcspi2_addrs,
3212         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi2_addrs),
3213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3214 };
3215
3216 /* mcspi2 slave ports */
3217 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3218         &omap44xx_l4_per__mcspi2,
3219 };
3220
3221 /* mcspi2 dev_attr */
3222 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3223         .num_chipselect = 2,
3224 };
3225
3226 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3227         .name           = "mcspi2",
3228         .class          = &omap44xx_mcspi_hwmod_class,
3229         .mpu_irqs       = omap44xx_mcspi2_irqs,
3230         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi2_irqs),
3231         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3232         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
3233         .main_clk       = "mcspi2_fck",
3234         .prcm = {
3235                 .omap4 = {
3236                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3237                 },
3238         },
3239         .dev_attr       = &mcspi2_dev_attr,
3240         .slaves         = omap44xx_mcspi2_slaves,
3241         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3242         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3243 };
3244
3245 /* mcspi3 */
3246 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3247 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3248         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3249 };
3250
3251 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3252         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3253         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3254         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3255         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3256 };
3257
3258 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3259         {
3260                 .pa_start       = 0x480b8000,
3261                 .pa_end         = 0x480b81ff,
3262                 .flags          = ADDR_TYPE_RT
3263         },
3264 };
3265
3266 /* l4_per -> mcspi3 */
3267 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3268         .master         = &omap44xx_l4_per_hwmod,
3269         .slave          = &omap44xx_mcspi3_hwmod,
3270         .clk            = "l4_div_ck",
3271         .addr           = omap44xx_mcspi3_addrs,
3272         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi3_addrs),
3273         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3274 };
3275
3276 /* mcspi3 slave ports */
3277 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3278         &omap44xx_l4_per__mcspi3,
3279 };
3280
3281 /* mcspi3 dev_attr */
3282 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3283         .num_chipselect = 2,
3284 };
3285
3286 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3287         .name           = "mcspi3",
3288         .class          = &omap44xx_mcspi_hwmod_class,
3289         .mpu_irqs       = omap44xx_mcspi3_irqs,
3290         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi3_irqs),
3291         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3292         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
3293         .main_clk       = "mcspi3_fck",
3294         .prcm = {
3295                 .omap4 = {
3296                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3297                 },
3298         },
3299         .dev_attr       = &mcspi3_dev_attr,
3300         .slaves         = omap44xx_mcspi3_slaves,
3301         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3302         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3303 };
3304
3305 /* mcspi4 */
3306 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3307 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3308         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3309 };
3310
3311 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3312         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3313         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3314 };
3315
3316 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3317         {
3318                 .pa_start       = 0x480ba000,
3319                 .pa_end         = 0x480ba1ff,
3320                 .flags          = ADDR_TYPE_RT
3321         },
3322 };
3323
3324 /* l4_per -> mcspi4 */
3325 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3326         .master         = &omap44xx_l4_per_hwmod,
3327         .slave          = &omap44xx_mcspi4_hwmod,
3328         .clk            = "l4_div_ck",
3329         .addr           = omap44xx_mcspi4_addrs,
3330         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi4_addrs),
3331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3332 };
3333
3334 /* mcspi4 slave ports */
3335 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3336         &omap44xx_l4_per__mcspi4,
3337 };
3338
3339 /* mcspi4 dev_attr */
3340 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3341         .num_chipselect = 1,
3342 };
3343
3344 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3345         .name           = "mcspi4",
3346         .class          = &omap44xx_mcspi_hwmod_class,
3347         .mpu_irqs       = omap44xx_mcspi4_irqs,
3348         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi4_irqs),
3349         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3350         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
3351         .main_clk       = "mcspi4_fck",
3352         .prcm = {
3353                 .omap4 = {
3354                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3355                 },
3356         },
3357         .dev_attr       = &mcspi4_dev_attr,
3358         .slaves         = omap44xx_mcspi4_slaves,
3359         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3360         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3361 };
3362
3363 /*
3364  * 'mmc' class
3365  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3366  */
3367
3368 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3369         .rev_offs       = 0x0000,
3370         .sysc_offs      = 0x0010,
3371         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3372                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3373                            SYSC_HAS_SOFTRESET),
3374         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3375                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3376                            MSTANDBY_SMART),
3377         .sysc_fields    = &omap_hwmod_sysc_type2,
3378 };
3379
3380 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3381         .name   = "mmc",
3382         .sysc   = &omap44xx_mmc_sysc,
3383 };
3384
3385 /* mmc1 */
3386 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3387         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3388 };
3389
3390 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3391         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3392         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3393 };
3394
3395 /* mmc1 master ports */
3396 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3397         &omap44xx_mmc1__l3_main_1,
3398 };
3399
3400 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3401         {
3402                 .pa_start       = 0x4809c000,
3403                 .pa_end         = 0x4809c3ff,
3404                 .flags          = ADDR_TYPE_RT
3405         },
3406 };
3407
3408 /* l4_per -> mmc1 */
3409 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3410         .master         = &omap44xx_l4_per_hwmod,
3411         .slave          = &omap44xx_mmc1_hwmod,
3412         .clk            = "l4_div_ck",
3413         .addr           = omap44xx_mmc1_addrs,
3414         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc1_addrs),
3415         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3416 };
3417
3418 /* mmc1 slave ports */
3419 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3420         &omap44xx_l4_per__mmc1,
3421 };
3422
3423 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3424         .name           = "mmc1",
3425         .class          = &omap44xx_mmc_hwmod_class,
3426         .mpu_irqs       = omap44xx_mmc1_irqs,
3427         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc1_irqs),
3428         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3429         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
3430         .main_clk       = "mmc1_fck",
3431         .prcm           = {
3432                 .omap4 = {
3433                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3434                 },
3435         },
3436         .slaves         = omap44xx_mmc1_slaves,
3437         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3438         .masters        = omap44xx_mmc1_masters,
3439         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3440         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3441 };
3442
3443 /* mmc2 */
3444 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3445         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3446 };
3447
3448 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3449         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3450         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3451 };
3452
3453 /* mmc2 master ports */
3454 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3455         &omap44xx_mmc2__l3_main_1,
3456 };
3457
3458 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3459         {
3460                 .pa_start       = 0x480b4000,
3461                 .pa_end         = 0x480b43ff,
3462                 .flags          = ADDR_TYPE_RT
3463         },
3464 };
3465
3466 /* l4_per -> mmc2 */
3467 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3468         .master         = &omap44xx_l4_per_hwmod,
3469         .slave          = &omap44xx_mmc2_hwmod,
3470         .clk            = "l4_div_ck",
3471         .addr           = omap44xx_mmc2_addrs,
3472         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc2_addrs),
3473         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3474 };
3475
3476 /* mmc2 slave ports */
3477 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3478         &omap44xx_l4_per__mmc2,
3479 };
3480
3481 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3482         .name           = "mmc2",
3483         .class          = &omap44xx_mmc_hwmod_class,
3484         .mpu_irqs       = omap44xx_mmc2_irqs,
3485         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc2_irqs),
3486         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3487         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
3488         .main_clk       = "mmc2_fck",
3489         .prcm           = {
3490                 .omap4 = {
3491                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3492                 },
3493         },
3494         .slaves         = omap44xx_mmc2_slaves,
3495         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3496         .masters        = omap44xx_mmc2_masters,
3497         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3498         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3499 };
3500
3501 /* mmc3 */
3502 static struct omap_hwmod omap44xx_mmc3_hwmod;
3503 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3504         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3505 };
3506
3507 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3508         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3509         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3510 };
3511
3512 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3513         {
3514                 .pa_start       = 0x480ad000,
3515                 .pa_end         = 0x480ad3ff,
3516                 .flags          = ADDR_TYPE_RT
3517         },
3518 };
3519
3520 /* l4_per -> mmc3 */
3521 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3522         .master         = &omap44xx_l4_per_hwmod,
3523         .slave          = &omap44xx_mmc3_hwmod,
3524         .clk            = "l4_div_ck",
3525         .addr           = omap44xx_mmc3_addrs,
3526         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc3_addrs),
3527         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3528 };
3529
3530 /* mmc3 slave ports */
3531 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3532         &omap44xx_l4_per__mmc3,
3533 };
3534
3535 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3536         .name           = "mmc3",
3537         .class          = &omap44xx_mmc_hwmod_class,
3538         .mpu_irqs       = omap44xx_mmc3_irqs,
3539         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc3_irqs),
3540         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3541         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
3542         .main_clk       = "mmc3_fck",
3543         .prcm           = {
3544                 .omap4 = {
3545                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3546                 },
3547         },
3548         .slaves         = omap44xx_mmc3_slaves,
3549         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3550         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3551 };
3552
3553 /* mmc4 */
3554 static struct omap_hwmod omap44xx_mmc4_hwmod;
3555 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3556         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3557 };
3558
3559 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3560         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3561         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3562 };
3563
3564 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3565         {
3566                 .pa_start       = 0x480d1000,
3567                 .pa_end         = 0x480d13ff,
3568                 .flags          = ADDR_TYPE_RT
3569         },
3570 };
3571
3572 /* l4_per -> mmc4 */
3573 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3574         .master         = &omap44xx_l4_per_hwmod,
3575         .slave          = &omap44xx_mmc4_hwmod,
3576         .clk            = "l4_div_ck",
3577         .addr           = omap44xx_mmc4_addrs,
3578         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc4_addrs),
3579         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3580 };
3581
3582 /* mmc4 slave ports */
3583 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3584         &omap44xx_l4_per__mmc4,
3585 };
3586
3587 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3588         .name           = "mmc4",
3589         .class          = &omap44xx_mmc_hwmod_class,
3590         .mpu_irqs       = omap44xx_mmc4_irqs,
3591         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc4_irqs),
3592         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3593         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
3594         .main_clk       = "mmc4_fck",
3595         .prcm           = {
3596                 .omap4 = {
3597                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3598                 },
3599         },
3600         .slaves         = omap44xx_mmc4_slaves,
3601         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3602         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3603 };
3604
3605 /* mmc5 */
3606 static struct omap_hwmod omap44xx_mmc5_hwmod;
3607 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3608         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3609 };
3610
3611 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3612         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3613         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3614 };
3615
3616 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3617         {
3618                 .pa_start       = 0x480d5000,
3619                 .pa_end         = 0x480d53ff,
3620                 .flags          = ADDR_TYPE_RT
3621         },
3622 };
3623
3624 /* l4_per -> mmc5 */
3625 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3626         .master         = &omap44xx_l4_per_hwmod,
3627         .slave          = &omap44xx_mmc5_hwmod,
3628         .clk            = "l4_div_ck",
3629         .addr           = omap44xx_mmc5_addrs,
3630         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc5_addrs),
3631         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3632 };
3633
3634 /* mmc5 slave ports */
3635 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3636         &omap44xx_l4_per__mmc5,
3637 };
3638
3639 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3640         .name           = "mmc5",
3641         .class          = &omap44xx_mmc_hwmod_class,
3642         .mpu_irqs       = omap44xx_mmc5_irqs,
3643         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc5_irqs),
3644         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3645         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
3646         .main_clk       = "mmc5_fck",
3647         .prcm           = {
3648                 .omap4 = {
3649                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3650                 },
3651         },
3652         .slaves         = omap44xx_mmc5_slaves,
3653         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3654         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3655 };
3656
3657 /*
3658  * 'mpu' class
3659  * mpu sub-system
3660  */
3661
3662 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3663         .name   = "mpu",
3664 };
3665
3666 /* mpu */
3667 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3668         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3669         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3670         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3671 };
3672
3673 /* mpu master ports */
3674 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3675         &omap44xx_mpu__l3_main_1,
3676         &omap44xx_mpu__l4_abe,
3677         &omap44xx_mpu__dmm,
3678 };
3679
3680 static struct omap_hwmod omap44xx_mpu_hwmod = {
3681         .name           = "mpu",
3682         .class          = &omap44xx_mpu_hwmod_class,
3683         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
3684         .mpu_irqs       = omap44xx_mpu_irqs,
3685         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
3686         .main_clk       = "dpll_mpu_m2_ck",
3687         .prcm = {
3688                 .omap4 = {
3689                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
3690                 },
3691         },
3692         .masters        = omap44xx_mpu_masters,
3693         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3694         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3695 };
3696
3697 /*
3698  * 'smartreflex' class
3699  * smartreflex module (monitor silicon performance and outputs a measure of
3700  * performance error)
3701  */
3702
3703 /* The IP is not compliant to type1 / type2 scheme */
3704 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3705         .sidle_shift    = 24,
3706         .enwkup_shift   = 26,
3707 };
3708
3709 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3710         .sysc_offs      = 0x0038,
3711         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3712         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3713                            SIDLE_SMART_WKUP),
3714         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3715 };
3716
3717 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3718         .name   = "smartreflex",
3719         .sysc   = &omap44xx_smartreflex_sysc,
3720         .rev    = 2,
3721 };
3722
3723 /* smartreflex_core */
3724 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3725 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3726         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3727 };
3728
3729 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3730         {
3731                 .pa_start       = 0x4a0dd000,
3732                 .pa_end         = 0x4a0dd03f,
3733                 .flags          = ADDR_TYPE_RT
3734         },
3735 };
3736
3737 /* l4_cfg -> smartreflex_core */
3738 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3739         .master         = &omap44xx_l4_cfg_hwmod,
3740         .slave          = &omap44xx_smartreflex_core_hwmod,
3741         .clk            = "l4_div_ck",
3742         .addr           = omap44xx_smartreflex_core_addrs,
3743         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
3744         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3745 };
3746
3747 /* smartreflex_core slave ports */
3748 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3749         &omap44xx_l4_cfg__smartreflex_core,
3750 };
3751
3752 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3753         .name           = "smartreflex_core",
3754         .class          = &omap44xx_smartreflex_hwmod_class,
3755         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
3756         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
3757         .main_clk       = "smartreflex_core_fck",
3758         .vdd_name       = "core",
3759         .prcm = {
3760                 .omap4 = {
3761                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3762                 },
3763         },
3764         .slaves         = omap44xx_smartreflex_core_slaves,
3765         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3766         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3767 };
3768
3769 /* smartreflex_iva */
3770 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3771 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3772         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3773 };
3774
3775 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3776         {
3777                 .pa_start       = 0x4a0db000,
3778                 .pa_end         = 0x4a0db03f,
3779                 .flags          = ADDR_TYPE_RT
3780         },
3781 };
3782
3783 /* l4_cfg -> smartreflex_iva */
3784 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3785         .master         = &omap44xx_l4_cfg_hwmod,
3786         .slave          = &omap44xx_smartreflex_iva_hwmod,
3787         .clk            = "l4_div_ck",
3788         .addr           = omap44xx_smartreflex_iva_addrs,
3789         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
3790         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3791 };
3792
3793 /* smartreflex_iva slave ports */
3794 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3795         &omap44xx_l4_cfg__smartreflex_iva,
3796 };
3797
3798 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3799         .name           = "smartreflex_iva",
3800         .class          = &omap44xx_smartreflex_hwmod_class,
3801         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3802         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
3803         .main_clk       = "smartreflex_iva_fck",
3804         .vdd_name       = "iva",
3805         .prcm = {
3806                 .omap4 = {
3807                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3808                 },
3809         },
3810         .slaves         = omap44xx_smartreflex_iva_slaves,
3811         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3812         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3813 };
3814
3815 /* smartreflex_mpu */
3816 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3817 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3818         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3819 };
3820
3821 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3822         {
3823                 .pa_start       = 0x4a0d9000,
3824                 .pa_end         = 0x4a0d903f,
3825                 .flags          = ADDR_TYPE_RT
3826         },
3827 };
3828
3829 /* l4_cfg -> smartreflex_mpu */
3830 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3831         .master         = &omap44xx_l4_cfg_hwmod,
3832         .slave          = &omap44xx_smartreflex_mpu_hwmod,
3833         .clk            = "l4_div_ck",
3834         .addr           = omap44xx_smartreflex_mpu_addrs,
3835         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
3836         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3837 };
3838
3839 /* smartreflex_mpu slave ports */
3840 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
3841         &omap44xx_l4_cfg__smartreflex_mpu,
3842 };
3843
3844 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3845         .name           = "smartreflex_mpu",
3846         .class          = &omap44xx_smartreflex_hwmod_class,
3847         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3848         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
3849         .main_clk       = "smartreflex_mpu_fck",
3850         .vdd_name       = "mpu",
3851         .prcm = {
3852                 .omap4 = {
3853                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
3854                 },
3855         },
3856         .slaves         = omap44xx_smartreflex_mpu_slaves,
3857         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
3858         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3859 };
3860
3861 /*
3862  * 'spinlock' class
3863  * spinlock provides hardware assistance for synchronizing the processes
3864  * running on multiple processors
3865  */
3866
3867 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3868         .rev_offs       = 0x0000,
3869         .sysc_offs      = 0x0010,
3870         .syss_offs      = 0x0014,
3871         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3872                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3873                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3874         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3875                            SIDLE_SMART_WKUP),
3876         .sysc_fields    = &omap_hwmod_sysc_type1,
3877 };
3878
3879 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3880         .name   = "spinlock",
3881         .sysc   = &omap44xx_spinlock_sysc,
3882 };
3883
3884 /* spinlock */
3885 static struct omap_hwmod omap44xx_spinlock_hwmod;
3886 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3887         {
3888                 .pa_start       = 0x4a0f6000,
3889                 .pa_end         = 0x4a0f6fff,
3890                 .flags          = ADDR_TYPE_RT
3891         },
3892 };
3893
3894 /* l4_cfg -> spinlock */
3895 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3896         .master         = &omap44xx_l4_cfg_hwmod,
3897         .slave          = &omap44xx_spinlock_hwmod,
3898         .clk            = "l4_div_ck",
3899         .addr           = omap44xx_spinlock_addrs,
3900         .addr_cnt       = ARRAY_SIZE(omap44xx_spinlock_addrs),
3901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3902 };
3903
3904 /* spinlock slave ports */
3905 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
3906         &omap44xx_l4_cfg__spinlock,
3907 };
3908
3909 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3910         .name           = "spinlock",
3911         .class          = &omap44xx_spinlock_hwmod_class,
3912         .prcm = {
3913                 .omap4 = {
3914                         .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
3915                 },
3916         },
3917         .slaves         = omap44xx_spinlock_slaves,
3918         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
3919         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3920 };
3921
3922 /*
3923  * 'timer' class
3924  * general purpose timer module with accurate 1ms tick
3925  * This class contains several variants: ['timer_1ms', 'timer']
3926  */
3927
3928 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3929         .rev_offs       = 0x0000,
3930         .sysc_offs      = 0x0010,
3931         .syss_offs      = 0x0014,
3932         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3933                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3934                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3935                            SYSS_HAS_RESET_STATUS),
3936         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3937         .sysc_fields    = &omap_hwmod_sysc_type1,
3938 };
3939
3940 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3941         .name   = "timer",
3942         .sysc   = &omap44xx_timer_1ms_sysc,
3943 };
3944
3945 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3946         .rev_offs       = 0x0000,
3947         .sysc_offs      = 0x0010,
3948         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3949                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3950         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3951                            SIDLE_SMART_WKUP),
3952         .sysc_fields    = &omap_hwmod_sysc_type2,
3953 };
3954
3955 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3956         .name   = "timer",
3957         .sysc   = &omap44xx_timer_sysc,
3958 };
3959
3960 /* timer1 */
3961 static struct omap_hwmod omap44xx_timer1_hwmod;
3962 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3963         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3964 };
3965
3966 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
3967         {
3968                 .pa_start       = 0x4a318000,
3969                 .pa_end         = 0x4a31807f,
3970                 .flags          = ADDR_TYPE_RT
3971         },
3972 };
3973
3974 /* l4_wkup -> timer1 */
3975 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
3976         .master         = &omap44xx_l4_wkup_hwmod,
3977         .slave          = &omap44xx_timer1_hwmod,
3978         .clk            = "l4_wkup_clk_mux_ck",
3979         .addr           = omap44xx_timer1_addrs,
3980         .addr_cnt       = ARRAY_SIZE(omap44xx_timer1_addrs),
3981         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3982 };
3983
3984 /* timer1 slave ports */
3985 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
3986         &omap44xx_l4_wkup__timer1,
3987 };
3988
3989 static struct omap_hwmod omap44xx_timer1_hwmod = {
3990         .name           = "timer1",
3991         .class          = &omap44xx_timer_1ms_hwmod_class,
3992         .mpu_irqs       = omap44xx_timer1_irqs,
3993         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer1_irqs),
3994         .main_clk       = "timer1_fck",
3995         .prcm = {
3996                 .omap4 = {
3997                         .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
3998                 },
3999         },
4000         .slaves         = omap44xx_timer1_slaves,
4001         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4002         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4003 };
4004
4005 /* timer2 */
4006 static struct omap_hwmod omap44xx_timer2_hwmod;
4007 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4008         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4009 };
4010
4011 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4012         {
4013                 .pa_start       = 0x48032000,
4014                 .pa_end         = 0x4803207f,
4015                 .flags          = ADDR_TYPE_RT
4016         },
4017 };
4018
4019 /* l4_per -> timer2 */
4020 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4021         .master         = &omap44xx_l4_per_hwmod,
4022         .slave          = &omap44xx_timer2_hwmod,
4023         .clk            = "l4_div_ck",
4024         .addr           = omap44xx_timer2_addrs,
4025         .addr_cnt       = ARRAY_SIZE(omap44xx_timer2_addrs),
4026         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4027 };
4028
4029 /* timer2 slave ports */
4030 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4031         &omap44xx_l4_per__timer2,
4032 };
4033
4034 static struct omap_hwmod omap44xx_timer2_hwmod = {
4035         .name           = "timer2",
4036         .class          = &omap44xx_timer_1ms_hwmod_class,
4037         .mpu_irqs       = omap44xx_timer2_irqs,
4038         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer2_irqs),
4039         .main_clk       = "timer2_fck",
4040         .prcm = {
4041                 .omap4 = {
4042                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4043                 },
4044         },
4045         .slaves         = omap44xx_timer2_slaves,
4046         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4047         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4048 };
4049
4050 /* timer3 */
4051 static struct omap_hwmod omap44xx_timer3_hwmod;
4052 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4053         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4054 };
4055
4056 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4057         {
4058                 .pa_start       = 0x48034000,
4059                 .pa_end         = 0x4803407f,
4060                 .flags          = ADDR_TYPE_RT
4061         },
4062 };
4063
4064 /* l4_per -> timer3 */
4065 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4066         .master         = &omap44xx_l4_per_hwmod,
4067         .slave          = &omap44xx_timer3_hwmod,
4068         .clk            = "l4_div_ck",
4069         .addr           = omap44xx_timer3_addrs,
4070         .addr_cnt       = ARRAY_SIZE(omap44xx_timer3_addrs),
4071         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4072 };
4073
4074 /* timer3 slave ports */
4075 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4076         &omap44xx_l4_per__timer3,
4077 };
4078
4079 static struct omap_hwmod omap44xx_timer3_hwmod = {
4080         .name           = "timer3",
4081         .class          = &omap44xx_timer_hwmod_class,
4082         .mpu_irqs       = omap44xx_timer3_irqs,
4083         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer3_irqs),
4084         .main_clk       = "timer3_fck",
4085         .prcm = {
4086                 .omap4 = {
4087                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4088                 },
4089         },
4090         .slaves         = omap44xx_timer3_slaves,
4091         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4092         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4093 };
4094
4095 /* timer4 */
4096 static struct omap_hwmod omap44xx_timer4_hwmod;
4097 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4098         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4099 };
4100
4101 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4102         {
4103                 .pa_start       = 0x48036000,
4104                 .pa_end         = 0x4803607f,
4105                 .flags          = ADDR_TYPE_RT
4106         },
4107 };
4108
4109 /* l4_per -> timer4 */
4110 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4111         .master         = &omap44xx_l4_per_hwmod,
4112         .slave          = &omap44xx_timer4_hwmod,
4113         .clk            = "l4_div_ck",
4114         .addr           = omap44xx_timer4_addrs,
4115         .addr_cnt       = ARRAY_SIZE(omap44xx_timer4_addrs),
4116         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4117 };
4118
4119 /* timer4 slave ports */
4120 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4121         &omap44xx_l4_per__timer4,
4122 };
4123
4124 static struct omap_hwmod omap44xx_timer4_hwmod = {
4125         .name           = "timer4",
4126         .class          = &omap44xx_timer_hwmod_class,
4127         .mpu_irqs       = omap44xx_timer4_irqs,
4128         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer4_irqs),
4129         .main_clk       = "timer4_fck",
4130         .prcm = {
4131                 .omap4 = {
4132                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4133                 },
4134         },
4135         .slaves         = omap44xx_timer4_slaves,
4136         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4137         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4138 };
4139
4140 /* timer5 */
4141 static struct omap_hwmod omap44xx_timer5_hwmod;
4142 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4143         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4144 };
4145
4146 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4147         {
4148                 .pa_start       = 0x40138000,
4149                 .pa_end         = 0x4013807f,
4150                 .flags          = ADDR_TYPE_RT
4151         },
4152 };
4153
4154 /* l4_abe -> timer5 */
4155 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4156         .master         = &omap44xx_l4_abe_hwmod,
4157         .slave          = &omap44xx_timer5_hwmod,
4158         .clk            = "ocp_abe_iclk",
4159         .addr           = omap44xx_timer5_addrs,
4160         .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_addrs),
4161         .user           = OCP_USER_MPU,
4162 };
4163
4164 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4165         {
4166                 .pa_start       = 0x49038000,
4167                 .pa_end         = 0x4903807f,
4168                 .flags          = ADDR_TYPE_RT
4169         },
4170 };
4171
4172 /* l4_abe -> timer5 (dma) */
4173 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4174         .master         = &omap44xx_l4_abe_hwmod,
4175         .slave          = &omap44xx_timer5_hwmod,
4176         .clk            = "ocp_abe_iclk",
4177         .addr           = omap44xx_timer5_dma_addrs,
4178         .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
4179         .user           = OCP_USER_SDMA,
4180 };
4181
4182 /* timer5 slave ports */
4183 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4184         &omap44xx_l4_abe__timer5,
4185         &omap44xx_l4_abe__timer5_dma,
4186 };
4187
4188 static struct omap_hwmod omap44xx_timer5_hwmod = {
4189         .name           = "timer5",
4190         .class          = &omap44xx_timer_hwmod_class,
4191         .mpu_irqs       = omap44xx_timer5_irqs,
4192         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer5_irqs),
4193         .main_clk       = "timer5_fck",
4194         .prcm = {
4195                 .omap4 = {
4196                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4197                 },
4198         },
4199         .slaves         = omap44xx_timer5_slaves,
4200         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4201         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4202 };
4203
4204 /* timer6 */
4205 static struct omap_hwmod omap44xx_timer6_hwmod;
4206 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4207         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4208 };
4209
4210 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4211         {
4212                 .pa_start       = 0x4013a000,
4213                 .pa_end         = 0x4013a07f,
4214                 .flags          = ADDR_TYPE_RT
4215         },
4216 };
4217
4218 /* l4_abe -> timer6 */
4219 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4220         .master         = &omap44xx_l4_abe_hwmod,
4221         .slave          = &omap44xx_timer6_hwmod,
4222         .clk            = "ocp_abe_iclk",
4223         .addr           = omap44xx_timer6_addrs,
4224         .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_addrs),
4225         .user           = OCP_USER_MPU,
4226 };
4227
4228 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4229         {
4230                 .pa_start       = 0x4903a000,
4231                 .pa_end         = 0x4903a07f,
4232                 .flags          = ADDR_TYPE_RT
4233         },
4234 };
4235
4236 /* l4_abe -> timer6 (dma) */
4237 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4238         .master         = &omap44xx_l4_abe_hwmod,
4239         .slave          = &omap44xx_timer6_hwmod,
4240         .clk            = "ocp_abe_iclk",
4241         .addr           = omap44xx_timer6_dma_addrs,
4242         .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
4243         .user           = OCP_USER_SDMA,
4244 };
4245
4246 /* timer6 slave ports */
4247 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4248         &omap44xx_l4_abe__timer6,
4249         &omap44xx_l4_abe__timer6_dma,
4250 };
4251
4252 static struct omap_hwmod omap44xx_timer6_hwmod = {
4253         .name           = "timer6",
4254         .class          = &omap44xx_timer_hwmod_class,
4255         .mpu_irqs       = omap44xx_timer6_irqs,
4256         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer6_irqs),
4257         .main_clk       = "timer6_fck",
4258         .prcm = {
4259                 .omap4 = {
4260                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4261                 },
4262         },
4263         .slaves         = omap44xx_timer6_slaves,
4264         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4265         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4266 };
4267
4268 /* timer7 */
4269 static struct omap_hwmod omap44xx_timer7_hwmod;
4270 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4271         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4272 };
4273
4274 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4275         {
4276                 .pa_start       = 0x4013c000,
4277                 .pa_end         = 0x4013c07f,
4278                 .flags          = ADDR_TYPE_RT
4279         },
4280 };
4281
4282 /* l4_abe -> timer7 */
4283 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4284         .master         = &omap44xx_l4_abe_hwmod,
4285         .slave          = &omap44xx_timer7_hwmod,
4286         .clk            = "ocp_abe_iclk",
4287         .addr           = omap44xx_timer7_addrs,
4288         .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_addrs),
4289         .user           = OCP_USER_MPU,
4290 };
4291
4292 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4293         {
4294                 .pa_start       = 0x4903c000,
4295                 .pa_end         = 0x4903c07f,
4296                 .flags          = ADDR_TYPE_RT
4297         },
4298 };
4299
4300 /* l4_abe -> timer7 (dma) */
4301 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4302         .master         = &omap44xx_l4_abe_hwmod,
4303         .slave          = &omap44xx_timer7_hwmod,
4304         .clk            = "ocp_abe_iclk",
4305         .addr           = omap44xx_timer7_dma_addrs,
4306         .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
4307         .user           = OCP_USER_SDMA,
4308 };
4309
4310 /* timer7 slave ports */
4311 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4312         &omap44xx_l4_abe__timer7,
4313         &omap44xx_l4_abe__timer7_dma,
4314 };
4315
4316 static struct omap_hwmod omap44xx_timer7_hwmod = {
4317         .name           = "timer7",
4318         .class          = &omap44xx_timer_hwmod_class,
4319         .mpu_irqs       = omap44xx_timer7_irqs,
4320         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer7_irqs),
4321         .main_clk       = "timer7_fck",
4322         .prcm = {
4323                 .omap4 = {
4324                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4325                 },
4326         },
4327         .slaves         = omap44xx_timer7_slaves,
4328         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4329         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4330 };
4331
4332 /* timer8 */
4333 static struct omap_hwmod omap44xx_timer8_hwmod;
4334 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4335         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4336 };
4337
4338 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4339         {
4340                 .pa_start       = 0x4013e000,
4341                 .pa_end         = 0x4013e07f,
4342                 .flags          = ADDR_TYPE_RT
4343         },
4344 };
4345
4346 /* l4_abe -> timer8 */
4347 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4348         .master         = &omap44xx_l4_abe_hwmod,
4349         .slave          = &omap44xx_timer8_hwmod,
4350         .clk            = "ocp_abe_iclk",
4351         .addr           = omap44xx_timer8_addrs,
4352         .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_addrs),
4353         .user           = OCP_USER_MPU,
4354 };
4355
4356 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4357         {
4358                 .pa_start       = 0x4903e000,
4359                 .pa_end         = 0x4903e07f,
4360                 .flags          = ADDR_TYPE_RT
4361         },
4362 };
4363
4364 /* l4_abe -> timer8 (dma) */
4365 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4366         .master         = &omap44xx_l4_abe_hwmod,
4367         .slave          = &omap44xx_timer8_hwmod,
4368         .clk            = "ocp_abe_iclk",
4369         .addr           = omap44xx_timer8_dma_addrs,
4370         .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
4371         .user           = OCP_USER_SDMA,
4372 };
4373
4374 /* timer8 slave ports */
4375 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4376         &omap44xx_l4_abe__timer8,
4377         &omap44xx_l4_abe__timer8_dma,
4378 };
4379
4380 static struct omap_hwmod omap44xx_timer8_hwmod = {
4381         .name           = "timer8",
4382         .class          = &omap44xx_timer_hwmod_class,
4383         .mpu_irqs       = omap44xx_timer8_irqs,
4384         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer8_irqs),
4385         .main_clk       = "timer8_fck",
4386         .prcm = {
4387                 .omap4 = {
4388                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4389                 },
4390         },
4391         .slaves         = omap44xx_timer8_slaves,
4392         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4393         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4394 };
4395
4396 /* timer9 */
4397 static struct omap_hwmod omap44xx_timer9_hwmod;
4398 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4399         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4400 };
4401
4402 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4403         {
4404                 .pa_start       = 0x4803e000,
4405                 .pa_end         = 0x4803e07f,
4406                 .flags          = ADDR_TYPE_RT
4407         },
4408 };
4409
4410 /* l4_per -> timer9 */
4411 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4412         .master         = &omap44xx_l4_per_hwmod,
4413         .slave          = &omap44xx_timer9_hwmod,
4414         .clk            = "l4_div_ck",
4415         .addr           = omap44xx_timer9_addrs,
4416         .addr_cnt       = ARRAY_SIZE(omap44xx_timer9_addrs),
4417         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4418 };
4419
4420 /* timer9 slave ports */
4421 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4422         &omap44xx_l4_per__timer9,
4423 };
4424
4425 static struct omap_hwmod omap44xx_timer9_hwmod = {
4426         .name           = "timer9",
4427         .class          = &omap44xx_timer_hwmod_class,
4428         .mpu_irqs       = omap44xx_timer9_irqs,
4429         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer9_irqs),
4430         .main_clk       = "timer9_fck",
4431         .prcm = {
4432                 .omap4 = {
4433                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4434                 },
4435         },
4436         .slaves         = omap44xx_timer9_slaves,
4437         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4438         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4439 };
4440
4441 /* timer10 */
4442 static struct omap_hwmod omap44xx_timer10_hwmod;
4443 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4444         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4445 };
4446
4447 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4448         {
4449                 .pa_start       = 0x48086000,
4450                 .pa_end         = 0x4808607f,
4451                 .flags          = ADDR_TYPE_RT
4452         },
4453 };
4454
4455 /* l4_per -> timer10 */
4456 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4457         .master         = &omap44xx_l4_per_hwmod,
4458         .slave          = &omap44xx_timer10_hwmod,
4459         .clk            = "l4_div_ck",
4460         .addr           = omap44xx_timer10_addrs,
4461         .addr_cnt       = ARRAY_SIZE(omap44xx_timer10_addrs),
4462         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4463 };
4464
4465 /* timer10 slave ports */
4466 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4467         &omap44xx_l4_per__timer10,
4468 };
4469
4470 static struct omap_hwmod omap44xx_timer10_hwmod = {
4471         .name           = "timer10",
4472         .class          = &omap44xx_timer_1ms_hwmod_class,
4473         .mpu_irqs       = omap44xx_timer10_irqs,
4474         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer10_irqs),
4475         .main_clk       = "timer10_fck",
4476         .prcm = {
4477                 .omap4 = {
4478                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4479                 },
4480         },
4481         .slaves         = omap44xx_timer10_slaves,
4482         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4483         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4484 };
4485
4486 /* timer11 */
4487 static struct omap_hwmod omap44xx_timer11_hwmod;
4488 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4489         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4490 };
4491
4492 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4493         {
4494                 .pa_start       = 0x48088000,
4495                 .pa_end         = 0x4808807f,
4496                 .flags          = ADDR_TYPE_RT
4497         },
4498 };
4499
4500 /* l4_per -> timer11 */
4501 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4502         .master         = &omap44xx_l4_per_hwmod,
4503         .slave          = &omap44xx_timer11_hwmod,
4504         .clk            = "l4_div_ck",
4505         .addr           = omap44xx_timer11_addrs,
4506         .addr_cnt       = ARRAY_SIZE(omap44xx_timer11_addrs),
4507         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4508 };
4509
4510 /* timer11 slave ports */
4511 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4512         &omap44xx_l4_per__timer11,
4513 };
4514
4515 static struct omap_hwmod omap44xx_timer11_hwmod = {
4516         .name           = "timer11",
4517         .class          = &omap44xx_timer_hwmod_class,
4518         .mpu_irqs       = omap44xx_timer11_irqs,
4519         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer11_irqs),
4520         .main_clk       = "timer11_fck",
4521         .prcm = {
4522                 .omap4 = {
4523                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4524                 },
4525         },
4526         .slaves         = omap44xx_timer11_slaves,
4527         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4528         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4529 };
4530
4531 /*
4532  * 'uart' class
4533  * universal asynchronous receiver/transmitter (uart)
4534  */
4535
4536 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4537         .rev_offs       = 0x0050,
4538         .sysc_offs      = 0x0054,
4539         .syss_offs      = 0x0058,
4540         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4541                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4542                            SYSS_HAS_RESET_STATUS),
4543         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4544                            SIDLE_SMART_WKUP),
4545         .sysc_fields    = &omap_hwmod_sysc_type1,
4546 };
4547
4548 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4549         .name   = "uart",
4550         .sysc   = &omap44xx_uart_sysc,
4551 };
4552
4553 /* uart1 */
4554 static struct omap_hwmod omap44xx_uart1_hwmod;
4555 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4556         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4557 };
4558
4559 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4560         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4561         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4562 };
4563
4564 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4565         {
4566                 .pa_start       = 0x4806a000,
4567                 .pa_end         = 0x4806a0ff,
4568                 .flags          = ADDR_TYPE_RT
4569         },
4570 };
4571
4572 /* l4_per -> uart1 */
4573 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4574         .master         = &omap44xx_l4_per_hwmod,
4575         .slave          = &omap44xx_uart1_hwmod,
4576         .clk            = "l4_div_ck",
4577         .addr           = omap44xx_uart1_addrs,
4578         .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
4579         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4580 };
4581
4582 /* uart1 slave ports */
4583 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4584         &omap44xx_l4_per__uart1,
4585 };
4586
4587 static struct omap_hwmod omap44xx_uart1_hwmod = {
4588         .name           = "uart1",
4589         .class          = &omap44xx_uart_hwmod_class,
4590         .mpu_irqs       = omap44xx_uart1_irqs,
4591         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
4592         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4593         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
4594         .main_clk       = "uart1_fck",
4595         .prcm = {
4596                 .omap4 = {
4597                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
4598                 },
4599         },
4600         .slaves         = omap44xx_uart1_slaves,
4601         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4602         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4603 };
4604
4605 /* uart2 */
4606 static struct omap_hwmod omap44xx_uart2_hwmod;
4607 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4608         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4609 };
4610
4611 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4612         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4613         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4614 };
4615
4616 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4617         {
4618                 .pa_start       = 0x4806c000,
4619                 .pa_end         = 0x4806c0ff,
4620                 .flags          = ADDR_TYPE_RT
4621         },
4622 };
4623
4624 /* l4_per -> uart2 */
4625 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4626         .master         = &omap44xx_l4_per_hwmod,
4627         .slave          = &omap44xx_uart2_hwmod,
4628         .clk            = "l4_div_ck",
4629         .addr           = omap44xx_uart2_addrs,
4630         .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
4631         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4632 };
4633
4634 /* uart2 slave ports */
4635 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4636         &omap44xx_l4_per__uart2,
4637 };
4638
4639 static struct omap_hwmod omap44xx_uart2_hwmod = {
4640         .name           = "uart2",
4641         .class          = &omap44xx_uart_hwmod_class,
4642         .mpu_irqs       = omap44xx_uart2_irqs,
4643         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
4644         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4645         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
4646         .main_clk       = "uart2_fck",
4647         .prcm = {
4648                 .omap4 = {
4649                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
4650                 },
4651         },
4652         .slaves         = omap44xx_uart2_slaves,
4653         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4654         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4655 };
4656
4657 /* uart3 */
4658 static struct omap_hwmod omap44xx_uart3_hwmod;
4659 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4660         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4661 };
4662
4663 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4664         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4665         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4666 };
4667
4668 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4669         {
4670                 .pa_start       = 0x48020000,
4671                 .pa_end         = 0x480200ff,
4672                 .flags          = ADDR_TYPE_RT
4673         },
4674 };
4675
4676 /* l4_per -> uart3 */
4677 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4678         .master         = &omap44xx_l4_per_hwmod,
4679         .slave          = &omap44xx_uart3_hwmod,
4680         .clk            = "l4_div_ck",
4681         .addr           = omap44xx_uart3_addrs,
4682         .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
4683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4684 };
4685
4686 /* uart3 slave ports */
4687 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4688         &omap44xx_l4_per__uart3,
4689 };
4690
4691 static struct omap_hwmod omap44xx_uart3_hwmod = {
4692         .name           = "uart3",
4693         .class          = &omap44xx_uart_hwmod_class,
4694         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
4695         .mpu_irqs       = omap44xx_uart3_irqs,
4696         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
4697         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
4698         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
4699         .main_clk       = "uart3_fck",
4700         .prcm = {
4701                 .omap4 = {
4702                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
4703                 },
4704         },
4705         .slaves         = omap44xx_uart3_slaves,
4706         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
4707         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4708 };
4709
4710 /* uart4 */
4711 static struct omap_hwmod omap44xx_uart4_hwmod;
4712 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4713         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4714 };
4715
4716 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4717         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4718         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4719 };
4720
4721 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4722         {
4723                 .pa_start       = 0x4806e000,
4724                 .pa_end         = 0x4806e0ff,
4725                 .flags          = ADDR_TYPE_RT
4726         },
4727 };
4728
4729 /* l4_per -> uart4 */
4730 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4731         .master         = &omap44xx_l4_per_hwmod,
4732         .slave          = &omap44xx_uart4_hwmod,
4733         .clk            = "l4_div_ck",
4734         .addr           = omap44xx_uart4_addrs,
4735         .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
4736         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4737 };
4738
4739 /* uart4 slave ports */
4740 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4741         &omap44xx_l4_per__uart4,
4742 };
4743
4744 static struct omap_hwmod omap44xx_uart4_hwmod = {
4745         .name           = "uart4",
4746         .class          = &omap44xx_uart_hwmod_class,
4747         .mpu_irqs       = omap44xx_uart4_irqs,
4748         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
4749         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
4750         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
4751         .main_clk       = "uart4_fck",
4752         .prcm = {
4753                 .omap4 = {
4754                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
4755                 },
4756         },
4757         .slaves         = omap44xx_uart4_slaves,
4758         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
4759         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4760 };
4761
4762 /*
4763  * 'usb_otg_hs' class
4764  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4765  */
4766
4767 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4768         .rev_offs       = 0x0400,
4769         .sysc_offs      = 0x0404,
4770         .syss_offs      = 0x0408,
4771         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4772                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4773                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4774         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4775                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4776                            MSTANDBY_SMART),
4777         .sysc_fields    = &omap_hwmod_sysc_type1,
4778 };
4779
4780 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4781         .name = "usb_otg_hs",
4782         .sysc = &omap44xx_usb_otg_hs_sysc,
4783 };
4784
4785 /* usb_otg_hs */
4786 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4787         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4788         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4789 };
4790
4791 /* usb_otg_hs master ports */
4792 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4793         &omap44xx_usb_otg_hs__l3_main_2,
4794 };
4795
4796 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4797         {
4798                 .pa_start       = 0x4a0ab000,
4799                 .pa_end         = 0x4a0ab003,
4800                 .flags          = ADDR_TYPE_RT
4801         },
4802 };
4803
4804 /* l4_cfg -> usb_otg_hs */
4805 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4806         .master         = &omap44xx_l4_cfg_hwmod,
4807         .slave          = &omap44xx_usb_otg_hs_hwmod,
4808         .clk            = "l4_div_ck",
4809         .addr           = omap44xx_usb_otg_hs_addrs,
4810         .addr_cnt       = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
4811         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4812 };
4813
4814 /* usb_otg_hs slave ports */
4815 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4816         &omap44xx_l4_cfg__usb_otg_hs,
4817 };
4818
4819 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4820         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
4821 };
4822
4823 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4824         .name           = "usb_otg_hs",
4825         .class          = &omap44xx_usb_otg_hs_hwmod_class,
4826         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4827         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
4828         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
4829         .main_clk       = "usb_otg_hs_ick",
4830         .prcm = {
4831                 .omap4 = {
4832                         .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
4833                 },
4834         },
4835         .opt_clks       = usb_otg_hs_opt_clks,
4836         .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
4837         .slaves         = omap44xx_usb_otg_hs_slaves,
4838         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4839         .masters        = omap44xx_usb_otg_hs_masters,
4840         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
4841         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4842 };
4843
4844 /*
4845  * 'wd_timer' class
4846  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
4847  * overflow condition
4848  */
4849
4850 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
4851         .rev_offs       = 0x0000,
4852         .sysc_offs      = 0x0010,
4853         .syss_offs      = 0x0014,
4854         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
4855                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4856         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4857                            SIDLE_SMART_WKUP),
4858         .sysc_fields    = &omap_hwmod_sysc_type1,
4859 };
4860
4861 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4862         .name           = "wd_timer",
4863         .sysc           = &omap44xx_wd_timer_sysc,
4864         .pre_shutdown   = &omap2_wd_timer_disable,
4865 };
4866
4867 /* wd_timer2 */
4868 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4869 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4870         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
4871 };
4872
4873 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
4874         {
4875                 .pa_start       = 0x4a314000,
4876                 .pa_end         = 0x4a31407f,
4877                 .flags          = ADDR_TYPE_RT
4878         },
4879 };
4880
4881 /* l4_wkup -> wd_timer2 */
4882 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4883         .master         = &omap44xx_l4_wkup_hwmod,
4884         .slave          = &omap44xx_wd_timer2_hwmod,
4885         .clk            = "l4_wkup_clk_mux_ck",
4886         .addr           = omap44xx_wd_timer2_addrs,
4887         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
4888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4889 };
4890
4891 /* wd_timer2 slave ports */
4892 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
4893         &omap44xx_l4_wkup__wd_timer2,
4894 };
4895
4896 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4897         .name           = "wd_timer2",
4898         .class          = &omap44xx_wd_timer_hwmod_class,
4899         .mpu_irqs       = omap44xx_wd_timer2_irqs,
4900         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
4901         .main_clk       = "wd_timer2_fck",
4902         .prcm = {
4903                 .omap4 = {
4904                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
4905                 },
4906         },
4907         .slaves         = omap44xx_wd_timer2_slaves,
4908         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
4909         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4910 };
4911
4912 /* wd_timer3 */
4913 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
4914 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
4915         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
4916 };
4917
4918 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4919         {
4920                 .pa_start       = 0x40130000,
4921                 .pa_end         = 0x4013007f,
4922                 .flags          = ADDR_TYPE_RT
4923         },
4924 };
4925
4926 /* l4_abe -> wd_timer3 */
4927 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4928         .master         = &omap44xx_l4_abe_hwmod,
4929         .slave          = &omap44xx_wd_timer3_hwmod,
4930         .clk            = "ocp_abe_iclk",
4931         .addr           = omap44xx_wd_timer3_addrs,
4932         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
4933         .user           = OCP_USER_MPU,
4934 };
4935
4936 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4937         {
4938                 .pa_start       = 0x49030000,
4939                 .pa_end         = 0x4903007f,
4940                 .flags          = ADDR_TYPE_RT
4941         },
4942 };
4943
4944 /* l4_abe -> wd_timer3 (dma) */
4945 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4946         .master         = &omap44xx_l4_abe_hwmod,
4947         .slave          = &omap44xx_wd_timer3_hwmod,
4948         .clk            = "ocp_abe_iclk",
4949         .addr           = omap44xx_wd_timer3_dma_addrs,
4950         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
4951         .user           = OCP_USER_SDMA,
4952 };
4953
4954 /* wd_timer3 slave ports */
4955 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
4956         &omap44xx_l4_abe__wd_timer3,
4957         &omap44xx_l4_abe__wd_timer3_dma,
4958 };
4959
4960 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
4961         .name           = "wd_timer3",
4962         .class          = &omap44xx_wd_timer_hwmod_class,
4963         .mpu_irqs       = omap44xx_wd_timer3_irqs,
4964         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
4965         .main_clk       = "wd_timer3_fck",
4966         .prcm = {
4967                 .omap4 = {
4968                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
4969                 },
4970         },
4971         .slaves         = omap44xx_wd_timer3_slaves,
4972         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
4973         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4974 };
4975
4976 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
4977
4978         /* dmm class */
4979         &omap44xx_dmm_hwmod,
4980
4981         /* emif_fw class */
4982         &omap44xx_emif_fw_hwmod,
4983
4984         /* l3 class */
4985         &omap44xx_l3_instr_hwmod,
4986         &omap44xx_l3_main_1_hwmod,
4987         &omap44xx_l3_main_2_hwmod,
4988         &omap44xx_l3_main_3_hwmod,
4989
4990         /* l4 class */
4991         &omap44xx_l4_abe_hwmod,
4992         &omap44xx_l4_cfg_hwmod,
4993         &omap44xx_l4_per_hwmod,
4994         &omap44xx_l4_wkup_hwmod,
4995
4996         /* mpu_bus class */
4997         &omap44xx_mpu_private_hwmod,
4998
4999         /* aess class */
5000 /*      &omap44xx_aess_hwmod, */
5001
5002         /* bandgap class */
5003         &omap44xx_bandgap_hwmod,
5004
5005         /* counter class */
5006 /*      &omap44xx_counter_32k_hwmod, */
5007
5008         /* dma class */
5009         &omap44xx_dma_system_hwmod,
5010
5011         /* dmic class */
5012         &omap44xx_dmic_hwmod,
5013
5014         /* dsp class */
5015         &omap44xx_dsp_hwmod,
5016         &omap44xx_dsp_c0_hwmod,
5017
5018         /* dss class */
5019         &omap44xx_dss_hwmod,
5020         &omap44xx_dss_dispc_hwmod,
5021         &omap44xx_dss_dsi1_hwmod,
5022         &omap44xx_dss_dsi2_hwmod,
5023         &omap44xx_dss_hdmi_hwmod,
5024         &omap44xx_dss_rfbi_hwmod,
5025         &omap44xx_dss_venc_hwmod,
5026
5027         /* gpio class */
5028         &omap44xx_gpio1_hwmod,
5029         &omap44xx_gpio2_hwmod,
5030         &omap44xx_gpio3_hwmod,
5031         &omap44xx_gpio4_hwmod,
5032         &omap44xx_gpio5_hwmod,
5033         &omap44xx_gpio6_hwmod,
5034
5035         /* hsi class */
5036 /*      &omap44xx_hsi_hwmod, */
5037
5038         /* i2c class */
5039         &omap44xx_i2c1_hwmod,
5040         &omap44xx_i2c2_hwmod,
5041         &omap44xx_i2c3_hwmod,
5042         &omap44xx_i2c4_hwmod,
5043
5044         /* ipu class */
5045         &omap44xx_ipu_hwmod,
5046         &omap44xx_ipu_c0_hwmod,
5047         &omap44xx_ipu_c1_hwmod,
5048
5049         /* iss class */
5050 /*      &omap44xx_iss_hwmod, */
5051
5052         /* iva class */
5053         &omap44xx_iva_hwmod,
5054         &omap44xx_iva_seq0_hwmod,
5055         &omap44xx_iva_seq1_hwmod,
5056
5057         /* kbd class */
5058 /*      &omap44xx_kbd_hwmod, */
5059
5060         /* mailbox class */
5061         &omap44xx_mailbox_hwmod,
5062
5063         /* mcbsp class */
5064         &omap44xx_mcbsp1_hwmod,
5065         &omap44xx_mcbsp2_hwmod,
5066         &omap44xx_mcbsp3_hwmod,
5067         &omap44xx_mcbsp4_hwmod,
5068
5069         /* mcpdm class */
5070 /*      &omap44xx_mcpdm_hwmod, */
5071
5072         /* mcspi class */
5073         &omap44xx_mcspi1_hwmod,
5074         &omap44xx_mcspi2_hwmod,
5075         &omap44xx_mcspi3_hwmod,
5076         &omap44xx_mcspi4_hwmod,
5077
5078         /* mmc class */
5079 /*      &omap44xx_mmc1_hwmod, */
5080 /*      &omap44xx_mmc2_hwmod, */
5081 /*      &omap44xx_mmc3_hwmod, */
5082 /*      &omap44xx_mmc4_hwmod, */
5083 /*      &omap44xx_mmc5_hwmod, */
5084
5085         /* mpu class */
5086         &omap44xx_mpu_hwmod,
5087
5088         /* smartreflex class */
5089         &omap44xx_smartreflex_core_hwmod,
5090         &omap44xx_smartreflex_iva_hwmod,
5091         &omap44xx_smartreflex_mpu_hwmod,
5092
5093         /* spinlock class */
5094         &omap44xx_spinlock_hwmod,
5095
5096         /* timer class */
5097         &omap44xx_timer1_hwmod,
5098         &omap44xx_timer2_hwmod,
5099         &omap44xx_timer3_hwmod,
5100         &omap44xx_timer4_hwmod,
5101         &omap44xx_timer5_hwmod,
5102         &omap44xx_timer6_hwmod,
5103         &omap44xx_timer7_hwmod,
5104         &omap44xx_timer8_hwmod,
5105         &omap44xx_timer9_hwmod,
5106         &omap44xx_timer10_hwmod,
5107         &omap44xx_timer11_hwmod,
5108
5109         /* uart class */
5110         &omap44xx_uart1_hwmod,
5111         &omap44xx_uart2_hwmod,
5112         &omap44xx_uart3_hwmod,
5113         &omap44xx_uart4_hwmod,
5114
5115         /* usb_otg_hs class */
5116         &omap44xx_usb_otg_hs_hwmod,
5117
5118         /* wd_timer class */
5119         &omap44xx_wd_timer2_hwmod,
5120         &omap44xx_wd_timer3_hwmod,
5121
5122         NULL,
5123 };
5124
5125 int __init omap44xx_hwmod_init(void)
5126 {
5127         return omap_hwmod_init(omap44xx_hwmods);
5128 }
5129