arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "prm-regbits-34xx.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "wd_timer.h"
  35 #include <mach/am35xx.h>
  36
  37 /*
  38  * OMAP3xxx hardware module integration data
  39  *
  40  * ALl of the data in this section should be autogeneratable from the
  41  * TI hardware database or other technical documentation.  Data that
  42  * is driver-specific or driver-kernel integration-specific belongs
  43  * elsewhere.
  44  */
  45
  46 static struct omap_hwmod omap3xxx_mpu_hwmod;
  47 static struct omap_hwmod omap3xxx_iva_hwmod;
  48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  67 static struct omap_hwmod omap34xx_sr1_hwmod;
  68 static struct omap_hwmod omap34xx_sr2_hwmod;
  69 static struct omap_hwmod omap34xx_mcspi1;
  70 static struct omap_hwmod omap34xx_mcspi2;
  71 static struct omap_hwmod omap34xx_mcspi3;
  72 static struct omap_hwmod omap34xx_mcspi4;
  73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  77
  78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  79
  80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  87
  88 /* L3 -> L4_CORE interface */
  89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  90         .master = &omap3xxx_l3_main_hwmod,
  91         .slave  = &omap3xxx_l4_core_hwmod,
  92         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  93 };
  94
  95 /* L3 -> L4_PER interface */
  96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  97         .master = &omap3xxx_l3_main_hwmod,
  98         .slave  = &omap3xxx_l4_per_hwmod,
  99         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 100 };
 101
 102 /* L3 taret configuration and error log registers */
 103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 104         { .irq = INT_34XX_L3_DBG_IRQ },
 105         { .irq = INT_34XX_L3_APP_IRQ },
 106 };
 107
 108 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 109         {
 110                 .pa_start       = 0x68000000,
 111                 .pa_end         = 0x6800ffff,
 112                 .flags          = ADDR_TYPE_RT,
 113         },
 114         { }
 115 };
 116
 117 /* MPU -> L3 interface */
 118 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 119         .master   = &omap3xxx_mpu_hwmod,
 120         .slave    = &omap3xxx_l3_main_hwmod,
 121         .addr     = omap3xxx_l3_main_addrs,
 122         .user   = OCP_USER_MPU,
 123 };
 124
 125 /* Slave interfaces on the L3 interconnect */
 126 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 127         &omap3xxx_mpu__l3_main,
 128 };
 129
 130 /* DSS -> l3 */
 131 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 132         .master         = &omap3xxx_dss_core_hwmod,
 133         .slave          = &omap3xxx_l3_main_hwmod,
 134         .fw = {
 135                 .omap2 = {
 136                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 137                         .flags  = OMAP_FIREWALL_L3,
 138                 }
 139         },
 140         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 141 };
 142
 143 /* Master interfaces on the L3 interconnect */
 144 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 145         &omap3xxx_l3_main__l4_core,
 146         &omap3xxx_l3_main__l4_per,
 147 };
 148
 149 /* L3 */
 150 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 151         .name           = "l3_main",
 152         .class          = &l3_hwmod_class,
 153         .mpu_irqs       = omap3xxx_l3_main_irqs,
 154         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_l3_main_irqs),
 155         .masters        = omap3xxx_l3_main_masters,
 156         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 157         .slaves         = omap3xxx_l3_main_slaves,
 158         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 159         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 160         .flags          = HWMOD_NO_IDLEST,
 161 };
 162
 163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 164 static struct omap_hwmod omap3xxx_uart1_hwmod;
 165 static struct omap_hwmod omap3xxx_uart2_hwmod;
 166 static struct omap_hwmod omap3xxx_uart3_hwmod;
 167 static struct omap_hwmod omap3xxx_uart4_hwmod;
 168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 169
 170 /* l3_core -> usbhsotg interface */
 171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 172         .master         = &omap3xxx_usbhsotg_hwmod,
 173         .slave          = &omap3xxx_l3_main_hwmod,
 174         .clk            = "core_l3_ick",
 175         .user           = OCP_USER_MPU,
 176 };
 177
 178 /* l3_core -> am35xx_usbhsotg interface */
 179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 180         .master         = &am35xx_usbhsotg_hwmod,
 181         .slave          = &omap3xxx_l3_main_hwmod,
 182         .clk            = "core_l3_ick",
 183         .user           = OCP_USER_MPU,
 184 };
 185 /* L4_CORE -> L4_WKUP interface */
 186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 187         .master = &omap3xxx_l4_core_hwmod,
 188         .slave  = &omap3xxx_l4_wkup_hwmod,
 189         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 190 };
 191
 192 /* L4 CORE -> MMC1 interface */
 193 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 194         .master         = &omap3xxx_l4_core_hwmod,
 195         .slave          = &omap3xxx_mmc1_hwmod,
 196         .clk            = "mmchs1_ick",
 197         .addr           = omap2430_mmc1_addr_space,
 198         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 199         .flags          = OMAP_FIREWALL_L4
 200 };
 201
 202 /* L4 CORE -> MMC2 interface */
 203 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 204         .master         = &omap3xxx_l4_core_hwmod,
 205         .slave          = &omap3xxx_mmc2_hwmod,
 206         .clk            = "mmchs2_ick",
 207         .addr           = omap2430_mmc2_addr_space,
 208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 209         .flags          = OMAP_FIREWALL_L4
 210 };
 211
 212 /* L4 CORE -> MMC3 interface */
 213 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 214         {
 215                 .pa_start       = 0x480ad000,
 216                 .pa_end         = 0x480ad1ff,
 217                 .flags          = ADDR_TYPE_RT,
 218         },
 219         { }
 220 };
 221
 222 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 223         .master         = &omap3xxx_l4_core_hwmod,
 224         .slave          = &omap3xxx_mmc3_hwmod,
 225         .clk            = "mmchs3_ick",
 226         .addr           = omap3xxx_mmc3_addr_space,
 227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 228         .flags          = OMAP_FIREWALL_L4
 229 };
 230
 231 /* L4 CORE -> UART1 interface */
 232 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 233         {
 234                 .pa_start       = OMAP3_UART1_BASE,
 235                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 236                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 237         },
 238         { }
 239 };
 240
 241 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 242         .master         = &omap3xxx_l4_core_hwmod,
 243         .slave          = &omap3xxx_uart1_hwmod,
 244         .clk            = "uart1_ick",
 245         .addr           = omap3xxx_uart1_addr_space,
 246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 247 };
 248
 249 /* L4 CORE -> UART2 interface */
 250 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 251         {
 252                 .pa_start       = OMAP3_UART2_BASE,
 253                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 254                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 255         },
 256         { }
 257 };
 258
 259 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 260         .master         = &omap3xxx_l4_core_hwmod,
 261         .slave          = &omap3xxx_uart2_hwmod,
 262         .clk            = "uart2_ick",
 263         .addr           = omap3xxx_uart2_addr_space,
 264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 265 };
 266
 267 /* L4 PER -> UART3 interface */
 268 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 269         {
 270                 .pa_start       = OMAP3_UART3_BASE,
 271                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 272                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 273         },
 274         { }
 275 };
 276
 277 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 278         .master         = &omap3xxx_l4_per_hwmod,
 279         .slave          = &omap3xxx_uart3_hwmod,
 280         .clk            = "uart3_ick",
 281         .addr           = omap3xxx_uart3_addr_space,
 282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 283 };
 284
 285 /* L4 PER -> UART4 interface */
 286 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 287         {
 288                 .pa_start       = OMAP3_UART4_BASE,
 289                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 290                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 291         },
 292         { }
 293 };
 294
 295 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 296         .master         = &omap3xxx_l4_per_hwmod,
 297         .slave          = &omap3xxx_uart4_hwmod,
 298         .clk            = "uart4_ick",
 299         .addr           = omap3xxx_uart4_addr_space,
 300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 301 };
 302
 303 /* L4 CORE -> I2C1 interface */
 304 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 305         .master         = &omap3xxx_l4_core_hwmod,
 306         .slave          = &omap3xxx_i2c1_hwmod,
 307         .clk            = "i2c1_ick",
 308         .addr           = omap2_i2c1_addr_space,
 309         .fw = {
 310                 .omap2 = {
 311                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 312                         .l4_prot_group = 7,
 313                         .flags  = OMAP_FIREWALL_L4,
 314                 }
 315         },
 316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 317 };
 318
 319 /* L4 CORE -> I2C2 interface */
 320 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 321         .master         = &omap3xxx_l4_core_hwmod,
 322         .slave          = &omap3xxx_i2c2_hwmod,
 323         .clk            = "i2c2_ick",
 324         .addr           = omap2_i2c2_addr_space,
 325         .fw = {
 326                 .omap2 = {
 327                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 328                         .l4_prot_group = 7,
 329                         .flags = OMAP_FIREWALL_L4,
 330                 }
 331         },
 332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 333 };
 334
 335 /* L4 CORE -> I2C3 interface */
 336 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 337         {
 338                 .pa_start       = 0x48060000,
 339                 .pa_end         = 0x48060000 + SZ_128 - 1,
 340                 .flags          = ADDR_TYPE_RT,
 341         },
 342         { }
 343 };
 344
 345 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 346         .master         = &omap3xxx_l4_core_hwmod,
 347         .slave          = &omap3xxx_i2c3_hwmod,
 348         .clk            = "i2c3_ick",
 349         .addr           = omap3xxx_i2c3_addr_space,
 350         .fw = {
 351                 .omap2 = {
 352                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 353                         .l4_prot_group = 7,
 354                         .flags = OMAP_FIREWALL_L4,
 355                 }
 356         },
 357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 358 };
 359
 360 /* L4 CORE -> SR1 interface */
 361 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 362         {
 363                 .pa_start       = OMAP34XX_SR1_BASE,
 364                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 365                 .flags          = ADDR_TYPE_RT,
 366         },
 367         { }
 368 };
 369
 370 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 371         .master         = &omap3xxx_l4_core_hwmod,
 372         .slave          = &omap34xx_sr1_hwmod,
 373         .clk            = "sr_l4_ick",
 374         .addr           = omap3_sr1_addr_space,
 375         .user           = OCP_USER_MPU,
 376 };
 377
 378 /* L4 CORE -> SR1 interface */
 379 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 380         {
 381                 .pa_start       = OMAP34XX_SR2_BASE,
 382                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 383                 .flags          = ADDR_TYPE_RT,
 384         },
 385         { }
 386 };
 387
 388 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 389         .master         = &omap3xxx_l4_core_hwmod,
 390         .slave          = &omap34xx_sr2_hwmod,
 391         .clk            = "sr_l4_ick",
 392         .addr           = omap3_sr2_addr_space,
 393         .user           = OCP_USER_MPU,
 394 };
 395
 396 /*
 397 * usbhsotg interface data
 398 */
 399
 400 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 401         {
 402                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 403                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 404                 .flags          = ADDR_TYPE_RT
 405         },
 406         { }
 407 };
 408
 409 /* l4_core -> usbhsotg  */
 410 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 411         .master         = &omap3xxx_l4_core_hwmod,
 412         .slave          = &omap3xxx_usbhsotg_hwmod,
 413         .clk            = "l4_ick",
 414         .addr           = omap3xxx_usbhsotg_addrs,
 415         .user           = OCP_USER_MPU,
 416 };
 417
 418 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 419         &omap3xxx_usbhsotg__l3,
 420 };
 421
 422 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 423         &omap3xxx_l4_core__usbhsotg,
 424 };
 425
 426 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 427         {
 428                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 429                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 430                 .flags          = ADDR_TYPE_RT
 431         },
 432         { }
 433 };
 434
 435 /* l4_core -> usbhsotg  */
 436 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 437         .master         = &omap3xxx_l4_core_hwmod,
 438         .slave          = &am35xx_usbhsotg_hwmod,
 439         .clk            = "l4_ick",
 440         .addr           = am35xx_usbhsotg_addrs,
 441         .user           = OCP_USER_MPU,
 442 };
 443
 444 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 445         &am35xx_usbhsotg__l3,
 446 };
 447
 448 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 449         &am35xx_l4_core__usbhsotg,
 450 };
 451 /* Slave interfaces on the L4_CORE interconnect */
 452 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 453         &omap3xxx_l3_main__l4_core,
 454 };
 455
 456 /* L4 CORE */
 457 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 458         .name           = "l4_core",
 459         .class          = &l4_hwmod_class,
 460         .slaves         = omap3xxx_l4_core_slaves,
 461         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 462         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 463         .flags          = HWMOD_NO_IDLEST,
 464 };
 465
 466 /* Slave interfaces on the L4_PER interconnect */
 467 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 468         &omap3xxx_l3_main__l4_per,
 469 };
 470
 471 /* L4 PER */
 472 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 473         .name           = "l4_per",
 474         .class          = &l4_hwmod_class,
 475         .slaves         = omap3xxx_l4_per_slaves,
 476         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 477         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 478         .flags          = HWMOD_NO_IDLEST,
 479 };
 480
 481 /* Slave interfaces on the L4_WKUP interconnect */
 482 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 483         &omap3xxx_l4_core__l4_wkup,
 484 };
 485
 486 /* L4 WKUP */
 487 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 488         .name           = "l4_wkup",
 489         .class          = &l4_hwmod_class,
 490         .slaves         = omap3xxx_l4_wkup_slaves,
 491         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 492         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 493         .flags          = HWMOD_NO_IDLEST,
 494 };
 495
 496 /* Master interfaces on the MPU device */
 497 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 498         &omap3xxx_mpu__l3_main,
 499 };
 500
 501 /* MPU */
 502 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 503         .name           = "mpu",
 504         .class          = &mpu_hwmod_class,
 505         .main_clk       = "arm_fck",
 506         .masters        = omap3xxx_mpu_masters,
 507         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 508         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 509 };
 510
 511 /*
 512  * IVA2_2 interface data
 513  */
 514
 515 /* IVA2 <- L3 interface */
 516 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 517         .master         = &omap3xxx_l3_main_hwmod,
 518         .slave          = &omap3xxx_iva_hwmod,
 519         .clk            = "iva2_ck",
 520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 521 };
 522
 523 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 524         &omap3xxx_l3__iva,
 525 };
 526
 527 /*
 528  * IVA2 (IVA2)
 529  */
 530
 531 static struct omap_hwmod omap3xxx_iva_hwmod = {
 532         .name           = "iva",
 533         .class          = &iva_hwmod_class,
 534         .masters        = omap3xxx_iva_masters,
 535         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 536         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 537 };
 538
 539 /* timer class */
 540 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 541         .rev_offs       = 0x0000,
 542         .sysc_offs      = 0x0010,
 543         .syss_offs      = 0x0014,
 544         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 545                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 546                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 547         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 548         .sysc_fields    = &omap_hwmod_sysc_type1,
 549 };
 550
 551 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 552         .name = "timer",
 553         .sysc = &omap3xxx_timer_1ms_sysc,
 554         .rev = OMAP_TIMER_IP_VERSION_1,
 555 };
 556
 557 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 558         .rev_offs       = 0x0000,
 559         .sysc_offs      = 0x0010,
 560         .syss_offs      = 0x0014,
 561         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 562                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 563         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 564         .sysc_fields    = &omap_hwmod_sysc_type1,
 565 };
 566
 567 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 568         .name = "timer",
 569         .sysc = &omap3xxx_timer_sysc,
 570         .rev =  OMAP_TIMER_IP_VERSION_1,
 571 };
 572
 573 /* timer1 */
 574 static struct omap_hwmod omap3xxx_timer1_hwmod;
 575 static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
 576         { .irq = 37, },
 577 };
 578
 579 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 580         {
 581                 .pa_start       = 0x48318000,
 582                 .pa_end         = 0x48318000 + SZ_1K - 1,
 583                 .flags          = ADDR_TYPE_RT
 584         },
 585         { }
 586 };
 587
 588 /* l4_wkup -> timer1 */
 589 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 590         .master         = &omap3xxx_l4_wkup_hwmod,
 591         .slave          = &omap3xxx_timer1_hwmod,
 592         .clk            = "gpt1_ick",
 593         .addr           = omap3xxx_timer1_addrs,
 594         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 595 };
 596
 597 /* timer1 slave port */
 598 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 599         &omap3xxx_l4_wkup__timer1,
 600 };
 601
 602 /* timer1 hwmod */
 603 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 604         .name           = "timer1",
 605         .mpu_irqs       = omap3xxx_timer1_mpu_irqs,
 606         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
 607         .main_clk       = "gpt1_fck",
 608         .prcm           = {
 609                 .omap2 = {
 610                         .prcm_reg_id = 1,
 611                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 612                         .module_offs = WKUP_MOD,
 613                         .idlest_reg_id = 1,
 614                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 615                 },
 616         },
 617         .slaves         = omap3xxx_timer1_slaves,
 618         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 619         .class          = &omap3xxx_timer_1ms_hwmod_class,
 620         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 621 };
 622
 623 /* timer2 */
 624 static struct omap_hwmod omap3xxx_timer2_hwmod;
 625 static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
 626         { .irq = 38, },
 627 };
 628
 629 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 630         {
 631                 .pa_start       = 0x49032000,
 632                 .pa_end         = 0x49032000 + SZ_1K - 1,
 633                 .flags          = ADDR_TYPE_RT
 634         },
 635         { }
 636 };
 637
 638 /* l4_per -> timer2 */
 639 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 640         .master         = &omap3xxx_l4_per_hwmod,
 641         .slave          = &omap3xxx_timer2_hwmod,
 642         .clk            = "gpt2_ick",
 643         .addr           = omap3xxx_timer2_addrs,
 644         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 645 };
 646
 647 /* timer2 slave port */
 648 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 649         &omap3xxx_l4_per__timer2,
 650 };
 651
 652 /* timer2 hwmod */
 653 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 654         .name           = "timer2",
 655         .mpu_irqs       = omap3xxx_timer2_mpu_irqs,
 656         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
 657         .main_clk       = "gpt2_fck",
 658         .prcm           = {
 659                 .omap2 = {
 660                         .prcm_reg_id = 1,
 661                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 662                         .module_offs = OMAP3430_PER_MOD,
 663                         .idlest_reg_id = 1,
 664                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 665                 },
 666         },
 667         .slaves         = omap3xxx_timer2_slaves,
 668         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 669         .class          = &omap3xxx_timer_1ms_hwmod_class,
 670         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 671 };
 672
 673 /* timer3 */
 674 static struct omap_hwmod omap3xxx_timer3_hwmod;
 675 static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
 676         { .irq = 39, },
 677 };
 678
 679 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 680         {
 681                 .pa_start       = 0x49034000,
 682                 .pa_end         = 0x49034000 + SZ_1K - 1,
 683                 .flags          = ADDR_TYPE_RT
 684         },
 685         { }
 686 };
 687
 688 /* l4_per -> timer3 */
 689 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 690         .master         = &omap3xxx_l4_per_hwmod,
 691         .slave          = &omap3xxx_timer3_hwmod,
 692         .clk            = "gpt3_ick",
 693         .addr           = omap3xxx_timer3_addrs,
 694         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 695 };
 696
 697 /* timer3 slave port */
 698 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 699         &omap3xxx_l4_per__timer3,
 700 };
 701
 702 /* timer3 hwmod */
 703 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 704         .name           = "timer3",
 705         .mpu_irqs       = omap3xxx_timer3_mpu_irqs,
 706         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
 707         .main_clk       = "gpt3_fck",
 708         .prcm           = {
 709                 .omap2 = {
 710                         .prcm_reg_id = 1,
 711                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 712                         .module_offs = OMAP3430_PER_MOD,
 713                         .idlest_reg_id = 1,
 714                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 715                 },
 716         },
 717         .slaves         = omap3xxx_timer3_slaves,
 718         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 719         .class          = &omap3xxx_timer_hwmod_class,
 720         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 721 };
 722
 723 /* timer4 */
 724 static struct omap_hwmod omap3xxx_timer4_hwmod;
 725 static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
 726         { .irq = 40, },
 727 };
 728
 729 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 730         {
 731                 .pa_start       = 0x49036000,
 732                 .pa_end         = 0x49036000 + SZ_1K - 1,
 733                 .flags          = ADDR_TYPE_RT
 734         },
 735         { }
 736 };
 737
 738 /* l4_per -> timer4 */
 739 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 740         .master         = &omap3xxx_l4_per_hwmod,
 741         .slave          = &omap3xxx_timer4_hwmod,
 742         .clk            = "gpt4_ick",
 743         .addr           = omap3xxx_timer4_addrs,
 744         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 745 };
 746
 747 /* timer4 slave port */
 748 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 749         &omap3xxx_l4_per__timer4,
 750 };
 751
 752 /* timer4 hwmod */
 753 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 754         .name           = "timer4",
 755         .mpu_irqs       = omap3xxx_timer4_mpu_irqs,
 756         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
 757         .main_clk       = "gpt4_fck",
 758         .prcm           = {
 759                 .omap2 = {
 760                         .prcm_reg_id = 1,
 761                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 762                         .module_offs = OMAP3430_PER_MOD,
 763                         .idlest_reg_id = 1,
 764                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 765                 },
 766         },
 767         .slaves         = omap3xxx_timer4_slaves,
 768         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 769         .class          = &omap3xxx_timer_hwmod_class,
 770         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 771 };
 772
 773 /* timer5 */
 774 static struct omap_hwmod omap3xxx_timer5_hwmod;
 775 static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
 776         { .irq = 41, },
 777 };
 778
 779 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 780         {
 781                 .pa_start       = 0x49038000,
 782                 .pa_end         = 0x49038000 + SZ_1K - 1,
 783                 .flags          = ADDR_TYPE_RT
 784         },
 785         { }
 786 };
 787
 788 /* l4_per -> timer5 */
 789 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 790         .master         = &omap3xxx_l4_per_hwmod,
 791         .slave          = &omap3xxx_timer5_hwmod,
 792         .clk            = "gpt5_ick",
 793         .addr           = omap3xxx_timer5_addrs,
 794         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 795 };
 796
 797 /* timer5 slave port */
 798 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 799         &omap3xxx_l4_per__timer5,
 800 };
 801
 802 /* timer5 hwmod */
 803 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 804         .name           = "timer5",
 805         .mpu_irqs       = omap3xxx_timer5_mpu_irqs,
 806         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
 807         .main_clk       = "gpt5_fck",
 808         .prcm           = {
 809                 .omap2 = {
 810                         .prcm_reg_id = 1,
 811                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 812                         .module_offs = OMAP3430_PER_MOD,
 813                         .idlest_reg_id = 1,
 814                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 815                 },
 816         },
 817         .slaves         = omap3xxx_timer5_slaves,
 818         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 819         .class          = &omap3xxx_timer_hwmod_class,
 820         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 821 };
 822
 823 /* timer6 */
 824 static struct omap_hwmod omap3xxx_timer6_hwmod;
 825 static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
 826         { .irq = 42, },
 827 };
 828
 829 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 830         {
 831                 .pa_start       = 0x4903A000,
 832                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 833                 .flags          = ADDR_TYPE_RT
 834         },
 835         { }
 836 };
 837
 838 /* l4_per -> timer6 */
 839 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 840         .master         = &omap3xxx_l4_per_hwmod,
 841         .slave          = &omap3xxx_timer6_hwmod,
 842         .clk            = "gpt6_ick",
 843         .addr           = omap3xxx_timer6_addrs,
 844         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 845 };
 846
 847 /* timer6 slave port */
 848 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 849         &omap3xxx_l4_per__timer6,
 850 };
 851
 852 /* timer6 hwmod */
 853 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 854         .name           = "timer6",
 855         .mpu_irqs       = omap3xxx_timer6_mpu_irqs,
 856         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
 857         .main_clk       = "gpt6_fck",
 858         .prcm           = {
 859                 .omap2 = {
 860                         .prcm_reg_id = 1,
 861                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 862                         .module_offs = OMAP3430_PER_MOD,
 863                         .idlest_reg_id = 1,
 864                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 865                 },
 866         },
 867         .slaves         = omap3xxx_timer6_slaves,
 868         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 869         .class          = &omap3xxx_timer_hwmod_class,
 870         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 871 };
 872
 873 /* timer7 */
 874 static struct omap_hwmod omap3xxx_timer7_hwmod;
 875 static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
 876         { .irq = 43, },
 877 };
 878
 879 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 880         {
 881                 .pa_start       = 0x4903C000,
 882                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 883                 .flags          = ADDR_TYPE_RT
 884         },
 885         { }
 886 };
 887
 888 /* l4_per -> timer7 */
 889 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 890         .master         = &omap3xxx_l4_per_hwmod,
 891         .slave          = &omap3xxx_timer7_hwmod,
 892         .clk            = "gpt7_ick",
 893         .addr           = omap3xxx_timer7_addrs,
 894         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 895 };
 896
 897 /* timer7 slave port */
 898 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 899         &omap3xxx_l4_per__timer7,
 900 };
 901
 902 /* timer7 hwmod */
 903 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 904         .name           = "timer7",
 905         .mpu_irqs       = omap3xxx_timer7_mpu_irqs,
 906         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
 907         .main_clk       = "gpt7_fck",
 908         .prcm           = {
 909                 .omap2 = {
 910                         .prcm_reg_id = 1,
 911                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 912                         .module_offs = OMAP3430_PER_MOD,
 913                         .idlest_reg_id = 1,
 914                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 915                 },
 916         },
 917         .slaves         = omap3xxx_timer7_slaves,
 918         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 919         .class          = &omap3xxx_timer_hwmod_class,
 920         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 921 };
 922
 923 /* timer8 */
 924 static struct omap_hwmod omap3xxx_timer8_hwmod;
 925 static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
 926         { .irq = 44, },
 927 };
 928
 929 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 930         {
 931                 .pa_start       = 0x4903E000,
 932                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 933                 .flags          = ADDR_TYPE_RT
 934         },
 935         { }
 936 };
 937
 938 /* l4_per -> timer8 */
 939 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 940         .master         = &omap3xxx_l4_per_hwmod,
 941         .slave          = &omap3xxx_timer8_hwmod,
 942         .clk            = "gpt8_ick",
 943         .addr           = omap3xxx_timer8_addrs,
 944         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 945 };
 946
 947 /* timer8 slave port */
 948 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 949         &omap3xxx_l4_per__timer8,
 950 };
 951
 952 /* timer8 hwmod */
 953 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 954         .name           = "timer8",
 955         .mpu_irqs       = omap3xxx_timer8_mpu_irqs,
 956         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
 957         .main_clk       = "gpt8_fck",
 958         .prcm           = {
 959                 .omap2 = {
 960                         .prcm_reg_id = 1,
 961                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 962                         .module_offs = OMAP3430_PER_MOD,
 963                         .idlest_reg_id = 1,
 964                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 965                 },
 966         },
 967         .slaves         = omap3xxx_timer8_slaves,
 968         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
 969         .class          = &omap3xxx_timer_hwmod_class,
 970         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 971 };
 972
 973 /* timer9 */
 974 static struct omap_hwmod omap3xxx_timer9_hwmod;
 975 static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
 976         { .irq = 45, },
 977 };
 978
 979 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
 980         {
 981                 .pa_start       = 0x49040000,
 982                 .pa_end         = 0x49040000 + SZ_1K - 1,
 983                 .flags          = ADDR_TYPE_RT
 984         },
 985         { }
 986 };
 987
 988 /* l4_per -> timer9 */
 989 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
 990         .master         = &omap3xxx_l4_per_hwmod,
 991         .slave          = &omap3xxx_timer9_hwmod,
 992         .clk            = "gpt9_ick",
 993         .addr           = omap3xxx_timer9_addrs,
 994         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 995 };
 996
 997 /* timer9 slave port */
 998 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
 999         &omap3xxx_l4_per__timer9,
1000 };
1001
1002 /* timer9 hwmod */
1003 static struct omap_hwmod omap3xxx_timer9_hwmod = {
1004         .name           = "timer9",
1005         .mpu_irqs       = omap3xxx_timer9_mpu_irqs,
1006         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
1007         .main_clk       = "gpt9_fck",
1008         .prcm           = {
1009                 .omap2 = {
1010                         .prcm_reg_id = 1,
1011                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
1012                         .module_offs = OMAP3430_PER_MOD,
1013                         .idlest_reg_id = 1,
1014                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1015                 },
1016         },
1017         .slaves         = omap3xxx_timer9_slaves,
1018         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
1019         .class          = &omap3xxx_timer_hwmod_class,
1020         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1021 };
1022
1023 /* timer10 */
1024 static struct omap_hwmod omap3xxx_timer10_hwmod;
1025 static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1026         { .irq = 46, },
1027 };
1028
1029 /* l4_core -> timer10 */
1030 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1031         .master         = &omap3xxx_l4_core_hwmod,
1032         .slave          = &omap3xxx_timer10_hwmod,
1033         .clk            = "gpt10_ick",
1034         .addr           = omap2_timer10_addrs,
1035         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1036 };
1037
1038 /* timer10 slave port */
1039 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1040         &omap3xxx_l4_core__timer10,
1041 };
1042
1043 /* timer10 hwmod */
1044 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1045         .name           = "timer10",
1046         .mpu_irqs       = omap3xxx_timer10_mpu_irqs,
1047         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
1048         .main_clk       = "gpt10_fck",
1049         .prcm           = {
1050                 .omap2 = {
1051                         .prcm_reg_id = 1,
1052                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1053                         .module_offs = CORE_MOD,
1054                         .idlest_reg_id = 1,
1055                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1056                 },
1057         },
1058         .slaves         = omap3xxx_timer10_slaves,
1059         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1060         .class          = &omap3xxx_timer_1ms_hwmod_class,
1061         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1062 };
1063
1064 /* timer11 */
1065 static struct omap_hwmod omap3xxx_timer11_hwmod;
1066 static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1067         { .irq = 47, },
1068 };
1069
1070 /* l4_core -> timer11 */
1071 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1072         .master         = &omap3xxx_l4_core_hwmod,
1073         .slave          = &omap3xxx_timer11_hwmod,
1074         .clk            = "gpt11_ick",
1075         .addr           = omap2_timer11_addrs,
1076         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1077 };
1078
1079 /* timer11 slave port */
1080 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1081         &omap3xxx_l4_core__timer11,
1082 };
1083
1084 /* timer11 hwmod */
1085 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1086         .name           = "timer11",
1087         .mpu_irqs       = omap3xxx_timer11_mpu_irqs,
1088         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
1089         .main_clk       = "gpt11_fck",
1090         .prcm           = {
1091                 .omap2 = {
1092                         .prcm_reg_id = 1,
1093                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1094                         .module_offs = CORE_MOD,
1095                         .idlest_reg_id = 1,
1096                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1097                 },
1098         },
1099         .slaves         = omap3xxx_timer11_slaves,
1100         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1101         .class          = &omap3xxx_timer_hwmod_class,
1102         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1103 };
1104
1105 /* timer12*/
1106 static struct omap_hwmod omap3xxx_timer12_hwmod;
1107 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1108         { .irq = 95, },
1109 };
1110
1111 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1112         {
1113                 .pa_start       = 0x48304000,
1114                 .pa_end         = 0x48304000 + SZ_1K - 1,
1115                 .flags          = ADDR_TYPE_RT
1116         },
1117         { }
1118 };
1119
1120 /* l4_core -> timer12 */
1121 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1122         .master         = &omap3xxx_l4_core_hwmod,
1123         .slave          = &omap3xxx_timer12_hwmod,
1124         .clk            = "gpt12_ick",
1125         .addr           = omap3xxx_timer12_addrs,
1126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1127 };
1128
1129 /* timer12 slave port */
1130 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1131         &omap3xxx_l4_core__timer12,
1132 };
1133
1134 /* timer12 hwmod */
1135 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1136         .name           = "timer12",
1137         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1138         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
1139         .main_clk       = "gpt12_fck",
1140         .prcm           = {
1141                 .omap2 = {
1142                         .prcm_reg_id = 1,
1143                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1144                         .module_offs = WKUP_MOD,
1145                         .idlest_reg_id = 1,
1146                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1147                 },
1148         },
1149         .slaves         = omap3xxx_timer12_slaves,
1150         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1151         .class          = &omap3xxx_timer_hwmod_class,
1152         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1153 };
1154
1155 /* l4_wkup -> wd_timer2 */
1156 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1157         {
1158                 .pa_start       = 0x48314000,
1159                 .pa_end         = 0x4831407f,
1160                 .flags          = ADDR_TYPE_RT
1161         },
1162         { }
1163 };
1164
1165 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1166         .master         = &omap3xxx_l4_wkup_hwmod,
1167         .slave          = &omap3xxx_wd_timer2_hwmod,
1168         .clk            = "wdt2_ick",
1169         .addr           = omap3xxx_wd_timer2_addrs,
1170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1171 };
1172
1173 /*
1174  * 'wd_timer' class
1175  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1176  * overflow condition
1177  */
1178
1179 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1180         .rev_offs       = 0x0000,
1181         .sysc_offs      = 0x0010,
1182         .syss_offs      = 0x0014,
1183         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1184                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1185                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1186                            SYSS_HAS_RESET_STATUS),
1187         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1188         .sysc_fields    = &omap_hwmod_sysc_type1,
1189 };
1190
1191 /* I2C common */
1192 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1193         .rev_offs       = 0x00,
1194         .sysc_offs      = 0x20,
1195         .syss_offs      = 0x10,
1196         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1197                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1198                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1199         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1200         .sysc_fields    = &omap_hwmod_sysc_type1,
1201 };
1202
1203 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1204         .name           = "wd_timer",
1205         .sysc           = &omap3xxx_wd_timer_sysc,
1206         .pre_shutdown   = &omap2_wd_timer_disable
1207 };
1208
1209 /* wd_timer2 */
1210 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1211         &omap3xxx_l4_wkup__wd_timer2,
1212 };
1213
1214 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1215         .name           = "wd_timer2",
1216         .class          = &omap3xxx_wd_timer_hwmod_class,
1217         .main_clk       = "wdt2_fck",
1218         .prcm           = {
1219                 .omap2 = {
1220                         .prcm_reg_id = 1,
1221                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1222                         .module_offs = WKUP_MOD,
1223                         .idlest_reg_id = 1,
1224                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1225                 },
1226         },
1227         .slaves         = omap3xxx_wd_timer2_slaves,
1228         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1229         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1230         /*
1231          * XXX: Use software supervised mode, HW supervised smartidle seems to
1232          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1233          */
1234         .flags          = HWMOD_SWSUP_SIDLE,
1235 };
1236
1237 /* UART common */
1238
1239 static struct omap_hwmod_class_sysconfig uart_sysc = {
1240         .rev_offs       = 0x50,
1241         .sysc_offs      = 0x54,
1242         .syss_offs      = 0x58,
1243         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
1244                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1245                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1246         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1247         .sysc_fields    = &omap_hwmod_sysc_type1,
1248 };
1249
1250 static struct omap_hwmod_class uart_class = {
1251         .name = "uart",
1252         .sysc = &uart_sysc,
1253 };
1254
1255 /* UART1 */
1256
1257 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1258         { .irq = INT_24XX_UART1_IRQ, },
1259 };
1260
1261 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1262         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1263         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1264 };
1265
1266 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1267         &omap3_l4_core__uart1,
1268 };
1269
1270 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1271         .name           = "uart1",
1272         .mpu_irqs       = uart1_mpu_irqs,
1273         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
1274         .sdma_reqs      = uart1_sdma_reqs,
1275         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
1276         .main_clk       = "uart1_fck",
1277         .prcm           = {
1278                 .omap2 = {
1279                         .module_offs = CORE_MOD,
1280                         .prcm_reg_id = 1,
1281                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1282                         .idlest_reg_id = 1,
1283                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1284                 },
1285         },
1286         .slaves         = omap3xxx_uart1_slaves,
1287         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1288         .class          = &uart_class,
1289         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1290 };
1291
1292 /* UART2 */
1293
1294 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1295         { .irq = INT_24XX_UART2_IRQ, },
1296 };
1297
1298 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1299         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1300         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1301 };
1302
1303 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1304         &omap3_l4_core__uart2,
1305 };
1306
1307 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1308         .name           = "uart2",
1309         .mpu_irqs       = uart2_mpu_irqs,
1310         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
1311         .sdma_reqs      = uart2_sdma_reqs,
1312         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
1313         .main_clk       = "uart2_fck",
1314         .prcm           = {
1315                 .omap2 = {
1316                         .module_offs = CORE_MOD,
1317                         .prcm_reg_id = 1,
1318                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1319                         .idlest_reg_id = 1,
1320                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1321                 },
1322         },
1323         .slaves         = omap3xxx_uart2_slaves,
1324         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1325         .class          = &uart_class,
1326         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1327 };
1328
1329 /* UART3 */
1330
1331 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1332         { .irq = INT_24XX_UART3_IRQ, },
1333 };
1334
1335 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1336         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1337         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1338 };
1339
1340 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1341         &omap3_l4_per__uart3,
1342 };
1343
1344 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1345         .name           = "uart3",
1346         .mpu_irqs       = uart3_mpu_irqs,
1347         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
1348         .sdma_reqs      = uart3_sdma_reqs,
1349         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
1350         .main_clk       = "uart3_fck",
1351         .prcm           = {
1352                 .omap2 = {
1353                         .module_offs = OMAP3430_PER_MOD,
1354                         .prcm_reg_id = 1,
1355                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1356                         .idlest_reg_id = 1,
1357                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1358                 },
1359         },
1360         .slaves         = omap3xxx_uart3_slaves,
1361         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1362         .class          = &uart_class,
1363         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1364 };
1365
1366 /* UART4 */
1367
1368 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1369         { .irq = INT_36XX_UART4_IRQ, },
1370 };
1371
1372 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1373         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1374         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1375 };
1376
1377 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1378         &omap3_l4_per__uart4,
1379 };
1380
1381 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1382         .name           = "uart4",
1383         .mpu_irqs       = uart4_mpu_irqs,
1384         .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
1385         .sdma_reqs      = uart4_sdma_reqs,
1386         .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
1387         .main_clk       = "uart4_fck",
1388         .prcm           = {
1389                 .omap2 = {
1390                         .module_offs = OMAP3430_PER_MOD,
1391                         .prcm_reg_id = 1,
1392                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1393                         .idlest_reg_id = 1,
1394                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1395                 },
1396         },
1397         .slaves         = omap3xxx_uart4_slaves,
1398         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1399         .class          = &uart_class,
1400         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1401 };
1402
1403 static struct omap_hwmod_class i2c_class = {
1404         .name = "i2c",
1405         .sysc = &i2c_sysc,
1406 };
1407
1408 /*
1409  * 'dss' class
1410  * display sub-system
1411  */
1412
1413 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1414         .rev_offs       = 0x0000,
1415         .sysc_offs      = 0x0010,
1416         .syss_offs      = 0x0014,
1417         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1418         .sysc_fields    = &omap_hwmod_sysc_type1,
1419 };
1420
1421 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1422         .name = "dss",
1423         .sysc = &omap3xxx_dss_sysc,
1424 };
1425
1426 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1427         { .name = "dispc", .dma_req = 5 },
1428         { .name = "dsi1", .dma_req = 74 },
1429 };
1430
1431 /* dss */
1432 /* dss master ports */
1433 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1434         &omap3xxx_dss__l3,
1435 };
1436
1437 /* l4_core -> dss */
1438 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1439         .master         = &omap3xxx_l4_core_hwmod,
1440         .slave          = &omap3430es1_dss_core_hwmod,
1441         .clk            = "dss_ick",
1442         .addr           = omap2_dss_addrs,
1443         .fw = {
1444                 .omap2 = {
1445                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1446                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1447                         .flags  = OMAP_FIREWALL_L4,
1448                 }
1449         },
1450         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1451 };
1452
1453 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1454         .master         = &omap3xxx_l4_core_hwmod,
1455         .slave          = &omap3xxx_dss_core_hwmod,
1456         .clk            = "dss_ick",
1457         .addr           = omap2_dss_addrs,
1458         .fw = {
1459                 .omap2 = {
1460                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1461                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1462                         .flags  = OMAP_FIREWALL_L4,
1463                 }
1464         },
1465         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1466 };
1467
1468 /* dss slave ports */
1469 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1470         &omap3430es1_l4_core__dss,
1471 };
1472
1473 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1474         &omap3xxx_l4_core__dss,
1475 };
1476
1477 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1478         { .role = "tv_clk", .clk = "dss_tv_fck" },
1479         { .role = "video_clk", .clk = "dss_96m_fck" },
1480         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1481 };
1482
1483 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1484         .name           = "dss_core",
1485         .class          = &omap3xxx_dss_hwmod_class,
1486         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1487         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1488         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1489
1490         .prcm           = {
1491                 .omap2 = {
1492                         .prcm_reg_id = 1,
1493                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1494                         .module_offs = OMAP3430_DSS_MOD,
1495                         .idlest_reg_id = 1,
1496                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1497                 },
1498         },
1499         .opt_clks       = dss_opt_clks,
1500         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1501         .slaves         = omap3430es1_dss_slaves,
1502         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1503         .masters        = omap3xxx_dss_masters,
1504         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1505         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1506         .flags          = HWMOD_NO_IDLEST,
1507 };
1508
1509 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1510         .name           = "dss_core",
1511         .class          = &omap3xxx_dss_hwmod_class,
1512         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1513         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1514         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1515
1516         .prcm           = {
1517                 .omap2 = {
1518                         .prcm_reg_id = 1,
1519                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1520                         .module_offs = OMAP3430_DSS_MOD,
1521                         .idlest_reg_id = 1,
1522                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1523                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1524                 },
1525         },
1526         .opt_clks       = dss_opt_clks,
1527         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1528         .slaves         = omap3xxx_dss_slaves,
1529         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1530         .masters        = omap3xxx_dss_masters,
1531         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1532         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1533                                 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1534 };
1535
1536 /*
1537  * 'dispc' class
1538  * display controller
1539  */
1540
1541 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1542         .rev_offs       = 0x0000,
1543         .sysc_offs      = 0x0010,
1544         .syss_offs      = 0x0014,
1545         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1546                            SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1547                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1548         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1549                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1550         .sysc_fields    = &omap_hwmod_sysc_type1,
1551 };
1552
1553 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1554         .name = "dispc",
1555         .sysc = &omap3xxx_dispc_sysc,
1556 };
1557
1558 static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
1559         { .irq = 25 },
1560 };
1561
1562 /* l4_core -> dss_dispc */
1563 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1564         .master         = &omap3xxx_l4_core_hwmod,
1565         .slave          = &omap3xxx_dss_dispc_hwmod,
1566         .clk            = "dss_ick",
1567         .addr           = omap2_dss_dispc_addrs,
1568         .fw = {
1569                 .omap2 = {
1570                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1571                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1572                         .flags  = OMAP_FIREWALL_L4,
1573                 }
1574         },
1575         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1576 };
1577
1578 /* dss_dispc slave ports */
1579 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1580         &omap3xxx_l4_core__dss_dispc,
1581 };
1582
1583 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1584         .name           = "dss_dispc",
1585         .class          = &omap3xxx_dispc_hwmod_class,
1586         .mpu_irqs       = omap3xxx_dispc_irqs,
1587         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dispc_irqs),
1588         .main_clk       = "dss1_alwon_fck",
1589         .prcm           = {
1590                 .omap2 = {
1591                         .prcm_reg_id = 1,
1592                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1593                         .module_offs = OMAP3430_DSS_MOD,
1594                 },
1595         },
1596         .slaves         = omap3xxx_dss_dispc_slaves,
1597         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1598         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1599                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1600                                 CHIP_GE_OMAP3630ES1_1),
1601         .flags          = HWMOD_NO_IDLEST,
1602 };
1603
1604 /*
1605  * 'dsi' class
1606  * display serial interface controller
1607  */
1608
1609 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1610         .name = "dsi",
1611 };
1612
1613 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1614         { .irq = 25 },
1615 };
1616
1617 /* dss_dsi1 */
1618 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1619         {
1620                 .pa_start       = 0x4804FC00,
1621                 .pa_end         = 0x4804FFFF,
1622                 .flags          = ADDR_TYPE_RT
1623         },
1624         { }
1625 };
1626
1627 /* l4_core -> dss_dsi1 */
1628 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1629         .master         = &omap3xxx_l4_core_hwmod,
1630         .slave          = &omap3xxx_dss_dsi1_hwmod,
1631         .addr           = omap3xxx_dss_dsi1_addrs,
1632         .fw = {
1633                 .omap2 = {
1634                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1635                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1636                         .flags  = OMAP_FIREWALL_L4,
1637                 }
1638         },
1639         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1640 };
1641
1642 /* dss_dsi1 slave ports */
1643 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1644         &omap3xxx_l4_core__dss_dsi1,
1645 };
1646
1647 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1648         .name           = "dss_dsi1",
1649         .class          = &omap3xxx_dsi_hwmod_class,
1650         .mpu_irqs       = omap3xxx_dsi1_irqs,
1651         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dsi1_irqs),
1652         .main_clk       = "dss1_alwon_fck",
1653         .prcm           = {
1654                 .omap2 = {
1655                         .prcm_reg_id = 1,
1656                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1657                         .module_offs = OMAP3430_DSS_MOD,
1658                 },
1659         },
1660         .slaves         = omap3xxx_dss_dsi1_slaves,
1661         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1662         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1663                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1664                                 CHIP_GE_OMAP3630ES1_1),
1665         .flags          = HWMOD_NO_IDLEST,
1666 };
1667
1668 /*
1669  * 'rfbi' class
1670  * remote frame buffer interface
1671  */
1672
1673 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1674         .rev_offs       = 0x0000,
1675         .sysc_offs      = 0x0010,
1676         .syss_offs      = 0x0014,
1677         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1678                            SYSC_HAS_AUTOIDLE),
1679         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1680         .sysc_fields    = &omap_hwmod_sysc_type1,
1681 };
1682
1683 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1684         .name = "rfbi",
1685         .sysc = &omap3xxx_rfbi_sysc,
1686 };
1687
1688 /* l4_core -> dss_rfbi */
1689 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1690         .master         = &omap3xxx_l4_core_hwmod,
1691         .slave          = &omap3xxx_dss_rfbi_hwmod,
1692         .clk            = "dss_ick",
1693         .addr           = omap2_dss_rfbi_addrs,
1694         .fw = {
1695                 .omap2 = {
1696                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1697                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1698                         .flags  = OMAP_FIREWALL_L4,
1699                 }
1700         },
1701         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1702 };
1703
1704 /* dss_rfbi slave ports */
1705 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1706         &omap3xxx_l4_core__dss_rfbi,
1707 };
1708
1709 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1710         .name           = "dss_rfbi",
1711         .class          = &omap3xxx_rfbi_hwmod_class,
1712         .main_clk       = "dss1_alwon_fck",
1713         .prcm           = {
1714                 .omap2 = {
1715                         .prcm_reg_id = 1,
1716                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1717                         .module_offs = OMAP3430_DSS_MOD,
1718                 },
1719         },
1720         .slaves         = omap3xxx_dss_rfbi_slaves,
1721         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1722         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1723                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1724                                 CHIP_GE_OMAP3630ES1_1),
1725         .flags          = HWMOD_NO_IDLEST,
1726 };
1727
1728 /*
1729  * 'venc' class
1730  * video encoder
1731  */
1732
1733 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1734         .name = "venc",
1735 };
1736
1737 /* l4_core -> dss_venc */
1738 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1739         .master         = &omap3xxx_l4_core_hwmod,
1740         .slave          = &omap3xxx_dss_venc_hwmod,
1741         .clk            = "dss_tv_fck",
1742         .addr           = omap2_dss_venc_addrs,
1743         .fw = {
1744                 .omap2 = {
1745                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1746                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1747                         .flags  = OMAP_FIREWALL_L4,
1748                 }
1749         },
1750         .flags          = OCPIF_SWSUP_IDLE,
1751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1752 };
1753
1754 /* dss_venc slave ports */
1755 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1756         &omap3xxx_l4_core__dss_venc,
1757 };
1758
1759 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1760         .name           = "dss_venc",
1761         .class          = &omap3xxx_venc_hwmod_class,
1762         .main_clk       = "dss1_alwon_fck",
1763         .prcm           = {
1764                 .omap2 = {
1765                         .prcm_reg_id = 1,
1766                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1767                         .module_offs = OMAP3430_DSS_MOD,
1768                 },
1769         },
1770         .slaves         = omap3xxx_dss_venc_slaves,
1771         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1772         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1773                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1774                                 CHIP_GE_OMAP3630ES1_1),
1775         .flags          = HWMOD_NO_IDLEST,
1776 };
1777
1778 /* I2C1 */
1779
1780 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1781         .fifo_depth     = 8, /* bytes */
1782 };
1783
1784 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1785         { .irq = INT_24XX_I2C1_IRQ, },
1786 };
1787
1788 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1789         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1790         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1791 };
1792
1793 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1794         &omap3_l4_core__i2c1,
1795 };
1796
1797 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1798         .name           = "i2c1",
1799         .mpu_irqs       = i2c1_mpu_irqs,
1800         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
1801         .sdma_reqs      = i2c1_sdma_reqs,
1802         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
1803         .main_clk       = "i2c1_fck",
1804         .prcm           = {
1805                 .omap2 = {
1806                         .module_offs = CORE_MOD,
1807                         .prcm_reg_id = 1,
1808                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1809                         .idlest_reg_id = 1,
1810                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1811                 },
1812         },
1813         .slaves         = omap3xxx_i2c1_slaves,
1814         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1815         .class          = &i2c_class,
1816         .dev_attr       = &i2c1_dev_attr,
1817         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1818 };
1819
1820 /* I2C2 */
1821
1822 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1823         .fifo_depth     = 8, /* bytes */
1824 };
1825
1826 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1827         { .irq = INT_24XX_I2C2_IRQ, },
1828 };
1829
1830 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1831         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1832         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1833 };
1834
1835 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1836         &omap3_l4_core__i2c2,
1837 };
1838
1839 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1840         .name           = "i2c2",
1841         .mpu_irqs       = i2c2_mpu_irqs,
1842         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
1843         .sdma_reqs      = i2c2_sdma_reqs,
1844         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
1845         .main_clk       = "i2c2_fck",
1846         .prcm           = {
1847                 .omap2 = {
1848                         .module_offs = CORE_MOD,
1849                         .prcm_reg_id = 1,
1850                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1851                         .idlest_reg_id = 1,
1852                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1853                 },
1854         },
1855         .slaves         = omap3xxx_i2c2_slaves,
1856         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1857         .class          = &i2c_class,
1858         .dev_attr       = &i2c2_dev_attr,
1859         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1860 };
1861
1862 /* I2C3 */
1863
1864 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1865         .fifo_depth     = 64, /* bytes */
1866 };
1867
1868 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1869         { .irq = INT_34XX_I2C3_IRQ, },
1870 };
1871
1872 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1873         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1874         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1875 };
1876
1877 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1878         &omap3_l4_core__i2c3,
1879 };
1880
1881 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1882         .name           = "i2c3",
1883         .mpu_irqs       = i2c3_mpu_irqs,
1884         .mpu_irqs_cnt   = ARRAY_SIZE(i2c3_mpu_irqs),
1885         .sdma_reqs      = i2c3_sdma_reqs,
1886         .sdma_reqs_cnt  = ARRAY_SIZE(i2c3_sdma_reqs),
1887         .main_clk       = "i2c3_fck",
1888         .prcm           = {
1889                 .omap2 = {
1890                         .module_offs = CORE_MOD,
1891                         .prcm_reg_id = 1,
1892                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1893                         .idlest_reg_id = 1,
1894                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1895                 },
1896         },
1897         .slaves         = omap3xxx_i2c3_slaves,
1898         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1899         .class          = &i2c_class,
1900         .dev_attr       = &i2c3_dev_attr,
1901         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1902 };
1903
1904 /* l4_wkup -> gpio1 */
1905 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1906         {
1907                 .pa_start       = 0x48310000,
1908                 .pa_end         = 0x483101ff,
1909                 .flags          = ADDR_TYPE_RT
1910         },
1911         { }
1912 };
1913
1914 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1915         .master         = &omap3xxx_l4_wkup_hwmod,
1916         .slave          = &omap3xxx_gpio1_hwmod,
1917         .addr           = omap3xxx_gpio1_addrs,
1918         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1919 };
1920
1921 /* l4_per -> gpio2 */
1922 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1923         {
1924                 .pa_start       = 0x49050000,
1925                 .pa_end         = 0x490501ff,
1926                 .flags          = ADDR_TYPE_RT
1927         },
1928         { }
1929 };
1930
1931 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1932         .master         = &omap3xxx_l4_per_hwmod,
1933         .slave          = &omap3xxx_gpio2_hwmod,
1934         .addr           = omap3xxx_gpio2_addrs,
1935         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1936 };
1937
1938 /* l4_per -> gpio3 */
1939 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1940         {
1941                 .pa_start       = 0x49052000,
1942                 .pa_end         = 0x490521ff,
1943                 .flags          = ADDR_TYPE_RT
1944         },
1945         { }
1946 };
1947
1948 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1949         .master         = &omap3xxx_l4_per_hwmod,
1950         .slave          = &omap3xxx_gpio3_hwmod,
1951         .addr           = omap3xxx_gpio3_addrs,
1952         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1953 };
1954
1955 /* l4_per -> gpio4 */
1956 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1957         {
1958                 .pa_start       = 0x49054000,
1959                 .pa_end         = 0x490541ff,
1960                 .flags          = ADDR_TYPE_RT
1961         },
1962         { }
1963 };
1964
1965 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1966         .master         = &omap3xxx_l4_per_hwmod,
1967         .slave          = &omap3xxx_gpio4_hwmod,
1968         .addr           = omap3xxx_gpio4_addrs,
1969         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1970 };
1971
1972 /* l4_per -> gpio5 */
1973 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1974         {
1975                 .pa_start       = 0x49056000,
1976                 .pa_end         = 0x490561ff,
1977                 .flags          = ADDR_TYPE_RT
1978         },
1979         { }
1980 };
1981
1982 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1983         .master         = &omap3xxx_l4_per_hwmod,
1984         .slave          = &omap3xxx_gpio5_hwmod,
1985         .addr           = omap3xxx_gpio5_addrs,
1986         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1987 };
1988
1989 /* l4_per -> gpio6 */
1990 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1991         {
1992                 .pa_start       = 0x49058000,
1993                 .pa_end         = 0x490581ff,
1994                 .flags          = ADDR_TYPE_RT
1995         },
1996         { }
1997 };
1998
1999 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2000         .master         = &omap3xxx_l4_per_hwmod,
2001         .slave          = &omap3xxx_gpio6_hwmod,
2002         .addr           = omap3xxx_gpio6_addrs,
2003         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2004 };
2005
2006 /*
2007  * 'gpio' class
2008  * general purpose io module
2009  */
2010
2011 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
2012         .rev_offs       = 0x0000,
2013         .sysc_offs      = 0x0010,
2014         .syss_offs      = 0x0014,
2015         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2016                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
2017                            SYSS_HAS_RESET_STATUS),
2018         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2019         .sysc_fields    = &omap_hwmod_sysc_type1,
2020 };
2021
2022 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
2023         .name = "gpio",
2024         .sysc = &omap3xxx_gpio_sysc,
2025         .rev = 1,
2026 };
2027
2028 /* gpio_dev_attr*/
2029 static struct omap_gpio_dev_attr gpio_dev_attr = {
2030         .bank_width = 32,
2031         .dbck_flag = true,
2032 };
2033
2034 /* gpio1 */
2035 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
2036         { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
2037 };
2038
2039 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
2040         { .role = "dbclk", .clk = "gpio1_dbck", },
2041 };
2042
2043 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
2044         &omap3xxx_l4_wkup__gpio1,
2045 };
2046
2047 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2048         .name           = "gpio1",
2049         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2050         .mpu_irqs       = omap3xxx_gpio1_irqs,
2051         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio1_irqs),
2052         .main_clk       = "gpio1_ick",
2053         .opt_clks       = gpio1_opt_clks,
2054         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
2055         .prcm           = {
2056                 .omap2 = {
2057                         .prcm_reg_id = 1,
2058                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
2059                         .module_offs = WKUP_MOD,
2060                         .idlest_reg_id = 1,
2061                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
2062                 },
2063         },
2064         .slaves         = omap3xxx_gpio1_slaves,
2065         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
2066         .class          = &omap3xxx_gpio_hwmod_class,
2067         .dev_attr       = &gpio_dev_attr,
2068         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2069 };
2070
2071 /* gpio2 */
2072 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
2073         { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
2074 };
2075
2076 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
2077         { .role = "dbclk", .clk = "gpio2_dbck", },
2078 };
2079
2080 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
2081         &omap3xxx_l4_per__gpio2,
2082 };
2083
2084 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2085         .name           = "gpio2",
2086         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2087         .mpu_irqs       = omap3xxx_gpio2_irqs,
2088         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio2_irqs),
2089         .main_clk       = "gpio2_ick",
2090         .opt_clks       = gpio2_opt_clks,
2091         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
2092         .prcm           = {
2093                 .omap2 = {
2094                         .prcm_reg_id = 1,
2095                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
2096                         .module_offs = OMAP3430_PER_MOD,
2097                         .idlest_reg_id = 1,
2098                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2099                 },
2100         },
2101         .slaves         = omap3xxx_gpio2_slaves,
2102         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2103         .class          = &omap3xxx_gpio_hwmod_class,
2104         .dev_attr       = &gpio_dev_attr,
2105         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2106 };
2107
2108 /* gpio3 */
2109 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
2110         { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
2111 };
2112
2113 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2114         { .role = "dbclk", .clk = "gpio3_dbck", },
2115 };
2116
2117 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2118         &omap3xxx_l4_per__gpio3,
2119 };
2120
2121 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2122         .name           = "gpio3",
2123         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2124         .mpu_irqs       = omap3xxx_gpio3_irqs,
2125         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio3_irqs),
2126         .main_clk       = "gpio3_ick",
2127         .opt_clks       = gpio3_opt_clks,
2128         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
2129         .prcm           = {
2130                 .omap2 = {
2131                         .prcm_reg_id = 1,
2132                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2133                         .module_offs = OMAP3430_PER_MOD,
2134                         .idlest_reg_id = 1,
2135                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2136                 },
2137         },
2138         .slaves         = omap3xxx_gpio3_slaves,
2139         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2140         .class          = &omap3xxx_gpio_hwmod_class,
2141         .dev_attr       = &gpio_dev_attr,
2142         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2143 };
2144
2145 /* gpio4 */
2146 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
2147         { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
2148 };
2149
2150 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2151         { .role = "dbclk", .clk = "gpio4_dbck", },
2152 };
2153
2154 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2155         &omap3xxx_l4_per__gpio4,
2156 };
2157
2158 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2159         .name           = "gpio4",
2160         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2161         .mpu_irqs       = omap3xxx_gpio4_irqs,
2162         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio4_irqs),
2163         .main_clk       = "gpio4_ick",
2164         .opt_clks       = gpio4_opt_clks,
2165         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2166         .prcm           = {
2167                 .omap2 = {
2168                         .prcm_reg_id = 1,
2169                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2170                         .module_offs = OMAP3430_PER_MOD,
2171                         .idlest_reg_id = 1,
2172                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2173                 },
2174         },
2175         .slaves         = omap3xxx_gpio4_slaves,
2176         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2177         .class          = &omap3xxx_gpio_hwmod_class,
2178         .dev_attr       = &gpio_dev_attr,
2179         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2180 };
2181
2182 /* gpio5 */
2183 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2184         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2185 };
2186
2187 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2188         { .role = "dbclk", .clk = "gpio5_dbck", },
2189 };
2190
2191 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2192         &omap3xxx_l4_per__gpio5,
2193 };
2194
2195 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2196         .name           = "gpio5",
2197         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2198         .mpu_irqs       = omap3xxx_gpio5_irqs,
2199         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio5_irqs),
2200         .main_clk       = "gpio5_ick",
2201         .opt_clks       = gpio5_opt_clks,
2202         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2203         .prcm           = {
2204                 .omap2 = {
2205                         .prcm_reg_id = 1,
2206                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2207                         .module_offs = OMAP3430_PER_MOD,
2208                         .idlest_reg_id = 1,
2209                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2210                 },
2211         },
2212         .slaves         = omap3xxx_gpio5_slaves,
2213         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2214         .class          = &omap3xxx_gpio_hwmod_class,
2215         .dev_attr       = &gpio_dev_attr,
2216         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2217 };
2218
2219 /* gpio6 */
2220 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2221         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2222 };
2223
2224 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2225         { .role = "dbclk", .clk = "gpio6_dbck", },
2226 };
2227
2228 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2229         &omap3xxx_l4_per__gpio6,
2230 };
2231
2232 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2233         .name           = "gpio6",
2234         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2235         .mpu_irqs       = omap3xxx_gpio6_irqs,
2236         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio6_irqs),
2237         .main_clk       = "gpio6_ick",
2238         .opt_clks       = gpio6_opt_clks,
2239         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2240         .prcm           = {
2241                 .omap2 = {
2242                         .prcm_reg_id = 1,
2243                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2244                         .module_offs = OMAP3430_PER_MOD,
2245                         .idlest_reg_id = 1,
2246                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2247                 },
2248         },
2249         .slaves         = omap3xxx_gpio6_slaves,
2250         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2251         .class          = &omap3xxx_gpio_hwmod_class,
2252         .dev_attr       = &gpio_dev_attr,
2253         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2254 };
2255
2256 /* dma_system -> L3 */
2257 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2258         .master         = &omap3xxx_dma_system_hwmod,
2259         .slave          = &omap3xxx_l3_main_hwmod,
2260         .clk            = "core_l3_ick",
2261         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2262 };
2263
2264 /* dma attributes */
2265 static struct omap_dma_dev_attr dma_dev_attr = {
2266         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2267                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2268         .lch_count = 32,
2269 };
2270
2271 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2272         .rev_offs       = 0x0000,
2273         .sysc_offs      = 0x002c,
2274         .syss_offs      = 0x0028,
2275         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2276                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2277                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2278                            SYSS_HAS_RESET_STATUS),
2279         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2280                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2281         .sysc_fields    = &omap_hwmod_sysc_type1,
2282 };
2283
2284 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2285         .name = "dma",
2286         .sysc = &omap3xxx_dma_sysc,
2287 };
2288
2289 /* dma_system */
2290 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
2291         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
2292         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
2293         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
2294         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
2295 };
2296
2297 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2298         {
2299                 .pa_start       = 0x48056000,
2300                 .pa_end         = 0x48056fff,
2301                 .flags          = ADDR_TYPE_RT
2302         },
2303         { }
2304 };
2305
2306 /* dma_system master ports */
2307 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2308         &omap3xxx_dma_system__l3,
2309 };
2310
2311 /* l4_cfg -> dma_system */
2312 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2313         .master         = &omap3xxx_l4_core_hwmod,
2314         .slave          = &omap3xxx_dma_system_hwmod,
2315         .clk            = "core_l4_ick",
2316         .addr           = omap3xxx_dma_system_addrs,
2317         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2318 };
2319
2320 /* dma_system slave ports */
2321 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2322         &omap3xxx_l4_core__dma_system,
2323 };
2324
2325 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2326         .name           = "dma",
2327         .class          = &omap3xxx_dma_hwmod_class,
2328         .mpu_irqs       = omap3xxx_dma_system_irqs,
2329         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dma_system_irqs),
2330         .main_clk       = "core_l3_ick",
2331         .prcm = {
2332                 .omap2 = {
2333                         .module_offs            = CORE_MOD,
2334                         .prcm_reg_id            = 1,
2335                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2336                         .idlest_reg_id          = 1,
2337                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2338                 },
2339         },
2340         .slaves         = omap3xxx_dma_system_slaves,
2341         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2342         .masters        = omap3xxx_dma_system_masters,
2343         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2344         .dev_attr       = &dma_dev_attr,
2345         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2346         .flags          = HWMOD_NO_IDLEST,
2347 };
2348
2349 /*
2350  * 'mcbsp' class
2351  * multi channel buffered serial port controller
2352  */
2353
2354 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2355         .sysc_offs      = 0x008c,
2356         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2357                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2358         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2359         .sysc_fields    = &omap_hwmod_sysc_type1,
2360         .clockact       = 0x2,
2361 };
2362
2363 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2364         .name = "mcbsp",
2365         .sysc = &omap3xxx_mcbsp_sysc,
2366         .rev  = MCBSP_CONFIG_TYPE3,
2367 };
2368
2369 /* mcbsp1 */
2370 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2371         { .name = "irq", .irq = 16 },
2372         { .name = "tx", .irq = 59 },
2373         { .name = "rx", .irq = 60 },
2374 };
2375
2376 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2377         { .name = "rx", .dma_req = 32 },
2378         { .name = "tx", .dma_req = 31 },
2379 };
2380
2381 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2382         {
2383                 .name           = "mpu",
2384                 .pa_start       = 0x48074000,
2385                 .pa_end         = 0x480740ff,
2386                 .flags          = ADDR_TYPE_RT
2387         },
2388         { }
2389 };
2390
2391 /* l4_core -> mcbsp1 */
2392 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2393         .master         = &omap3xxx_l4_core_hwmod,
2394         .slave          = &omap3xxx_mcbsp1_hwmod,
2395         .clk            = "mcbsp1_ick",
2396         .addr           = omap3xxx_mcbsp1_addrs,
2397         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2398 };
2399
2400 /* mcbsp1 slave ports */
2401 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2402         &omap3xxx_l4_core__mcbsp1,
2403 };
2404
2405 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2406         .name           = "mcbsp1",
2407         .class          = &omap3xxx_mcbsp_hwmod_class,
2408         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2409         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
2410         .sdma_reqs      = omap3xxx_mcbsp1_sdma_chs,
2411         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2412         .main_clk       = "mcbsp1_fck",
2413         .prcm           = {
2414                 .omap2 = {
2415                         .prcm_reg_id = 1,
2416                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2417                         .module_offs = CORE_MOD,
2418                         .idlest_reg_id = 1,
2419                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2420                 },
2421         },
2422         .slaves         = omap3xxx_mcbsp1_slaves,
2423         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2424         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2425 };
2426
2427 /* mcbsp2 */
2428 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2429         { .name = "irq", .irq = 17 },
2430         { .name = "tx", .irq = 62 },
2431         { .name = "rx", .irq = 63 },
2432 };
2433
2434 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2435         { .name = "rx", .dma_req = 34 },
2436         { .name = "tx", .dma_req = 33 },
2437 };
2438
2439 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2440         {
2441                 .name           = "mpu",
2442                 .pa_start       = 0x49022000,
2443                 .pa_end         = 0x490220ff,
2444                 .flags          = ADDR_TYPE_RT
2445         },
2446         { }
2447 };
2448
2449 /* l4_per -> mcbsp2 */
2450 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2451         .master         = &omap3xxx_l4_per_hwmod,
2452         .slave          = &omap3xxx_mcbsp2_hwmod,
2453         .clk            = "mcbsp2_ick",
2454         .addr           = omap3xxx_mcbsp2_addrs,
2455
2456         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2457 };
2458
2459 /* mcbsp2 slave ports */
2460 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2461         &omap3xxx_l4_per__mcbsp2,
2462 };
2463
2464 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2465         .sidetone       = "mcbsp2_sidetone",
2466 };
2467
2468 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2469         .name           = "mcbsp2",
2470         .class          = &omap3xxx_mcbsp_hwmod_class,
2471         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2472         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
2473         .sdma_reqs      = omap3xxx_mcbsp2_sdma_chs,
2474         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2475         .main_clk       = "mcbsp2_fck",
2476         .prcm           = {
2477                 .omap2 = {
2478                         .prcm_reg_id = 1,
2479                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2480                         .module_offs = OMAP3430_PER_MOD,
2481                         .idlest_reg_id = 1,
2482                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2483                 },
2484         },
2485         .slaves         = omap3xxx_mcbsp2_slaves,
2486         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2487         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2488         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2489 };
2490
2491 /* mcbsp3 */
2492 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2493         { .name = "irq", .irq = 22 },
2494         { .name = "tx", .irq = 89 },
2495         { .name = "rx", .irq = 90 },
2496 };
2497
2498 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2499         { .name = "rx", .dma_req = 18 },
2500         { .name = "tx", .dma_req = 17 },
2501 };
2502
2503 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2504         {
2505                 .name           = "mpu",
2506                 .pa_start       = 0x49024000,
2507                 .pa_end         = 0x490240ff,
2508                 .flags          = ADDR_TYPE_RT
2509         },
2510         { }
2511 };
2512
2513 /* l4_per -> mcbsp3 */
2514 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2515         .master         = &omap3xxx_l4_per_hwmod,
2516         .slave          = &omap3xxx_mcbsp3_hwmod,
2517         .clk            = "mcbsp3_ick",
2518         .addr           = omap3xxx_mcbsp3_addrs,
2519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2520 };
2521
2522 /* mcbsp3 slave ports */
2523 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2524         &omap3xxx_l4_per__mcbsp3,
2525 };
2526
2527 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2528         .sidetone       = "mcbsp3_sidetone",
2529 };
2530
2531 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2532         .name           = "mcbsp3",
2533         .class          = &omap3xxx_mcbsp_hwmod_class,
2534         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2535         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
2536         .sdma_reqs      = omap3xxx_mcbsp3_sdma_chs,
2537         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2538         .main_clk       = "mcbsp3_fck",
2539         .prcm           = {
2540                 .omap2 = {
2541                         .prcm_reg_id = 1,
2542                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2543                         .module_offs = OMAP3430_PER_MOD,
2544                         .idlest_reg_id = 1,
2545                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2546                 },
2547         },
2548         .slaves         = omap3xxx_mcbsp3_slaves,
2549         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2550         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2551         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2552 };
2553
2554 /* mcbsp4 */
2555 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2556         { .name = "irq", .irq = 23 },
2557         { .name = "tx", .irq = 54 },
2558         { .name = "rx", .irq = 55 },
2559 };
2560
2561 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2562         { .name = "rx", .dma_req = 20 },
2563         { .name = "tx", .dma_req = 19 },
2564 };
2565
2566 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2567         {
2568                 .name           = "mpu",
2569                 .pa_start       = 0x49026000,
2570                 .pa_end         = 0x490260ff,
2571                 .flags          = ADDR_TYPE_RT
2572         },
2573         { }
2574 };
2575
2576 /* l4_per -> mcbsp4 */
2577 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2578         .master         = &omap3xxx_l4_per_hwmod,
2579         .slave          = &omap3xxx_mcbsp4_hwmod,
2580         .clk            = "mcbsp4_ick",
2581         .addr           = omap3xxx_mcbsp4_addrs,
2582         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2583 };
2584
2585 /* mcbsp4 slave ports */
2586 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2587         &omap3xxx_l4_per__mcbsp4,
2588 };
2589
2590 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2591         .name           = "mcbsp4",
2592         .class          = &omap3xxx_mcbsp_hwmod_class,
2593         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2594         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
2595         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2596         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2597         .main_clk       = "mcbsp4_fck",
2598         .prcm           = {
2599                 .omap2 = {
2600                         .prcm_reg_id = 1,
2601                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2602                         .module_offs = OMAP3430_PER_MOD,
2603                         .idlest_reg_id = 1,
2604                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2605                 },
2606         },
2607         .slaves         = omap3xxx_mcbsp4_slaves,
2608         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2609         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2610 };
2611
2612 /* mcbsp5 */
2613 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2614         { .name = "irq", .irq = 27 },
2615         { .name = "tx", .irq = 81 },
2616         { .name = "rx", .irq = 82 },
2617 };
2618
2619 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2620         { .name = "rx", .dma_req = 22 },
2621         { .name = "tx", .dma_req = 21 },
2622 };
2623
2624 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2625         {
2626                 .name           = "mpu",
2627                 .pa_start       = 0x48096000,
2628                 .pa_end         = 0x480960ff,
2629                 .flags          = ADDR_TYPE_RT
2630         },
2631         { }
2632 };
2633
2634 /* l4_core -> mcbsp5 */
2635 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2636         .master         = &omap3xxx_l4_core_hwmod,
2637         .slave          = &omap3xxx_mcbsp5_hwmod,
2638         .clk            = "mcbsp5_ick",
2639         .addr           = omap3xxx_mcbsp5_addrs,
2640         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2641 };
2642
2643 /* mcbsp5 slave ports */
2644 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2645         &omap3xxx_l4_core__mcbsp5,
2646 };
2647
2648 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2649         .name           = "mcbsp5",
2650         .class          = &omap3xxx_mcbsp_hwmod_class,
2651         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2652         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
2653         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2654         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2655         .main_clk       = "mcbsp5_fck",
2656         .prcm           = {
2657                 .omap2 = {
2658                         .prcm_reg_id = 1,
2659                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2660                         .module_offs = CORE_MOD,
2661                         .idlest_reg_id = 1,
2662                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2663                 },
2664         },
2665         .slaves         = omap3xxx_mcbsp5_slaves,
2666         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2667         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2668 };
2669 /* 'mcbsp sidetone' class */
2670
2671 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2672         .sysc_offs      = 0x0010,
2673         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2674         .sysc_fields    = &omap_hwmod_sysc_type1,
2675 };
2676
2677 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2678         .name = "mcbsp_sidetone",
2679         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2680 };
2681
2682 /* mcbsp2_sidetone */
2683 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2684         { .name = "irq", .irq = 4 },
2685 };
2686
2687 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2688         {
2689                 .name           = "sidetone",
2690                 .pa_start       = 0x49028000,
2691                 .pa_end         = 0x490280ff,
2692                 .flags          = ADDR_TYPE_RT
2693         },
2694         { }
2695 };
2696
2697 /* l4_per -> mcbsp2_sidetone */
2698 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2699         .master         = &omap3xxx_l4_per_hwmod,
2700         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2701         .clk            = "mcbsp2_ick",
2702         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2703         .user           = OCP_USER_MPU,
2704 };
2705
2706 /* mcbsp2_sidetone slave ports */
2707 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2708         &omap3xxx_l4_per__mcbsp2_sidetone,
2709 };
2710
2711 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2712         .name           = "mcbsp2_sidetone",
2713         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2714         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2715         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
2716         .main_clk       = "mcbsp2_fck",
2717         .prcm           = {
2718                 .omap2 = {
2719                         .prcm_reg_id = 1,
2720                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2721                         .module_offs = OMAP3430_PER_MOD,
2722                         .idlest_reg_id = 1,
2723                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2724                 },
2725         },
2726         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2727         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2728         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2729 };
2730
2731 /* mcbsp3_sidetone */
2732 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2733         { .name = "irq", .irq = 5 },
2734 };
2735
2736 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2737         {
2738                 .name           = "sidetone",
2739                 .pa_start       = 0x4902A000,
2740                 .pa_end         = 0x4902A0ff,
2741                 .flags          = ADDR_TYPE_RT
2742         },
2743         { }
2744 };
2745
2746 /* l4_per -> mcbsp3_sidetone */
2747 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2748         .master         = &omap3xxx_l4_per_hwmod,
2749         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2750         .clk            = "mcbsp3_ick",
2751         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2752         .user           = OCP_USER_MPU,
2753 };
2754
2755 /* mcbsp3_sidetone slave ports */
2756 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2757         &omap3xxx_l4_per__mcbsp3_sidetone,
2758 };
2759
2760 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2761         .name           = "mcbsp3_sidetone",
2762         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2763         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2764         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
2765         .main_clk       = "mcbsp3_fck",
2766         .prcm           = {
2767                 .omap2 = {
2768                         .prcm_reg_id = 1,
2769                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2770                         .module_offs = OMAP3430_PER_MOD,
2771                         .idlest_reg_id = 1,
2772                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2773                 },
2774         },
2775         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2776         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2777         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2778 };
2779
2780
2781 /* SR common */
2782 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2783         .clkact_shift   = 20,
2784 };
2785
2786 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2787         .sysc_offs      = 0x24,
2788         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2789         .clockact       = CLOCKACT_TEST_ICLK,
2790         .sysc_fields    = &omap34xx_sr_sysc_fields,
2791 };
2792
2793 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2794         .name = "smartreflex",
2795         .sysc = &omap34xx_sr_sysc,
2796         .rev  = 1,
2797 };
2798
2799 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2800         .sidle_shift    = 24,
2801         .enwkup_shift   = 26
2802 };
2803
2804 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2805         .sysc_offs      = 0x38,
2806         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2807         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2808                         SYSC_NO_CACHE),
2809         .sysc_fields    = &omap36xx_sr_sysc_fields,
2810 };
2811
2812 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2813         .name = "smartreflex",
2814         .sysc = &omap36xx_sr_sysc,
2815         .rev  = 2,
2816 };
2817
2818 /* SR1 */
2819 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2820         &omap3_l4_core__sr1,
2821 };
2822
2823 static struct omap_hwmod omap34xx_sr1_hwmod = {
2824         .name           = "sr1_hwmod",
2825         .class          = &omap34xx_smartreflex_hwmod_class,
2826         .main_clk       = "sr1_fck",
2827         .vdd_name       = "mpu",
2828         .prcm           = {
2829                 .omap2 = {
2830                         .prcm_reg_id = 1,
2831                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2832                         .module_offs = WKUP_MOD,
2833                         .idlest_reg_id = 1,
2834                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2835                 },
2836         },
2837         .slaves         = omap3_sr1_slaves,
2838         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2839         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2840                                         CHIP_IS_OMAP3430ES3_0 |
2841                                         CHIP_IS_OMAP3430ES3_1),
2842         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2843 };
2844
2845 static struct omap_hwmod omap36xx_sr1_hwmod = {
2846         .name           = "sr1_hwmod",
2847         .class          = &omap36xx_smartreflex_hwmod_class,
2848         .main_clk       = "sr1_fck",
2849         .vdd_name       = "mpu",
2850         .prcm           = {
2851                 .omap2 = {
2852                         .prcm_reg_id = 1,
2853                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2854                         .module_offs = WKUP_MOD,
2855                         .idlest_reg_id = 1,
2856                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2857                 },
2858         },
2859         .slaves         = omap3_sr1_slaves,
2860         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2861         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2862 };
2863
2864 /* SR2 */
2865 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2866         &omap3_l4_core__sr2,
2867 };
2868
2869 static struct omap_hwmod omap34xx_sr2_hwmod = {
2870         .name           = "sr2_hwmod",
2871         .class          = &omap34xx_smartreflex_hwmod_class,
2872         .main_clk       = "sr2_fck",
2873         .vdd_name       = "core",
2874         .prcm           = {
2875                 .omap2 = {
2876                         .prcm_reg_id = 1,
2877                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2878                         .module_offs = WKUP_MOD,
2879                         .idlest_reg_id = 1,
2880                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2881                 },
2882         },
2883         .slaves         = omap3_sr2_slaves,
2884         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2885         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2886                                         CHIP_IS_OMAP3430ES3_0 |
2887                                         CHIP_IS_OMAP3430ES3_1),
2888         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2889 };
2890
2891 static struct omap_hwmod omap36xx_sr2_hwmod = {
2892         .name           = "sr2_hwmod",
2893         .class          = &omap36xx_smartreflex_hwmod_class,
2894         .main_clk       = "sr2_fck",
2895         .vdd_name       = "core",
2896         .prcm           = {
2897                 .omap2 = {
2898                         .prcm_reg_id = 1,
2899                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2900                         .module_offs = WKUP_MOD,
2901                         .idlest_reg_id = 1,
2902                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2903                 },
2904         },
2905         .slaves         = omap3_sr2_slaves,
2906         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2907         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2908 };
2909
2910 /*
2911  * 'mailbox' class
2912  * mailbox module allowing communication between the on-chip processors
2913  * using a queued mailbox-interrupt mechanism.
2914  */
2915
2916 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2917         .rev_offs       = 0x000,
2918         .sysc_offs      = 0x010,
2919         .syss_offs      = 0x014,
2920         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2921                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2922         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2923         .sysc_fields    = &omap_hwmod_sysc_type1,
2924 };
2925
2926 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2927         .name = "mailbox",
2928         .sysc = &omap3xxx_mailbox_sysc,
2929 };
2930
2931 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2932 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2933         { .irq = 26 },
2934 };
2935
2936 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2937         {
2938                 .pa_start       = 0x48094000,
2939                 .pa_end         = 0x480941ff,
2940                 .flags          = ADDR_TYPE_RT,
2941         },
2942         { }
2943 };
2944
2945 /* l4_core -> mailbox */
2946 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2947         .master         = &omap3xxx_l4_core_hwmod,
2948         .slave          = &omap3xxx_mailbox_hwmod,
2949         .addr           = omap3xxx_mailbox_addrs,
2950         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2951 };
2952
2953 /* mailbox slave ports */
2954 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2955         &omap3xxx_l4_core__mailbox,
2956 };
2957
2958 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2959         .name           = "mailbox",
2960         .class          = &omap3xxx_mailbox_hwmod_class,
2961         .mpu_irqs       = omap3xxx_mailbox_irqs,
2962         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mailbox_irqs),
2963         .main_clk       = "mailboxes_ick",
2964         .prcm           = {
2965                 .omap2 = {
2966                         .prcm_reg_id = 1,
2967                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2968                         .module_offs = CORE_MOD,
2969                         .idlest_reg_id = 1,
2970                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2971                 },
2972         },
2973         .slaves         = omap3xxx_mailbox_slaves,
2974         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2975         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2976 };
2977
2978 /* l4 core -> mcspi1 interface */
2979 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2980         .master         = &omap3xxx_l4_core_hwmod,
2981         .slave          = &omap34xx_mcspi1,
2982         .clk            = "mcspi1_ick",
2983         .addr           = omap2_mcspi1_addr_space,
2984         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2985 };
2986
2987 /* l4 core -> mcspi2 interface */
2988 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2989         .master         = &omap3xxx_l4_core_hwmod,
2990         .slave          = &omap34xx_mcspi2,
2991         .clk            = "mcspi2_ick",
2992         .addr           = omap2_mcspi2_addr_space,
2993         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2994 };
2995
2996 /* l4 core -> mcspi3 interface */
2997 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2998         .master         = &omap3xxx_l4_core_hwmod,
2999         .slave          = &omap34xx_mcspi3,
3000         .clk            = "mcspi3_ick",
3001         .addr           = omap2430_mcspi3_addr_space,
3002         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3003 };
3004
3005 /* l4 core -> mcspi4 interface */
3006 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3007         {
3008                 .pa_start       = 0x480ba000,
3009                 .pa_end         = 0x480ba0ff,
3010                 .flags          = ADDR_TYPE_RT,
3011         },
3012         { }
3013 };
3014
3015 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3016         .master         = &omap3xxx_l4_core_hwmod,
3017         .slave          = &omap34xx_mcspi4,
3018         .clk            = "mcspi4_ick",
3019         .addr           = omap34xx_mcspi4_addr_space,
3020         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3021 };
3022
3023 /*
3024  * 'mcspi' class
3025  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3026  * bus
3027  */
3028
3029 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
3030         .rev_offs       = 0x0000,
3031         .sysc_offs      = 0x0010,
3032         .syss_offs      = 0x0014,
3033         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3034                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3035                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3036         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3037         .sysc_fields    = &omap_hwmod_sysc_type1,
3038 };
3039
3040 static struct omap_hwmod_class omap34xx_mcspi_class = {
3041         .name = "mcspi",
3042         .sysc = &omap34xx_mcspi_sysc,
3043         .rev = OMAP3_MCSPI_REV,
3044 };
3045
3046 /* mcspi1 */
3047 static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
3048         { .name = "irq", .irq = 65 },
3049 };
3050
3051 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
3052         { .name = "tx0", .dma_req = 35 },
3053         { .name = "rx0", .dma_req = 36 },
3054         { .name = "tx1", .dma_req = 37 },
3055         { .name = "rx1", .dma_req = 38 },
3056         { .name = "tx2", .dma_req = 39 },
3057         { .name = "rx2", .dma_req = 40 },
3058         { .name = "tx3", .dma_req = 41 },
3059         { .name = "rx3", .dma_req = 42 },
3060 };
3061
3062 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
3063         &omap34xx_l4_core__mcspi1,
3064 };
3065
3066 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
3067         .num_chipselect = 4,
3068 };
3069
3070 static struct omap_hwmod omap34xx_mcspi1 = {
3071         .name           = "mcspi1",
3072         .mpu_irqs       = omap34xx_mcspi1_mpu_irqs,
3073         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
3074         .sdma_reqs      = omap34xx_mcspi1_sdma_reqs,
3075         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
3076         .main_clk       = "mcspi1_fck",
3077         .prcm           = {
3078                 .omap2 = {
3079                         .module_offs = CORE_MOD,
3080                         .prcm_reg_id = 1,
3081                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
3082                         .idlest_reg_id = 1,
3083                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
3084                 },
3085         },
3086         .slaves         = omap34xx_mcspi1_slaves,
3087         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
3088         .class          = &omap34xx_mcspi_class,
3089         .dev_attr       = &omap_mcspi1_dev_attr,
3090         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3091 };
3092
3093 /* mcspi2 */
3094 static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
3095         { .name = "irq", .irq = 66 },
3096 };
3097
3098 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
3099         { .name = "tx0", .dma_req = 43 },
3100         { .name = "rx0", .dma_req = 44 },
3101         { .name = "tx1", .dma_req = 45 },
3102         { .name = "rx1", .dma_req = 46 },
3103 };
3104
3105 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
3106         &omap34xx_l4_core__mcspi2,
3107 };
3108
3109 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
3110         .num_chipselect = 2,
3111 };
3112
3113 static struct omap_hwmod omap34xx_mcspi2 = {
3114         .name           = "mcspi2",
3115         .mpu_irqs       = omap34xx_mcspi2_mpu_irqs,
3116         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
3117         .sdma_reqs      = omap34xx_mcspi2_sdma_reqs,
3118         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
3119         .main_clk       = "mcspi2_fck",
3120         .prcm           = {
3121                 .omap2 = {
3122                         .module_offs = CORE_MOD,
3123                         .prcm_reg_id = 1,
3124                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
3125                         .idlest_reg_id = 1,
3126                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
3127                 },
3128         },
3129         .slaves         = omap34xx_mcspi2_slaves,
3130         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
3131         .class          = &omap34xx_mcspi_class,
3132         .dev_attr       = &omap_mcspi2_dev_attr,
3133         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3134 };
3135
3136 /* mcspi3 */
3137 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
3138         { .name = "irq", .irq = 91 }, /* 91 */
3139 };
3140
3141 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
3142         { .name = "tx0", .dma_req = 15 },
3143         { .name = "rx0", .dma_req = 16 },
3144         { .name = "tx1", .dma_req = 23 },
3145         { .name = "rx1", .dma_req = 24 },
3146 };
3147
3148 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
3149         &omap34xx_l4_core__mcspi3,
3150 };
3151
3152 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
3153         .num_chipselect = 2,
3154 };
3155
3156 static struct omap_hwmod omap34xx_mcspi3 = {
3157         .name           = "mcspi3",
3158         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
3159         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
3160         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
3161         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
3162         .main_clk       = "mcspi3_fck",
3163         .prcm           = {
3164                 .omap2 = {
3165                         .module_offs = CORE_MOD,
3166                         .prcm_reg_id = 1,
3167                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
3168                         .idlest_reg_id = 1,
3169                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
3170                 },
3171         },
3172         .slaves         = omap34xx_mcspi3_slaves,
3173         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3174         .class          = &omap34xx_mcspi_class,
3175         .dev_attr       = &omap_mcspi3_dev_attr,
3176         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3177 };
3178
3179 /* SPI4 */
3180 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3181         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3182 };
3183
3184 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3185         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3186         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3187 };
3188
3189 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3190         &omap34xx_l4_core__mcspi4,
3191 };
3192
3193 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3194         .num_chipselect = 1,
3195 };
3196
3197 static struct omap_hwmod omap34xx_mcspi4 = {
3198         .name           = "mcspi4",
3199         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
3200         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
3201         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
3202         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
3203         .main_clk       = "mcspi4_fck",
3204         .prcm           = {
3205                 .omap2 = {
3206                         .module_offs = CORE_MOD,
3207                         .prcm_reg_id = 1,
3208                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3209                         .idlest_reg_id = 1,
3210                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3211                 },
3212         },
3213         .slaves         = omap34xx_mcspi4_slaves,
3214         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3215         .class          = &omap34xx_mcspi_class,
3216         .dev_attr       = &omap_mcspi4_dev_attr,
3217         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3218 };
3219
3220 /*
3221  * usbhsotg
3222  */
3223 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3224         .rev_offs       = 0x0400,
3225         .sysc_offs      = 0x0404,
3226         .syss_offs      = 0x0408,
3227         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3228                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3229                           SYSC_HAS_AUTOIDLE),
3230         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3231                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3232         .sysc_fields    = &omap_hwmod_sysc_type1,
3233 };
3234
3235 static struct omap_hwmod_class usbotg_class = {
3236         .name = "usbotg",
3237         .sysc = &omap3xxx_usbhsotg_sysc,
3238 };
3239 /* usb_otg_hs */
3240 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3241
3242         { .name = "mc", .irq = 92 },
3243         { .name = "dma", .irq = 93 },
3244 };
3245
3246 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3247         .name           = "usb_otg_hs",
3248         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
3249         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
3250         .main_clk       = "hsotgusb_ick",
3251         .prcm           = {
3252                 .omap2 = {
3253                         .prcm_reg_id = 1,
3254                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3255                         .module_offs = CORE_MOD,
3256                         .idlest_reg_id = 1,
3257                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3258                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3259                 },
3260         },
3261         .masters        = omap3xxx_usbhsotg_masters,
3262         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3263         .slaves         = omap3xxx_usbhsotg_slaves,
3264         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3265         .class          = &usbotg_class,
3266
3267         /*
3268          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
3269          * broken when autoidle is enabled
3270          * workaround is to disable the autoidle bit at module level.
3271          */
3272         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3273                                 | HWMOD_SWSUP_MSTANDBY,
3274         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3275 };
3276
3277 /* usb_otg_hs */
3278 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3279
3280         { .name = "mc", .irq = 71 },
3281 };
3282
3283 static struct omap_hwmod_class am35xx_usbotg_class = {
3284         .name = "am35xx_usbotg",
3285         .sysc = NULL,
3286 };
3287
3288 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3289         .name           = "am35x_otg_hs",
3290         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3291         .mpu_irqs_cnt   = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
3292         .main_clk       = NULL,
3293         .prcm = {
3294                 .omap2 = {
3295                 },
3296         },
3297         .masters        = am35xx_usbhsotg_masters,
3298         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3299         .slaves         = am35xx_usbhsotg_slaves,
3300         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3301         .class          = &am35xx_usbotg_class,
3302         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3303 };
3304
3305 /* MMC/SD/SDIO common */
3306
3307 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3308         .rev_offs       = 0x1fc,
3309         .sysc_offs      = 0x10,
3310         .syss_offs      = 0x14,
3311         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3312                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3313                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3314         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3315         .sysc_fields    = &omap_hwmod_sysc_type1,
3316 };
3317
3318 static struct omap_hwmod_class omap34xx_mmc_class = {
3319         .name = "mmc",
3320         .sysc = &omap34xx_mmc_sysc,
3321 };
3322
3323 /* MMC/SD/SDIO1 */
3324
3325 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3326         { .irq = 83, },
3327 };
3328
3329 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3330         { .name = "tx", .dma_req = 61, },
3331         { .name = "rx", .dma_req = 62, },
3332 };
3333
3334 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3335         { .role = "dbck", .clk = "omap_32k_fck", },
3336 };
3337
3338 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3339         &omap3xxx_l4_core__mmc1,
3340 };
3341
3342 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3343         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3344 };
3345
3346 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3347         .name           = "mmc1",
3348         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3349         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
3350         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3351         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3352         .opt_clks       = omap34xx_mmc1_opt_clks,
3353         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3354         .main_clk       = "mmchs1_fck",
3355         .prcm           = {
3356                 .omap2 = {
3357                         .module_offs = CORE_MOD,
3358                         .prcm_reg_id = 1,
3359                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3360                         .idlest_reg_id = 1,
3361                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3362                 },
3363         },
3364         .dev_attr       = &mmc1_dev_attr,
3365         .slaves         = omap3xxx_mmc1_slaves,
3366         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3367         .class          = &omap34xx_mmc_class,
3368         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3369 };
3370
3371 /* MMC/SD/SDIO2 */
3372
3373 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3374         { .irq = INT_24XX_MMC2_IRQ, },
3375 };
3376
3377 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3378         { .name = "tx", .dma_req = 47, },
3379         { .name = "rx", .dma_req = 48, },
3380 };
3381
3382 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3383         { .role = "dbck", .clk = "omap_32k_fck", },
3384 };
3385
3386 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3387         &omap3xxx_l4_core__mmc2,
3388 };
3389
3390 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3391         .name           = "mmc2",
3392         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3393         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
3394         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3395         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3396         .opt_clks       = omap34xx_mmc2_opt_clks,
3397         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3398         .main_clk       = "mmchs2_fck",
3399         .prcm           = {
3400                 .omap2 = {
3401                         .module_offs = CORE_MOD,
3402                         .prcm_reg_id = 1,
3403                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3404                         .idlest_reg_id = 1,
3405                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3406                 },
3407         },
3408         .slaves         = omap3xxx_mmc2_slaves,
3409         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3410         .class          = &omap34xx_mmc_class,
3411         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3412 };
3413
3414 /* MMC/SD/SDIO3 */
3415
3416 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3417         { .irq = 94, },
3418 };
3419
3420 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3421         { .name = "tx", .dma_req = 77, },
3422         { .name = "rx", .dma_req = 78, },
3423 };
3424
3425 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3426         { .role = "dbck", .clk = "omap_32k_fck", },
3427 };
3428
3429 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3430         &omap3xxx_l4_core__mmc3,
3431 };
3432
3433 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3434         .name           = "mmc3",
3435         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3436         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
3437         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3438         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3439         .opt_clks       = omap34xx_mmc3_opt_clks,
3440         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3441         .main_clk       = "mmchs3_fck",
3442         .prcm           = {
3443                 .omap2 = {
3444                         .prcm_reg_id = 1,
3445                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3446                         .idlest_reg_id = 1,
3447                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3448                 },
3449         },
3450         .slaves         = omap3xxx_mmc3_slaves,
3451         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3452         .class          = &omap34xx_mmc_class,
3453         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3454 };
3455
3456 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3457         &omap3xxx_l3_main_hwmod,
3458         &omap3xxx_l4_core_hwmod,
3459         &omap3xxx_l4_per_hwmod,
3460         &omap3xxx_l4_wkup_hwmod,
3461         &omap3xxx_mmc1_hwmod,
3462         &omap3xxx_mmc2_hwmod,
3463         &omap3xxx_mmc3_hwmod,
3464         &omap3xxx_mpu_hwmod,
3465         &omap3xxx_iva_hwmod,
3466
3467         &omap3xxx_timer1_hwmod,
3468         &omap3xxx_timer2_hwmod,
3469         &omap3xxx_timer3_hwmod,
3470         &omap3xxx_timer4_hwmod,
3471         &omap3xxx_timer5_hwmod,
3472         &omap3xxx_timer6_hwmod,
3473         &omap3xxx_timer7_hwmod,
3474         &omap3xxx_timer8_hwmod,
3475         &omap3xxx_timer9_hwmod,
3476         &omap3xxx_timer10_hwmod,
3477         &omap3xxx_timer11_hwmod,
3478         &omap3xxx_timer12_hwmod,
3479
3480         &omap3xxx_wd_timer2_hwmod,
3481         &omap3xxx_uart1_hwmod,
3482         &omap3xxx_uart2_hwmod,
3483         &omap3xxx_uart3_hwmod,
3484         &omap3xxx_uart4_hwmod,
3485         /* dss class */
3486         &omap3430es1_dss_core_hwmod,
3487         &omap3xxx_dss_core_hwmod,
3488         &omap3xxx_dss_dispc_hwmod,
3489         &omap3xxx_dss_dsi1_hwmod,
3490         &omap3xxx_dss_rfbi_hwmod,
3491         &omap3xxx_dss_venc_hwmod,
3492
3493         /* i2c class */
3494         &omap3xxx_i2c1_hwmod,
3495         &omap3xxx_i2c2_hwmod,
3496         &omap3xxx_i2c3_hwmod,
3497         &omap34xx_sr1_hwmod,
3498         &omap34xx_sr2_hwmod,
3499         &omap36xx_sr1_hwmod,
3500         &omap36xx_sr2_hwmod,
3501
3502
3503         /* gpio class */
3504         &omap3xxx_gpio1_hwmod,
3505         &omap3xxx_gpio2_hwmod,
3506         &omap3xxx_gpio3_hwmod,
3507         &omap3xxx_gpio4_hwmod,
3508         &omap3xxx_gpio5_hwmod,
3509         &omap3xxx_gpio6_hwmod,
3510
3511         /* dma_system class*/
3512         &omap3xxx_dma_system_hwmod,
3513
3514         /* mcbsp class */
3515         &omap3xxx_mcbsp1_hwmod,
3516         &omap3xxx_mcbsp2_hwmod,
3517         &omap3xxx_mcbsp3_hwmod,
3518         &omap3xxx_mcbsp4_hwmod,
3519         &omap3xxx_mcbsp5_hwmod,
3520         &omap3xxx_mcbsp2_sidetone_hwmod,
3521         &omap3xxx_mcbsp3_sidetone_hwmod,
3522
3523         /* mailbox class */
3524         &omap3xxx_mailbox_hwmod,
3525
3526         /* mcspi class */
3527         &omap34xx_mcspi1,
3528         &omap34xx_mcspi2,
3529         &omap34xx_mcspi3,
3530         &omap34xx_mcspi4,
3531
3532         /* usbotg class */
3533         &omap3xxx_usbhsotg_hwmod,
3534
3535         /* usbotg for am35x */
3536         &am35xx_usbhsotg_hwmod,
3537
3538         NULL,
3539 };
3540
3541 int __init omap3xxx_hwmod_init(void)
3542 {
3543         return omap_hwmod_register(omap3xxx_hwmods);
3544 }