arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "prm-regbits-34xx.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "wd_timer.h"
  35 #include <mach/am35xx.h>
  36
  37 /*
  38  * OMAP3xxx hardware module integration data
  39  *
  40  * ALl of the data in this section should be autogeneratable from the
  41  * TI hardware database or other technical documentation.  Data that
  42  * is driver-specific or driver-kernel integration-specific belongs
  43  * elsewhere.
  44  */
  45
  46 static struct omap_hwmod omap3xxx_mpu_hwmod;
  47 static struct omap_hwmod omap3xxx_iva_hwmod;
  48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  67 static struct omap_hwmod omap34xx_sr1_hwmod;
  68 static struct omap_hwmod omap34xx_sr2_hwmod;
  69 static struct omap_hwmod omap34xx_mcspi1;
  70 static struct omap_hwmod omap34xx_mcspi2;
  71 static struct omap_hwmod omap34xx_mcspi3;
  72 static struct omap_hwmod omap34xx_mcspi4;
  73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  77
  78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  79
  80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  87
  88 /* L3 -> L4_CORE interface */
  89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  90         .master = &omap3xxx_l3_main_hwmod,
  91         .slave  = &omap3xxx_l4_core_hwmod,
  92         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  93 };
  94
  95 /* L3 -> L4_PER interface */
  96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  97         .master = &omap3xxx_l3_main_hwmod,
  98         .slave  = &omap3xxx_l4_per_hwmod,
  99         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 100 };
 101
 102 /* L3 taret configuration and error log registers */
 103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 104         { .irq = INT_34XX_L3_DBG_IRQ },
 105         { .irq = INT_34XX_L3_APP_IRQ },
 106         { .irq = -1 }
 107 };
 108
 109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 110         {
 111                 .pa_start       = 0x68000000,
 112                 .pa_end         = 0x6800ffff,
 113                 .flags          = ADDR_TYPE_RT,
 114         },
 115         { }
 116 };
 117
 118 /* MPU -> L3 interface */
 119 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 120         .master   = &omap3xxx_mpu_hwmod,
 121         .slave    = &omap3xxx_l3_main_hwmod,
 122         .addr     = omap3xxx_l3_main_addrs,
 123         .user   = OCP_USER_MPU,
 124 };
 125
 126 /* Slave interfaces on the L3 interconnect */
 127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 128         &omap3xxx_mpu__l3_main,
 129 };
 130
 131 /* DSS -> l3 */
 132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 133         .master         = &omap3xxx_dss_core_hwmod,
 134         .slave          = &omap3xxx_l3_main_hwmod,
 135         .fw = {
 136                 .omap2 = {
 137                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 138                         .flags  = OMAP_FIREWALL_L3,
 139                 }
 140         },
 141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 142 };
 143
 144 /* Master interfaces on the L3 interconnect */
 145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 146         &omap3xxx_l3_main__l4_core,
 147         &omap3xxx_l3_main__l4_per,
 148 };
 149
 150 /* L3 */
 151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 152         .name           = "l3_main",
 153         .class          = &l3_hwmod_class,
 154         .mpu_irqs       = omap3xxx_l3_main_irqs,
 155         .masters        = omap3xxx_l3_main_masters,
 156         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 157         .slaves         = omap3xxx_l3_main_slaves,
 158         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 159         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 160         .flags          = HWMOD_NO_IDLEST,
 161 };
 162
 163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 164 static struct omap_hwmod omap3xxx_uart1_hwmod;
 165 static struct omap_hwmod omap3xxx_uart2_hwmod;
 166 static struct omap_hwmod omap3xxx_uart3_hwmod;
 167 static struct omap_hwmod omap3xxx_uart4_hwmod;
 168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 169
 170 /* l3_core -> usbhsotg interface */
 171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 172         .master         = &omap3xxx_usbhsotg_hwmod,
 173         .slave          = &omap3xxx_l3_main_hwmod,
 174         .clk            = "core_l3_ick",
 175         .user           = OCP_USER_MPU,
 176 };
 177
 178 /* l3_core -> am35xx_usbhsotg interface */
 179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 180         .master         = &am35xx_usbhsotg_hwmod,
 181         .slave          = &omap3xxx_l3_main_hwmod,
 182         .clk            = "core_l3_ick",
 183         .user           = OCP_USER_MPU,
 184 };
 185 /* L4_CORE -> L4_WKUP interface */
 186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 187         .master = &omap3xxx_l4_core_hwmod,
 188         .slave  = &omap3xxx_l4_wkup_hwmod,
 189         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 190 };
 191
 192 /* L4 CORE -> MMC1 interface */
 193 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 194         .master         = &omap3xxx_l4_core_hwmod,
 195         .slave          = &omap3xxx_mmc1_hwmod,
 196         .clk            = "mmchs1_ick",
 197         .addr           = omap2430_mmc1_addr_space,
 198         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 199         .flags          = OMAP_FIREWALL_L4
 200 };
 201
 202 /* L4 CORE -> MMC2 interface */
 203 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 204         .master         = &omap3xxx_l4_core_hwmod,
 205         .slave          = &omap3xxx_mmc2_hwmod,
 206         .clk            = "mmchs2_ick",
 207         .addr           = omap2430_mmc2_addr_space,
 208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 209         .flags          = OMAP_FIREWALL_L4
 210 };
 211
 212 /* L4 CORE -> MMC3 interface */
 213 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 214         {
 215                 .pa_start       = 0x480ad000,
 216                 .pa_end         = 0x480ad1ff,
 217                 .flags          = ADDR_TYPE_RT,
 218         },
 219         { }
 220 };
 221
 222 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 223         .master         = &omap3xxx_l4_core_hwmod,
 224         .slave          = &omap3xxx_mmc3_hwmod,
 225         .clk            = "mmchs3_ick",
 226         .addr           = omap3xxx_mmc3_addr_space,
 227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 228         .flags          = OMAP_FIREWALL_L4
 229 };
 230
 231 /* L4 CORE -> UART1 interface */
 232 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 233         {
 234                 .pa_start       = OMAP3_UART1_BASE,
 235                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 236                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 237         },
 238         { }
 239 };
 240
 241 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 242         .master         = &omap3xxx_l4_core_hwmod,
 243         .slave          = &omap3xxx_uart1_hwmod,
 244         .clk            = "uart1_ick",
 245         .addr           = omap3xxx_uart1_addr_space,
 246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 247 };
 248
 249 /* L4 CORE -> UART2 interface */
 250 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 251         {
 252                 .pa_start       = OMAP3_UART2_BASE,
 253                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 254                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 255         },
 256         { }
 257 };
 258
 259 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 260         .master         = &omap3xxx_l4_core_hwmod,
 261         .slave          = &omap3xxx_uart2_hwmod,
 262         .clk            = "uart2_ick",
 263         .addr           = omap3xxx_uart2_addr_space,
 264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 265 };
 266
 267 /* L4 PER -> UART3 interface */
 268 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 269         {
 270                 .pa_start       = OMAP3_UART3_BASE,
 271                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 272                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 273         },
 274         { }
 275 };
 276
 277 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 278         .master         = &omap3xxx_l4_per_hwmod,
 279         .slave          = &omap3xxx_uart3_hwmod,
 280         .clk            = "uart3_ick",
 281         .addr           = omap3xxx_uart3_addr_space,
 282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 283 };
 284
 285 /* L4 PER -> UART4 interface */
 286 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 287         {
 288                 .pa_start       = OMAP3_UART4_BASE,
 289                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 290                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 291         },
 292         { }
 293 };
 294
 295 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 296         .master         = &omap3xxx_l4_per_hwmod,
 297         .slave          = &omap3xxx_uart4_hwmod,
 298         .clk            = "uart4_ick",
 299         .addr           = omap3xxx_uart4_addr_space,
 300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 301 };
 302
 303 /* L4 CORE -> I2C1 interface */
 304 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 305         .master         = &omap3xxx_l4_core_hwmod,
 306         .slave          = &omap3xxx_i2c1_hwmod,
 307         .clk            = "i2c1_ick",
 308         .addr           = omap2_i2c1_addr_space,
 309         .fw = {
 310                 .omap2 = {
 311                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 312                         .l4_prot_group = 7,
 313                         .flags  = OMAP_FIREWALL_L4,
 314                 }
 315         },
 316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 317 };
 318
 319 /* L4 CORE -> I2C2 interface */
 320 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 321         .master         = &omap3xxx_l4_core_hwmod,
 322         .slave          = &omap3xxx_i2c2_hwmod,
 323         .clk            = "i2c2_ick",
 324         .addr           = omap2_i2c2_addr_space,
 325         .fw = {
 326                 .omap2 = {
 327                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 328                         .l4_prot_group = 7,
 329                         .flags = OMAP_FIREWALL_L4,
 330                 }
 331         },
 332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 333 };
 334
 335 /* L4 CORE -> I2C3 interface */
 336 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 337         {
 338                 .pa_start       = 0x48060000,
 339                 .pa_end         = 0x48060000 + SZ_128 - 1,
 340                 .flags          = ADDR_TYPE_RT,
 341         },
 342         { }
 343 };
 344
 345 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 346         .master         = &omap3xxx_l4_core_hwmod,
 347         .slave          = &omap3xxx_i2c3_hwmod,
 348         .clk            = "i2c3_ick",
 349         .addr           = omap3xxx_i2c3_addr_space,
 350         .fw = {
 351                 .omap2 = {
 352                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 353                         .l4_prot_group = 7,
 354                         .flags = OMAP_FIREWALL_L4,
 355                 }
 356         },
 357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 358 };
 359
 360 /* L4 CORE -> SR1 interface */
 361 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 362         {
 363                 .pa_start       = OMAP34XX_SR1_BASE,
 364                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 365                 .flags          = ADDR_TYPE_RT,
 366         },
 367         { }
 368 };
 369
 370 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 371         .master         = &omap3xxx_l4_core_hwmod,
 372         .slave          = &omap34xx_sr1_hwmod,
 373         .clk            = "sr_l4_ick",
 374         .addr           = omap3_sr1_addr_space,
 375         .user           = OCP_USER_MPU,
 376 };
 377
 378 /* L4 CORE -> SR1 interface */
 379 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 380         {
 381                 .pa_start       = OMAP34XX_SR2_BASE,
 382                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 383                 .flags          = ADDR_TYPE_RT,
 384         },
 385         { }
 386 };
 387
 388 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 389         .master         = &omap3xxx_l4_core_hwmod,
 390         .slave          = &omap34xx_sr2_hwmod,
 391         .clk            = "sr_l4_ick",
 392         .addr           = omap3_sr2_addr_space,
 393         .user           = OCP_USER_MPU,
 394 };
 395
 396 /*
 397 * usbhsotg interface data
 398 */
 399
 400 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 401         {
 402                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 403                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 404                 .flags          = ADDR_TYPE_RT
 405         },
 406         { }
 407 };
 408
 409 /* l4_core -> usbhsotg  */
 410 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 411         .master         = &omap3xxx_l4_core_hwmod,
 412         .slave          = &omap3xxx_usbhsotg_hwmod,
 413         .clk            = "l4_ick",
 414         .addr           = omap3xxx_usbhsotg_addrs,
 415         .user           = OCP_USER_MPU,
 416 };
 417
 418 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 419         &omap3xxx_usbhsotg__l3,
 420 };
 421
 422 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 423         &omap3xxx_l4_core__usbhsotg,
 424 };
 425
 426 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 427         {
 428                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 429                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 430                 .flags          = ADDR_TYPE_RT
 431         },
 432         { }
 433 };
 434
 435 /* l4_core -> usbhsotg  */
 436 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 437         .master         = &omap3xxx_l4_core_hwmod,
 438         .slave          = &am35xx_usbhsotg_hwmod,
 439         .clk            = "l4_ick",
 440         .addr           = am35xx_usbhsotg_addrs,
 441         .user           = OCP_USER_MPU,
 442 };
 443
 444 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 445         &am35xx_usbhsotg__l3,
 446 };
 447
 448 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 449         &am35xx_l4_core__usbhsotg,
 450 };
 451 /* Slave interfaces on the L4_CORE interconnect */
 452 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 453         &omap3xxx_l3_main__l4_core,
 454 };
 455
 456 /* L4 CORE */
 457 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 458         .name           = "l4_core",
 459         .class          = &l4_hwmod_class,
 460         .slaves         = omap3xxx_l4_core_slaves,
 461         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 462         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 463         .flags          = HWMOD_NO_IDLEST,
 464 };
 465
 466 /* Slave interfaces on the L4_PER interconnect */
 467 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 468         &omap3xxx_l3_main__l4_per,
 469 };
 470
 471 /* L4 PER */
 472 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 473         .name           = "l4_per",
 474         .class          = &l4_hwmod_class,
 475         .slaves         = omap3xxx_l4_per_slaves,
 476         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 477         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 478         .flags          = HWMOD_NO_IDLEST,
 479 };
 480
 481 /* Slave interfaces on the L4_WKUP interconnect */
 482 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 483         &omap3xxx_l4_core__l4_wkup,
 484 };
 485
 486 /* L4 WKUP */
 487 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 488         .name           = "l4_wkup",
 489         .class          = &l4_hwmod_class,
 490         .slaves         = omap3xxx_l4_wkup_slaves,
 491         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 492         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 493         .flags          = HWMOD_NO_IDLEST,
 494 };
 495
 496 /* Master interfaces on the MPU device */
 497 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 498         &omap3xxx_mpu__l3_main,
 499 };
 500
 501 /* MPU */
 502 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 503         .name           = "mpu",
 504         .class          = &mpu_hwmod_class,
 505         .main_clk       = "arm_fck",
 506         .masters        = omap3xxx_mpu_masters,
 507         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 508         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 509 };
 510
 511 /*
 512  * IVA2_2 interface data
 513  */
 514
 515 /* IVA2 <- L3 interface */
 516 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 517         .master         = &omap3xxx_l3_main_hwmod,
 518         .slave          = &omap3xxx_iva_hwmod,
 519         .clk            = "iva2_ck",
 520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 521 };
 522
 523 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 524         &omap3xxx_l3__iva,
 525 };
 526
 527 /*
 528  * IVA2 (IVA2)
 529  */
 530
 531 static struct omap_hwmod omap3xxx_iva_hwmod = {
 532         .name           = "iva",
 533         .class          = &iva_hwmod_class,
 534         .masters        = omap3xxx_iva_masters,
 535         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 536         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 537 };
 538
 539 /* timer class */
 540 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 541         .rev_offs       = 0x0000,
 542         .sysc_offs      = 0x0010,
 543         .syss_offs      = 0x0014,
 544         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 545                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 546                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 547         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 548         .sysc_fields    = &omap_hwmod_sysc_type1,
 549 };
 550
 551 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 552         .name = "timer",
 553         .sysc = &omap3xxx_timer_1ms_sysc,
 554         .rev = OMAP_TIMER_IP_VERSION_1,
 555 };
 556
 557 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 558         .rev_offs       = 0x0000,
 559         .sysc_offs      = 0x0010,
 560         .syss_offs      = 0x0014,
 561         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 562                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 563         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 564         .sysc_fields    = &omap_hwmod_sysc_type1,
 565 };
 566
 567 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 568         .name = "timer",
 569         .sysc = &omap3xxx_timer_sysc,
 570         .rev =  OMAP_TIMER_IP_VERSION_1,
 571 };
 572
 573 /* timer1 */
 574 static struct omap_hwmod omap3xxx_timer1_hwmod;
 575
 576 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 577         {
 578                 .pa_start       = 0x48318000,
 579                 .pa_end         = 0x48318000 + SZ_1K - 1,
 580                 .flags          = ADDR_TYPE_RT
 581         },
 582         { }
 583 };
 584
 585 /* l4_wkup -> timer1 */
 586 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 587         .master         = &omap3xxx_l4_wkup_hwmod,
 588         .slave          = &omap3xxx_timer1_hwmod,
 589         .clk            = "gpt1_ick",
 590         .addr           = omap3xxx_timer1_addrs,
 591         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 592 };
 593
 594 /* timer1 slave port */
 595 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 596         &omap3xxx_l4_wkup__timer1,
 597 };
 598
 599 /* timer1 hwmod */
 600 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 601         .name           = "timer1",
 602         .mpu_irqs       = omap2_timer1_mpu_irqs,
 603         .main_clk       = "gpt1_fck",
 604         .prcm           = {
 605                 .omap2 = {
 606                         .prcm_reg_id = 1,
 607                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 608                         .module_offs = WKUP_MOD,
 609                         .idlest_reg_id = 1,
 610                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 611                 },
 612         },
 613         .slaves         = omap3xxx_timer1_slaves,
 614         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 615         .class          = &omap3xxx_timer_1ms_hwmod_class,
 616         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 617 };
 618
 619 /* timer2 */
 620 static struct omap_hwmod omap3xxx_timer2_hwmod;
 621
 622 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 623         {
 624                 .pa_start       = 0x49032000,
 625                 .pa_end         = 0x49032000 + SZ_1K - 1,
 626                 .flags          = ADDR_TYPE_RT
 627         },
 628         { }
 629 };
 630
 631 /* l4_per -> timer2 */
 632 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 633         .master         = &omap3xxx_l4_per_hwmod,
 634         .slave          = &omap3xxx_timer2_hwmod,
 635         .clk            = "gpt2_ick",
 636         .addr           = omap3xxx_timer2_addrs,
 637         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 638 };
 639
 640 /* timer2 slave port */
 641 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 642         &omap3xxx_l4_per__timer2,
 643 };
 644
 645 /* timer2 hwmod */
 646 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 647         .name           = "timer2",
 648         .mpu_irqs       = omap2_timer2_mpu_irqs,
 649         .main_clk       = "gpt2_fck",
 650         .prcm           = {
 651                 .omap2 = {
 652                         .prcm_reg_id = 1,
 653                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 654                         .module_offs = OMAP3430_PER_MOD,
 655                         .idlest_reg_id = 1,
 656                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 657                 },
 658         },
 659         .slaves         = omap3xxx_timer2_slaves,
 660         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 661         .class          = &omap3xxx_timer_1ms_hwmod_class,
 662         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 663 };
 664
 665 /* timer3 */
 666 static struct omap_hwmod omap3xxx_timer3_hwmod;
 667
 668 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 669         {
 670                 .pa_start       = 0x49034000,
 671                 .pa_end         = 0x49034000 + SZ_1K - 1,
 672                 .flags          = ADDR_TYPE_RT
 673         },
 674         { }
 675 };
 676
 677 /* l4_per -> timer3 */
 678 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 679         .master         = &omap3xxx_l4_per_hwmod,
 680         .slave          = &omap3xxx_timer3_hwmod,
 681         .clk            = "gpt3_ick",
 682         .addr           = omap3xxx_timer3_addrs,
 683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 684 };
 685
 686 /* timer3 slave port */
 687 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 688         &omap3xxx_l4_per__timer3,
 689 };
 690
 691 /* timer3 hwmod */
 692 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 693         .name           = "timer3",
 694         .mpu_irqs       = omap2_timer3_mpu_irqs,
 695         .main_clk       = "gpt3_fck",
 696         .prcm           = {
 697                 .omap2 = {
 698                         .prcm_reg_id = 1,
 699                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 700                         .module_offs = OMAP3430_PER_MOD,
 701                         .idlest_reg_id = 1,
 702                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 703                 },
 704         },
 705         .slaves         = omap3xxx_timer3_slaves,
 706         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 707         .class          = &omap3xxx_timer_hwmod_class,
 708         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 709 };
 710
 711 /* timer4 */
 712 static struct omap_hwmod omap3xxx_timer4_hwmod;
 713
 714 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 715         {
 716                 .pa_start       = 0x49036000,
 717                 .pa_end         = 0x49036000 + SZ_1K - 1,
 718                 .flags          = ADDR_TYPE_RT
 719         },
 720         { }
 721 };
 722
 723 /* l4_per -> timer4 */
 724 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 725         .master         = &omap3xxx_l4_per_hwmod,
 726         .slave          = &omap3xxx_timer4_hwmod,
 727         .clk            = "gpt4_ick",
 728         .addr           = omap3xxx_timer4_addrs,
 729         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 730 };
 731
 732 /* timer4 slave port */
 733 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 734         &omap3xxx_l4_per__timer4,
 735 };
 736
 737 /* timer4 hwmod */
 738 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 739         .name           = "timer4",
 740         .mpu_irqs       = omap2_timer4_mpu_irqs,
 741         .main_clk       = "gpt4_fck",
 742         .prcm           = {
 743                 .omap2 = {
 744                         .prcm_reg_id = 1,
 745                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 746                         .module_offs = OMAP3430_PER_MOD,
 747                         .idlest_reg_id = 1,
 748                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 749                 },
 750         },
 751         .slaves         = omap3xxx_timer4_slaves,
 752         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 753         .class          = &omap3xxx_timer_hwmod_class,
 754         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 755 };
 756
 757 /* timer5 */
 758 static struct omap_hwmod omap3xxx_timer5_hwmod;
 759
 760 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 761         {
 762                 .pa_start       = 0x49038000,
 763                 .pa_end         = 0x49038000 + SZ_1K - 1,
 764                 .flags          = ADDR_TYPE_RT
 765         },
 766         { }
 767 };
 768
 769 /* l4_per -> timer5 */
 770 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 771         .master         = &omap3xxx_l4_per_hwmod,
 772         .slave          = &omap3xxx_timer5_hwmod,
 773         .clk            = "gpt5_ick",
 774         .addr           = omap3xxx_timer5_addrs,
 775         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 776 };
 777
 778 /* timer5 slave port */
 779 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 780         &omap3xxx_l4_per__timer5,
 781 };
 782
 783 /* timer5 hwmod */
 784 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 785         .name           = "timer5",
 786         .mpu_irqs       = omap2_timer5_mpu_irqs,
 787         .main_clk       = "gpt5_fck",
 788         .prcm           = {
 789                 .omap2 = {
 790                         .prcm_reg_id = 1,
 791                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 792                         .module_offs = OMAP3430_PER_MOD,
 793                         .idlest_reg_id = 1,
 794                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 795                 },
 796         },
 797         .slaves         = omap3xxx_timer5_slaves,
 798         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 799         .class          = &omap3xxx_timer_hwmod_class,
 800         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 801 };
 802
 803 /* timer6 */
 804 static struct omap_hwmod omap3xxx_timer6_hwmod;
 805
 806 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 807         {
 808                 .pa_start       = 0x4903A000,
 809                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 810                 .flags          = ADDR_TYPE_RT
 811         },
 812         { }
 813 };
 814
 815 /* l4_per -> timer6 */
 816 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 817         .master         = &omap3xxx_l4_per_hwmod,
 818         .slave          = &omap3xxx_timer6_hwmod,
 819         .clk            = "gpt6_ick",
 820         .addr           = omap3xxx_timer6_addrs,
 821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 822 };
 823
 824 /* timer6 slave port */
 825 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 826         &omap3xxx_l4_per__timer6,
 827 };
 828
 829 /* timer6 hwmod */
 830 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 831         .name           = "timer6",
 832         .mpu_irqs       = omap2_timer6_mpu_irqs,
 833         .main_clk       = "gpt6_fck",
 834         .prcm           = {
 835                 .omap2 = {
 836                         .prcm_reg_id = 1,
 837                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 838                         .module_offs = OMAP3430_PER_MOD,
 839                         .idlest_reg_id = 1,
 840                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 841                 },
 842         },
 843         .slaves         = omap3xxx_timer6_slaves,
 844         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 845         .class          = &omap3xxx_timer_hwmod_class,
 846         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 847 };
 848
 849 /* timer7 */
 850 static struct omap_hwmod omap3xxx_timer7_hwmod;
 851
 852 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 853         {
 854                 .pa_start       = 0x4903C000,
 855                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 856                 .flags          = ADDR_TYPE_RT
 857         },
 858         { }
 859 };
 860
 861 /* l4_per -> timer7 */
 862 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 863         .master         = &omap3xxx_l4_per_hwmod,
 864         .slave          = &omap3xxx_timer7_hwmod,
 865         .clk            = "gpt7_ick",
 866         .addr           = omap3xxx_timer7_addrs,
 867         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 868 };
 869
 870 /* timer7 slave port */
 871 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 872         &omap3xxx_l4_per__timer7,
 873 };
 874
 875 /* timer7 hwmod */
 876 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 877         .name           = "timer7",
 878         .mpu_irqs       = omap2_timer7_mpu_irqs,
 879         .main_clk       = "gpt7_fck",
 880         .prcm           = {
 881                 .omap2 = {
 882                         .prcm_reg_id = 1,
 883                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 884                         .module_offs = OMAP3430_PER_MOD,
 885                         .idlest_reg_id = 1,
 886                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 887                 },
 888         },
 889         .slaves         = omap3xxx_timer7_slaves,
 890         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 891         .class          = &omap3xxx_timer_hwmod_class,
 892         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 893 };
 894
 895 /* timer8 */
 896 static struct omap_hwmod omap3xxx_timer8_hwmod;
 897
 898 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 899         {
 900                 .pa_start       = 0x4903E000,
 901                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 902                 .flags          = ADDR_TYPE_RT
 903         },
 904         { }
 905 };
 906
 907 /* l4_per -> timer8 */
 908 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 909         .master         = &omap3xxx_l4_per_hwmod,
 910         .slave          = &omap3xxx_timer8_hwmod,
 911         .clk            = "gpt8_ick",
 912         .addr           = omap3xxx_timer8_addrs,
 913         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 914 };
 915
 916 /* timer8 slave port */
 917 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 918         &omap3xxx_l4_per__timer8,
 919 };
 920
 921 /* timer8 hwmod */
 922 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 923         .name           = "timer8",
 924         .mpu_irqs       = omap2_timer8_mpu_irqs,
 925         .main_clk       = "gpt8_fck",
 926         .prcm           = {
 927                 .omap2 = {
 928                         .prcm_reg_id = 1,
 929                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 930                         .module_offs = OMAP3430_PER_MOD,
 931                         .idlest_reg_id = 1,
 932                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 933                 },
 934         },
 935         .slaves         = omap3xxx_timer8_slaves,
 936         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
 937         .class          = &omap3xxx_timer_hwmod_class,
 938         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 939 };
 940
 941 /* timer9 */
 942 static struct omap_hwmod omap3xxx_timer9_hwmod;
 943
 944 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
 945         {
 946                 .pa_start       = 0x49040000,
 947                 .pa_end         = 0x49040000 + SZ_1K - 1,
 948                 .flags          = ADDR_TYPE_RT
 949         },
 950         { }
 951 };
 952
 953 /* l4_per -> timer9 */
 954 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
 955         .master         = &omap3xxx_l4_per_hwmod,
 956         .slave          = &omap3xxx_timer9_hwmod,
 957         .clk            = "gpt9_ick",
 958         .addr           = omap3xxx_timer9_addrs,
 959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 960 };
 961
 962 /* timer9 slave port */
 963 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
 964         &omap3xxx_l4_per__timer9,
 965 };
 966
 967 /* timer9 hwmod */
 968 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 969         .name           = "timer9",
 970         .mpu_irqs       = omap2_timer9_mpu_irqs,
 971         .main_clk       = "gpt9_fck",
 972         .prcm           = {
 973                 .omap2 = {
 974                         .prcm_reg_id = 1,
 975                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 976                         .module_offs = OMAP3430_PER_MOD,
 977                         .idlest_reg_id = 1,
 978                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 979                 },
 980         },
 981         .slaves         = omap3xxx_timer9_slaves,
 982         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
 983         .class          = &omap3xxx_timer_hwmod_class,
 984         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 985 };
 986
 987 /* timer10 */
 988 static struct omap_hwmod omap3xxx_timer10_hwmod;
 989
 990 /* l4_core -> timer10 */
 991 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
 992         .master         = &omap3xxx_l4_core_hwmod,
 993         .slave          = &omap3xxx_timer10_hwmod,
 994         .clk            = "gpt10_ick",
 995         .addr           = omap2_timer10_addrs,
 996         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 997 };
 998
 999 /* timer10 slave port */
1000 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1001         &omap3xxx_l4_core__timer10,
1002 };
1003
1004 /* timer10 hwmod */
1005 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1006         .name           = "timer10",
1007         .mpu_irqs       = omap2_timer10_mpu_irqs,
1008         .main_clk       = "gpt10_fck",
1009         .prcm           = {
1010                 .omap2 = {
1011                         .prcm_reg_id = 1,
1012                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1013                         .module_offs = CORE_MOD,
1014                         .idlest_reg_id = 1,
1015                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1016                 },
1017         },
1018         .slaves         = omap3xxx_timer10_slaves,
1019         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1020         .class          = &omap3xxx_timer_1ms_hwmod_class,
1021         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1022 };
1023
1024 /* timer11 */
1025 static struct omap_hwmod omap3xxx_timer11_hwmod;
1026
1027 /* l4_core -> timer11 */
1028 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1029         .master         = &omap3xxx_l4_core_hwmod,
1030         .slave          = &omap3xxx_timer11_hwmod,
1031         .clk            = "gpt11_ick",
1032         .addr           = omap2_timer11_addrs,
1033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1034 };
1035
1036 /* timer11 slave port */
1037 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1038         &omap3xxx_l4_core__timer11,
1039 };
1040
1041 /* timer11 hwmod */
1042 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1043         .name           = "timer11",
1044         .mpu_irqs       = omap2_timer11_mpu_irqs,
1045         .main_clk       = "gpt11_fck",
1046         .prcm           = {
1047                 .omap2 = {
1048                         .prcm_reg_id = 1,
1049                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1050                         .module_offs = CORE_MOD,
1051                         .idlest_reg_id = 1,
1052                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1053                 },
1054         },
1055         .slaves         = omap3xxx_timer11_slaves,
1056         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1057         .class          = &omap3xxx_timer_hwmod_class,
1058         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1059 };
1060
1061 /* timer12*/
1062 static struct omap_hwmod omap3xxx_timer12_hwmod;
1063 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1064         { .irq = 95, },
1065         { .irq = -1 }
1066 };
1067
1068 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1069         {
1070                 .pa_start       = 0x48304000,
1071                 .pa_end         = 0x48304000 + SZ_1K - 1,
1072                 .flags          = ADDR_TYPE_RT
1073         },
1074         { }
1075 };
1076
1077 /* l4_core -> timer12 */
1078 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1079         .master         = &omap3xxx_l4_core_hwmod,
1080         .slave          = &omap3xxx_timer12_hwmod,
1081         .clk            = "gpt12_ick",
1082         .addr           = omap3xxx_timer12_addrs,
1083         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1084 };
1085
1086 /* timer12 slave port */
1087 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1088         &omap3xxx_l4_core__timer12,
1089 };
1090
1091 /* timer12 hwmod */
1092 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1093         .name           = "timer12",
1094         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1095         .main_clk       = "gpt12_fck",
1096         .prcm           = {
1097                 .omap2 = {
1098                         .prcm_reg_id = 1,
1099                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1100                         .module_offs = WKUP_MOD,
1101                         .idlest_reg_id = 1,
1102                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1103                 },
1104         },
1105         .slaves         = omap3xxx_timer12_slaves,
1106         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1107         .class          = &omap3xxx_timer_hwmod_class,
1108         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1109 };
1110
1111 /* l4_wkup -> wd_timer2 */
1112 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1113         {
1114                 .pa_start       = 0x48314000,
1115                 .pa_end         = 0x4831407f,
1116                 .flags          = ADDR_TYPE_RT
1117         },
1118         { }
1119 };
1120
1121 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1122         .master         = &omap3xxx_l4_wkup_hwmod,
1123         .slave          = &omap3xxx_wd_timer2_hwmod,
1124         .clk            = "wdt2_ick",
1125         .addr           = omap3xxx_wd_timer2_addrs,
1126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1127 };
1128
1129 /*
1130  * 'wd_timer' class
1131  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1132  * overflow condition
1133  */
1134
1135 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1136         .rev_offs       = 0x0000,
1137         .sysc_offs      = 0x0010,
1138         .syss_offs      = 0x0014,
1139         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1140                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1141                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1142                            SYSS_HAS_RESET_STATUS),
1143         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1144         .sysc_fields    = &omap_hwmod_sysc_type1,
1145 };
1146
1147 /* I2C common */
1148 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1149         .rev_offs       = 0x00,
1150         .sysc_offs      = 0x20,
1151         .syss_offs      = 0x10,
1152         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1153                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1154                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1155         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1156         .sysc_fields    = &omap_hwmod_sysc_type1,
1157 };
1158
1159 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1160         .name           = "wd_timer",
1161         .sysc           = &omap3xxx_wd_timer_sysc,
1162         .pre_shutdown   = &omap2_wd_timer_disable
1163 };
1164
1165 /* wd_timer2 */
1166 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1167         &omap3xxx_l4_wkup__wd_timer2,
1168 };
1169
1170 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1171         .name           = "wd_timer2",
1172         .class          = &omap3xxx_wd_timer_hwmod_class,
1173         .main_clk       = "wdt2_fck",
1174         .prcm           = {
1175                 .omap2 = {
1176                         .prcm_reg_id = 1,
1177                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1178                         .module_offs = WKUP_MOD,
1179                         .idlest_reg_id = 1,
1180                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1181                 },
1182         },
1183         .slaves         = omap3xxx_wd_timer2_slaves,
1184         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1185         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1186         /*
1187          * XXX: Use software supervised mode, HW supervised smartidle seems to
1188          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1189          */
1190         .flags          = HWMOD_SWSUP_SIDLE,
1191 };
1192
1193 /* UART1 */
1194
1195 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1196         &omap3_l4_core__uart1,
1197 };
1198
1199 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1200         .name           = "uart1",
1201         .mpu_irqs       = omap2_uart1_mpu_irqs,
1202         .sdma_reqs      = omap2_uart1_sdma_reqs,
1203         .main_clk       = "uart1_fck",
1204         .prcm           = {
1205                 .omap2 = {
1206                         .module_offs = CORE_MOD,
1207                         .prcm_reg_id = 1,
1208                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1209                         .idlest_reg_id = 1,
1210                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1211                 },
1212         },
1213         .slaves         = omap3xxx_uart1_slaves,
1214         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1215         .class          = &omap2_uart_class,
1216         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1217 };
1218
1219 /* UART2 */
1220
1221 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1222         &omap3_l4_core__uart2,
1223 };
1224
1225 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1226         .name           = "uart2",
1227         .mpu_irqs       = omap2_uart2_mpu_irqs,
1228         .sdma_reqs      = omap2_uart2_sdma_reqs,
1229         .main_clk       = "uart2_fck",
1230         .prcm           = {
1231                 .omap2 = {
1232                         .module_offs = CORE_MOD,
1233                         .prcm_reg_id = 1,
1234                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1235                         .idlest_reg_id = 1,
1236                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1237                 },
1238         },
1239         .slaves         = omap3xxx_uart2_slaves,
1240         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1241         .class          = &omap2_uart_class,
1242         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1243 };
1244
1245 /* UART3 */
1246
1247 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1248         &omap3_l4_per__uart3,
1249 };
1250
1251 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1252         .name           = "uart3",
1253         .mpu_irqs       = omap2_uart3_mpu_irqs,
1254         .sdma_reqs      = omap2_uart3_sdma_reqs,
1255         .main_clk       = "uart3_fck",
1256         .prcm           = {
1257                 .omap2 = {
1258                         .module_offs = OMAP3430_PER_MOD,
1259                         .prcm_reg_id = 1,
1260                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1261                         .idlest_reg_id = 1,
1262                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1263                 },
1264         },
1265         .slaves         = omap3xxx_uart3_slaves,
1266         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1267         .class          = &omap2_uart_class,
1268         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1269 };
1270
1271 /* UART4 */
1272
1273 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1274         { .irq = INT_36XX_UART4_IRQ, },
1275         { .irq = -1 }
1276 };
1277
1278 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1279         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1280         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1281         { .dma_req = -1 }
1282 };
1283
1284 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1285         &omap3_l4_per__uart4,
1286 };
1287
1288 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1289         .name           = "uart4",
1290         .mpu_irqs       = uart4_mpu_irqs,
1291         .sdma_reqs      = uart4_sdma_reqs,
1292         .main_clk       = "uart4_fck",
1293         .prcm           = {
1294                 .omap2 = {
1295                         .module_offs = OMAP3430_PER_MOD,
1296                         .prcm_reg_id = 1,
1297                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1298                         .idlest_reg_id = 1,
1299                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1300                 },
1301         },
1302         .slaves         = omap3xxx_uart4_slaves,
1303         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1304         .class          = &omap2_uart_class,
1305         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1306 };
1307
1308 static struct omap_hwmod_class i2c_class = {
1309         .name = "i2c",
1310         .sysc = &i2c_sysc,
1311         .rev  = OMAP_I2C_IP_VERSION_1,
1312 };
1313
1314 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1315         { .name = "dispc", .dma_req = 5 },
1316         { .name = "dsi1", .dma_req = 74 },
1317         { .dma_req = -1 }
1318 };
1319
1320 /* dss */
1321 /* dss master ports */
1322 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1323         &omap3xxx_dss__l3,
1324 };
1325
1326 /* l4_core -> dss */
1327 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1328         .master         = &omap3xxx_l4_core_hwmod,
1329         .slave          = &omap3430es1_dss_core_hwmod,
1330         .clk            = "dss_ick",
1331         .addr           = omap2_dss_addrs,
1332         .fw = {
1333                 .omap2 = {
1334                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1335                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1336                         .flags  = OMAP_FIREWALL_L4,
1337                 }
1338         },
1339         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1340 };
1341
1342 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1343         .master         = &omap3xxx_l4_core_hwmod,
1344         .slave          = &omap3xxx_dss_core_hwmod,
1345         .clk            = "dss_ick",
1346         .addr           = omap2_dss_addrs,
1347         .fw = {
1348                 .omap2 = {
1349                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1350                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1351                         .flags  = OMAP_FIREWALL_L4,
1352                 }
1353         },
1354         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1355 };
1356
1357 /* dss slave ports */
1358 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1359         &omap3430es1_l4_core__dss,
1360 };
1361
1362 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1363         &omap3xxx_l4_core__dss,
1364 };
1365
1366 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1367         { .role = "tv_clk", .clk = "dss_tv_fck" },
1368         { .role = "video_clk", .clk = "dss_96m_fck" },
1369         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1370 };
1371
1372 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1373         .name           = "dss_core",
1374         .class          = &omap2_dss_hwmod_class,
1375         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1376         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1377         .prcm           = {
1378                 .omap2 = {
1379                         .prcm_reg_id = 1,
1380                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1381                         .module_offs = OMAP3430_DSS_MOD,
1382                         .idlest_reg_id = 1,
1383                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1384                 },
1385         },
1386         .opt_clks       = dss_opt_clks,
1387         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1388         .slaves         = omap3430es1_dss_slaves,
1389         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1390         .masters        = omap3xxx_dss_masters,
1391         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1392         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1393         .flags          = HWMOD_NO_IDLEST,
1394 };
1395
1396 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1397         .name           = "dss_core",
1398         .class          = &omap2_dss_hwmod_class,
1399         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1400         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1401         .prcm           = {
1402                 .omap2 = {
1403                         .prcm_reg_id = 1,
1404                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1405                         .module_offs = OMAP3430_DSS_MOD,
1406                         .idlest_reg_id = 1,
1407                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1408                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1409                 },
1410         },
1411         .opt_clks       = dss_opt_clks,
1412         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1413         .slaves         = omap3xxx_dss_slaves,
1414         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1415         .masters        = omap3xxx_dss_masters,
1416         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1417         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1418                                 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1419 };
1420
1421 /* l4_core -> dss_dispc */
1422 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1423         .master         = &omap3xxx_l4_core_hwmod,
1424         .slave          = &omap3xxx_dss_dispc_hwmod,
1425         .clk            = "dss_ick",
1426         .addr           = omap2_dss_dispc_addrs,
1427         .fw = {
1428                 .omap2 = {
1429                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1430                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1431                         .flags  = OMAP_FIREWALL_L4,
1432                 }
1433         },
1434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1435 };
1436
1437 /* dss_dispc slave ports */
1438 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1439         &omap3xxx_l4_core__dss_dispc,
1440 };
1441
1442 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1443         .name           = "dss_dispc",
1444         .class          = &omap2_dispc_hwmod_class,
1445         .mpu_irqs       = omap2_dispc_irqs,
1446         .main_clk       = "dss1_alwon_fck",
1447         .prcm           = {
1448                 .omap2 = {
1449                         .prcm_reg_id = 1,
1450                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1451                         .module_offs = OMAP3430_DSS_MOD,
1452                 },
1453         },
1454         .slaves         = omap3xxx_dss_dispc_slaves,
1455         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1456         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1457                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1458                                 CHIP_GE_OMAP3630ES1_1),
1459         .flags          = HWMOD_NO_IDLEST,
1460 };
1461
1462 /*
1463  * 'dsi' class
1464  * display serial interface controller
1465  */
1466
1467 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1468         .name = "dsi",
1469 };
1470
1471 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1472         { .irq = 25 },
1473         { .irq = -1 }
1474 };
1475
1476 /* dss_dsi1 */
1477 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1478         {
1479                 .pa_start       = 0x4804FC00,
1480                 .pa_end         = 0x4804FFFF,
1481                 .flags          = ADDR_TYPE_RT
1482         },
1483         { }
1484 };
1485
1486 /* l4_core -> dss_dsi1 */
1487 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1488         .master         = &omap3xxx_l4_core_hwmod,
1489         .slave          = &omap3xxx_dss_dsi1_hwmod,
1490         .addr           = omap3xxx_dss_dsi1_addrs,
1491         .fw = {
1492                 .omap2 = {
1493                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1494                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1495                         .flags  = OMAP_FIREWALL_L4,
1496                 }
1497         },
1498         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1499 };
1500
1501 /* dss_dsi1 slave ports */
1502 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1503         &omap3xxx_l4_core__dss_dsi1,
1504 };
1505
1506 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1507         .name           = "dss_dsi1",
1508         .class          = &omap3xxx_dsi_hwmod_class,
1509         .mpu_irqs       = omap3xxx_dsi1_irqs,
1510         .main_clk       = "dss1_alwon_fck",
1511         .prcm           = {
1512                 .omap2 = {
1513                         .prcm_reg_id = 1,
1514                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1515                         .module_offs = OMAP3430_DSS_MOD,
1516                 },
1517         },
1518         .slaves         = omap3xxx_dss_dsi1_slaves,
1519         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1520         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1521                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1522                                 CHIP_GE_OMAP3630ES1_1),
1523         .flags          = HWMOD_NO_IDLEST,
1524 };
1525
1526 /* l4_core -> dss_rfbi */
1527 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1528         .master         = &omap3xxx_l4_core_hwmod,
1529         .slave          = &omap3xxx_dss_rfbi_hwmod,
1530         .clk            = "dss_ick",
1531         .addr           = omap2_dss_rfbi_addrs,
1532         .fw = {
1533                 .omap2 = {
1534                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1535                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1536                         .flags  = OMAP_FIREWALL_L4,
1537                 }
1538         },
1539         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1540 };
1541
1542 /* dss_rfbi slave ports */
1543 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1544         &omap3xxx_l4_core__dss_rfbi,
1545 };
1546
1547 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1548         .name           = "dss_rfbi",
1549         .class          = &omap2_rfbi_hwmod_class,
1550         .main_clk       = "dss1_alwon_fck",
1551         .prcm           = {
1552                 .omap2 = {
1553                         .prcm_reg_id = 1,
1554                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1555                         .module_offs = OMAP3430_DSS_MOD,
1556                 },
1557         },
1558         .slaves         = omap3xxx_dss_rfbi_slaves,
1559         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1560         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1561                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1562                                 CHIP_GE_OMAP3630ES1_1),
1563         .flags          = HWMOD_NO_IDLEST,
1564 };
1565
1566 /* l4_core -> dss_venc */
1567 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1568         .master         = &omap3xxx_l4_core_hwmod,
1569         .slave          = &omap3xxx_dss_venc_hwmod,
1570         .clk            = "dss_tv_fck",
1571         .addr           = omap2_dss_venc_addrs,
1572         .fw = {
1573                 .omap2 = {
1574                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1575                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1576                         .flags  = OMAP_FIREWALL_L4,
1577                 }
1578         },
1579         .flags          = OCPIF_SWSUP_IDLE,
1580         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1581 };
1582
1583 /* dss_venc slave ports */
1584 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1585         &omap3xxx_l4_core__dss_venc,
1586 };
1587
1588 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1589         .name           = "dss_venc",
1590         .class          = &omap2_venc_hwmod_class,
1591         .main_clk       = "dss1_alwon_fck",
1592         .prcm           = {
1593                 .omap2 = {
1594                         .prcm_reg_id = 1,
1595                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1596                         .module_offs = OMAP3430_DSS_MOD,
1597                 },
1598         },
1599         .slaves         = omap3xxx_dss_venc_slaves,
1600         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1601         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1602                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1603                                 CHIP_GE_OMAP3630ES1_1),
1604         .flags          = HWMOD_NO_IDLEST,
1605 };
1606
1607 /* I2C1 */
1608
1609 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1610         .fifo_depth     = 8, /* bytes */
1611 };
1612
1613 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1614         &omap3_l4_core__i2c1,
1615 };
1616
1617 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1618         .name           = "i2c1",
1619         .flags          = HWMOD_16BIT_REG,
1620         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1621         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1622         .main_clk       = "i2c1_fck",
1623         .prcm           = {
1624                 .omap2 = {
1625                         .module_offs = CORE_MOD,
1626                         .prcm_reg_id = 1,
1627                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1628                         .idlest_reg_id = 1,
1629                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1630                 },
1631         },
1632         .slaves         = omap3xxx_i2c1_slaves,
1633         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1634         .class          = &i2c_class,
1635         .dev_attr       = &i2c1_dev_attr,
1636         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1637 };
1638
1639 /* I2C2 */
1640
1641 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1642         .fifo_depth     = 8, /* bytes */
1643 };
1644
1645 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1646         &omap3_l4_core__i2c2,
1647 };
1648
1649 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1650         .name           = "i2c2",
1651         .flags          = HWMOD_16BIT_REG,
1652         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1653         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1654         .main_clk       = "i2c2_fck",
1655         .prcm           = {
1656                 .omap2 = {
1657                         .module_offs = CORE_MOD,
1658                         .prcm_reg_id = 1,
1659                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1660                         .idlest_reg_id = 1,
1661                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1662                 },
1663         },
1664         .slaves         = omap3xxx_i2c2_slaves,
1665         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1666         .class          = &i2c_class,
1667         .dev_attr       = &i2c2_dev_attr,
1668         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1669 };
1670
1671 /* I2C3 */
1672
1673 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1674         .fifo_depth     = 64, /* bytes */
1675 };
1676
1677 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1678         { .irq = INT_34XX_I2C3_IRQ, },
1679         { .irq = -1 }
1680 };
1681
1682 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1683         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1684         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1685         { .dma_req = -1 }
1686 };
1687
1688 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1689         &omap3_l4_core__i2c3,
1690 };
1691
1692 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1693         .name           = "i2c3",
1694         .flags          = HWMOD_16BIT_REG,
1695         .mpu_irqs       = i2c3_mpu_irqs,
1696         .sdma_reqs      = i2c3_sdma_reqs,
1697         .main_clk       = "i2c3_fck",
1698         .prcm           = {
1699                 .omap2 = {
1700                         .module_offs = CORE_MOD,
1701                         .prcm_reg_id = 1,
1702                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1703                         .idlest_reg_id = 1,
1704                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1705                 },
1706         },
1707         .slaves         = omap3xxx_i2c3_slaves,
1708         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1709         .class          = &i2c_class,
1710         .dev_attr       = &i2c3_dev_attr,
1711         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1712 };
1713
1714 /* l4_wkup -> gpio1 */
1715 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1716         {
1717                 .pa_start       = 0x48310000,
1718                 .pa_end         = 0x483101ff,
1719                 .flags          = ADDR_TYPE_RT
1720         },
1721         { }
1722 };
1723
1724 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1725         .master         = &omap3xxx_l4_wkup_hwmod,
1726         .slave          = &omap3xxx_gpio1_hwmod,
1727         .addr           = omap3xxx_gpio1_addrs,
1728         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1729 };
1730
1731 /* l4_per -> gpio2 */
1732 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1733         {
1734                 .pa_start       = 0x49050000,
1735                 .pa_end         = 0x490501ff,
1736                 .flags          = ADDR_TYPE_RT
1737         },
1738         { }
1739 };
1740
1741 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1742         .master         = &omap3xxx_l4_per_hwmod,
1743         .slave          = &omap3xxx_gpio2_hwmod,
1744         .addr           = omap3xxx_gpio2_addrs,
1745         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1746 };
1747
1748 /* l4_per -> gpio3 */
1749 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1750         {
1751                 .pa_start       = 0x49052000,
1752                 .pa_end         = 0x490521ff,
1753                 .flags          = ADDR_TYPE_RT
1754         },
1755         { }
1756 };
1757
1758 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1759         .master         = &omap3xxx_l4_per_hwmod,
1760         .slave          = &omap3xxx_gpio3_hwmod,
1761         .addr           = omap3xxx_gpio3_addrs,
1762         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1763 };
1764
1765 /* l4_per -> gpio4 */
1766 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1767         {
1768                 .pa_start       = 0x49054000,
1769                 .pa_end         = 0x490541ff,
1770                 .flags          = ADDR_TYPE_RT
1771         },
1772         { }
1773 };
1774
1775 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1776         .master         = &omap3xxx_l4_per_hwmod,
1777         .slave          = &omap3xxx_gpio4_hwmod,
1778         .addr           = omap3xxx_gpio4_addrs,
1779         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1780 };
1781
1782 /* l4_per -> gpio5 */
1783 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1784         {
1785                 .pa_start       = 0x49056000,
1786                 .pa_end         = 0x490561ff,
1787                 .flags          = ADDR_TYPE_RT
1788         },
1789         { }
1790 };
1791
1792 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1793         .master         = &omap3xxx_l4_per_hwmod,
1794         .slave          = &omap3xxx_gpio5_hwmod,
1795         .addr           = omap3xxx_gpio5_addrs,
1796         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1797 };
1798
1799 /* l4_per -> gpio6 */
1800 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1801         {
1802                 .pa_start       = 0x49058000,
1803                 .pa_end         = 0x490581ff,
1804                 .flags          = ADDR_TYPE_RT
1805         },
1806         { }
1807 };
1808
1809 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1810         .master         = &omap3xxx_l4_per_hwmod,
1811         .slave          = &omap3xxx_gpio6_hwmod,
1812         .addr           = omap3xxx_gpio6_addrs,
1813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1814 };
1815
1816 /*
1817  * 'gpio' class
1818  * general purpose io module
1819  */
1820
1821 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1822         .rev_offs       = 0x0000,
1823         .sysc_offs      = 0x0010,
1824         .syss_offs      = 0x0014,
1825         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1826                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1827                            SYSS_HAS_RESET_STATUS),
1828         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1829         .sysc_fields    = &omap_hwmod_sysc_type1,
1830 };
1831
1832 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1833         .name = "gpio",
1834         .sysc = &omap3xxx_gpio_sysc,
1835         .rev = 1,
1836 };
1837
1838 /* gpio_dev_attr*/
1839 static struct omap_gpio_dev_attr gpio_dev_attr = {
1840         .bank_width = 32,
1841         .dbck_flag = true,
1842 };
1843
1844 /* gpio1 */
1845 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1846         { .role = "dbclk", .clk = "gpio1_dbck", },
1847 };
1848
1849 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1850         &omap3xxx_l4_wkup__gpio1,
1851 };
1852
1853 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1854         .name           = "gpio1",
1855         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1856         .mpu_irqs       = omap2_gpio1_irqs,
1857         .main_clk       = "gpio1_ick",
1858         .opt_clks       = gpio1_opt_clks,
1859         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1860         .prcm           = {
1861                 .omap2 = {
1862                         .prcm_reg_id = 1,
1863                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1864                         .module_offs = WKUP_MOD,
1865                         .idlest_reg_id = 1,
1866                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1867                 },
1868         },
1869         .slaves         = omap3xxx_gpio1_slaves,
1870         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1871         .class          = &omap3xxx_gpio_hwmod_class,
1872         .dev_attr       = &gpio_dev_attr,
1873         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1874 };
1875
1876 /* gpio2 */
1877 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1878         { .role = "dbclk", .clk = "gpio2_dbck", },
1879 };
1880
1881 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1882         &omap3xxx_l4_per__gpio2,
1883 };
1884
1885 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1886         .name           = "gpio2",
1887         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1888         .mpu_irqs       = omap2_gpio2_irqs,
1889         .main_clk       = "gpio2_ick",
1890         .opt_clks       = gpio2_opt_clks,
1891         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1892         .prcm           = {
1893                 .omap2 = {
1894                         .prcm_reg_id = 1,
1895                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1896                         .module_offs = OMAP3430_PER_MOD,
1897                         .idlest_reg_id = 1,
1898                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1899                 },
1900         },
1901         .slaves         = omap3xxx_gpio2_slaves,
1902         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1903         .class          = &omap3xxx_gpio_hwmod_class,
1904         .dev_attr       = &gpio_dev_attr,
1905         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1906 };
1907
1908 /* gpio3 */
1909 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1910         { .role = "dbclk", .clk = "gpio3_dbck", },
1911 };
1912
1913 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1914         &omap3xxx_l4_per__gpio3,
1915 };
1916
1917 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1918         .name           = "gpio3",
1919         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1920         .mpu_irqs       = omap2_gpio3_irqs,
1921         .main_clk       = "gpio3_ick",
1922         .opt_clks       = gpio3_opt_clks,
1923         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1924         .prcm           = {
1925                 .omap2 = {
1926                         .prcm_reg_id = 1,
1927                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1928                         .module_offs = OMAP3430_PER_MOD,
1929                         .idlest_reg_id = 1,
1930                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1931                 },
1932         },
1933         .slaves         = omap3xxx_gpio3_slaves,
1934         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1935         .class          = &omap3xxx_gpio_hwmod_class,
1936         .dev_attr       = &gpio_dev_attr,
1937         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1938 };
1939
1940 /* gpio4 */
1941 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1942         { .role = "dbclk", .clk = "gpio4_dbck", },
1943 };
1944
1945 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1946         &omap3xxx_l4_per__gpio4,
1947 };
1948
1949 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1950         .name           = "gpio4",
1951         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1952         .mpu_irqs       = omap2_gpio4_irqs,
1953         .main_clk       = "gpio4_ick",
1954         .opt_clks       = gpio4_opt_clks,
1955         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1956         .prcm           = {
1957                 .omap2 = {
1958                         .prcm_reg_id = 1,
1959                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1960                         .module_offs = OMAP3430_PER_MOD,
1961                         .idlest_reg_id = 1,
1962                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1963                 },
1964         },
1965         .slaves         = omap3xxx_gpio4_slaves,
1966         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1967         .class          = &omap3xxx_gpio_hwmod_class,
1968         .dev_attr       = &gpio_dev_attr,
1969         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1970 };
1971
1972 /* gpio5 */
1973 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1974         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1975         { .irq = -1 }
1976 };
1977
1978 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1979         { .role = "dbclk", .clk = "gpio5_dbck", },
1980 };
1981
1982 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
1983         &omap3xxx_l4_per__gpio5,
1984 };
1985
1986 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1987         .name           = "gpio5",
1988         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1989         .mpu_irqs       = omap3xxx_gpio5_irqs,
1990         .main_clk       = "gpio5_ick",
1991         .opt_clks       = gpio5_opt_clks,
1992         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1993         .prcm           = {
1994                 .omap2 = {
1995                         .prcm_reg_id = 1,
1996                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1997                         .module_offs = OMAP3430_PER_MOD,
1998                         .idlest_reg_id = 1,
1999                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2000                 },
2001         },
2002         .slaves         = omap3xxx_gpio5_slaves,
2003         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2004         .class          = &omap3xxx_gpio_hwmod_class,
2005         .dev_attr       = &gpio_dev_attr,
2006         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2007 };
2008
2009 /* gpio6 */
2010 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2011         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2012         { .irq = -1 }
2013 };
2014
2015 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2016         { .role = "dbclk", .clk = "gpio6_dbck", },
2017 };
2018
2019 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2020         &omap3xxx_l4_per__gpio6,
2021 };
2022
2023 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2024         .name           = "gpio6",
2025         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2026         .mpu_irqs       = omap3xxx_gpio6_irqs,
2027         .main_clk       = "gpio6_ick",
2028         .opt_clks       = gpio6_opt_clks,
2029         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2030         .prcm           = {
2031                 .omap2 = {
2032                         .prcm_reg_id = 1,
2033                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2034                         .module_offs = OMAP3430_PER_MOD,
2035                         .idlest_reg_id = 1,
2036                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2037                 },
2038         },
2039         .slaves         = omap3xxx_gpio6_slaves,
2040         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2041         .class          = &omap3xxx_gpio_hwmod_class,
2042         .dev_attr       = &gpio_dev_attr,
2043         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2044 };
2045
2046 /* dma_system -> L3 */
2047 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2048         .master         = &omap3xxx_dma_system_hwmod,
2049         .slave          = &omap3xxx_l3_main_hwmod,
2050         .clk            = "core_l3_ick",
2051         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2052 };
2053
2054 /* dma attributes */
2055 static struct omap_dma_dev_attr dma_dev_attr = {
2056         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2057                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2058         .lch_count = 32,
2059 };
2060
2061 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2062         .rev_offs       = 0x0000,
2063         .sysc_offs      = 0x002c,
2064         .syss_offs      = 0x0028,
2065         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2066                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2067                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2068                            SYSS_HAS_RESET_STATUS),
2069         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2070                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2071         .sysc_fields    = &omap_hwmod_sysc_type1,
2072 };
2073
2074 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2075         .name = "dma",
2076         .sysc = &omap3xxx_dma_sysc,
2077 };
2078
2079 /* dma_system */
2080 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2081         {
2082                 .pa_start       = 0x48056000,
2083                 .pa_end         = 0x48056fff,
2084                 .flags          = ADDR_TYPE_RT
2085         },
2086         { }
2087 };
2088
2089 /* dma_system master ports */
2090 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2091         &omap3xxx_dma_system__l3,
2092 };
2093
2094 /* l4_cfg -> dma_system */
2095 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2096         .master         = &omap3xxx_l4_core_hwmod,
2097         .slave          = &omap3xxx_dma_system_hwmod,
2098         .clk            = "core_l4_ick",
2099         .addr           = omap3xxx_dma_system_addrs,
2100         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2101 };
2102
2103 /* dma_system slave ports */
2104 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2105         &omap3xxx_l4_core__dma_system,
2106 };
2107
2108 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2109         .name           = "dma",
2110         .class          = &omap3xxx_dma_hwmod_class,
2111         .mpu_irqs       = omap2_dma_system_irqs,
2112         .main_clk       = "core_l3_ick",
2113         .prcm = {
2114                 .omap2 = {
2115                         .module_offs            = CORE_MOD,
2116                         .prcm_reg_id            = 1,
2117                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2118                         .idlest_reg_id          = 1,
2119                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2120                 },
2121         },
2122         .slaves         = omap3xxx_dma_system_slaves,
2123         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2124         .masters        = omap3xxx_dma_system_masters,
2125         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2126         .dev_attr       = &dma_dev_attr,
2127         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2128         .flags          = HWMOD_NO_IDLEST,
2129 };
2130
2131 /*
2132  * 'mcbsp' class
2133  * multi channel buffered serial port controller
2134  */
2135
2136 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2137         .sysc_offs      = 0x008c,
2138         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2139                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2140         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2141         .sysc_fields    = &omap_hwmod_sysc_type1,
2142         .clockact       = 0x2,
2143 };
2144
2145 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2146         .name = "mcbsp",
2147         .sysc = &omap3xxx_mcbsp_sysc,
2148         .rev  = MCBSP_CONFIG_TYPE3,
2149 };
2150
2151 /* mcbsp1 */
2152 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2153         { .name = "irq", .irq = 16 },
2154         { .name = "tx", .irq = 59 },
2155         { .name = "rx", .irq = 60 },
2156         { .irq = -1 }
2157 };
2158
2159 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2160         {
2161                 .name           = "mpu",
2162                 .pa_start       = 0x48074000,
2163                 .pa_end         = 0x480740ff,
2164                 .flags          = ADDR_TYPE_RT
2165         },
2166         { }
2167 };
2168
2169 /* l4_core -> mcbsp1 */
2170 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2171         .master         = &omap3xxx_l4_core_hwmod,
2172         .slave          = &omap3xxx_mcbsp1_hwmod,
2173         .clk            = "mcbsp1_ick",
2174         .addr           = omap3xxx_mcbsp1_addrs,
2175         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2176 };
2177
2178 /* mcbsp1 slave ports */
2179 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2180         &omap3xxx_l4_core__mcbsp1,
2181 };
2182
2183 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2184         .name           = "mcbsp1",
2185         .class          = &omap3xxx_mcbsp_hwmod_class,
2186         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2187         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
2188         .main_clk       = "mcbsp1_fck",
2189         .prcm           = {
2190                 .omap2 = {
2191                         .prcm_reg_id = 1,
2192                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2193                         .module_offs = CORE_MOD,
2194                         .idlest_reg_id = 1,
2195                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2196                 },
2197         },
2198         .slaves         = omap3xxx_mcbsp1_slaves,
2199         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2200         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2201 };
2202
2203 /* mcbsp2 */
2204 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2205         { .name = "irq", .irq = 17 },
2206         { .name = "tx", .irq = 62 },
2207         { .name = "rx", .irq = 63 },
2208         { .irq = -1 }
2209 };
2210
2211 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2212         {
2213                 .name           = "mpu",
2214                 .pa_start       = 0x49022000,
2215                 .pa_end         = 0x490220ff,
2216                 .flags          = ADDR_TYPE_RT
2217         },
2218         { }
2219 };
2220
2221 /* l4_per -> mcbsp2 */
2222 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2223         .master         = &omap3xxx_l4_per_hwmod,
2224         .slave          = &omap3xxx_mcbsp2_hwmod,
2225         .clk            = "mcbsp2_ick",
2226         .addr           = omap3xxx_mcbsp2_addrs,
2227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2228 };
2229
2230 /* mcbsp2 slave ports */
2231 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2232         &omap3xxx_l4_per__mcbsp2,
2233 };
2234
2235 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2236         .sidetone       = "mcbsp2_sidetone",
2237 };
2238
2239 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2240         .name           = "mcbsp2",
2241         .class          = &omap3xxx_mcbsp_hwmod_class,
2242         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2243         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
2244         .main_clk       = "mcbsp2_fck",
2245         .prcm           = {
2246                 .omap2 = {
2247                         .prcm_reg_id = 1,
2248                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2249                         .module_offs = OMAP3430_PER_MOD,
2250                         .idlest_reg_id = 1,
2251                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2252                 },
2253         },
2254         .slaves         = omap3xxx_mcbsp2_slaves,
2255         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2256         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2257         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2258 };
2259
2260 /* mcbsp3 */
2261 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2262         { .name = "irq", .irq = 22 },
2263         { .name = "tx", .irq = 89 },
2264         { .name = "rx", .irq = 90 },
2265         { .irq = -1 }
2266 };
2267
2268 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2269         {
2270                 .name           = "mpu",
2271                 .pa_start       = 0x49024000,
2272                 .pa_end         = 0x490240ff,
2273                 .flags          = ADDR_TYPE_RT
2274         },
2275         { }
2276 };
2277
2278 /* l4_per -> mcbsp3 */
2279 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2280         .master         = &omap3xxx_l4_per_hwmod,
2281         .slave          = &omap3xxx_mcbsp3_hwmod,
2282         .clk            = "mcbsp3_ick",
2283         .addr           = omap3xxx_mcbsp3_addrs,
2284         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2285 };
2286
2287 /* mcbsp3 slave ports */
2288 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2289         &omap3xxx_l4_per__mcbsp3,
2290 };
2291
2292 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2293         .sidetone       = "mcbsp3_sidetone",
2294 };
2295
2296 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2297         .name           = "mcbsp3",
2298         .class          = &omap3xxx_mcbsp_hwmod_class,
2299         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2300         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
2301         .main_clk       = "mcbsp3_fck",
2302         .prcm           = {
2303                 .omap2 = {
2304                         .prcm_reg_id = 1,
2305                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2306                         .module_offs = OMAP3430_PER_MOD,
2307                         .idlest_reg_id = 1,
2308                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2309                 },
2310         },
2311         .slaves         = omap3xxx_mcbsp3_slaves,
2312         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2313         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2314         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2315 };
2316
2317 /* mcbsp4 */
2318 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2319         { .name = "irq", .irq = 23 },
2320         { .name = "tx", .irq = 54 },
2321         { .name = "rx", .irq = 55 },
2322         { .irq = -1 }
2323 };
2324
2325 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2326         { .name = "rx", .dma_req = 20 },
2327         { .name = "tx", .dma_req = 19 },
2328         { .dma_req = -1 }
2329 };
2330
2331 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2332         {
2333                 .name           = "mpu",
2334                 .pa_start       = 0x49026000,
2335                 .pa_end         = 0x490260ff,
2336                 .flags          = ADDR_TYPE_RT
2337         },
2338         { }
2339 };
2340
2341 /* l4_per -> mcbsp4 */
2342 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2343         .master         = &omap3xxx_l4_per_hwmod,
2344         .slave          = &omap3xxx_mcbsp4_hwmod,
2345         .clk            = "mcbsp4_ick",
2346         .addr           = omap3xxx_mcbsp4_addrs,
2347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2348 };
2349
2350 /* mcbsp4 slave ports */
2351 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2352         &omap3xxx_l4_per__mcbsp4,
2353 };
2354
2355 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2356         .name           = "mcbsp4",
2357         .class          = &omap3xxx_mcbsp_hwmod_class,
2358         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2359         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2360         .main_clk       = "mcbsp4_fck",
2361         .prcm           = {
2362                 .omap2 = {
2363                         .prcm_reg_id = 1,
2364                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2365                         .module_offs = OMAP3430_PER_MOD,
2366                         .idlest_reg_id = 1,
2367                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2368                 },
2369         },
2370         .slaves         = omap3xxx_mcbsp4_slaves,
2371         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2372         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2373 };
2374
2375 /* mcbsp5 */
2376 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2377         { .name = "irq", .irq = 27 },
2378         { .name = "tx", .irq = 81 },
2379         { .name = "rx", .irq = 82 },
2380         { .irq = -1 }
2381 };
2382
2383 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2384         { .name = "rx", .dma_req = 22 },
2385         { .name = "tx", .dma_req = 21 },
2386         { .dma_req = -1 }
2387 };
2388
2389 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2390         {
2391                 .name           = "mpu",
2392                 .pa_start       = 0x48096000,
2393                 .pa_end         = 0x480960ff,
2394                 .flags          = ADDR_TYPE_RT
2395         },
2396         { }
2397 };
2398
2399 /* l4_core -> mcbsp5 */
2400 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2401         .master         = &omap3xxx_l4_core_hwmod,
2402         .slave          = &omap3xxx_mcbsp5_hwmod,
2403         .clk            = "mcbsp5_ick",
2404         .addr           = omap3xxx_mcbsp5_addrs,
2405         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2406 };
2407
2408 /* mcbsp5 slave ports */
2409 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2410         &omap3xxx_l4_core__mcbsp5,
2411 };
2412
2413 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2414         .name           = "mcbsp5",
2415         .class          = &omap3xxx_mcbsp_hwmod_class,
2416         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2417         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2418         .main_clk       = "mcbsp5_fck",
2419         .prcm           = {
2420                 .omap2 = {
2421                         .prcm_reg_id = 1,
2422                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2423                         .module_offs = CORE_MOD,
2424                         .idlest_reg_id = 1,
2425                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2426                 },
2427         },
2428         .slaves         = omap3xxx_mcbsp5_slaves,
2429         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2430         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2431 };
2432 /* 'mcbsp sidetone' class */
2433
2434 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2435         .sysc_offs      = 0x0010,
2436         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2437         .sysc_fields    = &omap_hwmod_sysc_type1,
2438 };
2439
2440 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2441         .name = "mcbsp_sidetone",
2442         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2443 };
2444
2445 /* mcbsp2_sidetone */
2446 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2447         { .name = "irq", .irq = 4 },
2448         { .irq = -1 }
2449 };
2450
2451 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2452         {
2453                 .name           = "sidetone",
2454                 .pa_start       = 0x49028000,
2455                 .pa_end         = 0x490280ff,
2456                 .flags          = ADDR_TYPE_RT
2457         },
2458         { }
2459 };
2460
2461 /* l4_per -> mcbsp2_sidetone */
2462 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2463         .master         = &omap3xxx_l4_per_hwmod,
2464         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2465         .clk            = "mcbsp2_ick",
2466         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2467         .user           = OCP_USER_MPU,
2468 };
2469
2470 /* mcbsp2_sidetone slave ports */
2471 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2472         &omap3xxx_l4_per__mcbsp2_sidetone,
2473 };
2474
2475 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2476         .name           = "mcbsp2_sidetone",
2477         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2478         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2479         .main_clk       = "mcbsp2_fck",
2480         .prcm           = {
2481                 .omap2 = {
2482                         .prcm_reg_id = 1,
2483                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2484                         .module_offs = OMAP3430_PER_MOD,
2485                         .idlest_reg_id = 1,
2486                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2487                 },
2488         },
2489         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2490         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2491         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2492 };
2493
2494 /* mcbsp3_sidetone */
2495 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2496         { .name = "irq", .irq = 5 },
2497         { .irq = -1 }
2498 };
2499
2500 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2501         {
2502                 .name           = "sidetone",
2503                 .pa_start       = 0x4902A000,
2504                 .pa_end         = 0x4902A0ff,
2505                 .flags          = ADDR_TYPE_RT
2506         },
2507         { }
2508 };
2509
2510 /* l4_per -> mcbsp3_sidetone */
2511 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2512         .master         = &omap3xxx_l4_per_hwmod,
2513         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2514         .clk            = "mcbsp3_ick",
2515         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2516         .user           = OCP_USER_MPU,
2517 };
2518
2519 /* mcbsp3_sidetone slave ports */
2520 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2521         &omap3xxx_l4_per__mcbsp3_sidetone,
2522 };
2523
2524 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2525         .name           = "mcbsp3_sidetone",
2526         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2527         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2528         .main_clk       = "mcbsp3_fck",
2529         .prcm           = {
2530                 .omap2 = {
2531                         .prcm_reg_id = 1,
2532                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2533                         .module_offs = OMAP3430_PER_MOD,
2534                         .idlest_reg_id = 1,
2535                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2536                 },
2537         },
2538         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2539         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2540         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2541 };
2542
2543
2544 /* SR common */
2545 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2546         .clkact_shift   = 20,
2547 };
2548
2549 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2550         .sysc_offs      = 0x24,
2551         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2552         .clockact       = CLOCKACT_TEST_ICLK,
2553         .sysc_fields    = &omap34xx_sr_sysc_fields,
2554 };
2555
2556 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2557         .name = "smartreflex",
2558         .sysc = &omap34xx_sr_sysc,
2559         .rev  = 1,
2560 };
2561
2562 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2563         .sidle_shift    = 24,
2564         .enwkup_shift   = 26
2565 };
2566
2567 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2568         .sysc_offs      = 0x38,
2569         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2570         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2571                         SYSC_NO_CACHE),
2572         .sysc_fields    = &omap36xx_sr_sysc_fields,
2573 };
2574
2575 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2576         .name = "smartreflex",
2577         .sysc = &omap36xx_sr_sysc,
2578         .rev  = 2,
2579 };
2580
2581 /* SR1 */
2582 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2583         &omap3_l4_core__sr1,
2584 };
2585
2586 static struct omap_hwmod omap34xx_sr1_hwmod = {
2587         .name           = "sr1_hwmod",
2588         .class          = &omap34xx_smartreflex_hwmod_class,
2589         .main_clk       = "sr1_fck",
2590         .vdd_name       = "mpu",
2591         .prcm           = {
2592                 .omap2 = {
2593                         .prcm_reg_id = 1,
2594                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2595                         .module_offs = WKUP_MOD,
2596                         .idlest_reg_id = 1,
2597                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2598                 },
2599         },
2600         .slaves         = omap3_sr1_slaves,
2601         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2602         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2603                                         CHIP_IS_OMAP3430ES3_0 |
2604                                         CHIP_IS_OMAP3430ES3_1),
2605         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2606 };
2607
2608 static struct omap_hwmod omap36xx_sr1_hwmod = {
2609         .name           = "sr1_hwmod",
2610         .class          = &omap36xx_smartreflex_hwmod_class,
2611         .main_clk       = "sr1_fck",
2612         .vdd_name       = "mpu",
2613         .prcm           = {
2614                 .omap2 = {
2615                         .prcm_reg_id = 1,
2616                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2617                         .module_offs = WKUP_MOD,
2618                         .idlest_reg_id = 1,
2619                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2620                 },
2621         },
2622         .slaves         = omap3_sr1_slaves,
2623         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2624         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2625 };
2626
2627 /* SR2 */
2628 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2629         &omap3_l4_core__sr2,
2630 };
2631
2632 static struct omap_hwmod omap34xx_sr2_hwmod = {
2633         .name           = "sr2_hwmod",
2634         .class          = &omap34xx_smartreflex_hwmod_class,
2635         .main_clk       = "sr2_fck",
2636         .vdd_name       = "core",
2637         .prcm           = {
2638                 .omap2 = {
2639                         .prcm_reg_id = 1,
2640                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2641                         .module_offs = WKUP_MOD,
2642                         .idlest_reg_id = 1,
2643                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2644                 },
2645         },
2646         .slaves         = omap3_sr2_slaves,
2647         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2648         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2649                                         CHIP_IS_OMAP3430ES3_0 |
2650                                         CHIP_IS_OMAP3430ES3_1),
2651         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2652 };
2653
2654 static struct omap_hwmod omap36xx_sr2_hwmod = {
2655         .name           = "sr2_hwmod",
2656         .class          = &omap36xx_smartreflex_hwmod_class,
2657         .main_clk       = "sr2_fck",
2658         .vdd_name       = "core",
2659         .prcm           = {
2660                 .omap2 = {
2661                         .prcm_reg_id = 1,
2662                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2663                         .module_offs = WKUP_MOD,
2664                         .idlest_reg_id = 1,
2665                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2666                 },
2667         },
2668         .slaves         = omap3_sr2_slaves,
2669         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2670         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2671 };
2672
2673 /*
2674  * 'mailbox' class
2675  * mailbox module allowing communication between the on-chip processors
2676  * using a queued mailbox-interrupt mechanism.
2677  */
2678
2679 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2680         .rev_offs       = 0x000,
2681         .sysc_offs      = 0x010,
2682         .syss_offs      = 0x014,
2683         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2684                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2685         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2686         .sysc_fields    = &omap_hwmod_sysc_type1,
2687 };
2688
2689 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2690         .name = "mailbox",
2691         .sysc = &omap3xxx_mailbox_sysc,
2692 };
2693
2694 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2695 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2696         { .irq = 26 },
2697         { .irq = -1 }
2698 };
2699
2700 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2701         {
2702                 .pa_start       = 0x48094000,
2703                 .pa_end         = 0x480941ff,
2704                 .flags          = ADDR_TYPE_RT,
2705         },
2706         { }
2707 };
2708
2709 /* l4_core -> mailbox */
2710 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2711         .master         = &omap3xxx_l4_core_hwmod,
2712         .slave          = &omap3xxx_mailbox_hwmod,
2713         .addr           = omap3xxx_mailbox_addrs,
2714         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2715 };
2716
2717 /* mailbox slave ports */
2718 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2719         &omap3xxx_l4_core__mailbox,
2720 };
2721
2722 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2723         .name           = "mailbox",
2724         .class          = &omap3xxx_mailbox_hwmod_class,
2725         .mpu_irqs       = omap3xxx_mailbox_irqs,
2726         .main_clk       = "mailboxes_ick",
2727         .prcm           = {
2728                 .omap2 = {
2729                         .prcm_reg_id = 1,
2730                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2731                         .module_offs = CORE_MOD,
2732                         .idlest_reg_id = 1,
2733                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2734                 },
2735         },
2736         .slaves         = omap3xxx_mailbox_slaves,
2737         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2738         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2739 };
2740
2741 /* l4 core -> mcspi1 interface */
2742 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2743         .master         = &omap3xxx_l4_core_hwmod,
2744         .slave          = &omap34xx_mcspi1,
2745         .clk            = "mcspi1_ick",
2746         .addr           = omap2_mcspi1_addr_space,
2747         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2748 };
2749
2750 /* l4 core -> mcspi2 interface */
2751 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2752         .master         = &omap3xxx_l4_core_hwmod,
2753         .slave          = &omap34xx_mcspi2,
2754         .clk            = "mcspi2_ick",
2755         .addr           = omap2_mcspi2_addr_space,
2756         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2757 };
2758
2759 /* l4 core -> mcspi3 interface */
2760 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2761         .master         = &omap3xxx_l4_core_hwmod,
2762         .slave          = &omap34xx_mcspi3,
2763         .clk            = "mcspi3_ick",
2764         .addr           = omap2430_mcspi3_addr_space,
2765         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2766 };
2767
2768 /* l4 core -> mcspi4 interface */
2769 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2770         {
2771                 .pa_start       = 0x480ba000,
2772                 .pa_end         = 0x480ba0ff,
2773                 .flags          = ADDR_TYPE_RT,
2774         },
2775         { }
2776 };
2777
2778 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2779         .master         = &omap3xxx_l4_core_hwmod,
2780         .slave          = &omap34xx_mcspi4,
2781         .clk            = "mcspi4_ick",
2782         .addr           = omap34xx_mcspi4_addr_space,
2783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2784 };
2785
2786 /*
2787  * 'mcspi' class
2788  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2789  * bus
2790  */
2791
2792 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2793         .rev_offs       = 0x0000,
2794         .sysc_offs      = 0x0010,
2795         .syss_offs      = 0x0014,
2796         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2797                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2798                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2799         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2800         .sysc_fields    = &omap_hwmod_sysc_type1,
2801 };
2802
2803 static struct omap_hwmod_class omap34xx_mcspi_class = {
2804         .name = "mcspi",
2805         .sysc = &omap34xx_mcspi_sysc,
2806         .rev = OMAP3_MCSPI_REV,
2807 };
2808
2809 /* mcspi1 */
2810 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2811         &omap34xx_l4_core__mcspi1,
2812 };
2813
2814 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2815         .num_chipselect = 4,
2816 };
2817
2818 static struct omap_hwmod omap34xx_mcspi1 = {
2819         .name           = "mcspi1",
2820         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
2821         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
2822         .main_clk       = "mcspi1_fck",
2823         .prcm           = {
2824                 .omap2 = {
2825                         .module_offs = CORE_MOD,
2826                         .prcm_reg_id = 1,
2827                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2828                         .idlest_reg_id = 1,
2829                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2830                 },
2831         },
2832         .slaves         = omap34xx_mcspi1_slaves,
2833         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2834         .class          = &omap34xx_mcspi_class,
2835         .dev_attr       = &omap_mcspi1_dev_attr,
2836         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2837 };
2838
2839 /* mcspi2 */
2840 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2841         &omap34xx_l4_core__mcspi2,
2842 };
2843
2844 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2845         .num_chipselect = 2,
2846 };
2847
2848 static struct omap_hwmod omap34xx_mcspi2 = {
2849         .name           = "mcspi2",
2850         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
2851         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
2852         .main_clk       = "mcspi2_fck",
2853         .prcm           = {
2854                 .omap2 = {
2855                         .module_offs = CORE_MOD,
2856                         .prcm_reg_id = 1,
2857                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2858                         .idlest_reg_id = 1,
2859                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2860                 },
2861         },
2862         .slaves         = omap34xx_mcspi2_slaves,
2863         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2864         .class          = &omap34xx_mcspi_class,
2865         .dev_attr       = &omap_mcspi2_dev_attr,
2866         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2867 };
2868
2869 /* mcspi3 */
2870 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2871         { .name = "irq", .irq = 91 }, /* 91 */
2872         { .irq = -1 }
2873 };
2874
2875 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2876         { .name = "tx0", .dma_req = 15 },
2877         { .name = "rx0", .dma_req = 16 },
2878         { .name = "tx1", .dma_req = 23 },
2879         { .name = "rx1", .dma_req = 24 },
2880         { .dma_req = -1 }
2881 };
2882
2883 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2884         &omap34xx_l4_core__mcspi3,
2885 };
2886
2887 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2888         .num_chipselect = 2,
2889 };
2890
2891 static struct omap_hwmod omap34xx_mcspi3 = {
2892         .name           = "mcspi3",
2893         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
2894         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
2895         .main_clk       = "mcspi3_fck",
2896         .prcm           = {
2897                 .omap2 = {
2898                         .module_offs = CORE_MOD,
2899                         .prcm_reg_id = 1,
2900                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2901                         .idlest_reg_id = 1,
2902                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2903                 },
2904         },
2905         .slaves         = omap34xx_mcspi3_slaves,
2906         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2907         .class          = &omap34xx_mcspi_class,
2908         .dev_attr       = &omap_mcspi3_dev_attr,
2909         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2910 };
2911
2912 /* SPI4 */
2913 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2914         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2915         { .irq = -1 }
2916 };
2917
2918 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2919         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2920         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2921         { .dma_req = -1 }
2922 };
2923
2924 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2925         &omap34xx_l4_core__mcspi4,
2926 };
2927
2928 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2929         .num_chipselect = 1,
2930 };
2931
2932 static struct omap_hwmod omap34xx_mcspi4 = {
2933         .name           = "mcspi4",
2934         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
2935         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
2936         .main_clk       = "mcspi4_fck",
2937         .prcm           = {
2938                 .omap2 = {
2939                         .module_offs = CORE_MOD,
2940                         .prcm_reg_id = 1,
2941                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2942                         .idlest_reg_id = 1,
2943                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2944                 },
2945         },
2946         .slaves         = omap34xx_mcspi4_slaves,
2947         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2948         .class          = &omap34xx_mcspi_class,
2949         .dev_attr       = &omap_mcspi4_dev_attr,
2950         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2951 };
2952
2953 /*
2954  * usbhsotg
2955  */
2956 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2957         .rev_offs       = 0x0400,
2958         .sysc_offs      = 0x0404,
2959         .syss_offs      = 0x0408,
2960         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2961                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2962                           SYSC_HAS_AUTOIDLE),
2963         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2964                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2965         .sysc_fields    = &omap_hwmod_sysc_type1,
2966 };
2967
2968 static struct omap_hwmod_class usbotg_class = {
2969         .name = "usbotg",
2970         .sysc = &omap3xxx_usbhsotg_sysc,
2971 };
2972 /* usb_otg_hs */
2973 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2974
2975         { .name = "mc", .irq = 92 },
2976         { .name = "dma", .irq = 93 },
2977         { .irq = -1 }
2978 };
2979
2980 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
2981         .name           = "usb_otg_hs",
2982         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
2983         .main_clk       = "hsotgusb_ick",
2984         .prcm           = {
2985                 .omap2 = {
2986                         .prcm_reg_id = 1,
2987                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
2988                         .module_offs = CORE_MOD,
2989                         .idlest_reg_id = 1,
2990                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
2991                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
2992                 },
2993         },
2994         .masters        = omap3xxx_usbhsotg_masters,
2995         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
2996         .slaves         = omap3xxx_usbhsotg_slaves,
2997         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
2998         .class          = &usbotg_class,
2999
3000         /*
3001          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
3002          * broken when autoidle is enabled
3003          * workaround is to disable the autoidle bit at module level.
3004          */
3005         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3006                                 | HWMOD_SWSUP_MSTANDBY,
3007         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3008 };
3009
3010 /* usb_otg_hs */
3011 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3012
3013         { .name = "mc", .irq = 71 },
3014         { .irq = -1 }
3015 };
3016
3017 static struct omap_hwmod_class am35xx_usbotg_class = {
3018         .name = "am35xx_usbotg",
3019         .sysc = NULL,
3020 };
3021
3022 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3023         .name           = "am35x_otg_hs",
3024         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3025         .main_clk       = NULL,
3026         .prcm = {
3027                 .omap2 = {
3028                 },
3029         },
3030         .masters        = am35xx_usbhsotg_masters,
3031         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3032         .slaves         = am35xx_usbhsotg_slaves,
3033         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3034         .class          = &am35xx_usbotg_class,
3035         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3036 };
3037
3038 /* MMC/SD/SDIO common */
3039
3040 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3041         .rev_offs       = 0x1fc,
3042         .sysc_offs      = 0x10,
3043         .syss_offs      = 0x14,
3044         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3045                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3046                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3047         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3048         .sysc_fields    = &omap_hwmod_sysc_type1,
3049 };
3050
3051 static struct omap_hwmod_class omap34xx_mmc_class = {
3052         .name = "mmc",
3053         .sysc = &omap34xx_mmc_sysc,
3054 };
3055
3056 /* MMC/SD/SDIO1 */
3057
3058 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3059         { .irq = 83, },
3060         { .irq = -1 }
3061 };
3062
3063 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3064         { .name = "tx", .dma_req = 61, },
3065         { .name = "rx", .dma_req = 62, },
3066         { .dma_req = -1 }
3067 };
3068
3069 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3070         { .role = "dbck", .clk = "omap_32k_fck", },
3071 };
3072
3073 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3074         &omap3xxx_l4_core__mmc1,
3075 };
3076
3077 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3078         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3079 };
3080
3081 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3082         .name           = "mmc1",
3083         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3084         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3085         .opt_clks       = omap34xx_mmc1_opt_clks,
3086         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3087         .main_clk       = "mmchs1_fck",
3088         .prcm           = {
3089                 .omap2 = {
3090                         .module_offs = CORE_MOD,
3091                         .prcm_reg_id = 1,
3092                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3093                         .idlest_reg_id = 1,
3094                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3095                 },
3096         },
3097         .dev_attr       = &mmc1_dev_attr,
3098         .slaves         = omap3xxx_mmc1_slaves,
3099         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3100         .class          = &omap34xx_mmc_class,
3101         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3102 };
3103
3104 /* MMC/SD/SDIO2 */
3105
3106 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3107         { .irq = INT_24XX_MMC2_IRQ, },
3108         { .irq = -1 }
3109 };
3110
3111 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3112         { .name = "tx", .dma_req = 47, },
3113         { .name = "rx", .dma_req = 48, },
3114         { .dma_req = -1 }
3115 };
3116
3117 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3118         { .role = "dbck", .clk = "omap_32k_fck", },
3119 };
3120
3121 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3122         &omap3xxx_l4_core__mmc2,
3123 };
3124
3125 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3126         .name           = "mmc2",
3127         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3128         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3129         .opt_clks       = omap34xx_mmc2_opt_clks,
3130         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3131         .main_clk       = "mmchs2_fck",
3132         .prcm           = {
3133                 .omap2 = {
3134                         .module_offs = CORE_MOD,
3135                         .prcm_reg_id = 1,
3136                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3137                         .idlest_reg_id = 1,
3138                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3139                 },
3140         },
3141         .slaves         = omap3xxx_mmc2_slaves,
3142         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3143         .class          = &omap34xx_mmc_class,
3144         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3145 };
3146
3147 /* MMC/SD/SDIO3 */
3148
3149 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3150         { .irq = 94, },
3151         { .irq = -1 }
3152 };
3153
3154 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3155         { .name = "tx", .dma_req = 77, },
3156         { .name = "rx", .dma_req = 78, },
3157         { .dma_req = -1 }
3158 };
3159
3160 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3161         { .role = "dbck", .clk = "omap_32k_fck", },
3162 };
3163
3164 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3165         &omap3xxx_l4_core__mmc3,
3166 };
3167
3168 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3169         .name           = "mmc3",
3170         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3171         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3172         .opt_clks       = omap34xx_mmc3_opt_clks,
3173         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3174         .main_clk       = "mmchs3_fck",
3175         .prcm           = {
3176                 .omap2 = {
3177                         .prcm_reg_id = 1,
3178                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3179                         .idlest_reg_id = 1,
3180                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3181                 },
3182         },
3183         .slaves         = omap3xxx_mmc3_slaves,
3184         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3185         .class          = &omap34xx_mmc_class,
3186         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3187 };
3188
3189 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3190         &omap3xxx_l3_main_hwmod,
3191         &omap3xxx_l4_core_hwmod,
3192         &omap3xxx_l4_per_hwmod,
3193         &omap3xxx_l4_wkup_hwmod,
3194         &omap3xxx_mmc1_hwmod,
3195         &omap3xxx_mmc2_hwmod,
3196         &omap3xxx_mmc3_hwmod,
3197         &omap3xxx_mpu_hwmod,
3198         &omap3xxx_iva_hwmod,
3199
3200         &omap3xxx_timer1_hwmod,
3201         &omap3xxx_timer2_hwmod,
3202         &omap3xxx_timer3_hwmod,
3203         &omap3xxx_timer4_hwmod,
3204         &omap3xxx_timer5_hwmod,
3205         &omap3xxx_timer6_hwmod,
3206         &omap3xxx_timer7_hwmod,
3207         &omap3xxx_timer8_hwmod,
3208         &omap3xxx_timer9_hwmod,
3209         &omap3xxx_timer10_hwmod,
3210         &omap3xxx_timer11_hwmod,
3211         &omap3xxx_timer12_hwmod,
3212
3213         &omap3xxx_wd_timer2_hwmod,
3214         &omap3xxx_uart1_hwmod,
3215         &omap3xxx_uart2_hwmod,
3216         &omap3xxx_uart3_hwmod,
3217         &omap3xxx_uart4_hwmod,
3218         /* dss class */
3219         &omap3430es1_dss_core_hwmod,
3220         &omap3xxx_dss_core_hwmod,
3221         &omap3xxx_dss_dispc_hwmod,
3222         &omap3xxx_dss_dsi1_hwmod,
3223         &omap3xxx_dss_rfbi_hwmod,
3224         &omap3xxx_dss_venc_hwmod,
3225
3226         /* i2c class */
3227         &omap3xxx_i2c1_hwmod,
3228         &omap3xxx_i2c2_hwmod,
3229         &omap3xxx_i2c3_hwmod,
3230         &omap34xx_sr1_hwmod,
3231         &omap34xx_sr2_hwmod,
3232         &omap36xx_sr1_hwmod,
3233         &omap36xx_sr2_hwmod,
3234
3235
3236         /* gpio class */
3237         &omap3xxx_gpio1_hwmod,
3238         &omap3xxx_gpio2_hwmod,
3239         &omap3xxx_gpio3_hwmod,
3240         &omap3xxx_gpio4_hwmod,
3241         &omap3xxx_gpio5_hwmod,
3242         &omap3xxx_gpio6_hwmod,
3243
3244         /* dma_system class*/
3245         &omap3xxx_dma_system_hwmod,
3246
3247         /* mcbsp class */
3248         &omap3xxx_mcbsp1_hwmod,
3249         &omap3xxx_mcbsp2_hwmod,
3250         &omap3xxx_mcbsp3_hwmod,
3251         &omap3xxx_mcbsp4_hwmod,
3252         &omap3xxx_mcbsp5_hwmod,
3253         &omap3xxx_mcbsp2_sidetone_hwmod,
3254         &omap3xxx_mcbsp3_sidetone_hwmod,
3255
3256         /* mailbox class */
3257         &omap3xxx_mailbox_hwmod,
3258
3259         /* mcspi class */
3260         &omap34xx_mcspi1,
3261         &omap34xx_mcspi2,
3262         &omap34xx_mcspi3,
3263         &omap34xx_mcspi4,
3264
3265         /* usbotg class */
3266         &omap3xxx_usbhsotg_hwmod,
3267
3268         /* usbotg for am35x */
3269         &am35xx_usbhsotg_hwmod,
3270
3271         NULL,
3272 };
3273
3274 int __init omap3xxx_hwmod_init(void)
3275 {
3276         return omap_hwmod_register(omap3xxx_hwmods);
3277 }