arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "smartreflex.h"
  33 #include "prm-regbits-34xx.h"
  34 #include "cm-regbits-34xx.h"
  35 #include "wd_timer.h"
  36 #include <mach/am35xx.h>
  37
  38 /*
  39  * OMAP3xxx hardware module integration data
  40  *
  41  * ALl of the data in this section should be autogeneratable from the
  42  * TI hardware database or other technical documentation.  Data that
  43  * is driver-specific or driver-kernel integration-specific belongs
  44  * elsewhere.
  45  */
  46
  47 static struct omap_hwmod omap3xxx_mpu_hwmod;
  48 static struct omap_hwmod omap3xxx_iva_hwmod;
  49 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  51 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  52 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  53 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  58 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  61 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  67 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  68 static struct omap_hwmod omap34xx_sr1_hwmod;
  69 static struct omap_hwmod omap34xx_sr2_hwmod;
  70 static struct omap_hwmod omap34xx_mcspi1;
  71 static struct omap_hwmod omap34xx_mcspi2;
  72 static struct omap_hwmod omap34xx_mcspi3;
  73 static struct omap_hwmod omap34xx_mcspi4;
  74 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  75 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  76 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  77 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  78
  79 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  80
  81 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  83 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  87 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  88
  89 /* L3 -> L4_CORE interface */
  90 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  91         .master = &omap3xxx_l3_main_hwmod,
  92         .slave  = &omap3xxx_l4_core_hwmod,
  93         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  94 };
  95
  96 /* L3 -> L4_PER interface */
  97 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  98         .master = &omap3xxx_l3_main_hwmod,
  99         .slave  = &omap3xxx_l4_per_hwmod,
 100         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 101 };
 102
 103 /* L3 taret configuration and error log registers */
 104 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 105         { .irq = INT_34XX_L3_DBG_IRQ },
 106         { .irq = INT_34XX_L3_APP_IRQ },
 107         { .irq = -1 }
 108 };
 109
 110 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 111         {
 112                 .pa_start       = 0x68000000,
 113                 .pa_end         = 0x6800ffff,
 114                 .flags          = ADDR_TYPE_RT,
 115         },
 116         { }
 117 };
 118
 119 /* MPU -> L3 interface */
 120 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 121         .master   = &omap3xxx_mpu_hwmod,
 122         .slave    = &omap3xxx_l3_main_hwmod,
 123         .addr     = omap3xxx_l3_main_addrs,
 124         .user   = OCP_USER_MPU,
 125 };
 126
 127 /* Slave interfaces on the L3 interconnect */
 128 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 129         &omap3xxx_mpu__l3_main,
 130 };
 131
 132 /* DSS -> l3 */
 133 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 134         .master         = &omap3xxx_dss_core_hwmod,
 135         .slave          = &omap3xxx_l3_main_hwmod,
 136         .fw = {
 137                 .omap2 = {
 138                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 139                         .flags  = OMAP_FIREWALL_L3,
 140                 }
 141         },
 142         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 143 };
 144
 145 /* Master interfaces on the L3 interconnect */
 146 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 147         &omap3xxx_l3_main__l4_core,
 148         &omap3xxx_l3_main__l4_per,
 149 };
 150
 151 /* L3 */
 152 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 153         .name           = "l3_main",
 154         .class          = &l3_hwmod_class,
 155         .mpu_irqs       = omap3xxx_l3_main_irqs,
 156         .masters        = omap3xxx_l3_main_masters,
 157         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 158         .slaves         = omap3xxx_l3_main_slaves,
 159         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 160         .flags          = HWMOD_NO_IDLEST,
 161 };
 162
 163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 164 static struct omap_hwmod omap3xxx_uart1_hwmod;
 165 static struct omap_hwmod omap3xxx_uart2_hwmod;
 166 static struct omap_hwmod omap3xxx_uart3_hwmod;
 167 static struct omap_hwmod omap3xxx_uart4_hwmod;
 168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 169
 170 /* l3_core -> usbhsotg interface */
 171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 172         .master         = &omap3xxx_usbhsotg_hwmod,
 173         .slave          = &omap3xxx_l3_main_hwmod,
 174         .clk            = "core_l3_ick",
 175         .user           = OCP_USER_MPU,
 176 };
 177
 178 /* l3_core -> am35xx_usbhsotg interface */
 179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 180         .master         = &am35xx_usbhsotg_hwmod,
 181         .slave          = &omap3xxx_l3_main_hwmod,
 182         .clk            = "core_l3_ick",
 183         .user           = OCP_USER_MPU,
 184 };
 185 /* L4_CORE -> L4_WKUP interface */
 186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 187         .master = &omap3xxx_l4_core_hwmod,
 188         .slave  = &omap3xxx_l4_wkup_hwmod,
 189         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 190 };
 191
 192 /* L4 CORE -> MMC1 interface */
 193 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 194         .master         = &omap3xxx_l4_core_hwmod,
 195         .slave          = &omap3xxx_mmc1_hwmod,
 196         .clk            = "mmchs1_ick",
 197         .addr           = omap2430_mmc1_addr_space,
 198         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 199         .flags          = OMAP_FIREWALL_L4
 200 };
 201
 202 /* L4 CORE -> MMC2 interface */
 203 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 204         .master         = &omap3xxx_l4_core_hwmod,
 205         .slave          = &omap3xxx_mmc2_hwmod,
 206         .clk            = "mmchs2_ick",
 207         .addr           = omap2430_mmc2_addr_space,
 208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 209         .flags          = OMAP_FIREWALL_L4
 210 };
 211
 212 /* L4 CORE -> MMC3 interface */
 213 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 214         {
 215                 .pa_start       = 0x480ad000,
 216                 .pa_end         = 0x480ad1ff,
 217                 .flags          = ADDR_TYPE_RT,
 218         },
 219         { }
 220 };
 221
 222 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 223         .master         = &omap3xxx_l4_core_hwmod,
 224         .slave          = &omap3xxx_mmc3_hwmod,
 225         .clk            = "mmchs3_ick",
 226         .addr           = omap3xxx_mmc3_addr_space,
 227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 228         .flags          = OMAP_FIREWALL_L4
 229 };
 230
 231 /* L4 CORE -> UART1 interface */
 232 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 233         {
 234                 .pa_start       = OMAP3_UART1_BASE,
 235                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 236                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 237         },
 238         { }
 239 };
 240
 241 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 242         .master         = &omap3xxx_l4_core_hwmod,
 243         .slave          = &omap3xxx_uart1_hwmod,
 244         .clk            = "uart1_ick",
 245         .addr           = omap3xxx_uart1_addr_space,
 246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 247 };
 248
 249 /* L4 CORE -> UART2 interface */
 250 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 251         {
 252                 .pa_start       = OMAP3_UART2_BASE,
 253                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 254                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 255         },
 256         { }
 257 };
 258
 259 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 260         .master         = &omap3xxx_l4_core_hwmod,
 261         .slave          = &omap3xxx_uart2_hwmod,
 262         .clk            = "uart2_ick",
 263         .addr           = omap3xxx_uart2_addr_space,
 264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 265 };
 266
 267 /* L4 PER -> UART3 interface */
 268 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 269         {
 270                 .pa_start       = OMAP3_UART3_BASE,
 271                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 272                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 273         },
 274         { }
 275 };
 276
 277 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 278         .master         = &omap3xxx_l4_per_hwmod,
 279         .slave          = &omap3xxx_uart3_hwmod,
 280         .clk            = "uart3_ick",
 281         .addr           = omap3xxx_uart3_addr_space,
 282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 283 };
 284
 285 /* L4 PER -> UART4 interface */
 286 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 287         {
 288                 .pa_start       = OMAP3_UART4_BASE,
 289                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 290                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 291         },
 292         { }
 293 };
 294
 295 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 296         .master         = &omap3xxx_l4_per_hwmod,
 297         .slave          = &omap3xxx_uart4_hwmod,
 298         .clk            = "uart4_ick",
 299         .addr           = omap3xxx_uart4_addr_space,
 300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 301 };
 302
 303 /* L4 CORE -> I2C1 interface */
 304 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 305         .master         = &omap3xxx_l4_core_hwmod,
 306         .slave          = &omap3xxx_i2c1_hwmod,
 307         .clk            = "i2c1_ick",
 308         .addr           = omap2_i2c1_addr_space,
 309         .fw = {
 310                 .omap2 = {
 311                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 312                         .l4_prot_group = 7,
 313                         .flags  = OMAP_FIREWALL_L4,
 314                 }
 315         },
 316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 317 };
 318
 319 /* L4 CORE -> I2C2 interface */
 320 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 321         .master         = &omap3xxx_l4_core_hwmod,
 322         .slave          = &omap3xxx_i2c2_hwmod,
 323         .clk            = "i2c2_ick",
 324         .addr           = omap2_i2c2_addr_space,
 325         .fw = {
 326                 .omap2 = {
 327                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 328                         .l4_prot_group = 7,
 329                         .flags = OMAP_FIREWALL_L4,
 330                 }
 331         },
 332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 333 };
 334
 335 /* L4 CORE -> I2C3 interface */
 336 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 337         {
 338                 .pa_start       = 0x48060000,
 339                 .pa_end         = 0x48060000 + SZ_128 - 1,
 340                 .flags          = ADDR_TYPE_RT,
 341         },
 342         { }
 343 };
 344
 345 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 346         .master         = &omap3xxx_l4_core_hwmod,
 347         .slave          = &omap3xxx_i2c3_hwmod,
 348         .clk            = "i2c3_ick",
 349         .addr           = omap3xxx_i2c3_addr_space,
 350         .fw = {
 351                 .omap2 = {
 352                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 353                         .l4_prot_group = 7,
 354                         .flags = OMAP_FIREWALL_L4,
 355                 }
 356         },
 357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 358 };
 359
 360 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
 361         { .irq = 18},
 362         { .irq = -1 }
 363 };
 364
 365 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
 366         { .irq = 19},
 367         { .irq = -1 }
 368 };
 369
 370 /* L4 CORE -> SR1 interface */
 371 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 372         {
 373                 .pa_start       = OMAP34XX_SR1_BASE,
 374                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 375                 .flags          = ADDR_TYPE_RT,
 376         },
 377         { }
 378 };
 379
 380 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 381         .master         = &omap3xxx_l4_core_hwmod,
 382         .slave          = &omap34xx_sr1_hwmod,
 383         .clk            = "sr_l4_ick",
 384         .addr           = omap3_sr1_addr_space,
 385         .user           = OCP_USER_MPU,
 386 };
 387
 388 /* L4 CORE -> SR1 interface */
 389 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 390         {
 391                 .pa_start       = OMAP34XX_SR2_BASE,
 392                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 393                 .flags          = ADDR_TYPE_RT,
 394         },
 395         { }
 396 };
 397
 398 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 399         .master         = &omap3xxx_l4_core_hwmod,
 400         .slave          = &omap34xx_sr2_hwmod,
 401         .clk            = "sr_l4_ick",
 402         .addr           = omap3_sr2_addr_space,
 403         .user           = OCP_USER_MPU,
 404 };
 405
 406 /*
 407 * usbhsotg interface data
 408 */
 409
 410 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 411         {
 412                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 413                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 414                 .flags          = ADDR_TYPE_RT
 415         },
 416         { }
 417 };
 418
 419 /* l4_core -> usbhsotg  */
 420 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 421         .master         = &omap3xxx_l4_core_hwmod,
 422         .slave          = &omap3xxx_usbhsotg_hwmod,
 423         .clk            = "l4_ick",
 424         .addr           = omap3xxx_usbhsotg_addrs,
 425         .user           = OCP_USER_MPU,
 426 };
 427
 428 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 429         &omap3xxx_usbhsotg__l3,
 430 };
 431
 432 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 433         &omap3xxx_l4_core__usbhsotg,
 434 };
 435
 436 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 437         {
 438                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 439                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 440                 .flags          = ADDR_TYPE_RT
 441         },
 442         { }
 443 };
 444
 445 /* l4_core -> usbhsotg  */
 446 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 447         .master         = &omap3xxx_l4_core_hwmod,
 448         .slave          = &am35xx_usbhsotg_hwmod,
 449         .clk            = "l4_ick",
 450         .addr           = am35xx_usbhsotg_addrs,
 451         .user           = OCP_USER_MPU,
 452 };
 453
 454 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 455         &am35xx_usbhsotg__l3,
 456 };
 457
 458 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 459         &am35xx_l4_core__usbhsotg,
 460 };
 461 /* Slave interfaces on the L4_CORE interconnect */
 462 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 463         &omap3xxx_l3_main__l4_core,
 464 };
 465
 466 /* L4 CORE */
 467 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 468         .name           = "l4_core",
 469         .class          = &l4_hwmod_class,
 470         .slaves         = omap3xxx_l4_core_slaves,
 471         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 472         .flags          = HWMOD_NO_IDLEST,
 473 };
 474
 475 /* Slave interfaces on the L4_PER interconnect */
 476 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 477         &omap3xxx_l3_main__l4_per,
 478 };
 479
 480 /* L4 PER */
 481 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 482         .name           = "l4_per",
 483         .class          = &l4_hwmod_class,
 484         .slaves         = omap3xxx_l4_per_slaves,
 485         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 486         .flags          = HWMOD_NO_IDLEST,
 487 };
 488
 489 /* Slave interfaces on the L4_WKUP interconnect */
 490 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 491         &omap3xxx_l4_core__l4_wkup,
 492 };
 493
 494 /* L4 WKUP */
 495 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 496         .name           = "l4_wkup",
 497         .class          = &l4_hwmod_class,
 498         .slaves         = omap3xxx_l4_wkup_slaves,
 499         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 500         .flags          = HWMOD_NO_IDLEST,
 501 };
 502
 503 /* Master interfaces on the MPU device */
 504 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 505         &omap3xxx_mpu__l3_main,
 506 };
 507
 508 /* MPU */
 509 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 510         .name           = "mpu",
 511         .class          = &mpu_hwmod_class,
 512         .main_clk       = "arm_fck",
 513         .masters        = omap3xxx_mpu_masters,
 514         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 515 };
 516
 517 /*
 518  * IVA2_2 interface data
 519  */
 520
 521 /* IVA2 <- L3 interface */
 522 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 523         .master         = &omap3xxx_l3_main_hwmod,
 524         .slave          = &omap3xxx_iva_hwmod,
 525         .clk            = "iva2_ck",
 526         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 527 };
 528
 529 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 530         &omap3xxx_l3__iva,
 531 };
 532
 533 /*
 534  * IVA2 (IVA2)
 535  */
 536
 537 static struct omap_hwmod omap3xxx_iva_hwmod = {
 538         .name           = "iva",
 539         .class          = &iva_hwmod_class,
 540         .masters        = omap3xxx_iva_masters,
 541         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 542 };
 543
 544 /* timer class */
 545 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 546         .rev_offs       = 0x0000,
 547         .sysc_offs      = 0x0010,
 548         .syss_offs      = 0x0014,
 549         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 550                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 551                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 552         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 553         .sysc_fields    = &omap_hwmod_sysc_type1,
 554 };
 555
 556 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 557         .name = "timer",
 558         .sysc = &omap3xxx_timer_1ms_sysc,
 559         .rev = OMAP_TIMER_IP_VERSION_1,
 560 };
 561
 562 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 563         .rev_offs       = 0x0000,
 564         .sysc_offs      = 0x0010,
 565         .syss_offs      = 0x0014,
 566         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 567                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 568         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 569         .sysc_fields    = &omap_hwmod_sysc_type1,
 570 };
 571
 572 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 573         .name = "timer",
 574         .sysc = &omap3xxx_timer_sysc,
 575         .rev =  OMAP_TIMER_IP_VERSION_1,
 576 };
 577
 578 /* secure timers dev attribute */
 579 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 580         .timer_capability       = OMAP_TIMER_SECURE,
 581 };
 582
 583 /* always-on timers dev attribute */
 584 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 585         .timer_capability       = OMAP_TIMER_ALWON,
 586 };
 587
 588 /* pwm timers dev attribute */
 589 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 590         .timer_capability       = OMAP_TIMER_HAS_PWM,
 591 };
 592
 593 /* timer1 */
 594 static struct omap_hwmod omap3xxx_timer1_hwmod;
 595
 596 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 597         {
 598                 .pa_start       = 0x48318000,
 599                 .pa_end         = 0x48318000 + SZ_1K - 1,
 600                 .flags          = ADDR_TYPE_RT
 601         },
 602         { }
 603 };
 604
 605 /* l4_wkup -> timer1 */
 606 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 607         .master         = &omap3xxx_l4_wkup_hwmod,
 608         .slave          = &omap3xxx_timer1_hwmod,
 609         .clk            = "gpt1_ick",
 610         .addr           = omap3xxx_timer1_addrs,
 611         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 612 };
 613
 614 /* timer1 slave port */
 615 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 616         &omap3xxx_l4_wkup__timer1,
 617 };
 618
 619 /* timer1 hwmod */
 620 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 621         .name           = "timer1",
 622         .mpu_irqs       = omap2_timer1_mpu_irqs,
 623         .main_clk       = "gpt1_fck",
 624         .prcm           = {
 625                 .omap2 = {
 626                         .prcm_reg_id = 1,
 627                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 628                         .module_offs = WKUP_MOD,
 629                         .idlest_reg_id = 1,
 630                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 631                 },
 632         },
 633         .dev_attr       = &capability_alwon_dev_attr,
 634         .slaves         = omap3xxx_timer1_slaves,
 635         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 636         .class          = &omap3xxx_timer_1ms_hwmod_class,
 637 };
 638
 639 /* timer2 */
 640 static struct omap_hwmod omap3xxx_timer2_hwmod;
 641
 642 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 643         {
 644                 .pa_start       = 0x49032000,
 645                 .pa_end         = 0x49032000 + SZ_1K - 1,
 646                 .flags          = ADDR_TYPE_RT
 647         },
 648         { }
 649 };
 650
 651 /* l4_per -> timer2 */
 652 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 653         .master         = &omap3xxx_l4_per_hwmod,
 654         .slave          = &omap3xxx_timer2_hwmod,
 655         .clk            = "gpt2_ick",
 656         .addr           = omap3xxx_timer2_addrs,
 657         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 658 };
 659
 660 /* timer2 slave port */
 661 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 662         &omap3xxx_l4_per__timer2,
 663 };
 664
 665 /* timer2 hwmod */
 666 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 667         .name           = "timer2",
 668         .mpu_irqs       = omap2_timer2_mpu_irqs,
 669         .main_clk       = "gpt2_fck",
 670         .prcm           = {
 671                 .omap2 = {
 672                         .prcm_reg_id = 1,
 673                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 674                         .module_offs = OMAP3430_PER_MOD,
 675                         .idlest_reg_id = 1,
 676                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 677                 },
 678         },
 679         .dev_attr       = &capability_alwon_dev_attr,
 680         .slaves         = omap3xxx_timer2_slaves,
 681         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 682         .class          = &omap3xxx_timer_1ms_hwmod_class,
 683 };
 684
 685 /* timer3 */
 686 static struct omap_hwmod omap3xxx_timer3_hwmod;
 687
 688 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 689         {
 690                 .pa_start       = 0x49034000,
 691                 .pa_end         = 0x49034000 + SZ_1K - 1,
 692                 .flags          = ADDR_TYPE_RT
 693         },
 694         { }
 695 };
 696
 697 /* l4_per -> timer3 */
 698 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 699         .master         = &omap3xxx_l4_per_hwmod,
 700         .slave          = &omap3xxx_timer3_hwmod,
 701         .clk            = "gpt3_ick",
 702         .addr           = omap3xxx_timer3_addrs,
 703         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 704 };
 705
 706 /* timer3 slave port */
 707 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 708         &omap3xxx_l4_per__timer3,
 709 };
 710
 711 /* timer3 hwmod */
 712 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 713         .name           = "timer3",
 714         .mpu_irqs       = omap2_timer3_mpu_irqs,
 715         .main_clk       = "gpt3_fck",
 716         .prcm           = {
 717                 .omap2 = {
 718                         .prcm_reg_id = 1,
 719                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 720                         .module_offs = OMAP3430_PER_MOD,
 721                         .idlest_reg_id = 1,
 722                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 723                 },
 724         },
 725         .dev_attr       = &capability_alwon_dev_attr,
 726         .slaves         = omap3xxx_timer3_slaves,
 727         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 728         .class          = &omap3xxx_timer_hwmod_class,
 729 };
 730
 731 /* timer4 */
 732 static struct omap_hwmod omap3xxx_timer4_hwmod;
 733
 734 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 735         {
 736                 .pa_start       = 0x49036000,
 737                 .pa_end         = 0x49036000 + SZ_1K - 1,
 738                 .flags          = ADDR_TYPE_RT
 739         },
 740         { }
 741 };
 742
 743 /* l4_per -> timer4 */
 744 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 745         .master         = &omap3xxx_l4_per_hwmod,
 746         .slave          = &omap3xxx_timer4_hwmod,
 747         .clk            = "gpt4_ick",
 748         .addr           = omap3xxx_timer4_addrs,
 749         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 750 };
 751
 752 /* timer4 slave port */
 753 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 754         &omap3xxx_l4_per__timer4,
 755 };
 756
 757 /* timer4 hwmod */
 758 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 759         .name           = "timer4",
 760         .mpu_irqs       = omap2_timer4_mpu_irqs,
 761         .main_clk       = "gpt4_fck",
 762         .prcm           = {
 763                 .omap2 = {
 764                         .prcm_reg_id = 1,
 765                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 766                         .module_offs = OMAP3430_PER_MOD,
 767                         .idlest_reg_id = 1,
 768                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 769                 },
 770         },
 771         .dev_attr       = &capability_alwon_dev_attr,
 772         .slaves         = omap3xxx_timer4_slaves,
 773         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 774         .class          = &omap3xxx_timer_hwmod_class,
 775 };
 776
 777 /* timer5 */
 778 static struct omap_hwmod omap3xxx_timer5_hwmod;
 779
 780 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 781         {
 782                 .pa_start       = 0x49038000,
 783                 .pa_end         = 0x49038000 + SZ_1K - 1,
 784                 .flags          = ADDR_TYPE_RT
 785         },
 786         { }
 787 };
 788
 789 /* l4_per -> timer5 */
 790 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 791         .master         = &omap3xxx_l4_per_hwmod,
 792         .slave          = &omap3xxx_timer5_hwmod,
 793         .clk            = "gpt5_ick",
 794         .addr           = omap3xxx_timer5_addrs,
 795         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 796 };
 797
 798 /* timer5 slave port */
 799 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 800         &omap3xxx_l4_per__timer5,
 801 };
 802
 803 /* timer5 hwmod */
 804 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 805         .name           = "timer5",
 806         .mpu_irqs       = omap2_timer5_mpu_irqs,
 807         .main_clk       = "gpt5_fck",
 808         .prcm           = {
 809                 .omap2 = {
 810                         .prcm_reg_id = 1,
 811                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 812                         .module_offs = OMAP3430_PER_MOD,
 813                         .idlest_reg_id = 1,
 814                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 815                 },
 816         },
 817         .dev_attr       = &capability_alwon_dev_attr,
 818         .slaves         = omap3xxx_timer5_slaves,
 819         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 820         .class          = &omap3xxx_timer_hwmod_class,
 821 };
 822
 823 /* timer6 */
 824 static struct omap_hwmod omap3xxx_timer6_hwmod;
 825
 826 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 827         {
 828                 .pa_start       = 0x4903A000,
 829                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 830                 .flags          = ADDR_TYPE_RT
 831         },
 832         { }
 833 };
 834
 835 /* l4_per -> timer6 */
 836 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 837         .master         = &omap3xxx_l4_per_hwmod,
 838         .slave          = &omap3xxx_timer6_hwmod,
 839         .clk            = "gpt6_ick",
 840         .addr           = omap3xxx_timer6_addrs,
 841         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 842 };
 843
 844 /* timer6 slave port */
 845 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 846         &omap3xxx_l4_per__timer6,
 847 };
 848
 849 /* timer6 hwmod */
 850 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 851         .name           = "timer6",
 852         .mpu_irqs       = omap2_timer6_mpu_irqs,
 853         .main_clk       = "gpt6_fck",
 854         .prcm           = {
 855                 .omap2 = {
 856                         .prcm_reg_id = 1,
 857                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 858                         .module_offs = OMAP3430_PER_MOD,
 859                         .idlest_reg_id = 1,
 860                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 861                 },
 862         },
 863         .dev_attr       = &capability_alwon_dev_attr,
 864         .slaves         = omap3xxx_timer6_slaves,
 865         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 866         .class          = &omap3xxx_timer_hwmod_class,
 867 };
 868
 869 /* timer7 */
 870 static struct omap_hwmod omap3xxx_timer7_hwmod;
 871
 872 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 873         {
 874                 .pa_start       = 0x4903C000,
 875                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 876                 .flags          = ADDR_TYPE_RT
 877         },
 878         { }
 879 };
 880
 881 /* l4_per -> timer7 */
 882 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 883         .master         = &omap3xxx_l4_per_hwmod,
 884         .slave          = &omap3xxx_timer7_hwmod,
 885         .clk            = "gpt7_ick",
 886         .addr           = omap3xxx_timer7_addrs,
 887         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 888 };
 889
 890 /* timer7 slave port */
 891 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 892         &omap3xxx_l4_per__timer7,
 893 };
 894
 895 /* timer7 hwmod */
 896 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 897         .name           = "timer7",
 898         .mpu_irqs       = omap2_timer7_mpu_irqs,
 899         .main_clk       = "gpt7_fck",
 900         .prcm           = {
 901                 .omap2 = {
 902                         .prcm_reg_id = 1,
 903                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 904                         .module_offs = OMAP3430_PER_MOD,
 905                         .idlest_reg_id = 1,
 906                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 907                 },
 908         },
 909         .dev_attr       = &capability_alwon_dev_attr,
 910         .slaves         = omap3xxx_timer7_slaves,
 911         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 912         .class          = &omap3xxx_timer_hwmod_class,
 913 };
 914
 915 /* timer8 */
 916 static struct omap_hwmod omap3xxx_timer8_hwmod;
 917
 918 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 919         {
 920                 .pa_start       = 0x4903E000,
 921                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 922                 .flags          = ADDR_TYPE_RT
 923         },
 924         { }
 925 };
 926
 927 /* l4_per -> timer8 */
 928 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 929         .master         = &omap3xxx_l4_per_hwmod,
 930         .slave          = &omap3xxx_timer8_hwmod,
 931         .clk            = "gpt8_ick",
 932         .addr           = omap3xxx_timer8_addrs,
 933         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 934 };
 935
 936 /* timer8 slave port */
 937 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 938         &omap3xxx_l4_per__timer8,
 939 };
 940
 941 /* timer8 hwmod */
 942 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 943         .name           = "timer8",
 944         .mpu_irqs       = omap2_timer8_mpu_irqs,
 945         .main_clk       = "gpt8_fck",
 946         .prcm           = {
 947                 .omap2 = {
 948                         .prcm_reg_id = 1,
 949                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 950                         .module_offs = OMAP3430_PER_MOD,
 951                         .idlest_reg_id = 1,
 952                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 953                 },
 954         },
 955         .dev_attr       = &capability_pwm_dev_attr,
 956         .slaves         = omap3xxx_timer8_slaves,
 957         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
 958         .class          = &omap3xxx_timer_hwmod_class,
 959 };
 960
 961 /* timer9 */
 962 static struct omap_hwmod omap3xxx_timer9_hwmod;
 963
 964 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
 965         {
 966                 .pa_start       = 0x49040000,
 967                 .pa_end         = 0x49040000 + SZ_1K - 1,
 968                 .flags          = ADDR_TYPE_RT
 969         },
 970         { }
 971 };
 972
 973 /* l4_per -> timer9 */
 974 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
 975         .master         = &omap3xxx_l4_per_hwmod,
 976         .slave          = &omap3xxx_timer9_hwmod,
 977         .clk            = "gpt9_ick",
 978         .addr           = omap3xxx_timer9_addrs,
 979         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 980 };
 981
 982 /* timer9 slave port */
 983 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
 984         &omap3xxx_l4_per__timer9,
 985 };
 986
 987 /* timer9 hwmod */
 988 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 989         .name           = "timer9",
 990         .mpu_irqs       = omap2_timer9_mpu_irqs,
 991         .main_clk       = "gpt9_fck",
 992         .prcm           = {
 993                 .omap2 = {
 994                         .prcm_reg_id = 1,
 995                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 996                         .module_offs = OMAP3430_PER_MOD,
 997                         .idlest_reg_id = 1,
 998                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 999                 },
1000         },
1001         .dev_attr       = &capability_pwm_dev_attr,
1002         .slaves         = omap3xxx_timer9_slaves,
1003         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
1004         .class          = &omap3xxx_timer_hwmod_class,
1005 };
1006
1007 /* timer10 */
1008 static struct omap_hwmod omap3xxx_timer10_hwmod;
1009
1010 /* l4_core -> timer10 */
1011 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1012         .master         = &omap3xxx_l4_core_hwmod,
1013         .slave          = &omap3xxx_timer10_hwmod,
1014         .clk            = "gpt10_ick",
1015         .addr           = omap2_timer10_addrs,
1016         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1017 };
1018
1019 /* timer10 slave port */
1020 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1021         &omap3xxx_l4_core__timer10,
1022 };
1023
1024 /* timer10 hwmod */
1025 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1026         .name           = "timer10",
1027         .mpu_irqs       = omap2_timer10_mpu_irqs,
1028         .main_clk       = "gpt10_fck",
1029         .prcm           = {
1030                 .omap2 = {
1031                         .prcm_reg_id = 1,
1032                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1033                         .module_offs = CORE_MOD,
1034                         .idlest_reg_id = 1,
1035                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1036                 },
1037         },
1038         .dev_attr       = &capability_pwm_dev_attr,
1039         .slaves         = omap3xxx_timer10_slaves,
1040         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1041         .class          = &omap3xxx_timer_1ms_hwmod_class,
1042 };
1043
1044 /* timer11 */
1045 static struct omap_hwmod omap3xxx_timer11_hwmod;
1046
1047 /* l4_core -> timer11 */
1048 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1049         .master         = &omap3xxx_l4_core_hwmod,
1050         .slave          = &omap3xxx_timer11_hwmod,
1051         .clk            = "gpt11_ick",
1052         .addr           = omap2_timer11_addrs,
1053         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1054 };
1055
1056 /* timer11 slave port */
1057 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1058         &omap3xxx_l4_core__timer11,
1059 };
1060
1061 /* timer11 hwmod */
1062 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1063         .name           = "timer11",
1064         .mpu_irqs       = omap2_timer11_mpu_irqs,
1065         .main_clk       = "gpt11_fck",
1066         .prcm           = {
1067                 .omap2 = {
1068                         .prcm_reg_id = 1,
1069                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1070                         .module_offs = CORE_MOD,
1071                         .idlest_reg_id = 1,
1072                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1073                 },
1074         },
1075         .dev_attr       = &capability_pwm_dev_attr,
1076         .slaves         = omap3xxx_timer11_slaves,
1077         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1078         .class          = &omap3xxx_timer_hwmod_class,
1079 };
1080
1081 /* timer12 */
1082 static struct omap_hwmod omap3xxx_timer12_hwmod;
1083 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1084         { .irq = 95, },
1085         { .irq = -1 }
1086 };
1087
1088 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1089         {
1090                 .pa_start       = 0x48304000,
1091                 .pa_end         = 0x48304000 + SZ_1K - 1,
1092                 .flags          = ADDR_TYPE_RT
1093         },
1094         { }
1095 };
1096
1097 /* l4_core -> timer12 */
1098 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1099         .master         = &omap3xxx_l4_core_hwmod,
1100         .slave          = &omap3xxx_timer12_hwmod,
1101         .clk            = "gpt12_ick",
1102         .addr           = omap3xxx_timer12_addrs,
1103         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1104 };
1105
1106 /* timer12 slave port */
1107 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1108         &omap3xxx_l4_core__timer12,
1109 };
1110
1111 /* timer12 hwmod */
1112 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1113         .name           = "timer12",
1114         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1115         .main_clk       = "gpt12_fck",
1116         .prcm           = {
1117                 .omap2 = {
1118                         .prcm_reg_id = 1,
1119                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1120                         .module_offs = WKUP_MOD,
1121                         .idlest_reg_id = 1,
1122                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1123                 },
1124         },
1125         .dev_attr       = &capability_secure_dev_attr,
1126         .slaves         = omap3xxx_timer12_slaves,
1127         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1128         .class          = &omap3xxx_timer_hwmod_class,
1129 };
1130
1131 /* l4_wkup -> wd_timer2 */
1132 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1133         {
1134                 .pa_start       = 0x48314000,
1135                 .pa_end         = 0x4831407f,
1136                 .flags          = ADDR_TYPE_RT
1137         },
1138         { }
1139 };
1140
1141 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1142         .master         = &omap3xxx_l4_wkup_hwmod,
1143         .slave          = &omap3xxx_wd_timer2_hwmod,
1144         .clk            = "wdt2_ick",
1145         .addr           = omap3xxx_wd_timer2_addrs,
1146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1147 };
1148
1149 /*
1150  * 'wd_timer' class
1151  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1152  * overflow condition
1153  */
1154
1155 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1156         .rev_offs       = 0x0000,
1157         .sysc_offs      = 0x0010,
1158         .syss_offs      = 0x0014,
1159         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1160                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1161                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1162                            SYSS_HAS_RESET_STATUS),
1163         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1164         .sysc_fields    = &omap_hwmod_sysc_type1,
1165 };
1166
1167 /* I2C common */
1168 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1169         .rev_offs       = 0x00,
1170         .sysc_offs      = 0x20,
1171         .syss_offs      = 0x10,
1172         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1173                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1174                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1175         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1176         .sysc_fields    = &omap_hwmod_sysc_type1,
1177 };
1178
1179 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1180         .name           = "wd_timer",
1181         .sysc           = &omap3xxx_wd_timer_sysc,
1182         .pre_shutdown   = &omap2_wd_timer_disable
1183 };
1184
1185 /* wd_timer2 */
1186 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1187         &omap3xxx_l4_wkup__wd_timer2,
1188 };
1189
1190 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1191         .name           = "wd_timer2",
1192         .class          = &omap3xxx_wd_timer_hwmod_class,
1193         .main_clk       = "wdt2_fck",
1194         .prcm           = {
1195                 .omap2 = {
1196                         .prcm_reg_id = 1,
1197                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1198                         .module_offs = WKUP_MOD,
1199                         .idlest_reg_id = 1,
1200                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1201                 },
1202         },
1203         .slaves         = omap3xxx_wd_timer2_slaves,
1204         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1205         /*
1206          * XXX: Use software supervised mode, HW supervised smartidle seems to
1207          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1208          */
1209         .flags          = HWMOD_SWSUP_SIDLE,
1210 };
1211
1212 /* UART1 */
1213
1214 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1215         &omap3_l4_core__uart1,
1216 };
1217
1218 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1219         .name           = "uart1",
1220         .mpu_irqs       = omap2_uart1_mpu_irqs,
1221         .sdma_reqs      = omap2_uart1_sdma_reqs,
1222         .main_clk       = "uart1_fck",
1223         .prcm           = {
1224                 .omap2 = {
1225                         .module_offs = CORE_MOD,
1226                         .prcm_reg_id = 1,
1227                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1228                         .idlest_reg_id = 1,
1229                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1230                 },
1231         },
1232         .slaves         = omap3xxx_uart1_slaves,
1233         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1234         .class          = &omap2_uart_class,
1235 };
1236
1237 /* UART2 */
1238
1239 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1240         &omap3_l4_core__uart2,
1241 };
1242
1243 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1244         .name           = "uart2",
1245         .mpu_irqs       = omap2_uart2_mpu_irqs,
1246         .sdma_reqs      = omap2_uart2_sdma_reqs,
1247         .main_clk       = "uart2_fck",
1248         .prcm           = {
1249                 .omap2 = {
1250                         .module_offs = CORE_MOD,
1251                         .prcm_reg_id = 1,
1252                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1253                         .idlest_reg_id = 1,
1254                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1255                 },
1256         },
1257         .slaves         = omap3xxx_uart2_slaves,
1258         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1259         .class          = &omap2_uart_class,
1260 };
1261
1262 /* UART3 */
1263
1264 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1265         &omap3_l4_per__uart3,
1266 };
1267
1268 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1269         .name           = "uart3",
1270         .mpu_irqs       = omap2_uart3_mpu_irqs,
1271         .sdma_reqs      = omap2_uart3_sdma_reqs,
1272         .main_clk       = "uart3_fck",
1273         .prcm           = {
1274                 .omap2 = {
1275                         .module_offs = OMAP3430_PER_MOD,
1276                         .prcm_reg_id = 1,
1277                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1278                         .idlest_reg_id = 1,
1279                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1280                 },
1281         },
1282         .slaves         = omap3xxx_uart3_slaves,
1283         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1284         .class          = &omap2_uart_class,
1285 };
1286
1287 /* UART4 */
1288
1289 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1290         { .irq = INT_36XX_UART4_IRQ, },
1291         { .irq = -1 }
1292 };
1293
1294 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1295         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1296         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1297         { .dma_req = -1 }
1298 };
1299
1300 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1301         &omap3_l4_per__uart4,
1302 };
1303
1304 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1305         .name           = "uart4",
1306         .mpu_irqs       = uart4_mpu_irqs,
1307         .sdma_reqs      = uart4_sdma_reqs,
1308         .main_clk       = "uart4_fck",
1309         .prcm           = {
1310                 .omap2 = {
1311                         .module_offs = OMAP3430_PER_MOD,
1312                         .prcm_reg_id = 1,
1313                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1314                         .idlest_reg_id = 1,
1315                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1316                 },
1317         },
1318         .slaves         = omap3xxx_uart4_slaves,
1319         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1320         .class          = &omap2_uart_class,
1321 };
1322
1323 static struct omap_hwmod_class i2c_class = {
1324         .name   = "i2c",
1325         .sysc   = &i2c_sysc,
1326         .rev    = OMAP_I2C_IP_VERSION_1,
1327         .reset  = &omap_i2c_reset,
1328 };
1329
1330 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1331         { .name = "dispc", .dma_req = 5 },
1332         { .name = "dsi1", .dma_req = 74 },
1333         { .dma_req = -1 }
1334 };
1335
1336 /* dss */
1337 /* dss master ports */
1338 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1339         &omap3xxx_dss__l3,
1340 };
1341
1342 /* l4_core -> dss */
1343 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1344         .master         = &omap3xxx_l4_core_hwmod,
1345         .slave          = &omap3430es1_dss_core_hwmod,
1346         .clk            = "dss_ick",
1347         .addr           = omap2_dss_addrs,
1348         .fw = {
1349                 .omap2 = {
1350                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1351                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1352                         .flags  = OMAP_FIREWALL_L4,
1353                 }
1354         },
1355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1356 };
1357
1358 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1359         .master         = &omap3xxx_l4_core_hwmod,
1360         .slave          = &omap3xxx_dss_core_hwmod,
1361         .clk            = "dss_ick",
1362         .addr           = omap2_dss_addrs,
1363         .fw = {
1364                 .omap2 = {
1365                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1366                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1367                         .flags  = OMAP_FIREWALL_L4,
1368                 }
1369         },
1370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1371 };
1372
1373 /* dss slave ports */
1374 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1375         &omap3430es1_l4_core__dss,
1376 };
1377
1378 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1379         &omap3xxx_l4_core__dss,
1380 };
1381
1382 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1383         /*
1384          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1385          * driver does not use these clocks.
1386          */
1387         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1388         { .role = "tv_clk", .clk = "dss_tv_fck" },
1389         /* required only on OMAP3430 */
1390         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1391 };
1392
1393 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1394         .name           = "dss_core",
1395         .class          = &omap2_dss_hwmod_class,
1396         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1397         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1398         .prcm           = {
1399                 .omap2 = {
1400                         .prcm_reg_id = 1,
1401                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1402                         .module_offs = OMAP3430_DSS_MOD,
1403                         .idlest_reg_id = 1,
1404                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1405                 },
1406         },
1407         .opt_clks       = dss_opt_clks,
1408         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1409         .slaves         = omap3430es1_dss_slaves,
1410         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1411         .masters        = omap3xxx_dss_masters,
1412         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1413         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1414 };
1415
1416 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1417         .name           = "dss_core",
1418         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1419         .class          = &omap2_dss_hwmod_class,
1420         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1421         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1422         .prcm           = {
1423                 .omap2 = {
1424                         .prcm_reg_id = 1,
1425                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1426                         .module_offs = OMAP3430_DSS_MOD,
1427                         .idlest_reg_id = 1,
1428                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1429                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1430                 },
1431         },
1432         .opt_clks       = dss_opt_clks,
1433         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1434         .slaves         = omap3xxx_dss_slaves,
1435         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1436         .masters        = omap3xxx_dss_masters,
1437         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1438 };
1439
1440 /*
1441  * 'dispc' class
1442  * display controller
1443  */
1444
1445 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
1446         .rev_offs       = 0x0000,
1447         .sysc_offs      = 0x0010,
1448         .syss_offs      = 0x0014,
1449         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1450                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1451                            SYSC_HAS_ENAWAKEUP),
1452         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1453                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1454         .sysc_fields    = &omap_hwmod_sysc_type1,
1455 };
1456
1457 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1458         .name   = "dispc",
1459         .sysc   = &omap3_dispc_sysc,
1460 };
1461
1462 /* l4_core -> dss_dispc */
1463 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1464         .master         = &omap3xxx_l4_core_hwmod,
1465         .slave          = &omap3xxx_dss_dispc_hwmod,
1466         .clk            = "dss_ick",
1467         .addr           = omap2_dss_dispc_addrs,
1468         .fw = {
1469                 .omap2 = {
1470                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1471                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1472                         .flags  = OMAP_FIREWALL_L4,
1473                 }
1474         },
1475         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1476 };
1477
1478 /* dss_dispc slave ports */
1479 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1480         &omap3xxx_l4_core__dss_dispc,
1481 };
1482
1483 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1484         .name           = "dss_dispc",
1485         .class          = &omap3_dispc_hwmod_class,
1486         .mpu_irqs       = omap2_dispc_irqs,
1487         .main_clk       = "dss1_alwon_fck",
1488         .prcm           = {
1489                 .omap2 = {
1490                         .prcm_reg_id = 1,
1491                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1492                         .module_offs = OMAP3430_DSS_MOD,
1493                 },
1494         },
1495         .slaves         = omap3xxx_dss_dispc_slaves,
1496         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1497         .flags          = HWMOD_NO_IDLEST,
1498         .dev_attr       = &omap2_3_dss_dispc_dev_attr
1499 };
1500
1501 /*
1502  * 'dsi' class
1503  * display serial interface controller
1504  */
1505
1506 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1507         .name = "dsi",
1508 };
1509
1510 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1511         { .irq = 25 },
1512         { .irq = -1 }
1513 };
1514
1515 /* dss_dsi1 */
1516 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1517         {
1518                 .pa_start       = 0x4804FC00,
1519                 .pa_end         = 0x4804FFFF,
1520                 .flags          = ADDR_TYPE_RT
1521         },
1522         { }
1523 };
1524
1525 /* l4_core -> dss_dsi1 */
1526 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1527         .master         = &omap3xxx_l4_core_hwmod,
1528         .slave          = &omap3xxx_dss_dsi1_hwmod,
1529         .clk            = "dss_ick",
1530         .addr           = omap3xxx_dss_dsi1_addrs,
1531         .fw = {
1532                 .omap2 = {
1533                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1534                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1535                         .flags  = OMAP_FIREWALL_L4,
1536                 }
1537         },
1538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1539 };
1540
1541 /* dss_dsi1 slave ports */
1542 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1543         &omap3xxx_l4_core__dss_dsi1,
1544 };
1545
1546 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1547         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1548 };
1549
1550 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1551         .name           = "dss_dsi1",
1552         .class          = &omap3xxx_dsi_hwmod_class,
1553         .mpu_irqs       = omap3xxx_dsi1_irqs,
1554         .main_clk       = "dss1_alwon_fck",
1555         .prcm           = {
1556                 .omap2 = {
1557                         .prcm_reg_id = 1,
1558                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1559                         .module_offs = OMAP3430_DSS_MOD,
1560                 },
1561         },
1562         .opt_clks       = dss_dsi1_opt_clks,
1563         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1564         .slaves         = omap3xxx_dss_dsi1_slaves,
1565         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1566         .flags          = HWMOD_NO_IDLEST,
1567 };
1568
1569 /* l4_core -> dss_rfbi */
1570 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1571         .master         = &omap3xxx_l4_core_hwmod,
1572         .slave          = &omap3xxx_dss_rfbi_hwmod,
1573         .clk            = "dss_ick",
1574         .addr           = omap2_dss_rfbi_addrs,
1575         .fw = {
1576                 .omap2 = {
1577                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1578                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1579                         .flags  = OMAP_FIREWALL_L4,
1580                 }
1581         },
1582         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1583 };
1584
1585 /* dss_rfbi slave ports */
1586 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1587         &omap3xxx_l4_core__dss_rfbi,
1588 };
1589
1590 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1591         { .role = "ick", .clk = "dss_ick" },
1592 };
1593
1594 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1595         .name           = "dss_rfbi",
1596         .class          = &omap2_rfbi_hwmod_class,
1597         .main_clk       = "dss1_alwon_fck",
1598         .prcm           = {
1599                 .omap2 = {
1600                         .prcm_reg_id = 1,
1601                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1602                         .module_offs = OMAP3430_DSS_MOD,
1603                 },
1604         },
1605         .opt_clks       = dss_rfbi_opt_clks,
1606         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1607         .slaves         = omap3xxx_dss_rfbi_slaves,
1608         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1609         .flags          = HWMOD_NO_IDLEST,
1610 };
1611
1612 /* l4_core -> dss_venc */
1613 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1614         .master         = &omap3xxx_l4_core_hwmod,
1615         .slave          = &omap3xxx_dss_venc_hwmod,
1616         .clk            = "dss_ick",
1617         .addr           = omap2_dss_venc_addrs,
1618         .fw = {
1619                 .omap2 = {
1620                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1621                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1622                         .flags  = OMAP_FIREWALL_L4,
1623                 }
1624         },
1625         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1626 };
1627
1628 /* dss_venc slave ports */
1629 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1630         &omap3xxx_l4_core__dss_venc,
1631 };
1632
1633 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1634         /* required only on OMAP3430 */
1635         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1636 };
1637
1638 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1639         .name           = "dss_venc",
1640         .class          = &omap2_venc_hwmod_class,
1641         .main_clk       = "dss_tv_fck",
1642         .prcm           = {
1643                 .omap2 = {
1644                         .prcm_reg_id = 1,
1645                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1646                         .module_offs = OMAP3430_DSS_MOD,
1647                 },
1648         },
1649         .opt_clks       = dss_venc_opt_clks,
1650         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
1651         .slaves         = omap3xxx_dss_venc_slaves,
1652         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1653         .flags          = HWMOD_NO_IDLEST,
1654 };
1655
1656 /* I2C1 */
1657
1658 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1659         .fifo_depth     = 8, /* bytes */
1660         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1661                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1662                           OMAP_I2C_FLAG_BUS_SHIFT_2,
1663 };
1664
1665 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1666         &omap3_l4_core__i2c1,
1667 };
1668
1669 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1670         .name           = "i2c1",
1671         .flags          = HWMOD_16BIT_REG,
1672         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1673         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1674         .main_clk       = "i2c1_fck",
1675         .prcm           = {
1676                 .omap2 = {
1677                         .module_offs = CORE_MOD,
1678                         .prcm_reg_id = 1,
1679                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1680                         .idlest_reg_id = 1,
1681                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1682                 },
1683         },
1684         .slaves         = omap3xxx_i2c1_slaves,
1685         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1686         .class          = &i2c_class,
1687         .dev_attr       = &i2c1_dev_attr,
1688 };
1689
1690 /* I2C2 */
1691
1692 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1693         .fifo_depth     = 8, /* bytes */
1694         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1695                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1696                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1697 };
1698
1699 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1700         &omap3_l4_core__i2c2,
1701 };
1702
1703 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1704         .name           = "i2c2",
1705         .flags          = HWMOD_16BIT_REG,
1706         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1707         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1708         .main_clk       = "i2c2_fck",
1709         .prcm           = {
1710                 .omap2 = {
1711                         .module_offs = CORE_MOD,
1712                         .prcm_reg_id = 1,
1713                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1714                         .idlest_reg_id = 1,
1715                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1716                 },
1717         },
1718         .slaves         = omap3xxx_i2c2_slaves,
1719         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1720         .class          = &i2c_class,
1721         .dev_attr       = &i2c2_dev_attr,
1722 };
1723
1724 /* I2C3 */
1725
1726 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1727         .fifo_depth     = 64, /* bytes */
1728         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1729                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1730                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1731 };
1732
1733 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1734         { .irq = INT_34XX_I2C3_IRQ, },
1735         { .irq = -1 }
1736 };
1737
1738 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1739         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1740         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1741         { .dma_req = -1 }
1742 };
1743
1744 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1745         &omap3_l4_core__i2c3,
1746 };
1747
1748 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1749         .name           = "i2c3",
1750         .flags          = HWMOD_16BIT_REG,
1751         .mpu_irqs       = i2c3_mpu_irqs,
1752         .sdma_reqs      = i2c3_sdma_reqs,
1753         .main_clk       = "i2c3_fck",
1754         .prcm           = {
1755                 .omap2 = {
1756                         .module_offs = CORE_MOD,
1757                         .prcm_reg_id = 1,
1758                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1759                         .idlest_reg_id = 1,
1760                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1761                 },
1762         },
1763         .slaves         = omap3xxx_i2c3_slaves,
1764         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1765         .class          = &i2c_class,
1766         .dev_attr       = &i2c3_dev_attr,
1767 };
1768
1769 /* l4_wkup -> gpio1 */
1770 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1771         {
1772                 .pa_start       = 0x48310000,
1773                 .pa_end         = 0x483101ff,
1774                 .flags          = ADDR_TYPE_RT
1775         },
1776         { }
1777 };
1778
1779 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1780         .master         = &omap3xxx_l4_wkup_hwmod,
1781         .slave          = &omap3xxx_gpio1_hwmod,
1782         .addr           = omap3xxx_gpio1_addrs,
1783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1784 };
1785
1786 /* l4_per -> gpio2 */
1787 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1788         {
1789                 .pa_start       = 0x49050000,
1790                 .pa_end         = 0x490501ff,
1791                 .flags          = ADDR_TYPE_RT
1792         },
1793         { }
1794 };
1795
1796 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1797         .master         = &omap3xxx_l4_per_hwmod,
1798         .slave          = &omap3xxx_gpio2_hwmod,
1799         .addr           = omap3xxx_gpio2_addrs,
1800         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1801 };
1802
1803 /* l4_per -> gpio3 */
1804 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1805         {
1806                 .pa_start       = 0x49052000,
1807                 .pa_end         = 0x490521ff,
1808                 .flags          = ADDR_TYPE_RT
1809         },
1810         { }
1811 };
1812
1813 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1814         .master         = &omap3xxx_l4_per_hwmod,
1815         .slave          = &omap3xxx_gpio3_hwmod,
1816         .addr           = omap3xxx_gpio3_addrs,
1817         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1818 };
1819
1820 /* l4_per -> gpio4 */
1821 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1822         {
1823                 .pa_start       = 0x49054000,
1824                 .pa_end         = 0x490541ff,
1825                 .flags          = ADDR_TYPE_RT
1826         },
1827         { }
1828 };
1829
1830 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1831         .master         = &omap3xxx_l4_per_hwmod,
1832         .slave          = &omap3xxx_gpio4_hwmod,
1833         .addr           = omap3xxx_gpio4_addrs,
1834         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1835 };
1836
1837 /* l4_per -> gpio5 */
1838 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1839         {
1840                 .pa_start       = 0x49056000,
1841                 .pa_end         = 0x490561ff,
1842                 .flags          = ADDR_TYPE_RT
1843         },
1844         { }
1845 };
1846
1847 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1848         .master         = &omap3xxx_l4_per_hwmod,
1849         .slave          = &omap3xxx_gpio5_hwmod,
1850         .addr           = omap3xxx_gpio5_addrs,
1851         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1852 };
1853
1854 /* l4_per -> gpio6 */
1855 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1856         {
1857                 .pa_start       = 0x49058000,
1858                 .pa_end         = 0x490581ff,
1859                 .flags          = ADDR_TYPE_RT
1860         },
1861         { }
1862 };
1863
1864 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1865         .master         = &omap3xxx_l4_per_hwmod,
1866         .slave          = &omap3xxx_gpio6_hwmod,
1867         .addr           = omap3xxx_gpio6_addrs,
1868         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1869 };
1870
1871 /*
1872  * 'gpio' class
1873  * general purpose io module
1874  */
1875
1876 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1877         .rev_offs       = 0x0000,
1878         .sysc_offs      = 0x0010,
1879         .syss_offs      = 0x0014,
1880         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1881                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1882                            SYSS_HAS_RESET_STATUS),
1883         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1884         .sysc_fields    = &omap_hwmod_sysc_type1,
1885 };
1886
1887 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1888         .name = "gpio",
1889         .sysc = &omap3xxx_gpio_sysc,
1890         .rev = 1,
1891 };
1892
1893 /* gpio_dev_attr*/
1894 static struct omap_gpio_dev_attr gpio_dev_attr = {
1895         .bank_width = 32,
1896         .dbck_flag = true,
1897 };
1898
1899 /* gpio1 */
1900 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1901         { .role = "dbclk", .clk = "gpio1_dbck", },
1902 };
1903
1904 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1905         &omap3xxx_l4_wkup__gpio1,
1906 };
1907
1908 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1909         .name           = "gpio1",
1910         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1911         .mpu_irqs       = omap2_gpio1_irqs,
1912         .main_clk       = "gpio1_ick",
1913         .opt_clks       = gpio1_opt_clks,
1914         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1915         .prcm           = {
1916                 .omap2 = {
1917                         .prcm_reg_id = 1,
1918                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1919                         .module_offs = WKUP_MOD,
1920                         .idlest_reg_id = 1,
1921                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1922                 },
1923         },
1924         .slaves         = omap3xxx_gpio1_slaves,
1925         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1926         .class          = &omap3xxx_gpio_hwmod_class,
1927         .dev_attr       = &gpio_dev_attr,
1928 };
1929
1930 /* gpio2 */
1931 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1932         { .role = "dbclk", .clk = "gpio2_dbck", },
1933 };
1934
1935 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1936         &omap3xxx_l4_per__gpio2,
1937 };
1938
1939 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1940         .name           = "gpio2",
1941         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1942         .mpu_irqs       = omap2_gpio2_irqs,
1943         .main_clk       = "gpio2_ick",
1944         .opt_clks       = gpio2_opt_clks,
1945         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1946         .prcm           = {
1947                 .omap2 = {
1948                         .prcm_reg_id = 1,
1949                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1950                         .module_offs = OMAP3430_PER_MOD,
1951                         .idlest_reg_id = 1,
1952                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1953                 },
1954         },
1955         .slaves         = omap3xxx_gpio2_slaves,
1956         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1957         .class          = &omap3xxx_gpio_hwmod_class,
1958         .dev_attr       = &gpio_dev_attr,
1959 };
1960
1961 /* gpio3 */
1962 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1963         { .role = "dbclk", .clk = "gpio3_dbck", },
1964 };
1965
1966 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1967         &omap3xxx_l4_per__gpio3,
1968 };
1969
1970 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1971         .name           = "gpio3",
1972         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1973         .mpu_irqs       = omap2_gpio3_irqs,
1974         .main_clk       = "gpio3_ick",
1975         .opt_clks       = gpio3_opt_clks,
1976         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1977         .prcm           = {
1978                 .omap2 = {
1979                         .prcm_reg_id = 1,
1980                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1981                         .module_offs = OMAP3430_PER_MOD,
1982                         .idlest_reg_id = 1,
1983                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1984                 },
1985         },
1986         .slaves         = omap3xxx_gpio3_slaves,
1987         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1988         .class          = &omap3xxx_gpio_hwmod_class,
1989         .dev_attr       = &gpio_dev_attr,
1990 };
1991
1992 /* gpio4 */
1993 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1994         { .role = "dbclk", .clk = "gpio4_dbck", },
1995 };
1996
1997 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1998         &omap3xxx_l4_per__gpio4,
1999 };
2000
2001 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2002         .name           = "gpio4",
2003         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2004         .mpu_irqs       = omap2_gpio4_irqs,
2005         .main_clk       = "gpio4_ick",
2006         .opt_clks       = gpio4_opt_clks,
2007         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2008         .prcm           = {
2009                 .omap2 = {
2010                         .prcm_reg_id = 1,
2011                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2012                         .module_offs = OMAP3430_PER_MOD,
2013                         .idlest_reg_id = 1,
2014                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2015                 },
2016         },
2017         .slaves         = omap3xxx_gpio4_slaves,
2018         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2019         .class          = &omap3xxx_gpio_hwmod_class,
2020         .dev_attr       = &gpio_dev_attr,
2021 };
2022
2023 /* gpio5 */
2024 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2025         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2026         { .irq = -1 }
2027 };
2028
2029 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2030         { .role = "dbclk", .clk = "gpio5_dbck", },
2031 };
2032
2033 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2034         &omap3xxx_l4_per__gpio5,
2035 };
2036
2037 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2038         .name           = "gpio5",
2039         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2040         .mpu_irqs       = omap3xxx_gpio5_irqs,
2041         .main_clk       = "gpio5_ick",
2042         .opt_clks       = gpio5_opt_clks,
2043         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2044         .prcm           = {
2045                 .omap2 = {
2046                         .prcm_reg_id = 1,
2047                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2048                         .module_offs = OMAP3430_PER_MOD,
2049                         .idlest_reg_id = 1,
2050                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2051                 },
2052         },
2053         .slaves         = omap3xxx_gpio5_slaves,
2054         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2055         .class          = &omap3xxx_gpio_hwmod_class,
2056         .dev_attr       = &gpio_dev_attr,
2057 };
2058
2059 /* gpio6 */
2060 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2061         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2062         { .irq = -1 }
2063 };
2064
2065 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2066         { .role = "dbclk", .clk = "gpio6_dbck", },
2067 };
2068
2069 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2070         &omap3xxx_l4_per__gpio6,
2071 };
2072
2073 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2074         .name           = "gpio6",
2075         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2076         .mpu_irqs       = omap3xxx_gpio6_irqs,
2077         .main_clk       = "gpio6_ick",
2078         .opt_clks       = gpio6_opt_clks,
2079         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2080         .prcm           = {
2081                 .omap2 = {
2082                         .prcm_reg_id = 1,
2083                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2084                         .module_offs = OMAP3430_PER_MOD,
2085                         .idlest_reg_id = 1,
2086                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2087                 },
2088         },
2089         .slaves         = omap3xxx_gpio6_slaves,
2090         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2091         .class          = &omap3xxx_gpio_hwmod_class,
2092         .dev_attr       = &gpio_dev_attr,
2093 };
2094
2095 /* dma_system -> L3 */
2096 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2097         .master         = &omap3xxx_dma_system_hwmod,
2098         .slave          = &omap3xxx_l3_main_hwmod,
2099         .clk            = "core_l3_ick",
2100         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2101 };
2102
2103 /* dma attributes */
2104 static struct omap_dma_dev_attr dma_dev_attr = {
2105         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2106                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2107         .lch_count = 32,
2108 };
2109
2110 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2111         .rev_offs       = 0x0000,
2112         .sysc_offs      = 0x002c,
2113         .syss_offs      = 0x0028,
2114         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2115                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2116                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2117                            SYSS_HAS_RESET_STATUS),
2118         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2119                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2120         .sysc_fields    = &omap_hwmod_sysc_type1,
2121 };
2122
2123 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2124         .name = "dma",
2125         .sysc = &omap3xxx_dma_sysc,
2126 };
2127
2128 /* dma_system */
2129 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2130         {
2131                 .pa_start       = 0x48056000,
2132                 .pa_end         = 0x48056fff,
2133                 .flags          = ADDR_TYPE_RT
2134         },
2135         { }
2136 };
2137
2138 /* dma_system master ports */
2139 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2140         &omap3xxx_dma_system__l3,
2141 };
2142
2143 /* l4_cfg -> dma_system */
2144 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2145         .master         = &omap3xxx_l4_core_hwmod,
2146         .slave          = &omap3xxx_dma_system_hwmod,
2147         .clk            = "core_l4_ick",
2148         .addr           = omap3xxx_dma_system_addrs,
2149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2150 };
2151
2152 /* dma_system slave ports */
2153 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2154         &omap3xxx_l4_core__dma_system,
2155 };
2156
2157 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2158         .name           = "dma",
2159         .class          = &omap3xxx_dma_hwmod_class,
2160         .mpu_irqs       = omap2_dma_system_irqs,
2161         .main_clk       = "core_l3_ick",
2162         .prcm = {
2163                 .omap2 = {
2164                         .module_offs            = CORE_MOD,
2165                         .prcm_reg_id            = 1,
2166                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2167                         .idlest_reg_id          = 1,
2168                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2169                 },
2170         },
2171         .slaves         = omap3xxx_dma_system_slaves,
2172         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2173         .masters        = omap3xxx_dma_system_masters,
2174         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2175         .dev_attr       = &dma_dev_attr,
2176         .flags          = HWMOD_NO_IDLEST,
2177 };
2178
2179 /*
2180  * 'mcbsp' class
2181  * multi channel buffered serial port controller
2182  */
2183
2184 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2185         .sysc_offs      = 0x008c,
2186         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2187                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2188         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2189         .sysc_fields    = &omap_hwmod_sysc_type1,
2190         .clockact       = 0x2,
2191 };
2192
2193 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2194         .name = "mcbsp",
2195         .sysc = &omap3xxx_mcbsp_sysc,
2196         .rev  = MCBSP_CONFIG_TYPE3,
2197 };
2198
2199 /* mcbsp1 */
2200 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2201         { .name = "irq", .irq = 16 },
2202         { .name = "tx", .irq = 59 },
2203         { .name = "rx", .irq = 60 },
2204         { .irq = -1 }
2205 };
2206
2207 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2208         {
2209                 .name           = "mpu",
2210                 .pa_start       = 0x48074000,
2211                 .pa_end         = 0x480740ff,
2212                 .flags          = ADDR_TYPE_RT
2213         },
2214         { }
2215 };
2216
2217 /* l4_core -> mcbsp1 */
2218 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2219         .master         = &omap3xxx_l4_core_hwmod,
2220         .slave          = &omap3xxx_mcbsp1_hwmod,
2221         .clk            = "mcbsp1_ick",
2222         .addr           = omap3xxx_mcbsp1_addrs,
2223         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2224 };
2225
2226 /* mcbsp1 slave ports */
2227 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2228         &omap3xxx_l4_core__mcbsp1,
2229 };
2230
2231 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2232         .name           = "mcbsp1",
2233         .class          = &omap3xxx_mcbsp_hwmod_class,
2234         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2235         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
2236         .main_clk       = "mcbsp1_fck",
2237         .prcm           = {
2238                 .omap2 = {
2239                         .prcm_reg_id = 1,
2240                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2241                         .module_offs = CORE_MOD,
2242                         .idlest_reg_id = 1,
2243                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2244                 },
2245         },
2246         .slaves         = omap3xxx_mcbsp1_slaves,
2247         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2248 };
2249
2250 /* mcbsp2 */
2251 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2252         { .name = "irq", .irq = 17 },
2253         { .name = "tx", .irq = 62 },
2254         { .name = "rx", .irq = 63 },
2255         { .irq = -1 }
2256 };
2257
2258 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2259         {
2260                 .name           = "mpu",
2261                 .pa_start       = 0x49022000,
2262                 .pa_end         = 0x490220ff,
2263                 .flags          = ADDR_TYPE_RT
2264         },
2265         { }
2266 };
2267
2268 /* l4_per -> mcbsp2 */
2269 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2270         .master         = &omap3xxx_l4_per_hwmod,
2271         .slave          = &omap3xxx_mcbsp2_hwmod,
2272         .clk            = "mcbsp2_ick",
2273         .addr           = omap3xxx_mcbsp2_addrs,
2274         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2275 };
2276
2277 /* mcbsp2 slave ports */
2278 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2279         &omap3xxx_l4_per__mcbsp2,
2280 };
2281
2282 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2283         .sidetone       = "mcbsp2_sidetone",
2284 };
2285
2286 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2287         .name           = "mcbsp2",
2288         .class          = &omap3xxx_mcbsp_hwmod_class,
2289         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2290         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
2291         .main_clk       = "mcbsp2_fck",
2292         .prcm           = {
2293                 .omap2 = {
2294                         .prcm_reg_id = 1,
2295                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2296                         .module_offs = OMAP3430_PER_MOD,
2297                         .idlest_reg_id = 1,
2298                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2299                 },
2300         },
2301         .slaves         = omap3xxx_mcbsp2_slaves,
2302         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2303         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2304 };
2305
2306 /* mcbsp3 */
2307 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2308         { .name = "irq", .irq = 22 },
2309         { .name = "tx", .irq = 89 },
2310         { .name = "rx", .irq = 90 },
2311         { .irq = -1 }
2312 };
2313
2314 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2315         {
2316                 .name           = "mpu",
2317                 .pa_start       = 0x49024000,
2318                 .pa_end         = 0x490240ff,
2319                 .flags          = ADDR_TYPE_RT
2320         },
2321         { }
2322 };
2323
2324 /* l4_per -> mcbsp3 */
2325 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2326         .master         = &omap3xxx_l4_per_hwmod,
2327         .slave          = &omap3xxx_mcbsp3_hwmod,
2328         .clk            = "mcbsp3_ick",
2329         .addr           = omap3xxx_mcbsp3_addrs,
2330         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2331 };
2332
2333 /* mcbsp3 slave ports */
2334 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2335         &omap3xxx_l4_per__mcbsp3,
2336 };
2337
2338 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2339         .sidetone       = "mcbsp3_sidetone",
2340 };
2341
2342 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2343         .name           = "mcbsp3",
2344         .class          = &omap3xxx_mcbsp_hwmod_class,
2345         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2346         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
2347         .main_clk       = "mcbsp3_fck",
2348         .prcm           = {
2349                 .omap2 = {
2350                         .prcm_reg_id = 1,
2351                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2352                         .module_offs = OMAP3430_PER_MOD,
2353                         .idlest_reg_id = 1,
2354                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2355                 },
2356         },
2357         .slaves         = omap3xxx_mcbsp3_slaves,
2358         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2359         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2360 };
2361
2362 /* mcbsp4 */
2363 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2364         { .name = "irq", .irq = 23 },
2365         { .name = "tx", .irq = 54 },
2366         { .name = "rx", .irq = 55 },
2367         { .irq = -1 }
2368 };
2369
2370 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2371         { .name = "rx", .dma_req = 20 },
2372         { .name = "tx", .dma_req = 19 },
2373         { .dma_req = -1 }
2374 };
2375
2376 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2377         {
2378                 .name           = "mpu",
2379                 .pa_start       = 0x49026000,
2380                 .pa_end         = 0x490260ff,
2381                 .flags          = ADDR_TYPE_RT
2382         },
2383         { }
2384 };
2385
2386 /* l4_per -> mcbsp4 */
2387 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2388         .master         = &omap3xxx_l4_per_hwmod,
2389         .slave          = &omap3xxx_mcbsp4_hwmod,
2390         .clk            = "mcbsp4_ick",
2391         .addr           = omap3xxx_mcbsp4_addrs,
2392         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2393 };
2394
2395 /* mcbsp4 slave ports */
2396 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2397         &omap3xxx_l4_per__mcbsp4,
2398 };
2399
2400 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2401         .name           = "mcbsp4",
2402         .class          = &omap3xxx_mcbsp_hwmod_class,
2403         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2404         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2405         .main_clk       = "mcbsp4_fck",
2406         .prcm           = {
2407                 .omap2 = {
2408                         .prcm_reg_id = 1,
2409                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2410                         .module_offs = OMAP3430_PER_MOD,
2411                         .idlest_reg_id = 1,
2412                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2413                 },
2414         },
2415         .slaves         = omap3xxx_mcbsp4_slaves,
2416         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2417 };
2418
2419 /* mcbsp5 */
2420 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2421         { .name = "irq", .irq = 27 },
2422         { .name = "tx", .irq = 81 },
2423         { .name = "rx", .irq = 82 },
2424         { .irq = -1 }
2425 };
2426
2427 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2428         { .name = "rx", .dma_req = 22 },
2429         { .name = "tx", .dma_req = 21 },
2430         { .dma_req = -1 }
2431 };
2432
2433 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2434         {
2435                 .name           = "mpu",
2436                 .pa_start       = 0x48096000,
2437                 .pa_end         = 0x480960ff,
2438                 .flags          = ADDR_TYPE_RT
2439         },
2440         { }
2441 };
2442
2443 /* l4_core -> mcbsp5 */
2444 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2445         .master         = &omap3xxx_l4_core_hwmod,
2446         .slave          = &omap3xxx_mcbsp5_hwmod,
2447         .clk            = "mcbsp5_ick",
2448         .addr           = omap3xxx_mcbsp5_addrs,
2449         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2450 };
2451
2452 /* mcbsp5 slave ports */
2453 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2454         &omap3xxx_l4_core__mcbsp5,
2455 };
2456
2457 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2458         .name           = "mcbsp5",
2459         .class          = &omap3xxx_mcbsp_hwmod_class,
2460         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2461         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2462         .main_clk       = "mcbsp5_fck",
2463         .prcm           = {
2464                 .omap2 = {
2465                         .prcm_reg_id = 1,
2466                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2467                         .module_offs = CORE_MOD,
2468                         .idlest_reg_id = 1,
2469                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2470                 },
2471         },
2472         .slaves         = omap3xxx_mcbsp5_slaves,
2473         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2474 };
2475 /* 'mcbsp sidetone' class */
2476
2477 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2478         .sysc_offs      = 0x0010,
2479         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2480         .sysc_fields    = &omap_hwmod_sysc_type1,
2481 };
2482
2483 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2484         .name = "mcbsp_sidetone",
2485         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2486 };
2487
2488 /* mcbsp2_sidetone */
2489 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2490         { .name = "irq", .irq = 4 },
2491         { .irq = -1 }
2492 };
2493
2494 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2495         {
2496                 .name           = "sidetone",
2497                 .pa_start       = 0x49028000,
2498                 .pa_end         = 0x490280ff,
2499                 .flags          = ADDR_TYPE_RT
2500         },
2501         { }
2502 };
2503
2504 /* l4_per -> mcbsp2_sidetone */
2505 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2506         .master         = &omap3xxx_l4_per_hwmod,
2507         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2508         .clk            = "mcbsp2_ick",
2509         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2510         .user           = OCP_USER_MPU,
2511 };
2512
2513 /* mcbsp2_sidetone slave ports */
2514 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2515         &omap3xxx_l4_per__mcbsp2_sidetone,
2516 };
2517
2518 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2519         .name           = "mcbsp2_sidetone",
2520         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2521         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2522         .main_clk       = "mcbsp2_fck",
2523         .prcm           = {
2524                 .omap2 = {
2525                         .prcm_reg_id = 1,
2526                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2527                         .module_offs = OMAP3430_PER_MOD,
2528                         .idlest_reg_id = 1,
2529                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2530                 },
2531         },
2532         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2533         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2534 };
2535
2536 /* mcbsp3_sidetone */
2537 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2538         { .name = "irq", .irq = 5 },
2539         { .irq = -1 }
2540 };
2541
2542 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2543         {
2544                 .name           = "sidetone",
2545                 .pa_start       = 0x4902A000,
2546                 .pa_end         = 0x4902A0ff,
2547                 .flags          = ADDR_TYPE_RT
2548         },
2549         { }
2550 };
2551
2552 /* l4_per -> mcbsp3_sidetone */
2553 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2554         .master         = &omap3xxx_l4_per_hwmod,
2555         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2556         .clk            = "mcbsp3_ick",
2557         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2558         .user           = OCP_USER_MPU,
2559 };
2560
2561 /* mcbsp3_sidetone slave ports */
2562 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2563         &omap3xxx_l4_per__mcbsp3_sidetone,
2564 };
2565
2566 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2567         .name           = "mcbsp3_sidetone",
2568         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2569         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2570         .main_clk       = "mcbsp3_fck",
2571         .prcm           = {
2572                 .omap2 = {
2573                         .prcm_reg_id = 1,
2574                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2575                         .module_offs = OMAP3430_PER_MOD,
2576                         .idlest_reg_id = 1,
2577                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2578                 },
2579         },
2580         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2581         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2582 };
2583
2584
2585 /* SR common */
2586 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2587         .clkact_shift   = 20,
2588 };
2589
2590 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2591         .sysc_offs      = 0x24,
2592         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2593         .clockact       = CLOCKACT_TEST_ICLK,
2594         .sysc_fields    = &omap34xx_sr_sysc_fields,
2595 };
2596
2597 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2598         .name = "smartreflex",
2599         .sysc = &omap34xx_sr_sysc,
2600         .rev  = 1,
2601 };
2602
2603 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2604         .sidle_shift    = 24,
2605         .enwkup_shift   = 26
2606 };
2607
2608 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2609         .sysc_offs      = 0x38,
2610         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2611         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2612                         SYSC_NO_CACHE),
2613         .sysc_fields    = &omap36xx_sr_sysc_fields,
2614 };
2615
2616 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2617         .name = "smartreflex",
2618         .sysc = &omap36xx_sr_sysc,
2619         .rev  = 2,
2620 };
2621
2622 /* SR1 */
2623 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
2624         .sensor_voltdm_name   = "mpu_iva",
2625 };
2626
2627 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2628         &omap3_l4_core__sr1,
2629 };
2630
2631 static struct omap_hwmod omap34xx_sr1_hwmod = {
2632         .name           = "sr1",
2633         .class          = &omap34xx_smartreflex_hwmod_class,
2634         .main_clk       = "sr1_fck",
2635         .prcm           = {
2636                 .omap2 = {
2637                         .prcm_reg_id = 1,
2638                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2639                         .module_offs = WKUP_MOD,
2640                         .idlest_reg_id = 1,
2641                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2642                 },
2643         },
2644         .slaves         = omap3_sr1_slaves,
2645         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2646         .dev_attr       = &sr1_dev_attr,
2647         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
2648         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2649 };
2650
2651 static struct omap_hwmod omap36xx_sr1_hwmod = {
2652         .name           = "sr1",
2653         .class          = &omap36xx_smartreflex_hwmod_class,
2654         .main_clk       = "sr1_fck",
2655         .prcm           = {
2656                 .omap2 = {
2657                         .prcm_reg_id = 1,
2658                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2659                         .module_offs = WKUP_MOD,
2660                         .idlest_reg_id = 1,
2661                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2662                 },
2663         },
2664         .slaves         = omap3_sr1_slaves,
2665         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2666         .dev_attr       = &sr1_dev_attr,
2667         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
2668 };
2669
2670 /* SR2 */
2671 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
2672         .sensor_voltdm_name     = "core",
2673 };
2674
2675 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2676         &omap3_l4_core__sr2,
2677 };
2678
2679 static struct omap_hwmod omap34xx_sr2_hwmod = {
2680         .name           = "sr2",
2681         .class          = &omap34xx_smartreflex_hwmod_class,
2682         .main_clk       = "sr2_fck",
2683         .prcm           = {
2684                 .omap2 = {
2685                         .prcm_reg_id = 1,
2686                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2687                         .module_offs = WKUP_MOD,
2688                         .idlest_reg_id = 1,
2689                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2690                 },
2691         },
2692         .slaves         = omap3_sr2_slaves,
2693         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2694         .dev_attr       = &sr2_dev_attr,
2695         .mpu_irqs       = omap3_smartreflex_core_irqs,
2696         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2697 };
2698
2699 static struct omap_hwmod omap36xx_sr2_hwmod = {
2700         .name           = "sr2",
2701         .class          = &omap36xx_smartreflex_hwmod_class,
2702         .main_clk       = "sr2_fck",
2703         .prcm           = {
2704                 .omap2 = {
2705                         .prcm_reg_id = 1,
2706                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2707                         .module_offs = WKUP_MOD,
2708                         .idlest_reg_id = 1,
2709                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2710                 },
2711         },
2712         .slaves         = omap3_sr2_slaves,
2713         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2714         .dev_attr       = &sr2_dev_attr,
2715         .mpu_irqs       = omap3_smartreflex_core_irqs,
2716 };
2717
2718 /*
2719  * 'mailbox' class
2720  * mailbox module allowing communication between the on-chip processors
2721  * using a queued mailbox-interrupt mechanism.
2722  */
2723
2724 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2725         .rev_offs       = 0x000,
2726         .sysc_offs      = 0x010,
2727         .syss_offs      = 0x014,
2728         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2729                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2730         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2731         .sysc_fields    = &omap_hwmod_sysc_type1,
2732 };
2733
2734 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2735         .name = "mailbox",
2736         .sysc = &omap3xxx_mailbox_sysc,
2737 };
2738
2739 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2740 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2741         { .irq = 26 },
2742         { .irq = -1 }
2743 };
2744
2745 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2746         {
2747                 .pa_start       = 0x48094000,
2748                 .pa_end         = 0x480941ff,
2749                 .flags          = ADDR_TYPE_RT,
2750         },
2751         { }
2752 };
2753
2754 /* l4_core -> mailbox */
2755 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2756         .master         = &omap3xxx_l4_core_hwmod,
2757         .slave          = &omap3xxx_mailbox_hwmod,
2758         .addr           = omap3xxx_mailbox_addrs,
2759         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2760 };
2761
2762 /* mailbox slave ports */
2763 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2764         &omap3xxx_l4_core__mailbox,
2765 };
2766
2767 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2768         .name           = "mailbox",
2769         .class          = &omap3xxx_mailbox_hwmod_class,
2770         .mpu_irqs       = omap3xxx_mailbox_irqs,
2771         .main_clk       = "mailboxes_ick",
2772         .prcm           = {
2773                 .omap2 = {
2774                         .prcm_reg_id = 1,
2775                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2776                         .module_offs = CORE_MOD,
2777                         .idlest_reg_id = 1,
2778                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2779                 },
2780         },
2781         .slaves         = omap3xxx_mailbox_slaves,
2782         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2783 };
2784
2785 /* l4 core -> mcspi1 interface */
2786 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2787         .master         = &omap3xxx_l4_core_hwmod,
2788         .slave          = &omap34xx_mcspi1,
2789         .clk            = "mcspi1_ick",
2790         .addr           = omap2_mcspi1_addr_space,
2791         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2792 };
2793
2794 /* l4 core -> mcspi2 interface */
2795 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2796         .master         = &omap3xxx_l4_core_hwmod,
2797         .slave          = &omap34xx_mcspi2,
2798         .clk            = "mcspi2_ick",
2799         .addr           = omap2_mcspi2_addr_space,
2800         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2801 };
2802
2803 /* l4 core -> mcspi3 interface */
2804 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2805         .master         = &omap3xxx_l4_core_hwmod,
2806         .slave          = &omap34xx_mcspi3,
2807         .clk            = "mcspi3_ick",
2808         .addr           = omap2430_mcspi3_addr_space,
2809         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2810 };
2811
2812 /* l4 core -> mcspi4 interface */
2813 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2814         {
2815                 .pa_start       = 0x480ba000,
2816                 .pa_end         = 0x480ba0ff,
2817                 .flags          = ADDR_TYPE_RT,
2818         },
2819         { }
2820 };
2821
2822 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2823         .master         = &omap3xxx_l4_core_hwmod,
2824         .slave          = &omap34xx_mcspi4,
2825         .clk            = "mcspi4_ick",
2826         .addr           = omap34xx_mcspi4_addr_space,
2827         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2828 };
2829
2830 /*
2831  * 'mcspi' class
2832  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2833  * bus
2834  */
2835
2836 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2837         .rev_offs       = 0x0000,
2838         .sysc_offs      = 0x0010,
2839         .syss_offs      = 0x0014,
2840         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2841                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2842                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2843         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2844         .sysc_fields    = &omap_hwmod_sysc_type1,
2845 };
2846
2847 static struct omap_hwmod_class omap34xx_mcspi_class = {
2848         .name = "mcspi",
2849         .sysc = &omap34xx_mcspi_sysc,
2850         .rev = OMAP3_MCSPI_REV,
2851 };
2852
2853 /* mcspi1 */
2854 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2855         &omap34xx_l4_core__mcspi1,
2856 };
2857
2858 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2859         .num_chipselect = 4,
2860 };
2861
2862 static struct omap_hwmod omap34xx_mcspi1 = {
2863         .name           = "mcspi1",
2864         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
2865         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
2866         .main_clk       = "mcspi1_fck",
2867         .prcm           = {
2868                 .omap2 = {
2869                         .module_offs = CORE_MOD,
2870                         .prcm_reg_id = 1,
2871                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2872                         .idlest_reg_id = 1,
2873                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2874                 },
2875         },
2876         .slaves         = omap34xx_mcspi1_slaves,
2877         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2878         .class          = &omap34xx_mcspi_class,
2879         .dev_attr       = &omap_mcspi1_dev_attr,
2880 };
2881
2882 /* mcspi2 */
2883 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2884         &omap34xx_l4_core__mcspi2,
2885 };
2886
2887 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2888         .num_chipselect = 2,
2889 };
2890
2891 static struct omap_hwmod omap34xx_mcspi2 = {
2892         .name           = "mcspi2",
2893         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
2894         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
2895         .main_clk       = "mcspi2_fck",
2896         .prcm           = {
2897                 .omap2 = {
2898                         .module_offs = CORE_MOD,
2899                         .prcm_reg_id = 1,
2900                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2901                         .idlest_reg_id = 1,
2902                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2903                 },
2904         },
2905         .slaves         = omap34xx_mcspi2_slaves,
2906         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2907         .class          = &omap34xx_mcspi_class,
2908         .dev_attr       = &omap_mcspi2_dev_attr,
2909 };
2910
2911 /* mcspi3 */
2912 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2913         { .name = "irq", .irq = 91 }, /* 91 */
2914         { .irq = -1 }
2915 };
2916
2917 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2918         { .name = "tx0", .dma_req = 15 },
2919         { .name = "rx0", .dma_req = 16 },
2920         { .name = "tx1", .dma_req = 23 },
2921         { .name = "rx1", .dma_req = 24 },
2922         { .dma_req = -1 }
2923 };
2924
2925 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2926         &omap34xx_l4_core__mcspi3,
2927 };
2928
2929 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2930         .num_chipselect = 2,
2931 };
2932
2933 static struct omap_hwmod omap34xx_mcspi3 = {
2934         .name           = "mcspi3",
2935         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
2936         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
2937         .main_clk       = "mcspi3_fck",
2938         .prcm           = {
2939                 .omap2 = {
2940                         .module_offs = CORE_MOD,
2941                         .prcm_reg_id = 1,
2942                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2943                         .idlest_reg_id = 1,
2944                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2945                 },
2946         },
2947         .slaves         = omap34xx_mcspi3_slaves,
2948         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2949         .class          = &omap34xx_mcspi_class,
2950         .dev_attr       = &omap_mcspi3_dev_attr,
2951 };
2952
2953 /* SPI4 */
2954 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2955         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2956         { .irq = -1 }
2957 };
2958
2959 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2960         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2961         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2962         { .dma_req = -1 }
2963 };
2964
2965 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2966         &omap34xx_l4_core__mcspi4,
2967 };
2968
2969 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2970         .num_chipselect = 1,
2971 };
2972
2973 static struct omap_hwmod omap34xx_mcspi4 = {
2974         .name           = "mcspi4",
2975         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
2976         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
2977         .main_clk       = "mcspi4_fck",
2978         .prcm           = {
2979                 .omap2 = {
2980                         .module_offs = CORE_MOD,
2981                         .prcm_reg_id = 1,
2982                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2983                         .idlest_reg_id = 1,
2984                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2985                 },
2986         },
2987         .slaves         = omap34xx_mcspi4_slaves,
2988         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2989         .class          = &omap34xx_mcspi_class,
2990         .dev_attr       = &omap_mcspi4_dev_attr,
2991 };
2992
2993 /* temp. sensor */
2994 struct omap_hwmod_class omap34xx_bandgap_ts_class = {
2995         .name   = "bandgap_ts",
2996 };
2997
2998 static struct omap_hwmod_addr_space omap3xxx_bandgap_ts_addrs[] = {
2999         {
3000                 .name           = "mpu",
3001                 .pa_start       = 0x48002524,
3002                 .pa_end         = 0x48002524 + 4,
3003                 .flags          = ADDR_TYPE_RT
3004         },
3005         { }
3006 };
3007
3008 static struct omap_hwmod omap34xx_bandgap_ts;
3009
3010 /* l4_core -> bandgap */
3011 static struct omap_hwmod_ocp_if omap3xxx_l4_core__bandgap_ts = {
3012         .master         = &omap3xxx_l4_core_hwmod,
3013         .slave          = &omap34xx_bandgap_ts,
3014         .addr           = omap3xxx_bandgap_ts_addrs,
3015         .user           = OCP_USER_MPU,
3016 };
3017
3018 static struct omap_hwmod_ocp_if *omap3xxx_bandgap_ts_slaves[] = {
3019         &omap3xxx_l4_core__bandgap_ts,
3020 };
3021
3022 static struct omap_hwmod omap34xx_bandgap_ts = {
3023         .name           = "bandgap_ts",
3024         .main_clk       = "ts_fck",
3025         .slaves         = omap3xxx_bandgap_ts_slaves,
3026         .slaves_cnt     = ARRAY_SIZE(omap3xxx_bandgap_ts_slaves),
3027         .class          = &omap34xx_bandgap_ts_class,
3028         .flags          = HWMOD_NO_IDLEST,
3029 };
3030
3031 /*
3032  * usbhsotg
3033  */
3034 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3035         .rev_offs       = 0x0400,
3036         .sysc_offs      = 0x0404,
3037         .syss_offs      = 0x0408,
3038         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3039                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3040                           SYSC_HAS_AUTOIDLE),
3041         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3042                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3043         .sysc_fields    = &omap_hwmod_sysc_type1,
3044 };
3045
3046 static struct omap_hwmod_class usbotg_class = {
3047         .name = "usbotg",
3048         .sysc = &omap3xxx_usbhsotg_sysc,
3049 };
3050 /* usb_otg_hs */
3051 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3052
3053         { .name = "mc", .irq = 92 },
3054         { .name = "dma", .irq = 93 },
3055         { .irq = -1 }
3056 };
3057
3058 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3059         .name           = "usb_otg_hs",
3060         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
3061         .main_clk       = "hsotgusb_ick",
3062         .prcm           = {
3063                 .omap2 = {
3064                         .prcm_reg_id = 1,
3065                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3066                         .module_offs = CORE_MOD,
3067                         .idlest_reg_id = 1,
3068                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3069                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3070                 },
3071         },
3072         .masters        = omap3xxx_usbhsotg_masters,
3073         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3074         .slaves         = omap3xxx_usbhsotg_slaves,
3075         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3076         .class          = &usbotg_class,
3077
3078         /*
3079          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
3080          * broken when autoidle is enabled
3081          * workaround is to disable the autoidle bit at module level.
3082          *
3083          * Enabling the device in any other MIDLEMODE setting but force-idle
3084          * causes core_pwrdm not enter idle states at least on OMAP3630.
3085          * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
3086          * signal when MIDLEMODE is set to force-idle.
3087          */
3088         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3089                                 | HWMOD_FORCE_MSTANDBY,
3090 };
3091
3092 /* usb_otg_hs */
3093 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3094
3095         { .name = "mc", .irq = 71 },
3096         { .irq = -1 }
3097 };
3098
3099 static struct omap_hwmod_class am35xx_usbotg_class = {
3100         .name = "am35xx_usbotg",
3101         .sysc = NULL,
3102 };
3103
3104 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3105         .name           = "am35x_otg_hs",
3106         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3107         .main_clk       = NULL,
3108         .prcm = {
3109                 .omap2 = {
3110                 },
3111         },
3112         .masters        = am35xx_usbhsotg_masters,
3113         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3114         .slaves         = am35xx_usbhsotg_slaves,
3115         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3116         .class          = &am35xx_usbotg_class,
3117 };
3118
3119 /* MMC/SD/SDIO common */
3120
3121 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3122         .rev_offs       = 0x1fc,
3123         .sysc_offs      = 0x10,
3124         .syss_offs      = 0x14,
3125         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3126                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3127                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3128         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3129         .sysc_fields    = &omap_hwmod_sysc_type1,
3130 };
3131
3132 static struct omap_hwmod_class omap34xx_mmc_class = {
3133         .name = "mmc",
3134         .sysc = &omap34xx_mmc_sysc,
3135 };
3136
3137 /* MMC/SD/SDIO1 */
3138
3139 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3140         { .irq = 83, },
3141         { .irq = -1 }
3142 };
3143
3144 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3145         { .name = "tx", .dma_req = 61, },
3146         { .name = "rx", .dma_req = 62, },
3147         { .dma_req = -1 }
3148 };
3149
3150 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3151         { .role = "dbck", .clk = "omap_32k_fck", },
3152 };
3153
3154 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3155         &omap3xxx_l4_core__mmc1,
3156 };
3157
3158 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3159         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3160 };
3161
3162 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3163 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
3164         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
3165                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
3166 };
3167
3168 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
3169         .name           = "mmc1",
3170         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3171         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3172         .opt_clks       = omap34xx_mmc1_opt_clks,
3173         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3174         .main_clk       = "mmchs1_fck",
3175         .prcm           = {
3176                 .omap2 = {
3177                         .module_offs = CORE_MOD,
3178                         .prcm_reg_id = 1,
3179                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3180                         .idlest_reg_id = 1,
3181                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3182                 },
3183         },
3184         .dev_attr       = &mmc1_pre_es3_dev_attr,
3185         .slaves         = omap3xxx_mmc1_slaves,
3186         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3187         .class          = &omap34xx_mmc_class,
3188 };
3189
3190 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
3191         .name           = "mmc1",
3192         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3193         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3194         .opt_clks       = omap34xx_mmc1_opt_clks,
3195         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3196         .main_clk       = "mmchs1_fck",
3197         .prcm           = {
3198                 .omap2 = {
3199                         .module_offs = CORE_MOD,
3200                         .prcm_reg_id = 1,
3201                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3202                         .idlest_reg_id = 1,
3203                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3204                 },
3205         },
3206         .dev_attr       = &mmc1_dev_attr,
3207         .slaves         = omap3xxx_mmc1_slaves,
3208         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3209         .class          = &omap34xx_mmc_class,
3210 };
3211
3212 /* MMC/SD/SDIO2 */
3213
3214 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3215         { .irq = INT_24XX_MMC2_IRQ, },
3216         { .irq = -1 }
3217 };
3218
3219 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3220         { .name = "tx", .dma_req = 47, },
3221         { .name = "rx", .dma_req = 48, },
3222         { .dma_req = -1 }
3223 };
3224
3225 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3226         { .role = "dbck", .clk = "omap_32k_fck", },
3227 };
3228
3229 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3230         &omap3xxx_l4_core__mmc2,
3231 };
3232
3233 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3234 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
3235         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
3236 };
3237
3238 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
3239         .name           = "mmc2",
3240         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3241         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3242         .opt_clks       = omap34xx_mmc2_opt_clks,
3243         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3244         .main_clk       = "mmchs2_fck",
3245         .prcm           = {
3246                 .omap2 = {
3247                         .module_offs = CORE_MOD,
3248                         .prcm_reg_id = 1,
3249                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3250                         .idlest_reg_id = 1,
3251                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3252                 },
3253         },
3254         .dev_attr       = &mmc2_pre_es3_dev_attr,
3255         .slaves         = omap3xxx_mmc2_slaves,
3256         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3257         .class          = &omap34xx_mmc_class,
3258 };
3259
3260 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
3261         .name           = "mmc2",
3262         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3263         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3264         .opt_clks       = omap34xx_mmc2_opt_clks,
3265         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3266         .main_clk       = "mmchs2_fck",
3267         .prcm           = {
3268                 .omap2 = {
3269                         .module_offs = CORE_MOD,
3270                         .prcm_reg_id = 1,
3271                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3272                         .idlest_reg_id = 1,
3273                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3274                 },
3275         },
3276         .slaves         = omap3xxx_mmc2_slaves,
3277         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3278         .class          = &omap34xx_mmc_class,
3279 };
3280
3281 /* MMC/SD/SDIO3 */
3282
3283 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3284         { .irq = 94, },
3285         { .irq = -1 }
3286 };
3287
3288 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3289         { .name = "tx", .dma_req = 77, },
3290         { .name = "rx", .dma_req = 78, },
3291         { .dma_req = -1 }
3292 };
3293
3294 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3295         { .role = "dbck", .clk = "omap_32k_fck", },
3296 };
3297
3298 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3299         &omap3xxx_l4_core__mmc3,
3300 };
3301
3302 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3303         .name           = "mmc3",
3304         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3305         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3306         .opt_clks       = omap34xx_mmc3_opt_clks,
3307         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3308         .main_clk       = "mmchs3_fck",
3309         .prcm           = {
3310                 .omap2 = {
3311                         .prcm_reg_id = 1,
3312                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3313                         .idlest_reg_id = 1,
3314                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3315                 },
3316         },
3317         .slaves         = omap3xxx_mmc3_slaves,
3318         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3319         .class          = &omap34xx_mmc_class,
3320 };
3321
3322 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3323         &omap3xxx_l3_main_hwmod,
3324         &omap3xxx_l4_core_hwmod,
3325         &omap3xxx_l4_per_hwmod,
3326         &omap3xxx_l4_wkup_hwmod,
3327         &omap3xxx_mmc3_hwmod,
3328         &omap3xxx_mpu_hwmod,
3329
3330         &omap3xxx_timer1_hwmod,
3331         &omap3xxx_timer2_hwmod,
3332         &omap3xxx_timer3_hwmod,
3333         &omap3xxx_timer4_hwmod,
3334         &omap3xxx_timer5_hwmod,
3335         &omap3xxx_timer6_hwmod,
3336         &omap3xxx_timer7_hwmod,
3337         &omap3xxx_timer8_hwmod,
3338         &omap3xxx_timer9_hwmod,
3339         &omap3xxx_timer10_hwmod,
3340         &omap3xxx_timer11_hwmod,
3341
3342         &omap3xxx_wd_timer2_hwmod,
3343         &omap3xxx_uart1_hwmod,
3344         &omap3xxx_uart2_hwmod,
3345         &omap3xxx_uart3_hwmod,
3346
3347         /* i2c class */
3348         &omap3xxx_i2c1_hwmod,
3349         &omap3xxx_i2c2_hwmod,
3350         &omap3xxx_i2c3_hwmod,
3351
3352         /* gpio class */
3353         &omap3xxx_gpio1_hwmod,
3354         &omap3xxx_gpio2_hwmod,
3355         &omap3xxx_gpio3_hwmod,
3356         &omap3xxx_gpio4_hwmod,
3357         &omap3xxx_gpio5_hwmod,
3358         &omap3xxx_gpio6_hwmod,
3359
3360         /* dma_system class*/
3361         &omap3xxx_dma_system_hwmod,
3362
3363         /* mcbsp class */
3364         &omap3xxx_mcbsp1_hwmod,
3365         &omap3xxx_mcbsp2_hwmod,
3366         &omap3xxx_mcbsp3_hwmod,
3367         &omap3xxx_mcbsp4_hwmod,
3368         &omap3xxx_mcbsp5_hwmod,
3369         &omap3xxx_mcbsp2_sidetone_hwmod,
3370         &omap3xxx_mcbsp3_sidetone_hwmod,
3371
3372
3373         /* mcspi class */
3374         &omap34xx_mcspi1,
3375         &omap34xx_mcspi2,
3376         &omap34xx_mcspi3,
3377         &omap34xx_mcspi4,
3378
3379         &omap34xx_bandgap_ts,
3380
3381         NULL,
3382 };
3383
3384 /* GP-only hwmods */
3385 static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
3386         &omap3xxx_timer12_hwmod,
3387         NULL
3388 };
3389
3390 /* 3430ES1-only hwmods */
3391 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
3392         &omap3430es1_dss_core_hwmod,
3393         NULL
3394 };
3395
3396 /* 3430ES2+-only hwmods */
3397 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
3398         &omap3xxx_dss_core_hwmod,
3399         &omap3xxx_usbhsotg_hwmod,
3400         NULL
3401 };
3402
3403 /* <= 3430ES3-only hwmods */
3404 static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
3405         &omap3xxx_pre_es3_mmc1_hwmod,
3406         &omap3xxx_pre_es3_mmc2_hwmod,
3407         NULL
3408 };
3409
3410 /* 3430ES3+-only hwmods */
3411 static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
3412         &omap3xxx_es3plus_mmc1_hwmod,
3413         &omap3xxx_es3plus_mmc2_hwmod,
3414         NULL
3415 };
3416
3417 /* 34xx-only hwmods (all ES revisions) */
3418 static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
3419         &omap3xxx_iva_hwmod,
3420         &omap34xx_sr1_hwmod,
3421         &omap34xx_sr2_hwmod,
3422         &omap3xxx_mailbox_hwmod,
3423         NULL
3424 };
3425
3426 /* 36xx-only hwmods (all ES revisions) */
3427 static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
3428         &omap3xxx_iva_hwmod,
3429         &omap3xxx_uart4_hwmod,
3430         &omap3xxx_dss_core_hwmod,
3431         &omap36xx_sr1_hwmod,
3432         &omap36xx_sr2_hwmod,
3433         &omap3xxx_usbhsotg_hwmod,
3434         &omap3xxx_mailbox_hwmod,
3435         &omap3xxx_es3plus_mmc1_hwmod,
3436         &omap3xxx_es3plus_mmc2_hwmod,
3437         NULL
3438 };
3439
3440 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3441         &omap3xxx_dss_core_hwmod, /* XXX ??? */
3442         &am35xx_usbhsotg_hwmod,
3443         &omap3xxx_es3plus_mmc1_hwmod,
3444         &omap3xxx_es3plus_mmc2_hwmod,
3445         NULL
3446 };
3447
3448 static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
3449         /* dss class */
3450         &omap3xxx_dss_dispc_hwmod,
3451         &omap3xxx_dss_dsi1_hwmod,
3452         &omap3xxx_dss_rfbi_hwmod,
3453         &omap3xxx_dss_venc_hwmod,
3454         NULL
3455 };
3456
3457 int __init omap3xxx_hwmod_init(void)
3458 {
3459         int r;
3460         struct omap_hwmod **h = NULL;
3461         unsigned int rev;
3462
3463         /* Register hwmods common to all OMAP3 */
3464         r = omap_hwmod_register(omap3xxx_hwmods);
3465         if (r < 0)
3466                 return r;
3467
3468         /* Register GP-only hwmods. */
3469         if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3470                 r = omap_hwmod_register(omap3xxx_gp_hwmods);
3471                 if (r < 0)
3472                         return r;
3473         }
3474
3475         rev = omap_rev();
3476
3477         /*
3478          * Register hwmods common to individual OMAP3 families, all
3479          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3480          * All possible revisions should be included in this conditional.
3481          */
3482         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3483             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3484             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3485                 h = omap34xx_hwmods;
3486         } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3487                 h = am35xx_hwmods;
3488         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3489                    rev == OMAP3630_REV_ES1_2) {
3490                 h = omap36xx_hwmods;
3491         } else {
3492                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3493                 return -EINVAL;
3494         };
3495
3496         r = omap_hwmod_register(h);
3497         if (r < 0)
3498                 return r;
3499
3500         /*
3501          * Register hwmods specific to certain ES levels of a
3502          * particular family of silicon (e.g., 34xx ES1.0)
3503          */
3504         h = NULL;
3505         if (rev == OMAP3430_REV_ES1_0) {
3506                 h = omap3430es1_hwmods;
3507         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3508                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3509                    rev == OMAP3430_REV_ES3_1_2) {
3510                 h = omap3430es2plus_hwmods;
3511         };
3512
3513         if (h) {
3514                 r = omap_hwmod_register(h);
3515                 if (r < 0)
3516                         return r;
3517         }
3518
3519         h = NULL;
3520         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3521             rev == OMAP3430_REV_ES2_1) {
3522                 h = omap3430_pre_es3_hwmods;
3523         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3524                    rev == OMAP3430_REV_ES3_1_2) {
3525                 h = omap3430_es3plus_hwmods;
3526         };
3527
3528         if (h)
3529                 r = omap_hwmod_register(h);
3530         if (r < 0)
3531                 return r;
3532
3533         /*
3534          * DSS code presumes that dss_core hwmod is handled first,
3535          * _before_ any other DSS related hwmods so register common
3536          * DSS hwmods last to ensure that dss_core is already registered.
3537          * Otherwise some change things may happen, for ex. if dispc
3538          * is handled before dss_core and DSS is enabled in bootloader
3539          * DIPSC will be reset with outputs enabled which sometimes leads
3540          * to unrecoverable L3 error.
3541          */
3542         r = omap_hwmod_register(omap3xxx_dss_hwmods);
3543
3544         return r;
3545 }