arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "smartreflex.h"
  33 #include "prm-regbits-34xx.h"
  34 #include "cm-regbits-34xx.h"
  35 #include "wd_timer.h"
  36 #include <mach/am35xx.h>
  37
  38 /*
  39  * OMAP3xxx hardware module integration data
  40  *
  41  * ALl of the data in this section should be autogeneratable from the
  42  * TI hardware database or other technical documentation.  Data that
  43  * is driver-specific or driver-kernel integration-specific belongs
  44  * elsewhere.
  45  */
  46
  47 static struct omap_hwmod omap3xxx_mpu_hwmod;
  48 static struct omap_hwmod omap3xxx_iva_hwmod;
  49 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  51 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  52 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  53 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  58 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  61 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  67 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  68 static struct omap_hwmod omap34xx_sr1_hwmod;
  69 static struct omap_hwmod omap34xx_sr2_hwmod;
  70 static struct omap_hwmod omap34xx_mcspi1;
  71 static struct omap_hwmod omap34xx_mcspi2;
  72 static struct omap_hwmod omap34xx_mcspi3;
  73 static struct omap_hwmod omap34xx_mcspi4;
  74 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  75 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  76 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  77 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  78
  79 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  80
  81 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  83 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  87 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  88 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
  89 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
  90
  91 /* L3 -> L4_CORE interface */
  92 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  93         .master = &omap3xxx_l3_main_hwmod,
  94         .slave  = &omap3xxx_l4_core_hwmod,
  95         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  96 };
  97
  98 /* L3 -> L4_PER interface */
  99 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
 100         .master = &omap3xxx_l3_main_hwmod,
 101         .slave  = &omap3xxx_l4_per_hwmod,
 102         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 103 };
 104
 105 /* L3 taret configuration and error log registers */
 106 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 107         { .irq = INT_34XX_L3_DBG_IRQ },
 108         { .irq = INT_34XX_L3_APP_IRQ },
 109         { .irq = -1 }
 110 };
 111
 112 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 113         {
 114                 .pa_start       = 0x68000000,
 115                 .pa_end         = 0x6800ffff,
 116                 .flags          = ADDR_TYPE_RT,
 117         },
 118         { }
 119 };
 120
 121 /* MPU -> L3 interface */
 122 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 123         .master   = &omap3xxx_mpu_hwmod,
 124         .slave    = &omap3xxx_l3_main_hwmod,
 125         .addr     = omap3xxx_l3_main_addrs,
 126         .user   = OCP_USER_MPU,
 127 };
 128
 129 /* Slave interfaces on the L3 interconnect */
 130 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 131         &omap3xxx_mpu__l3_main,
 132 };
 133
 134 /* DSS -> l3 */
 135 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 136         .master         = &omap3xxx_dss_core_hwmod,
 137         .slave          = &omap3xxx_l3_main_hwmod,
 138         .fw = {
 139                 .omap2 = {
 140                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 141                         .flags  = OMAP_FIREWALL_L3,
 142                 }
 143         },
 144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 145 };
 146
 147 /* Master interfaces on the L3 interconnect */
 148 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 149         &omap3xxx_l3_main__l4_core,
 150         &omap3xxx_l3_main__l4_per,
 151 };
 152
 153 /* L3 */
 154 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 155         .name           = "l3_main",
 156         .class          = &l3_hwmod_class,
 157         .mpu_irqs       = omap3xxx_l3_main_irqs,
 158         .masters        = omap3xxx_l3_main_masters,
 159         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 160         .slaves         = omap3xxx_l3_main_slaves,
 161         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 162         .flags          = HWMOD_NO_IDLEST,
 163 };
 164
 165 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 166 static struct omap_hwmod omap3xxx_uart1_hwmod;
 167 static struct omap_hwmod omap3xxx_uart2_hwmod;
 168 static struct omap_hwmod omap3xxx_uart3_hwmod;
 169 static struct omap_hwmod omap3xxx_uart4_hwmod;
 170 static struct omap_hwmod am35xx_uart4_hwmod;
 171 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 172
 173 /* l3_core -> usbhsotg interface */
 174 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 175         .master         = &omap3xxx_usbhsotg_hwmod,
 176         .slave          = &omap3xxx_l3_main_hwmod,
 177         .clk            = "core_l3_ick",
 178         .user           = OCP_USER_MPU,
 179 };
 180
 181 /* l3_core -> am35xx_usbhsotg interface */
 182 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 183         .master         = &am35xx_usbhsotg_hwmod,
 184         .slave          = &omap3xxx_l3_main_hwmod,
 185         .clk            = "core_l3_ick",
 186         .user           = OCP_USER_MPU,
 187 };
 188 /* L4_CORE -> L4_WKUP interface */
 189 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 190         .master = &omap3xxx_l4_core_hwmod,
 191         .slave  = &omap3xxx_l4_wkup_hwmod,
 192         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 193 };
 194
 195 /* L4 CORE -> MMC1 interface */
 196 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 197         .master         = &omap3xxx_l4_core_hwmod,
 198         .slave          = &omap3xxx_mmc1_hwmod,
 199         .clk            = "mmchs1_ick",
 200         .addr           = omap2430_mmc1_addr_space,
 201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 202         .flags          = OMAP_FIREWALL_L4
 203 };
 204
 205 /* L4 CORE -> MMC2 interface */
 206 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 207         .master         = &omap3xxx_l4_core_hwmod,
 208         .slave          = &omap3xxx_mmc2_hwmod,
 209         .clk            = "mmchs2_ick",
 210         .addr           = omap2430_mmc2_addr_space,
 211         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 212         .flags          = OMAP_FIREWALL_L4
 213 };
 214
 215 /* L4 CORE -> MMC3 interface */
 216 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 217         {
 218                 .pa_start       = 0x480ad000,
 219                 .pa_end         = 0x480ad1ff,
 220                 .flags          = ADDR_TYPE_RT,
 221         },
 222         { }
 223 };
 224
 225 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 226         .master         = &omap3xxx_l4_core_hwmod,
 227         .slave          = &omap3xxx_mmc3_hwmod,
 228         .clk            = "mmchs3_ick",
 229         .addr           = omap3xxx_mmc3_addr_space,
 230         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 231         .flags          = OMAP_FIREWALL_L4
 232 };
 233
 234 /* L4 CORE -> UART1 interface */
 235 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 236         {
 237                 .pa_start       = OMAP3_UART1_BASE,
 238                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 239                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 240         },
 241         { }
 242 };
 243
 244 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 245         .master         = &omap3xxx_l4_core_hwmod,
 246         .slave          = &omap3xxx_uart1_hwmod,
 247         .clk            = "uart1_ick",
 248         .addr           = omap3xxx_uart1_addr_space,
 249         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 250 };
 251
 252 /* L4 CORE -> UART2 interface */
 253 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 254         {
 255                 .pa_start       = OMAP3_UART2_BASE,
 256                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 257                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 258         },
 259         { }
 260 };
 261
 262 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 263         .master         = &omap3xxx_l4_core_hwmod,
 264         .slave          = &omap3xxx_uart2_hwmod,
 265         .clk            = "uart2_ick",
 266         .addr           = omap3xxx_uart2_addr_space,
 267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 268 };
 269
 270 /* L4 PER -> UART3 interface */
 271 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 272         {
 273                 .pa_start       = OMAP3_UART3_BASE,
 274                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 275                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 276         },
 277         { }
 278 };
 279
 280 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 281         .master         = &omap3xxx_l4_per_hwmod,
 282         .slave          = &omap3xxx_uart3_hwmod,
 283         .clk            = "uart3_ick",
 284         .addr           = omap3xxx_uart3_addr_space,
 285         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 286 };
 287
 288 /* L4 PER -> UART4 interface */
 289 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 290         {
 291                 .pa_start       = OMAP3_UART4_BASE,
 292                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 293                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 294         },
 295         { }
 296 };
 297
 298 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 299         .master         = &omap3xxx_l4_per_hwmod,
 300         .slave          = &omap3xxx_uart4_hwmod,
 301         .clk            = "uart4_ick",
 302         .addr           = omap3xxx_uart4_addr_space,
 303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 304 };
 305
 306 /* AM35xx: L4 CORE -> UART4 interface */
 307 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
 308         {
 309                 .pa_start       = OMAP3_UART4_AM35XX_BASE,
 310                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
 311                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 312         },
 313 };
 314
 315 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
 316         .master         = &omap3xxx_l4_core_hwmod,
 317         .slave          = &am35xx_uart4_hwmod,
 318         .clk            = "uart4_ick",
 319         .addr           = am35xx_uart4_addr_space,
 320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 321 };
 322
 323 /* L4 CORE -> I2C1 interface */
 324 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 325         .master         = &omap3xxx_l4_core_hwmod,
 326         .slave          = &omap3xxx_i2c1_hwmod,
 327         .clk            = "i2c1_ick",
 328         .addr           = omap2_i2c1_addr_space,
 329         .fw = {
 330                 .omap2 = {
 331                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 332                         .l4_prot_group = 7,
 333                         .flags  = OMAP_FIREWALL_L4,
 334                 }
 335         },
 336         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 337 };
 338
 339 /* L4 CORE -> I2C2 interface */
 340 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 341         .master         = &omap3xxx_l4_core_hwmod,
 342         .slave          = &omap3xxx_i2c2_hwmod,
 343         .clk            = "i2c2_ick",
 344         .addr           = omap2_i2c2_addr_space,
 345         .fw = {
 346                 .omap2 = {
 347                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 348                         .l4_prot_group = 7,
 349                         .flags = OMAP_FIREWALL_L4,
 350                 }
 351         },
 352         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 353 };
 354
 355 /* L4 CORE -> I2C3 interface */
 356 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 357         {
 358                 .pa_start       = 0x48060000,
 359                 .pa_end         = 0x48060000 + SZ_128 - 1,
 360                 .flags          = ADDR_TYPE_RT,
 361         },
 362         { }
 363 };
 364
 365 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 366         .master         = &omap3xxx_l4_core_hwmod,
 367         .slave          = &omap3xxx_i2c3_hwmod,
 368         .clk            = "i2c3_ick",
 369         .addr           = omap3xxx_i2c3_addr_space,
 370         .fw = {
 371                 .omap2 = {
 372                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 373                         .l4_prot_group = 7,
 374                         .flags = OMAP_FIREWALL_L4,
 375                 }
 376         },
 377         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 378 };
 379
 380 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
 381         { .irq = 18},
 382         { .irq = -1 }
 383 };
 384
 385 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
 386         { .irq = 19},
 387         { .irq = -1 }
 388 };
 389
 390 /* L4 CORE -> SR1 interface */
 391 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 392         {
 393                 .pa_start       = OMAP34XX_SR1_BASE,
 394                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 395                 .flags          = ADDR_TYPE_RT,
 396         },
 397         { }
 398 };
 399
 400 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 401         .master         = &omap3xxx_l4_core_hwmod,
 402         .slave          = &omap34xx_sr1_hwmod,
 403         .clk            = "sr_l4_ick",
 404         .addr           = omap3_sr1_addr_space,
 405         .user           = OCP_USER_MPU,
 406 };
 407
 408 /* L4 CORE -> SR1 interface */
 409 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 410         {
 411                 .pa_start       = OMAP34XX_SR2_BASE,
 412                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 413                 .flags          = ADDR_TYPE_RT,
 414         },
 415         { }
 416 };
 417
 418 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 419         .master         = &omap3xxx_l4_core_hwmod,
 420         .slave          = &omap34xx_sr2_hwmod,
 421         .clk            = "sr_l4_ick",
 422         .addr           = omap3_sr2_addr_space,
 423         .user           = OCP_USER_MPU,
 424 };
 425
 426 /*
 427 * usbhsotg interface data
 428 */
 429
 430 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 431         {
 432                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 433                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 434                 .flags          = ADDR_TYPE_RT
 435         },
 436         { }
 437 };
 438
 439 /* l4_core -> usbhsotg  */
 440 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 441         .master         = &omap3xxx_l4_core_hwmod,
 442         .slave          = &omap3xxx_usbhsotg_hwmod,
 443         .clk            = "l4_ick",
 444         .addr           = omap3xxx_usbhsotg_addrs,
 445         .user           = OCP_USER_MPU,
 446 };
 447
 448 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 449         &omap3xxx_usbhsotg__l3,
 450 };
 451
 452 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 453         &omap3xxx_l4_core__usbhsotg,
 454 };
 455
 456 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 457         {
 458                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 459                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 460                 .flags          = ADDR_TYPE_RT
 461         },
 462         { }
 463 };
 464
 465 /* l4_core -> usbhsotg  */
 466 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 467         .master         = &omap3xxx_l4_core_hwmod,
 468         .slave          = &am35xx_usbhsotg_hwmod,
 469         .clk            = "l4_ick",
 470         .addr           = am35xx_usbhsotg_addrs,
 471         .user           = OCP_USER_MPU,
 472 };
 473
 474 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 475         &am35xx_usbhsotg__l3,
 476 };
 477
 478 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 479         &am35xx_l4_core__usbhsotg,
 480 };
 481 /* Slave interfaces on the L4_CORE interconnect */
 482 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 483         &omap3xxx_l3_main__l4_core,
 484 };
 485
 486 /* L4 CORE */
 487 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 488         .name           = "l4_core",
 489         .class          = &l4_hwmod_class,
 490         .slaves         = omap3xxx_l4_core_slaves,
 491         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 492         .flags          = HWMOD_NO_IDLEST,
 493 };
 494
 495 /* Slave interfaces on the L4_PER interconnect */
 496 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 497         &omap3xxx_l3_main__l4_per,
 498 };
 499
 500 /* L4 PER */
 501 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 502         .name           = "l4_per",
 503         .class          = &l4_hwmod_class,
 504         .slaves         = omap3xxx_l4_per_slaves,
 505         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 506         .flags          = HWMOD_NO_IDLEST,
 507 };
 508
 509 /* Slave interfaces on the L4_WKUP interconnect */
 510 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 511         &omap3xxx_l4_core__l4_wkup,
 512 };
 513
 514 /* L4 WKUP */
 515 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 516         .name           = "l4_wkup",
 517         .class          = &l4_hwmod_class,
 518         .slaves         = omap3xxx_l4_wkup_slaves,
 519         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 520         .flags          = HWMOD_NO_IDLEST,
 521 };
 522
 523 /* Master interfaces on the MPU device */
 524 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 525         &omap3xxx_mpu__l3_main,
 526 };
 527
 528 /* MPU */
 529 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 530         .name           = "mpu",
 531         .class          = &mpu_hwmod_class,
 532         .main_clk       = "arm_fck",
 533         .masters        = omap3xxx_mpu_masters,
 534         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 535 };
 536
 537 /*
 538  * IVA2_2 interface data
 539  */
 540
 541 /* IVA2 <- L3 interface */
 542 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 543         .master         = &omap3xxx_l3_main_hwmod,
 544         .slave          = &omap3xxx_iva_hwmod,
 545         .clk            = "iva2_ck",
 546         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 547 };
 548
 549 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 550         &omap3xxx_l3__iva,
 551 };
 552
 553 /*
 554  * IVA2 (IVA2)
 555  */
 556
 557 static struct omap_hwmod omap3xxx_iva_hwmod = {
 558         .name           = "iva",
 559         .class          = &iva_hwmod_class,
 560         .masters        = omap3xxx_iva_masters,
 561         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 562 };
 563
 564 /* timer class */
 565 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 566         .rev_offs       = 0x0000,
 567         .sysc_offs      = 0x0010,
 568         .syss_offs      = 0x0014,
 569         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 570                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 571                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 572         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 573         .sysc_fields    = &omap_hwmod_sysc_type1,
 574 };
 575
 576 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 577         .name = "timer",
 578         .sysc = &omap3xxx_timer_1ms_sysc,
 579         .rev = OMAP_TIMER_IP_VERSION_1,
 580 };
 581
 582 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 583         .rev_offs       = 0x0000,
 584         .sysc_offs      = 0x0010,
 585         .syss_offs      = 0x0014,
 586         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 587                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 588         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 589         .sysc_fields    = &omap_hwmod_sysc_type1,
 590 };
 591
 592 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 593         .name = "timer",
 594         .sysc = &omap3xxx_timer_sysc,
 595         .rev =  OMAP_TIMER_IP_VERSION_1,
 596 };
 597
 598 /* secure timers dev attribute */
 599 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 600         .timer_capability       = OMAP_TIMER_SECURE,
 601 };
 602
 603 /* always-on timers dev attribute */
 604 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 605         .timer_capability       = OMAP_TIMER_ALWON,
 606 };
 607
 608 /* pwm timers dev attribute */
 609 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 610         .timer_capability       = OMAP_TIMER_HAS_PWM,
 611 };
 612
 613 /* timer1 */
 614 static struct omap_hwmod omap3xxx_timer1_hwmod;
 615
 616 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 617         {
 618                 .pa_start       = 0x48318000,
 619                 .pa_end         = 0x48318000 + SZ_1K - 1,
 620                 .flags          = ADDR_TYPE_RT
 621         },
 622         { }
 623 };
 624
 625 /* l4_wkup -> timer1 */
 626 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 627         .master         = &omap3xxx_l4_wkup_hwmod,
 628         .slave          = &omap3xxx_timer1_hwmod,
 629         .clk            = "gpt1_ick",
 630         .addr           = omap3xxx_timer1_addrs,
 631         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 632 };
 633
 634 /* timer1 slave port */
 635 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 636         &omap3xxx_l4_wkup__timer1,
 637 };
 638
 639 /* timer1 hwmod */
 640 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 641         .name           = "timer1",
 642         .mpu_irqs       = omap2_timer1_mpu_irqs,
 643         .main_clk       = "gpt1_fck",
 644         .prcm           = {
 645                 .omap2 = {
 646                         .prcm_reg_id = 1,
 647                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 648                         .module_offs = WKUP_MOD,
 649                         .idlest_reg_id = 1,
 650                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 651                 },
 652         },
 653         .dev_attr       = &capability_alwon_dev_attr,
 654         .slaves         = omap3xxx_timer1_slaves,
 655         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 656         .class          = &omap3xxx_timer_1ms_hwmod_class,
 657 };
 658
 659 /* timer2 */
 660 static struct omap_hwmod omap3xxx_timer2_hwmod;
 661
 662 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 663         {
 664                 .pa_start       = 0x49032000,
 665                 .pa_end         = 0x49032000 + SZ_1K - 1,
 666                 .flags          = ADDR_TYPE_RT
 667         },
 668         { }
 669 };
 670
 671 /* l4_per -> timer2 */
 672 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 673         .master         = &omap3xxx_l4_per_hwmod,
 674         .slave          = &omap3xxx_timer2_hwmod,
 675         .clk            = "gpt2_ick",
 676         .addr           = omap3xxx_timer2_addrs,
 677         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 678 };
 679
 680 /* timer2 slave port */
 681 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 682         &omap3xxx_l4_per__timer2,
 683 };
 684
 685 /* timer2 hwmod */
 686 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 687         .name           = "timer2",
 688         .mpu_irqs       = omap2_timer2_mpu_irqs,
 689         .main_clk       = "gpt2_fck",
 690         .prcm           = {
 691                 .omap2 = {
 692                         .prcm_reg_id = 1,
 693                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 694                         .module_offs = OMAP3430_PER_MOD,
 695                         .idlest_reg_id = 1,
 696                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 697                 },
 698         },
 699         .dev_attr       = &capability_alwon_dev_attr,
 700         .slaves         = omap3xxx_timer2_slaves,
 701         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 702         .class          = &omap3xxx_timer_1ms_hwmod_class,
 703 };
 704
 705 /* timer3 */
 706 static struct omap_hwmod omap3xxx_timer3_hwmod;
 707
 708 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 709         {
 710                 .pa_start       = 0x49034000,
 711                 .pa_end         = 0x49034000 + SZ_1K - 1,
 712                 .flags          = ADDR_TYPE_RT
 713         },
 714         { }
 715 };
 716
 717 /* l4_per -> timer3 */
 718 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 719         .master         = &omap3xxx_l4_per_hwmod,
 720         .slave          = &omap3xxx_timer3_hwmod,
 721         .clk            = "gpt3_ick",
 722         .addr           = omap3xxx_timer3_addrs,
 723         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 724 };
 725
 726 /* timer3 slave port */
 727 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 728         &omap3xxx_l4_per__timer3,
 729 };
 730
 731 /* timer3 hwmod */
 732 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 733         .name           = "timer3",
 734         .mpu_irqs       = omap2_timer3_mpu_irqs,
 735         .main_clk       = "gpt3_fck",
 736         .prcm           = {
 737                 .omap2 = {
 738                         .prcm_reg_id = 1,
 739                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 740                         .module_offs = OMAP3430_PER_MOD,
 741                         .idlest_reg_id = 1,
 742                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 743                 },
 744         },
 745         .dev_attr       = &capability_alwon_dev_attr,
 746         .slaves         = omap3xxx_timer3_slaves,
 747         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 748         .class          = &omap3xxx_timer_hwmod_class,
 749 };
 750
 751 /* timer4 */
 752 static struct omap_hwmod omap3xxx_timer4_hwmod;
 753
 754 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 755         {
 756                 .pa_start       = 0x49036000,
 757                 .pa_end         = 0x49036000 + SZ_1K - 1,
 758                 .flags          = ADDR_TYPE_RT
 759         },
 760         { }
 761 };
 762
 763 /* l4_per -> timer4 */
 764 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 765         .master         = &omap3xxx_l4_per_hwmod,
 766         .slave          = &omap3xxx_timer4_hwmod,
 767         .clk            = "gpt4_ick",
 768         .addr           = omap3xxx_timer4_addrs,
 769         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 770 };
 771
 772 /* timer4 slave port */
 773 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 774         &omap3xxx_l4_per__timer4,
 775 };
 776
 777 /* timer4 hwmod */
 778 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 779         .name           = "timer4",
 780         .mpu_irqs       = omap2_timer4_mpu_irqs,
 781         .main_clk       = "gpt4_fck",
 782         .prcm           = {
 783                 .omap2 = {
 784                         .prcm_reg_id = 1,
 785                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 786                         .module_offs = OMAP3430_PER_MOD,
 787                         .idlest_reg_id = 1,
 788                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 789                 },
 790         },
 791         .dev_attr       = &capability_alwon_dev_attr,
 792         .slaves         = omap3xxx_timer4_slaves,
 793         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 794         .class          = &omap3xxx_timer_hwmod_class,
 795 };
 796
 797 /* timer5 */
 798 static struct omap_hwmod omap3xxx_timer5_hwmod;
 799
 800 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 801         {
 802                 .pa_start       = 0x49038000,
 803                 .pa_end         = 0x49038000 + SZ_1K - 1,
 804                 .flags          = ADDR_TYPE_RT
 805         },
 806         { }
 807 };
 808
 809 /* l4_per -> timer5 */
 810 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 811         .master         = &omap3xxx_l4_per_hwmod,
 812         .slave          = &omap3xxx_timer5_hwmod,
 813         .clk            = "gpt5_ick",
 814         .addr           = omap3xxx_timer5_addrs,
 815         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 816 };
 817
 818 /* timer5 slave port */
 819 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 820         &omap3xxx_l4_per__timer5,
 821 };
 822
 823 /* timer5 hwmod */
 824 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 825         .name           = "timer5",
 826         .mpu_irqs       = omap2_timer5_mpu_irqs,
 827         .main_clk       = "gpt5_fck",
 828         .prcm           = {
 829                 .omap2 = {
 830                         .prcm_reg_id = 1,
 831                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 832                         .module_offs = OMAP3430_PER_MOD,
 833                         .idlest_reg_id = 1,
 834                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 835                 },
 836         },
 837         .dev_attr       = &capability_alwon_dev_attr,
 838         .slaves         = omap3xxx_timer5_slaves,
 839         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 840         .class          = &omap3xxx_timer_hwmod_class,
 841 };
 842
 843 /* timer6 */
 844 static struct omap_hwmod omap3xxx_timer6_hwmod;
 845
 846 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 847         {
 848                 .pa_start       = 0x4903A000,
 849                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 850                 .flags          = ADDR_TYPE_RT
 851         },
 852         { }
 853 };
 854
 855 /* l4_per -> timer6 */
 856 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 857         .master         = &omap3xxx_l4_per_hwmod,
 858         .slave          = &omap3xxx_timer6_hwmod,
 859         .clk            = "gpt6_ick",
 860         .addr           = omap3xxx_timer6_addrs,
 861         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 862 };
 863
 864 /* timer6 slave port */
 865 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 866         &omap3xxx_l4_per__timer6,
 867 };
 868
 869 /* timer6 hwmod */
 870 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 871         .name           = "timer6",
 872         .mpu_irqs       = omap2_timer6_mpu_irqs,
 873         .main_clk       = "gpt6_fck",
 874         .prcm           = {
 875                 .omap2 = {
 876                         .prcm_reg_id = 1,
 877                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 878                         .module_offs = OMAP3430_PER_MOD,
 879                         .idlest_reg_id = 1,
 880                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 881                 },
 882         },
 883         .dev_attr       = &capability_alwon_dev_attr,
 884         .slaves         = omap3xxx_timer6_slaves,
 885         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 886         .class          = &omap3xxx_timer_hwmod_class,
 887 };
 888
 889 /* timer7 */
 890 static struct omap_hwmod omap3xxx_timer7_hwmod;
 891
 892 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 893         {
 894                 .pa_start       = 0x4903C000,
 895                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 896                 .flags          = ADDR_TYPE_RT
 897         },
 898         { }
 899 };
 900
 901 /* l4_per -> timer7 */
 902 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 903         .master         = &omap3xxx_l4_per_hwmod,
 904         .slave          = &omap3xxx_timer7_hwmod,
 905         .clk            = "gpt7_ick",
 906         .addr           = omap3xxx_timer7_addrs,
 907         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 908 };
 909
 910 /* timer7 slave port */
 911 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 912         &omap3xxx_l4_per__timer7,
 913 };
 914
 915 /* timer7 hwmod */
 916 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 917         .name           = "timer7",
 918         .mpu_irqs       = omap2_timer7_mpu_irqs,
 919         .main_clk       = "gpt7_fck",
 920         .prcm           = {
 921                 .omap2 = {
 922                         .prcm_reg_id = 1,
 923                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 924                         .module_offs = OMAP3430_PER_MOD,
 925                         .idlest_reg_id = 1,
 926                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 927                 },
 928         },
 929         .dev_attr       = &capability_alwon_dev_attr,
 930         .slaves         = omap3xxx_timer7_slaves,
 931         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 932         .class          = &omap3xxx_timer_hwmod_class,
 933 };
 934
 935 /* timer8 */
 936 static struct omap_hwmod omap3xxx_timer8_hwmod;
 937
 938 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 939         {
 940                 .pa_start       = 0x4903E000,
 941                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 942                 .flags          = ADDR_TYPE_RT
 943         },
 944         { }
 945 };
 946
 947 /* l4_per -> timer8 */
 948 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 949         .master         = &omap3xxx_l4_per_hwmod,
 950         .slave          = &omap3xxx_timer8_hwmod,
 951         .clk            = "gpt8_ick",
 952         .addr           = omap3xxx_timer8_addrs,
 953         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 954 };
 955
 956 /* timer8 slave port */
 957 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 958         &omap3xxx_l4_per__timer8,
 959 };
 960
 961 /* timer8 hwmod */
 962 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 963         .name           = "timer8",
 964         .mpu_irqs       = omap2_timer8_mpu_irqs,
 965         .main_clk       = "gpt8_fck",
 966         .prcm           = {
 967                 .omap2 = {
 968                         .prcm_reg_id = 1,
 969                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 970                         .module_offs = OMAP3430_PER_MOD,
 971                         .idlest_reg_id = 1,
 972                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 973                 },
 974         },
 975         .dev_attr       = &capability_pwm_dev_attr,
 976         .slaves         = omap3xxx_timer8_slaves,
 977         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
 978         .class          = &omap3xxx_timer_hwmod_class,
 979 };
 980
 981 /* timer9 */
 982 static struct omap_hwmod omap3xxx_timer9_hwmod;
 983
 984 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
 985         {
 986                 .pa_start       = 0x49040000,
 987                 .pa_end         = 0x49040000 + SZ_1K - 1,
 988                 .flags          = ADDR_TYPE_RT
 989         },
 990         { }
 991 };
 992
 993 /* l4_per -> timer9 */
 994 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
 995         .master         = &omap3xxx_l4_per_hwmod,
 996         .slave          = &omap3xxx_timer9_hwmod,
 997         .clk            = "gpt9_ick",
 998         .addr           = omap3xxx_timer9_addrs,
 999         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1000 };
1001
1002 /* timer9 slave port */
1003 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1004         &omap3xxx_l4_per__timer9,
1005 };
1006
1007 /* timer9 hwmod */
1008 static struct omap_hwmod omap3xxx_timer9_hwmod = {
1009         .name           = "timer9",
1010         .mpu_irqs       = omap2_timer9_mpu_irqs,
1011         .main_clk       = "gpt9_fck",
1012         .prcm           = {
1013                 .omap2 = {
1014                         .prcm_reg_id = 1,
1015                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
1016                         .module_offs = OMAP3430_PER_MOD,
1017                         .idlest_reg_id = 1,
1018                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1019                 },
1020         },
1021         .dev_attr       = &capability_pwm_dev_attr,
1022         .slaves         = omap3xxx_timer9_slaves,
1023         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
1024         .class          = &omap3xxx_timer_hwmod_class,
1025 };
1026
1027 /* timer10 */
1028 static struct omap_hwmod omap3xxx_timer10_hwmod;
1029
1030 /* l4_core -> timer10 */
1031 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1032         .master         = &omap3xxx_l4_core_hwmod,
1033         .slave          = &omap3xxx_timer10_hwmod,
1034         .clk            = "gpt10_ick",
1035         .addr           = omap2_timer10_addrs,
1036         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1037 };
1038
1039 /* timer10 slave port */
1040 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1041         &omap3xxx_l4_core__timer10,
1042 };
1043
1044 /* timer10 hwmod */
1045 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1046         .name           = "timer10",
1047         .mpu_irqs       = omap2_timer10_mpu_irqs,
1048         .main_clk       = "gpt10_fck",
1049         .prcm           = {
1050                 .omap2 = {
1051                         .prcm_reg_id = 1,
1052                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1053                         .module_offs = CORE_MOD,
1054                         .idlest_reg_id = 1,
1055                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1056                 },
1057         },
1058         .dev_attr       = &capability_pwm_dev_attr,
1059         .slaves         = omap3xxx_timer10_slaves,
1060         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1061         .class          = &omap3xxx_timer_1ms_hwmod_class,
1062 };
1063
1064 /* timer11 */
1065 static struct omap_hwmod omap3xxx_timer11_hwmod;
1066
1067 /* l4_core -> timer11 */
1068 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1069         .master         = &omap3xxx_l4_core_hwmod,
1070         .slave          = &omap3xxx_timer11_hwmod,
1071         .clk            = "gpt11_ick",
1072         .addr           = omap2_timer11_addrs,
1073         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1074 };
1075
1076 /* timer11 slave port */
1077 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1078         &omap3xxx_l4_core__timer11,
1079 };
1080
1081 /* timer11 hwmod */
1082 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1083         .name           = "timer11",
1084         .mpu_irqs       = omap2_timer11_mpu_irqs,
1085         .main_clk       = "gpt11_fck",
1086         .prcm           = {
1087                 .omap2 = {
1088                         .prcm_reg_id = 1,
1089                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1090                         .module_offs = CORE_MOD,
1091                         .idlest_reg_id = 1,
1092                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1093                 },
1094         },
1095         .dev_attr       = &capability_pwm_dev_attr,
1096         .slaves         = omap3xxx_timer11_slaves,
1097         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1098         .class          = &omap3xxx_timer_hwmod_class,
1099 };
1100
1101 /* timer12*/
1102 static struct omap_hwmod omap3xxx_timer12_hwmod;
1103 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1104         { .irq = 95, },
1105         { .irq = -1 }
1106 };
1107
1108 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1109         {
1110                 .pa_start       = 0x48304000,
1111                 .pa_end         = 0x48304000 + SZ_1K - 1,
1112                 .flags          = ADDR_TYPE_RT
1113         },
1114         { }
1115 };
1116
1117 /* l4_core -> timer12 */
1118 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1119         .master         = &omap3xxx_l4_core_hwmod,
1120         .slave          = &omap3xxx_timer12_hwmod,
1121         .clk            = "gpt12_ick",
1122         .addr           = omap3xxx_timer12_addrs,
1123         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1124 };
1125
1126 /* timer12 slave port */
1127 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1128         &omap3xxx_l4_core__timer12,
1129 };
1130
1131 /* timer12 hwmod */
1132 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1133         .name           = "timer12",
1134         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1135         .main_clk       = "gpt12_fck",
1136         .prcm           = {
1137                 .omap2 = {
1138                         .prcm_reg_id = 1,
1139                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1140                         .module_offs = WKUP_MOD,
1141                         .idlest_reg_id = 1,
1142                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1143                 },
1144         },
1145         .dev_attr       = &capability_secure_dev_attr,
1146         .slaves         = omap3xxx_timer12_slaves,
1147         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1148         .class          = &omap3xxx_timer_hwmod_class,
1149 };
1150
1151 /* l4_wkup -> wd_timer2 */
1152 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1153         {
1154                 .pa_start       = 0x48314000,
1155                 .pa_end         = 0x4831407f,
1156                 .flags          = ADDR_TYPE_RT
1157         },
1158         { }
1159 };
1160
1161 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1162         .master         = &omap3xxx_l4_wkup_hwmod,
1163         .slave          = &omap3xxx_wd_timer2_hwmod,
1164         .clk            = "wdt2_ick",
1165         .addr           = omap3xxx_wd_timer2_addrs,
1166         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1167 };
1168
1169 /*
1170  * 'wd_timer' class
1171  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1172  * overflow condition
1173  */
1174
1175 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1176         .rev_offs       = 0x0000,
1177         .sysc_offs      = 0x0010,
1178         .syss_offs      = 0x0014,
1179         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1180                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1181                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1182                            SYSS_HAS_RESET_STATUS),
1183         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1184         .sysc_fields    = &omap_hwmod_sysc_type1,
1185 };
1186
1187 /* I2C common */
1188 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1189         .rev_offs       = 0x00,
1190         .sysc_offs      = 0x20,
1191         .syss_offs      = 0x10,
1192         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1193                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1194                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1195         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1196         .clockact       = CLOCKACT_TEST_ICLK,
1197         .sysc_fields    = &omap_hwmod_sysc_type1,
1198 };
1199
1200 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1201         .name           = "wd_timer",
1202         .sysc           = &omap3xxx_wd_timer_sysc,
1203         .pre_shutdown   = &omap2_wd_timer_disable
1204 };
1205
1206 /* wd_timer2 */
1207 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1208         &omap3xxx_l4_wkup__wd_timer2,
1209 };
1210
1211 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1212         .name           = "wd_timer2",
1213         .class          = &omap3xxx_wd_timer_hwmod_class,
1214         .main_clk       = "wdt2_fck",
1215         .prcm           = {
1216                 .omap2 = {
1217                         .prcm_reg_id = 1,
1218                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1219                         .module_offs = WKUP_MOD,
1220                         .idlest_reg_id = 1,
1221                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1222                 },
1223         },
1224         .slaves         = omap3xxx_wd_timer2_slaves,
1225         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1226         /*
1227          * XXX: Use software supervised mode, HW supervised smartidle seems to
1228          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1229          */
1230         .flags          = HWMOD_SWSUP_SIDLE,
1231 };
1232
1233 /* UART1 */
1234
1235 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1236         &omap3_l4_core__uart1,
1237 };
1238
1239 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1240         .name           = "uart1",
1241         .mpu_irqs       = omap2_uart1_mpu_irqs,
1242         .sdma_reqs      = omap2_uart1_sdma_reqs,
1243         .main_clk       = "uart1_fck",
1244         .prcm           = {
1245                 .omap2 = {
1246                         .module_offs = CORE_MOD,
1247                         .prcm_reg_id = 1,
1248                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1249                         .idlest_reg_id = 1,
1250                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1251                 },
1252         },
1253         .slaves         = omap3xxx_uart1_slaves,
1254         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1255         .class          = &omap2_uart_class,
1256 };
1257
1258 /* UART2 */
1259
1260 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1261         &omap3_l4_core__uart2,
1262 };
1263
1264 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1265         .name           = "uart2",
1266         .mpu_irqs       = omap2_uart2_mpu_irqs,
1267         .sdma_reqs      = omap2_uart2_sdma_reqs,
1268         .main_clk       = "uart2_fck",
1269         .prcm           = {
1270                 .omap2 = {
1271                         .module_offs = CORE_MOD,
1272                         .prcm_reg_id = 1,
1273                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1274                         .idlest_reg_id = 1,
1275                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1276                 },
1277         },
1278         .slaves         = omap3xxx_uart2_slaves,
1279         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1280         .class          = &omap2_uart_class,
1281 };
1282
1283 /* UART3 */
1284
1285 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1286         &omap3_l4_per__uart3,
1287 };
1288
1289 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1290         .name           = "uart3",
1291         .mpu_irqs       = omap2_uart3_mpu_irqs,
1292         .sdma_reqs      = omap2_uart3_sdma_reqs,
1293         .main_clk       = "uart3_fck",
1294         .prcm           = {
1295                 .omap2 = {
1296                         .module_offs = OMAP3430_PER_MOD,
1297                         .prcm_reg_id = 1,
1298                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1299                         .idlest_reg_id = 1,
1300                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1301                 },
1302         },
1303         .slaves         = omap3xxx_uart3_slaves,
1304         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1305         .class          = &omap2_uart_class,
1306 };
1307
1308 /* UART4 */
1309
1310 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1311         { .irq = INT_36XX_UART4_IRQ, },
1312         { .irq = -1 }
1313 };
1314
1315 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1316         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1317         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1318         { .dma_req = -1 }
1319 };
1320
1321 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1322         &omap3_l4_per__uart4,
1323 };
1324
1325 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1326         .name           = "uart4",
1327         .mpu_irqs       = uart4_mpu_irqs,
1328         .sdma_reqs      = uart4_sdma_reqs,
1329         .main_clk       = "uart4_fck",
1330         .prcm           = {
1331                 .omap2 = {
1332                         .module_offs = OMAP3430_PER_MOD,
1333                         .prcm_reg_id = 1,
1334                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1335                         .idlest_reg_id = 1,
1336                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1337                 },
1338         },
1339         .slaves         = omap3xxx_uart4_slaves,
1340         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1341         .class          = &omap2_uart_class,
1342 };
1343
1344 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
1345         { .irq = INT_35XX_UART4_IRQ, },
1346 };
1347
1348 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
1349         { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
1350         { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
1351 };
1352
1353 static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = {
1354         &am35xx_l4_core__uart4,
1355 };
1356
1357 static struct omap_hwmod am35xx_uart4_hwmod = {
1358         .name           = "uart4",
1359         .mpu_irqs       = am35xx_uart4_mpu_irqs,
1360         .sdma_reqs      = am35xx_uart4_sdma_reqs,
1361         .main_clk       = "uart4_fck",
1362         .prcm           = {
1363                 .omap2 = {
1364                         .module_offs = CORE_MOD,
1365                         .prcm_reg_id = 1,
1366                         .module_bit = OMAP3430_EN_UART4_SHIFT,
1367                         .idlest_reg_id = 1,
1368                         .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
1369                 },
1370         },
1371         .slaves         = am35xx_uart4_slaves,
1372         .slaves_cnt     = ARRAY_SIZE(am35xx_uart4_slaves),
1373         .class          = &omap2_uart_class,
1374 };
1375
1376
1377 static struct omap_hwmod_class i2c_class = {
1378         .name   = "i2c",
1379         .sysc   = &i2c_sysc,
1380         .rev    = OMAP_I2C_IP_VERSION_1,
1381         .reset  = &omap_i2c_reset,
1382 };
1383
1384 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1385         { .name = "dispc", .dma_req = 5 },
1386         { .name = "dsi1", .dma_req = 74 },
1387         { .dma_req = -1 }
1388 };
1389
1390 /* dss */
1391 /* dss master ports */
1392 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1393         &omap3xxx_dss__l3,
1394 };
1395
1396 /* l4_core -> dss */
1397 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1398         .master         = &omap3xxx_l4_core_hwmod,
1399         .slave          = &omap3430es1_dss_core_hwmod,
1400         .clk            = "dss_ick",
1401         .addr           = omap2_dss_addrs,
1402         .fw = {
1403                 .omap2 = {
1404                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1405                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1406                         .flags  = OMAP_FIREWALL_L4,
1407                 }
1408         },
1409         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1410 };
1411
1412 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1413         .master         = &omap3xxx_l4_core_hwmod,
1414         .slave          = &omap3xxx_dss_core_hwmod,
1415         .clk            = "dss_ick",
1416         .addr           = omap2_dss_addrs,
1417         .fw = {
1418                 .omap2 = {
1419                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1420                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1421                         .flags  = OMAP_FIREWALL_L4,
1422                 }
1423         },
1424         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1425 };
1426
1427 /* dss slave ports */
1428 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1429         &omap3430es1_l4_core__dss,
1430 };
1431
1432 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1433         &omap3xxx_l4_core__dss,
1434 };
1435
1436 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1437         /*
1438          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1439          * driver does not use these clocks.
1440          */
1441         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1442         { .role = "tv_clk", .clk = "dss_tv_fck" },
1443         /* required only on OMAP3430 */
1444         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1445 };
1446
1447 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1448         .name           = "dss_core",
1449         .class          = &omap2_dss_hwmod_class,
1450         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1451         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1452         .prcm           = {
1453                 .omap2 = {
1454                         .prcm_reg_id = 1,
1455                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1456                         .module_offs = OMAP3430_DSS_MOD,
1457                         .idlest_reg_id = 1,
1458                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1459                 },
1460         },
1461         .opt_clks       = dss_opt_clks,
1462         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1463         .slaves         = omap3430es1_dss_slaves,
1464         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1465         .masters        = omap3xxx_dss_masters,
1466         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1467         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1468 };
1469
1470 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1471         .name           = "dss_core",
1472         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1473         .class          = &omap2_dss_hwmod_class,
1474         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1475         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1476         .prcm           = {
1477                 .omap2 = {
1478                         .prcm_reg_id = 1,
1479                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1480                         .module_offs = OMAP3430_DSS_MOD,
1481                         .idlest_reg_id = 1,
1482                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1483                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1484                 },
1485         },
1486         .opt_clks       = dss_opt_clks,
1487         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1488         .slaves         = omap3xxx_dss_slaves,
1489         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1490         .masters        = omap3xxx_dss_masters,
1491         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1492 };
1493
1494 /*
1495  * 'dispc' class
1496  * display controller
1497  */
1498
1499 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
1500         .rev_offs       = 0x0000,
1501         .sysc_offs      = 0x0010,
1502         .syss_offs      = 0x0014,
1503         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1504                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1505                            SYSC_HAS_ENAWAKEUP),
1506         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1507                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1508         .sysc_fields    = &omap_hwmod_sysc_type1,
1509 };
1510
1511 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1512         .name   = "dispc",
1513         .sysc   = &omap3_dispc_sysc,
1514 };
1515
1516 /* l4_core -> dss_dispc */
1517 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1518         .master         = &omap3xxx_l4_core_hwmod,
1519         .slave          = &omap3xxx_dss_dispc_hwmod,
1520         .clk            = "dss_ick",
1521         .addr           = omap2_dss_dispc_addrs,
1522         .fw = {
1523                 .omap2 = {
1524                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1525                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1526                         .flags  = OMAP_FIREWALL_L4,
1527                 }
1528         },
1529         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1530 };
1531
1532 /* dss_dispc slave ports */
1533 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1534         &omap3xxx_l4_core__dss_dispc,
1535 };
1536
1537 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1538         .name           = "dss_dispc",
1539         .class          = &omap3_dispc_hwmod_class,
1540         .mpu_irqs       = omap2_dispc_irqs,
1541         .main_clk       = "dss1_alwon_fck",
1542         .prcm           = {
1543                 .omap2 = {
1544                         .prcm_reg_id = 1,
1545                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1546                         .module_offs = OMAP3430_DSS_MOD,
1547                 },
1548         },
1549         .slaves         = omap3xxx_dss_dispc_slaves,
1550         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1551         .flags          = HWMOD_NO_IDLEST,
1552         .dev_attr       = &omap2_3_dss_dispc_dev_attr
1553 };
1554
1555 /*
1556  * 'dsi' class
1557  * display serial interface controller
1558  */
1559
1560 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1561         .name = "dsi",
1562 };
1563
1564 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1565         { .irq = 25 },
1566         { .irq = -1 }
1567 };
1568
1569 /* dss_dsi1 */
1570 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1571         {
1572                 .pa_start       = 0x4804FC00,
1573                 .pa_end         = 0x4804FFFF,
1574                 .flags          = ADDR_TYPE_RT
1575         },
1576         { }
1577 };
1578
1579 /* l4_core -> dss_dsi1 */
1580 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1581         .master         = &omap3xxx_l4_core_hwmod,
1582         .slave          = &omap3xxx_dss_dsi1_hwmod,
1583         .clk            = "dss_ick",
1584         .addr           = omap3xxx_dss_dsi1_addrs,
1585         .fw = {
1586                 .omap2 = {
1587                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1588                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1589                         .flags  = OMAP_FIREWALL_L4,
1590                 }
1591         },
1592         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1593 };
1594
1595 /* dss_dsi1 slave ports */
1596 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1597         &omap3xxx_l4_core__dss_dsi1,
1598 };
1599
1600 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1601         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1602 };
1603
1604 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1605         .name           = "dss_dsi1",
1606         .class          = &omap3xxx_dsi_hwmod_class,
1607         .mpu_irqs       = omap3xxx_dsi1_irqs,
1608         .main_clk       = "dss1_alwon_fck",
1609         .prcm           = {
1610                 .omap2 = {
1611                         .prcm_reg_id = 1,
1612                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1613                         .module_offs = OMAP3430_DSS_MOD,
1614                 },
1615         },
1616         .opt_clks       = dss_dsi1_opt_clks,
1617         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1618         .slaves         = omap3xxx_dss_dsi1_slaves,
1619         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1620         .flags          = HWMOD_NO_IDLEST,
1621 };
1622
1623 /* l4_core -> dss_rfbi */
1624 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1625         .master         = &omap3xxx_l4_core_hwmod,
1626         .slave          = &omap3xxx_dss_rfbi_hwmod,
1627         .clk            = "dss_ick",
1628         .addr           = omap2_dss_rfbi_addrs,
1629         .fw = {
1630                 .omap2 = {
1631                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1632                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1633                         .flags  = OMAP_FIREWALL_L4,
1634                 }
1635         },
1636         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1637 };
1638
1639 /* dss_rfbi slave ports */
1640 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1641         &omap3xxx_l4_core__dss_rfbi,
1642 };
1643
1644 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1645         { .role = "ick", .clk = "dss_ick" },
1646 };
1647
1648 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1649         .name           = "dss_rfbi",
1650         .class          = &omap2_rfbi_hwmod_class,
1651         .main_clk       = "dss1_alwon_fck",
1652         .prcm           = {
1653                 .omap2 = {
1654                         .prcm_reg_id = 1,
1655                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1656                         .module_offs = OMAP3430_DSS_MOD,
1657                 },
1658         },
1659         .opt_clks       = dss_rfbi_opt_clks,
1660         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1661         .slaves         = omap3xxx_dss_rfbi_slaves,
1662         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1663         .flags          = HWMOD_NO_IDLEST,
1664 };
1665
1666 /* l4_core -> dss_venc */
1667 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1668         .master         = &omap3xxx_l4_core_hwmod,
1669         .slave          = &omap3xxx_dss_venc_hwmod,
1670         .clk            = "dss_ick",
1671         .addr           = omap2_dss_venc_addrs,
1672         .fw = {
1673                 .omap2 = {
1674                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1675                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1676                         .flags  = OMAP_FIREWALL_L4,
1677                 }
1678         },
1679         .flags          = OCPIF_SWSUP_IDLE,
1680         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1681 };
1682
1683 /* dss_venc slave ports */
1684 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1685         &omap3xxx_l4_core__dss_venc,
1686 };
1687
1688 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1689         /* required only on OMAP3430 */
1690         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1691 };
1692
1693 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1694         .name           = "dss_venc",
1695         .class          = &omap2_venc_hwmod_class,
1696         .main_clk       = "dss_tv_fck",
1697         .prcm           = {
1698                 .omap2 = {
1699                         .prcm_reg_id = 1,
1700                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1701                         .module_offs = OMAP3430_DSS_MOD,
1702                 },
1703         },
1704         .opt_clks       = dss_venc_opt_clks,
1705         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
1706         .slaves         = omap3xxx_dss_venc_slaves,
1707         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1708         .flags          = HWMOD_NO_IDLEST,
1709 };
1710
1711 /* I2C1 */
1712
1713 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1714         .fifo_depth     = 8, /* bytes */
1715         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1716                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1717                           OMAP_I2C_FLAG_BUS_SHIFT_2,
1718 };
1719
1720 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1721         &omap3_l4_core__i2c1,
1722 };
1723
1724 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1725         .name           = "i2c1",
1726         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1727         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1728         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1729         .main_clk       = "i2c1_fck",
1730         .prcm           = {
1731                 .omap2 = {
1732                         .module_offs = CORE_MOD,
1733                         .prcm_reg_id = 1,
1734                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1735                         .idlest_reg_id = 1,
1736                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1737                 },
1738         },
1739         .slaves         = omap3xxx_i2c1_slaves,
1740         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1741         .class          = &i2c_class,
1742         .dev_attr       = &i2c1_dev_attr,
1743 };
1744
1745 /* I2C2 */
1746
1747 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1748         .fifo_depth     = 8, /* bytes */
1749         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1750                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1751                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1752 };
1753
1754 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1755         &omap3_l4_core__i2c2,
1756 };
1757
1758 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1759         .name           = "i2c2",
1760         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1761         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1762         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1763         .main_clk       = "i2c2_fck",
1764         .prcm           = {
1765                 .omap2 = {
1766                         .module_offs = CORE_MOD,
1767                         .prcm_reg_id = 1,
1768                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1769                         .idlest_reg_id = 1,
1770                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1771                 },
1772         },
1773         .slaves         = omap3xxx_i2c2_slaves,
1774         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1775         .class          = &i2c_class,
1776         .dev_attr       = &i2c2_dev_attr,
1777 };
1778
1779 /* I2C3 */
1780
1781 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1782         .fifo_depth     = 64, /* bytes */
1783         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1784                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1785                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1786 };
1787
1788 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1789         { .irq = INT_34XX_I2C3_IRQ, },
1790         { .irq = -1 }
1791 };
1792
1793 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1794         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1795         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1796         { .dma_req = -1 }
1797 };
1798
1799 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1800         &omap3_l4_core__i2c3,
1801 };
1802
1803 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1804         .name           = "i2c3",
1805         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1806         .mpu_irqs       = i2c3_mpu_irqs,
1807         .sdma_reqs      = i2c3_sdma_reqs,
1808         .main_clk       = "i2c3_fck",
1809         .prcm           = {
1810                 .omap2 = {
1811                         .module_offs = CORE_MOD,
1812                         .prcm_reg_id = 1,
1813                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1814                         .idlest_reg_id = 1,
1815                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1816                 },
1817         },
1818         .slaves         = omap3xxx_i2c3_slaves,
1819         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1820         .class          = &i2c_class,
1821         .dev_attr       = &i2c3_dev_attr,
1822 };
1823
1824 /* l4_wkup -> gpio1 */
1825 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1826         {
1827                 .pa_start       = 0x48310000,
1828                 .pa_end         = 0x483101ff,
1829                 .flags          = ADDR_TYPE_RT
1830         },
1831         { }
1832 };
1833
1834 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1835         .master         = &omap3xxx_l4_wkup_hwmod,
1836         .slave          = &omap3xxx_gpio1_hwmod,
1837         .addr           = omap3xxx_gpio1_addrs,
1838         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1839 };
1840
1841 /* l4_per -> gpio2 */
1842 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1843         {
1844                 .pa_start       = 0x49050000,
1845                 .pa_end         = 0x490501ff,
1846                 .flags          = ADDR_TYPE_RT
1847         },
1848         { }
1849 };
1850
1851 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1852         .master         = &omap3xxx_l4_per_hwmod,
1853         .slave          = &omap3xxx_gpio2_hwmod,
1854         .addr           = omap3xxx_gpio2_addrs,
1855         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1856 };
1857
1858 /* l4_per -> gpio3 */
1859 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1860         {
1861                 .pa_start       = 0x49052000,
1862                 .pa_end         = 0x490521ff,
1863                 .flags          = ADDR_TYPE_RT
1864         },
1865         { }
1866 };
1867
1868 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1869         .master         = &omap3xxx_l4_per_hwmod,
1870         .slave          = &omap3xxx_gpio3_hwmod,
1871         .addr           = omap3xxx_gpio3_addrs,
1872         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1873 };
1874
1875 /* l4_per -> gpio4 */
1876 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1877         {
1878                 .pa_start       = 0x49054000,
1879                 .pa_end         = 0x490541ff,
1880                 .flags          = ADDR_TYPE_RT
1881         },
1882         { }
1883 };
1884
1885 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1886         .master         = &omap3xxx_l4_per_hwmod,
1887         .slave          = &omap3xxx_gpio4_hwmod,
1888         .addr           = omap3xxx_gpio4_addrs,
1889         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1890 };
1891
1892 /* l4_per -> gpio5 */
1893 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1894         {
1895                 .pa_start       = 0x49056000,
1896                 .pa_end         = 0x490561ff,
1897                 .flags          = ADDR_TYPE_RT
1898         },
1899         { }
1900 };
1901
1902 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1903         .master         = &omap3xxx_l4_per_hwmod,
1904         .slave          = &omap3xxx_gpio5_hwmod,
1905         .addr           = omap3xxx_gpio5_addrs,
1906         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1907 };
1908
1909 /* l4_per -> gpio6 */
1910 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1911         {
1912                 .pa_start       = 0x49058000,
1913                 .pa_end         = 0x490581ff,
1914                 .flags          = ADDR_TYPE_RT
1915         },
1916         { }
1917 };
1918
1919 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1920         .master         = &omap3xxx_l4_per_hwmod,
1921         .slave          = &omap3xxx_gpio6_hwmod,
1922         .addr           = omap3xxx_gpio6_addrs,
1923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1924 };
1925
1926 /*
1927  * 'gpio' class
1928  * general purpose io module
1929  */
1930
1931 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1932         .rev_offs       = 0x0000,
1933         .sysc_offs      = 0x0010,
1934         .syss_offs      = 0x0014,
1935         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1936                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1937                            SYSS_HAS_RESET_STATUS),
1938         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1939         .sysc_fields    = &omap_hwmod_sysc_type1,
1940 };
1941
1942 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1943         .name = "gpio",
1944         .sysc = &omap3xxx_gpio_sysc,
1945         .rev = 1,
1946 };
1947
1948 /* gpio_dev_attr*/
1949 static struct omap_gpio_dev_attr gpio_dev_attr = {
1950         .bank_width = 32,
1951         .dbck_flag = true,
1952 };
1953
1954 /* gpio1 */
1955 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1956         { .role = "dbclk", .clk = "gpio1_dbck", },
1957 };
1958
1959 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1960         &omap3xxx_l4_wkup__gpio1,
1961 };
1962
1963 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1964         .name           = "gpio1",
1965         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1966         .mpu_irqs       = omap2_gpio1_irqs,
1967         .main_clk       = "gpio1_ick",
1968         .opt_clks       = gpio1_opt_clks,
1969         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1970         .prcm           = {
1971                 .omap2 = {
1972                         .prcm_reg_id = 1,
1973                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1974                         .module_offs = WKUP_MOD,
1975                         .idlest_reg_id = 1,
1976                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1977                 },
1978         },
1979         .slaves         = omap3xxx_gpio1_slaves,
1980         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1981         .class          = &omap3xxx_gpio_hwmod_class,
1982         .dev_attr       = &gpio_dev_attr,
1983 };
1984
1985 /* gpio2 */
1986 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1987         { .role = "dbclk", .clk = "gpio2_dbck", },
1988 };
1989
1990 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1991         &omap3xxx_l4_per__gpio2,
1992 };
1993
1994 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1995         .name           = "gpio2",
1996         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1997         .mpu_irqs       = omap2_gpio2_irqs,
1998         .main_clk       = "gpio2_ick",
1999         .opt_clks       = gpio2_opt_clks,
2000         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
2001         .prcm           = {
2002                 .omap2 = {
2003                         .prcm_reg_id = 1,
2004                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
2005                         .module_offs = OMAP3430_PER_MOD,
2006                         .idlest_reg_id = 1,
2007                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2008                 },
2009         },
2010         .slaves         = omap3xxx_gpio2_slaves,
2011         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2012         .class          = &omap3xxx_gpio_hwmod_class,
2013         .dev_attr       = &gpio_dev_attr,
2014 };
2015
2016 /* gpio3 */
2017 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2018         { .role = "dbclk", .clk = "gpio3_dbck", },
2019 };
2020
2021 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2022         &omap3xxx_l4_per__gpio3,
2023 };
2024
2025 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2026         .name           = "gpio3",
2027         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2028         .mpu_irqs       = omap2_gpio3_irqs,
2029         .main_clk       = "gpio3_ick",
2030         .opt_clks       = gpio3_opt_clks,
2031         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
2032         .prcm           = {
2033                 .omap2 = {
2034                         .prcm_reg_id = 1,
2035                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2036                         .module_offs = OMAP3430_PER_MOD,
2037                         .idlest_reg_id = 1,
2038                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2039                 },
2040         },
2041         .slaves         = omap3xxx_gpio3_slaves,
2042         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2043         .class          = &omap3xxx_gpio_hwmod_class,
2044         .dev_attr       = &gpio_dev_attr,
2045 };
2046
2047 /* gpio4 */
2048 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2049         { .role = "dbclk", .clk = "gpio4_dbck", },
2050 };
2051
2052 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2053         &omap3xxx_l4_per__gpio4,
2054 };
2055
2056 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2057         .name           = "gpio4",
2058         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2059         .mpu_irqs       = omap2_gpio4_irqs,
2060         .main_clk       = "gpio4_ick",
2061         .opt_clks       = gpio4_opt_clks,
2062         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2063         .prcm           = {
2064                 .omap2 = {
2065                         .prcm_reg_id = 1,
2066                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2067                         .module_offs = OMAP3430_PER_MOD,
2068                         .idlest_reg_id = 1,
2069                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2070                 },
2071         },
2072         .slaves         = omap3xxx_gpio4_slaves,
2073         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2074         .class          = &omap3xxx_gpio_hwmod_class,
2075         .dev_attr       = &gpio_dev_attr,
2076 };
2077
2078 /* gpio5 */
2079 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2080         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2081         { .irq = -1 }
2082 };
2083
2084 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2085         { .role = "dbclk", .clk = "gpio5_dbck", },
2086 };
2087
2088 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2089         &omap3xxx_l4_per__gpio5,
2090 };
2091
2092 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2093         .name           = "gpio5",
2094         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2095         .mpu_irqs       = omap3xxx_gpio5_irqs,
2096         .main_clk       = "gpio5_ick",
2097         .opt_clks       = gpio5_opt_clks,
2098         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2099         .prcm           = {
2100                 .omap2 = {
2101                         .prcm_reg_id = 1,
2102                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2103                         .module_offs = OMAP3430_PER_MOD,
2104                         .idlest_reg_id = 1,
2105                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2106                 },
2107         },
2108         .slaves         = omap3xxx_gpio5_slaves,
2109         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2110         .class          = &omap3xxx_gpio_hwmod_class,
2111         .dev_attr       = &gpio_dev_attr,
2112 };
2113
2114 /* gpio6 */
2115 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2116         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2117         { .irq = -1 }
2118 };
2119
2120 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2121         { .role = "dbclk", .clk = "gpio6_dbck", },
2122 };
2123
2124 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2125         &omap3xxx_l4_per__gpio6,
2126 };
2127
2128 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2129         .name           = "gpio6",
2130         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2131         .mpu_irqs       = omap3xxx_gpio6_irqs,
2132         .main_clk       = "gpio6_ick",
2133         .opt_clks       = gpio6_opt_clks,
2134         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2135         .prcm           = {
2136                 .omap2 = {
2137                         .prcm_reg_id = 1,
2138                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2139                         .module_offs = OMAP3430_PER_MOD,
2140                         .idlest_reg_id = 1,
2141                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2142                 },
2143         },
2144         .slaves         = omap3xxx_gpio6_slaves,
2145         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2146         .class          = &omap3xxx_gpio_hwmod_class,
2147         .dev_attr       = &gpio_dev_attr,
2148 };
2149
2150 /* dma_system -> L3 */
2151 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2152         .master         = &omap3xxx_dma_system_hwmod,
2153         .slave          = &omap3xxx_l3_main_hwmod,
2154         .clk            = "core_l3_ick",
2155         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2156 };
2157
2158 /* dma attributes */
2159 static struct omap_dma_dev_attr dma_dev_attr = {
2160         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2161                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2162         .lch_count = 32,
2163 };
2164
2165 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2166         .rev_offs       = 0x0000,
2167         .sysc_offs      = 0x002c,
2168         .syss_offs      = 0x0028,
2169         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2170                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2171                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2172                            SYSS_HAS_RESET_STATUS),
2173         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2174                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2175         .sysc_fields    = &omap_hwmod_sysc_type1,
2176 };
2177
2178 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2179         .name = "dma",
2180         .sysc = &omap3xxx_dma_sysc,
2181 };
2182
2183 /* dma_system */
2184 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2185         {
2186                 .pa_start       = 0x48056000,
2187                 .pa_end         = 0x48056fff,
2188                 .flags          = ADDR_TYPE_RT
2189         },
2190         { }
2191 };
2192
2193 /* dma_system master ports */
2194 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2195         &omap3xxx_dma_system__l3,
2196 };
2197
2198 /* l4_cfg -> dma_system */
2199 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2200         .master         = &omap3xxx_l4_core_hwmod,
2201         .slave          = &omap3xxx_dma_system_hwmod,
2202         .clk            = "core_l4_ick",
2203         .addr           = omap3xxx_dma_system_addrs,
2204         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2205 };
2206
2207 /* dma_system slave ports */
2208 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2209         &omap3xxx_l4_core__dma_system,
2210 };
2211
2212 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2213         .name           = "dma",
2214         .class          = &omap3xxx_dma_hwmod_class,
2215         .mpu_irqs       = omap2_dma_system_irqs,
2216         .main_clk       = "core_l3_ick",
2217         .prcm = {
2218                 .omap2 = {
2219                         .module_offs            = CORE_MOD,
2220                         .prcm_reg_id            = 1,
2221                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2222                         .idlest_reg_id          = 1,
2223                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2224                 },
2225         },
2226         .slaves         = omap3xxx_dma_system_slaves,
2227         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2228         .masters        = omap3xxx_dma_system_masters,
2229         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2230         .dev_attr       = &dma_dev_attr,
2231         .flags          = HWMOD_NO_IDLEST,
2232 };
2233
2234 /*
2235  * 'mcbsp' class
2236  * multi channel buffered serial port controller
2237  */
2238
2239 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2240         .sysc_offs      = 0x008c,
2241         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2242                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2243         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2244         .sysc_fields    = &omap_hwmod_sysc_type1,
2245         .clockact       = 0x2,
2246 };
2247
2248 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2249         .name = "mcbsp",
2250         .sysc = &omap3xxx_mcbsp_sysc,
2251         .rev  = MCBSP_CONFIG_TYPE3,
2252 };
2253
2254 /* mcbsp1 */
2255 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2256         { .name = "irq", .irq = 16 },
2257         { .name = "tx", .irq = 59 },
2258         { .name = "rx", .irq = 60 },
2259         { .irq = -1 }
2260 };
2261
2262 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2263         {
2264                 .name           = "mpu",
2265                 .pa_start       = 0x48074000,
2266                 .pa_end         = 0x480740ff,
2267                 .flags          = ADDR_TYPE_RT
2268         },
2269         { }
2270 };
2271
2272 /* l4_core -> mcbsp1 */
2273 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2274         .master         = &omap3xxx_l4_core_hwmod,
2275         .slave          = &omap3xxx_mcbsp1_hwmod,
2276         .clk            = "mcbsp1_ick",
2277         .addr           = omap3xxx_mcbsp1_addrs,
2278         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2279 };
2280
2281 /* mcbsp1 slave ports */
2282 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2283         &omap3xxx_l4_core__mcbsp1,
2284 };
2285
2286 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2287         .name           = "mcbsp1",
2288         .class          = &omap3xxx_mcbsp_hwmod_class,
2289         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2290         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
2291         .main_clk       = "mcbsp1_fck",
2292         .prcm           = {
2293                 .omap2 = {
2294                         .prcm_reg_id = 1,
2295                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2296                         .module_offs = CORE_MOD,
2297                         .idlest_reg_id = 1,
2298                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2299                 },
2300         },
2301         .slaves         = omap3xxx_mcbsp1_slaves,
2302         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2303 };
2304
2305 /* mcbsp2 */
2306 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2307         { .name = "irq", .irq = 17 },
2308         { .name = "tx", .irq = 62 },
2309         { .name = "rx", .irq = 63 },
2310         { .irq = -1 }
2311 };
2312
2313 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2314         {
2315                 .name           = "mpu",
2316                 .pa_start       = 0x49022000,
2317                 .pa_end         = 0x490220ff,
2318                 .flags          = ADDR_TYPE_RT
2319         },
2320         { }
2321 };
2322
2323 /* l4_per -> mcbsp2 */
2324 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2325         .master         = &omap3xxx_l4_per_hwmod,
2326         .slave          = &omap3xxx_mcbsp2_hwmod,
2327         .clk            = "mcbsp2_ick",
2328         .addr           = omap3xxx_mcbsp2_addrs,
2329         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2330 };
2331
2332 /* mcbsp2 slave ports */
2333 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2334         &omap3xxx_l4_per__mcbsp2,
2335 };
2336
2337 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2338         .sidetone       = "mcbsp2_sidetone",
2339 };
2340
2341 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2342         .name           = "mcbsp2",
2343         .class          = &omap3xxx_mcbsp_hwmod_class,
2344         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2345         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
2346         .main_clk       = "mcbsp2_fck",
2347         .prcm           = {
2348                 .omap2 = {
2349                         .prcm_reg_id = 1,
2350                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2351                         .module_offs = OMAP3430_PER_MOD,
2352                         .idlest_reg_id = 1,
2353                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2354                 },
2355         },
2356         .slaves         = omap3xxx_mcbsp2_slaves,
2357         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2358         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2359 };
2360
2361 /* mcbsp3 */
2362 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2363         { .name = "irq", .irq = 22 },
2364         { .name = "tx", .irq = 89 },
2365         { .name = "rx", .irq = 90 },
2366         { .irq = -1 }
2367 };
2368
2369 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2370         {
2371                 .name           = "mpu",
2372                 .pa_start       = 0x49024000,
2373                 .pa_end         = 0x490240ff,
2374                 .flags          = ADDR_TYPE_RT
2375         },
2376         { }
2377 };
2378
2379 /* l4_per -> mcbsp3 */
2380 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2381         .master         = &omap3xxx_l4_per_hwmod,
2382         .slave          = &omap3xxx_mcbsp3_hwmod,
2383         .clk            = "mcbsp3_ick",
2384         .addr           = omap3xxx_mcbsp3_addrs,
2385         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2386 };
2387
2388 /* mcbsp3 slave ports */
2389 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2390         &omap3xxx_l4_per__mcbsp3,
2391 };
2392
2393 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2394         .sidetone       = "mcbsp3_sidetone",
2395 };
2396
2397 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2398         .name           = "mcbsp3",
2399         .class          = &omap3xxx_mcbsp_hwmod_class,
2400         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2401         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
2402         .main_clk       = "mcbsp3_fck",
2403         .prcm           = {
2404                 .omap2 = {
2405                         .prcm_reg_id = 1,
2406                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2407                         .module_offs = OMAP3430_PER_MOD,
2408                         .idlest_reg_id = 1,
2409                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2410                 },
2411         },
2412         .slaves         = omap3xxx_mcbsp3_slaves,
2413         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2414         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2415 };
2416
2417 /* mcbsp4 */
2418 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2419         { .name = "irq", .irq = 23 },
2420         { .name = "tx", .irq = 54 },
2421         { .name = "rx", .irq = 55 },
2422         { .irq = -1 }
2423 };
2424
2425 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2426         { .name = "rx", .dma_req = 20 },
2427         { .name = "tx", .dma_req = 19 },
2428         { .dma_req = -1 }
2429 };
2430
2431 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2432         {
2433                 .name           = "mpu",
2434                 .pa_start       = 0x49026000,
2435                 .pa_end         = 0x490260ff,
2436                 .flags          = ADDR_TYPE_RT
2437         },
2438         { }
2439 };
2440
2441 /* l4_per -> mcbsp4 */
2442 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2443         .master         = &omap3xxx_l4_per_hwmod,
2444         .slave          = &omap3xxx_mcbsp4_hwmod,
2445         .clk            = "mcbsp4_ick",
2446         .addr           = omap3xxx_mcbsp4_addrs,
2447         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2448 };
2449
2450 /* mcbsp4 slave ports */
2451 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2452         &omap3xxx_l4_per__mcbsp4,
2453 };
2454
2455 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2456         .name           = "mcbsp4",
2457         .class          = &omap3xxx_mcbsp_hwmod_class,
2458         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2459         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2460         .main_clk       = "mcbsp4_fck",
2461         .prcm           = {
2462                 .omap2 = {
2463                         .prcm_reg_id = 1,
2464                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2465                         .module_offs = OMAP3430_PER_MOD,
2466                         .idlest_reg_id = 1,
2467                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2468                 },
2469         },
2470         .slaves         = omap3xxx_mcbsp4_slaves,
2471         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2472 };
2473
2474 /* mcbsp5 */
2475 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2476         { .name = "irq", .irq = 27 },
2477         { .name = "tx", .irq = 81 },
2478         { .name = "rx", .irq = 82 },
2479         { .irq = -1 }
2480 };
2481
2482 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2483         { .name = "rx", .dma_req = 22 },
2484         { .name = "tx", .dma_req = 21 },
2485         { .dma_req = -1 }
2486 };
2487
2488 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2489         {
2490                 .name           = "mpu",
2491                 .pa_start       = 0x48096000,
2492                 .pa_end         = 0x480960ff,
2493                 .flags          = ADDR_TYPE_RT
2494         },
2495         { }
2496 };
2497
2498 /* l4_core -> mcbsp5 */
2499 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2500         .master         = &omap3xxx_l4_core_hwmod,
2501         .slave          = &omap3xxx_mcbsp5_hwmod,
2502         .clk            = "mcbsp5_ick",
2503         .addr           = omap3xxx_mcbsp5_addrs,
2504         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2505 };
2506
2507 /* mcbsp5 slave ports */
2508 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2509         &omap3xxx_l4_core__mcbsp5,
2510 };
2511
2512 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2513         .name           = "mcbsp5",
2514         .class          = &omap3xxx_mcbsp_hwmod_class,
2515         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2516         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2517         .main_clk       = "mcbsp5_fck",
2518         .prcm           = {
2519                 .omap2 = {
2520                         .prcm_reg_id = 1,
2521                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2522                         .module_offs = CORE_MOD,
2523                         .idlest_reg_id = 1,
2524                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2525                 },
2526         },
2527         .slaves         = omap3xxx_mcbsp5_slaves,
2528         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2529 };
2530 /* 'mcbsp sidetone' class */
2531
2532 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2533         .sysc_offs      = 0x0010,
2534         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2535         .sysc_fields    = &omap_hwmod_sysc_type1,
2536 };
2537
2538 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2539         .name = "mcbsp_sidetone",
2540         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2541 };
2542
2543 /* mcbsp2_sidetone */
2544 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2545         { .name = "irq", .irq = 4 },
2546         { .irq = -1 }
2547 };
2548
2549 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2550         {
2551                 .name           = "sidetone",
2552                 .pa_start       = 0x49028000,
2553                 .pa_end         = 0x490280ff,
2554                 .flags          = ADDR_TYPE_RT
2555         },
2556         { }
2557 };
2558
2559 /* l4_per -> mcbsp2_sidetone */
2560 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2561         .master         = &omap3xxx_l4_per_hwmod,
2562         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2563         .clk            = "mcbsp2_ick",
2564         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2565         .user           = OCP_USER_MPU,
2566 };
2567
2568 /* mcbsp2_sidetone slave ports */
2569 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2570         &omap3xxx_l4_per__mcbsp2_sidetone,
2571 };
2572
2573 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2574         .name           = "mcbsp2_sidetone",
2575         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2576         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2577         .main_clk       = "mcbsp2_fck",
2578         .prcm           = {
2579                 .omap2 = {
2580                         .prcm_reg_id = 1,
2581                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2582                         .module_offs = OMAP3430_PER_MOD,
2583                         .idlest_reg_id = 1,
2584                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2585                 },
2586         },
2587         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2588         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2589 };
2590
2591 /* mcbsp3_sidetone */
2592 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2593         { .name = "irq", .irq = 5 },
2594         { .irq = -1 }
2595 };
2596
2597 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2598         {
2599                 .name           = "sidetone",
2600                 .pa_start       = 0x4902A000,
2601                 .pa_end         = 0x4902A0ff,
2602                 .flags          = ADDR_TYPE_RT
2603         },
2604         { }
2605 };
2606
2607 /* l4_per -> mcbsp3_sidetone */
2608 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2609         .master         = &omap3xxx_l4_per_hwmod,
2610         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2611         .clk            = "mcbsp3_ick",
2612         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2613         .user           = OCP_USER_MPU,
2614 };
2615
2616 /* mcbsp3_sidetone slave ports */
2617 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2618         &omap3xxx_l4_per__mcbsp3_sidetone,
2619 };
2620
2621 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2622         .name           = "mcbsp3_sidetone",
2623         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2624         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2625         .main_clk       = "mcbsp3_fck",
2626         .prcm           = {
2627                 .omap2 = {
2628                         .prcm_reg_id = 1,
2629                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2630                         .module_offs = OMAP3430_PER_MOD,
2631                         .idlest_reg_id = 1,
2632                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2633                 },
2634         },
2635         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2636         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2637 };
2638
2639
2640 /* SR common */
2641 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2642         .clkact_shift   = 20,
2643 };
2644
2645 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2646         .sysc_offs      = 0x24,
2647         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2648         .clockact       = CLOCKACT_TEST_ICLK,
2649         .sysc_fields    = &omap34xx_sr_sysc_fields,
2650 };
2651
2652 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2653         .name = "smartreflex",
2654         .sysc = &omap34xx_sr_sysc,
2655         .rev  = 1,
2656 };
2657
2658 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2659         .sidle_shift    = 24,
2660         .enwkup_shift   = 26
2661 };
2662
2663 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2664         .sysc_offs      = 0x38,
2665         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2666         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2667                         SYSC_NO_CACHE),
2668         .sysc_fields    = &omap36xx_sr_sysc_fields,
2669 };
2670
2671 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2672         .name = "smartreflex",
2673         .sysc = &omap36xx_sr_sysc,
2674         .rev  = 2,
2675 };
2676
2677 /* SR1 */
2678 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
2679         .sensor_voltdm_name   = "mpu_iva",
2680 };
2681
2682 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2683         &omap3_l4_core__sr1,
2684 };
2685
2686 static struct omap_hwmod omap34xx_sr1_hwmod = {
2687         .name           = "sr1_hwmod",
2688         .class          = &omap34xx_smartreflex_hwmod_class,
2689         .main_clk       = "sr1_fck",
2690         .prcm           = {
2691                 .omap2 = {
2692                         .prcm_reg_id = 1,
2693                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2694                         .module_offs = WKUP_MOD,
2695                         .idlest_reg_id = 1,
2696                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2697                 },
2698         },
2699         .slaves         = omap3_sr1_slaves,
2700         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2701         .dev_attr       = &sr1_dev_attr,
2702         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
2703         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2704 };
2705
2706 static struct omap_hwmod omap36xx_sr1_hwmod = {
2707         .name           = "sr1_hwmod",
2708         .class          = &omap36xx_smartreflex_hwmod_class,
2709         .main_clk       = "sr1_fck",
2710         .prcm           = {
2711                 .omap2 = {
2712                         .prcm_reg_id = 1,
2713                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2714                         .module_offs = WKUP_MOD,
2715                         .idlest_reg_id = 1,
2716                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2717                 },
2718         },
2719         .slaves         = omap3_sr1_slaves,
2720         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2721         .dev_attr       = &sr1_dev_attr,
2722         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
2723 };
2724
2725 /* SR2 */
2726 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
2727         .sensor_voltdm_name     = "core",
2728 };
2729
2730 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2731         &omap3_l4_core__sr2,
2732 };
2733
2734 static struct omap_hwmod omap34xx_sr2_hwmod = {
2735         .name           = "sr2_hwmod",
2736         .class          = &omap34xx_smartreflex_hwmod_class,
2737         .main_clk       = "sr2_fck",
2738         .prcm           = {
2739                 .omap2 = {
2740                         .prcm_reg_id = 1,
2741                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2742                         .module_offs = WKUP_MOD,
2743                         .idlest_reg_id = 1,
2744                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2745                 },
2746         },
2747         .slaves         = omap3_sr2_slaves,
2748         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2749         .dev_attr       = &sr2_dev_attr,
2750         .mpu_irqs       = omap3_smartreflex_core_irqs,
2751         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2752 };
2753
2754 static struct omap_hwmod omap36xx_sr2_hwmod = {
2755         .name           = "sr2_hwmod",
2756         .class          = &omap36xx_smartreflex_hwmod_class,
2757         .main_clk       = "sr2_fck",
2758         .prcm           = {
2759                 .omap2 = {
2760                         .prcm_reg_id = 1,
2761                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2762                         .module_offs = WKUP_MOD,
2763                         .idlest_reg_id = 1,
2764                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2765                 },
2766         },
2767         .slaves         = omap3_sr2_slaves,
2768         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2769         .dev_attr       = &sr2_dev_attr,
2770         .mpu_irqs       = omap3_smartreflex_core_irqs,
2771 };
2772
2773 /*
2774  * 'mailbox' class
2775  * mailbox module allowing communication between the on-chip processors
2776  * using a queued mailbox-interrupt mechanism.
2777  */
2778
2779 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2780         .rev_offs       = 0x000,
2781         .sysc_offs      = 0x010,
2782         .syss_offs      = 0x014,
2783         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2784                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2785         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2786         .sysc_fields    = &omap_hwmod_sysc_type1,
2787 };
2788
2789 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2790         .name = "mailbox",
2791         .sysc = &omap3xxx_mailbox_sysc,
2792 };
2793
2794 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2795 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2796         { .irq = 26 },
2797         { .irq = -1 }
2798 };
2799
2800 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2801         {
2802                 .pa_start       = 0x48094000,
2803                 .pa_end         = 0x480941ff,
2804                 .flags          = ADDR_TYPE_RT,
2805         },
2806         { }
2807 };
2808
2809 /* l4_core -> mailbox */
2810 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2811         .master         = &omap3xxx_l4_core_hwmod,
2812         .slave          = &omap3xxx_mailbox_hwmod,
2813         .addr           = omap3xxx_mailbox_addrs,
2814         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2815 };
2816
2817 /* mailbox slave ports */
2818 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2819         &omap3xxx_l4_core__mailbox,
2820 };
2821
2822 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2823         .name           = "mailbox",
2824         .class          = &omap3xxx_mailbox_hwmod_class,
2825         .mpu_irqs       = omap3xxx_mailbox_irqs,
2826         .main_clk       = "mailboxes_ick",
2827         .prcm           = {
2828                 .omap2 = {
2829                         .prcm_reg_id = 1,
2830                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2831                         .module_offs = CORE_MOD,
2832                         .idlest_reg_id = 1,
2833                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2834                 },
2835         },
2836         .slaves         = omap3xxx_mailbox_slaves,
2837         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2838 };
2839
2840 /* l4 core -> mcspi1 interface */
2841 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2842         .master         = &omap3xxx_l4_core_hwmod,
2843         .slave          = &omap34xx_mcspi1,
2844         .clk            = "mcspi1_ick",
2845         .addr           = omap2_mcspi1_addr_space,
2846         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2847 };
2848
2849 /* l4 core -> mcspi2 interface */
2850 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2851         .master         = &omap3xxx_l4_core_hwmod,
2852         .slave          = &omap34xx_mcspi2,
2853         .clk            = "mcspi2_ick",
2854         .addr           = omap2_mcspi2_addr_space,
2855         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2856 };
2857
2858 /* l4 core -> mcspi3 interface */
2859 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2860         .master         = &omap3xxx_l4_core_hwmod,
2861         .slave          = &omap34xx_mcspi3,
2862         .clk            = "mcspi3_ick",
2863         .addr           = omap2430_mcspi3_addr_space,
2864         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2865 };
2866
2867 /* l4 core -> mcspi4 interface */
2868 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2869         {
2870                 .pa_start       = 0x480ba000,
2871                 .pa_end         = 0x480ba0ff,
2872                 .flags          = ADDR_TYPE_RT,
2873         },
2874         { }
2875 };
2876
2877 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2878         .master         = &omap3xxx_l4_core_hwmod,
2879         .slave          = &omap34xx_mcspi4,
2880         .clk            = "mcspi4_ick",
2881         .addr           = omap34xx_mcspi4_addr_space,
2882         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2883 };
2884
2885 /*
2886  * 'mcspi' class
2887  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2888  * bus
2889  */
2890
2891 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2892         .rev_offs       = 0x0000,
2893         .sysc_offs      = 0x0010,
2894         .syss_offs      = 0x0014,
2895         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2896                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2897                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2898         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2899         .sysc_fields    = &omap_hwmod_sysc_type1,
2900 };
2901
2902 static struct omap_hwmod_class omap34xx_mcspi_class = {
2903         .name = "mcspi",
2904         .sysc = &omap34xx_mcspi_sysc,
2905         .rev = OMAP3_MCSPI_REV,
2906 };
2907
2908 /* mcspi1 */
2909 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2910         &omap34xx_l4_core__mcspi1,
2911 };
2912
2913 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2914         .num_chipselect = 4,
2915 };
2916
2917 static struct omap_hwmod omap34xx_mcspi1 = {
2918         .name           = "mcspi1",
2919         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
2920         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
2921         .main_clk       = "mcspi1_fck",
2922         .prcm           = {
2923                 .omap2 = {
2924                         .module_offs = CORE_MOD,
2925                         .prcm_reg_id = 1,
2926                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2927                         .idlest_reg_id = 1,
2928                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2929                 },
2930         },
2931         .slaves         = omap34xx_mcspi1_slaves,
2932         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2933         .class          = &omap34xx_mcspi_class,
2934         .dev_attr       = &omap_mcspi1_dev_attr,
2935 };
2936
2937 /* mcspi2 */
2938 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2939         &omap34xx_l4_core__mcspi2,
2940 };
2941
2942 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2943         .num_chipselect = 2,
2944 };
2945
2946 static struct omap_hwmod omap34xx_mcspi2 = {
2947         .name           = "mcspi2",
2948         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
2949         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
2950         .main_clk       = "mcspi2_fck",
2951         .prcm           = {
2952                 .omap2 = {
2953                         .module_offs = CORE_MOD,
2954                         .prcm_reg_id = 1,
2955                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2956                         .idlest_reg_id = 1,
2957                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2958                 },
2959         },
2960         .slaves         = omap34xx_mcspi2_slaves,
2961         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2962         .class          = &omap34xx_mcspi_class,
2963         .dev_attr       = &omap_mcspi2_dev_attr,
2964 };
2965
2966 /* mcspi3 */
2967 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2968         { .name = "irq", .irq = 91 }, /* 91 */
2969         { .irq = -1 }
2970 };
2971
2972 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2973         { .name = "tx0", .dma_req = 15 },
2974         { .name = "rx0", .dma_req = 16 },
2975         { .name = "tx1", .dma_req = 23 },
2976         { .name = "rx1", .dma_req = 24 },
2977         { .dma_req = -1 }
2978 };
2979
2980 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2981         &omap34xx_l4_core__mcspi3,
2982 };
2983
2984 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2985         .num_chipselect = 2,
2986 };
2987
2988 static struct omap_hwmod omap34xx_mcspi3 = {
2989         .name           = "mcspi3",
2990         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
2991         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
2992         .main_clk       = "mcspi3_fck",
2993         .prcm           = {
2994                 .omap2 = {
2995                         .module_offs = CORE_MOD,
2996                         .prcm_reg_id = 1,
2997                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2998                         .idlest_reg_id = 1,
2999                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
3000                 },
3001         },
3002         .slaves         = omap34xx_mcspi3_slaves,
3003         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3004         .class          = &omap34xx_mcspi_class,
3005         .dev_attr       = &omap_mcspi3_dev_attr,
3006 };
3007
3008 /* SPI4 */
3009 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3010         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3011         { .irq = -1 }
3012 };
3013
3014 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3015         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3016         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3017         { .dma_req = -1 }
3018 };
3019
3020 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3021         &omap34xx_l4_core__mcspi4,
3022 };
3023
3024 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3025         .num_chipselect = 1,
3026 };
3027
3028 static struct omap_hwmod omap34xx_mcspi4 = {
3029         .name           = "mcspi4",
3030         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
3031         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
3032         .main_clk       = "mcspi4_fck",
3033         .prcm           = {
3034                 .omap2 = {
3035                         .module_offs = CORE_MOD,
3036                         .prcm_reg_id = 1,
3037                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3038                         .idlest_reg_id = 1,
3039                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3040                 },
3041         },
3042         .slaves         = omap34xx_mcspi4_slaves,
3043         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3044         .class          = &omap34xx_mcspi_class,
3045         .dev_attr       = &omap_mcspi4_dev_attr,
3046 };
3047
3048 /*
3049  * usbhsotg
3050  */
3051 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3052         .rev_offs       = 0x0400,
3053         .sysc_offs      = 0x0404,
3054         .syss_offs      = 0x0408,
3055         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3056                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3057                           SYSC_HAS_AUTOIDLE),
3058         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3059                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3060         .sysc_fields    = &omap_hwmod_sysc_type1,
3061 };
3062
3063 static struct omap_hwmod_class usbotg_class = {
3064         .name = "usbotg",
3065         .sysc = &omap3xxx_usbhsotg_sysc,
3066 };
3067 /* usb_otg_hs */
3068 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3069
3070         { .name = "mc", .irq = 92 },
3071         { .name = "dma", .irq = 93 },
3072         { .irq = -1 }
3073 };
3074
3075 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3076         .name           = "usb_otg_hs",
3077         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
3078         .main_clk       = "hsotgusb_ick",
3079         .prcm           = {
3080                 .omap2 = {
3081                         .prcm_reg_id = 1,
3082                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3083                         .module_offs = CORE_MOD,
3084                         .idlest_reg_id = 1,
3085                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3086                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3087                 },
3088         },
3089         .masters        = omap3xxx_usbhsotg_masters,
3090         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3091         .slaves         = omap3xxx_usbhsotg_slaves,
3092         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3093         .class          = &usbotg_class,
3094
3095         /*
3096          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
3097          * broken when autoidle is enabled
3098          * workaround is to disable the autoidle bit at module level.
3099          */
3100         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3101                                 | HWMOD_SWSUP_MSTANDBY,
3102 };
3103
3104 /* usb_otg_hs */
3105 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3106
3107         { .name = "mc", .irq = 71 },
3108         { .irq = -1 }
3109 };
3110
3111 static struct omap_hwmod_class am35xx_usbotg_class = {
3112         .name = "am35xx_usbotg",
3113         .sysc = NULL,
3114 };
3115
3116 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3117         .name           = "am35x_otg_hs",
3118         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3119         .main_clk       = NULL,
3120         .prcm = {
3121                 .omap2 = {
3122                 },
3123         },
3124         .masters        = am35xx_usbhsotg_masters,
3125         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3126         .slaves         = am35xx_usbhsotg_slaves,
3127         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3128         .class          = &am35xx_usbotg_class,
3129 };
3130
3131 /* MMC/SD/SDIO common */
3132
3133 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3134         .rev_offs       = 0x1fc,
3135         .sysc_offs      = 0x10,
3136         .syss_offs      = 0x14,
3137         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3138                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3139                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3140         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3141         .sysc_fields    = &omap_hwmod_sysc_type1,
3142 };
3143
3144 static struct omap_hwmod_class omap34xx_mmc_class = {
3145         .name = "mmc",
3146         .sysc = &omap34xx_mmc_sysc,
3147 };
3148
3149 /* MMC/SD/SDIO1 */
3150
3151 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3152         { .irq = 83, },
3153         { .irq = -1 }
3154 };
3155
3156 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3157         { .name = "tx", .dma_req = 61, },
3158         { .name = "rx", .dma_req = 62, },
3159         { .dma_req = -1 }
3160 };
3161
3162 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3163         { .role = "dbck", .clk = "omap_32k_fck", },
3164 };
3165
3166 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3167         &omap3xxx_l4_core__mmc1,
3168 };
3169
3170 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3171         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3172 };
3173
3174 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3175 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
3176         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
3177                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
3178 };
3179
3180 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
3181         .name           = "mmc1",
3182         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3183         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3184         .opt_clks       = omap34xx_mmc1_opt_clks,
3185         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3186         .main_clk       = "mmchs1_fck",
3187         .prcm           = {
3188                 .omap2 = {
3189                         .module_offs = CORE_MOD,
3190                         .prcm_reg_id = 1,
3191                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3192                         .idlest_reg_id = 1,
3193                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3194                 },
3195         },
3196         .dev_attr       = &mmc1_pre_es3_dev_attr,
3197         .slaves         = omap3xxx_mmc1_slaves,
3198         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3199         .class          = &omap34xx_mmc_class,
3200 };
3201
3202 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
3203         .name           = "mmc1",
3204         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3205         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3206         .opt_clks       = omap34xx_mmc1_opt_clks,
3207         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3208         .main_clk       = "mmchs1_fck",
3209         .prcm           = {
3210                 .omap2 = {
3211                         .module_offs = CORE_MOD,
3212                         .prcm_reg_id = 1,
3213                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3214                         .idlest_reg_id = 1,
3215                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3216                 },
3217         },
3218         .dev_attr       = &mmc1_dev_attr,
3219         .slaves         = omap3xxx_mmc1_slaves,
3220         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3221         .class          = &omap34xx_mmc_class,
3222 };
3223
3224 /* MMC/SD/SDIO2 */
3225
3226 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3227         { .irq = INT_24XX_MMC2_IRQ, },
3228         { .irq = -1 }
3229 };
3230
3231 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3232         { .name = "tx", .dma_req = 47, },
3233         { .name = "rx", .dma_req = 48, },
3234         { .dma_req = -1 }
3235 };
3236
3237 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3238         { .role = "dbck", .clk = "omap_32k_fck", },
3239 };
3240
3241 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3242         &omap3xxx_l4_core__mmc2,
3243 };
3244
3245 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3246 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
3247         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
3248 };
3249
3250 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
3251         .name           = "mmc2",
3252         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3253         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3254         .opt_clks       = omap34xx_mmc2_opt_clks,
3255         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3256         .main_clk       = "mmchs2_fck",
3257         .prcm           = {
3258                 .omap2 = {
3259                         .module_offs = CORE_MOD,
3260                         .prcm_reg_id = 1,
3261                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3262                         .idlest_reg_id = 1,
3263                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3264                 },
3265         },
3266         .dev_attr       = &mmc2_pre_es3_dev_attr,
3267         .slaves         = omap3xxx_mmc2_slaves,
3268         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3269         .class          = &omap34xx_mmc_class,
3270 };
3271
3272 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
3273         .name           = "mmc2",
3274         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3275         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3276         .opt_clks       = omap34xx_mmc2_opt_clks,
3277         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3278         .main_clk       = "mmchs2_fck",
3279         .prcm           = {
3280                 .omap2 = {
3281                         .module_offs = CORE_MOD,
3282                         .prcm_reg_id = 1,
3283                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3284                         .idlest_reg_id = 1,
3285                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3286                 },
3287         },
3288         .slaves         = omap3xxx_mmc2_slaves,
3289         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3290         .class          = &omap34xx_mmc_class,
3291 };
3292
3293 /* MMC/SD/SDIO3 */
3294
3295 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3296         { .irq = 94, },
3297         { .irq = -1 }
3298 };
3299
3300 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3301         { .name = "tx", .dma_req = 77, },
3302         { .name = "rx", .dma_req = 78, },
3303         { .dma_req = -1 }
3304 };
3305
3306 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3307         { .role = "dbck", .clk = "omap_32k_fck", },
3308 };
3309
3310 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3311         &omap3xxx_l4_core__mmc3,
3312 };
3313
3314 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3315         .name           = "mmc3",
3316         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3317         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3318         .opt_clks       = omap34xx_mmc3_opt_clks,
3319         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3320         .main_clk       = "mmchs3_fck",
3321         .prcm           = {
3322                 .omap2 = {
3323                         .prcm_reg_id = 1,
3324                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3325                         .idlest_reg_id = 1,
3326                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3327                 },
3328         },
3329         .slaves         = omap3xxx_mmc3_slaves,
3330         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3331         .class          = &omap34xx_mmc_class,
3332 };
3333
3334 /*
3335  * 'usb_host_hs' class
3336  * high-speed multi-port usb host controller
3337  */
3338 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3339         .master         = &omap3xxx_usb_host_hs_hwmod,
3340         .slave          = &omap3xxx_l3_main_hwmod,
3341         .clk            = "core_l3_ick",
3342         .user           = OCP_USER_MPU,
3343 };
3344
3345 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
3346         .rev_offs       = 0x0000,
3347         .sysc_offs      = 0x0010,
3348         .syss_offs      = 0x0014,
3349         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
3350                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
3351                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
3352         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3353                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3354         .sysc_fields    = &omap_hwmod_sysc_type1,
3355 };
3356
3357 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
3358         .name = "usb_host_hs",
3359         .sysc = &omap3xxx_usb_host_hs_sysc,
3360 };
3361
3362 static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = {
3363         &omap3xxx_usb_host_hs__l3_main_2,
3364 };
3365
3366 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3367         {
3368                 .name           = "uhh",
3369                 .pa_start       = 0x48064000,
3370                 .pa_end         = 0x480643ff,
3371                 .flags          = ADDR_TYPE_RT
3372         },
3373         {
3374                 .name           = "ohci",
3375                 .pa_start       = 0x48064400,
3376                 .pa_end         = 0x480647ff,
3377         },
3378         {
3379                 .name           = "ehci",
3380                 .pa_start       = 0x48064800,
3381                 .pa_end         = 0x48064cff,
3382         },
3383         {}
3384 };
3385
3386 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3387         .master         = &omap3xxx_l4_core_hwmod,
3388         .slave          = &omap3xxx_usb_host_hs_hwmod,
3389         .clk            = "usbhost_ick",
3390         .addr           = omap3xxx_usb_host_hs_addrs,
3391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3392 };
3393
3394 static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = {
3395         &omap3xxx_l4_core__usb_host_hs,
3396 };
3397
3398 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
3399           { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
3400 };
3401
3402 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
3403         { .name = "ohci-irq", .irq = 76 },
3404         { .name = "ehci-irq", .irq = 77 },
3405         { .irq = -1 }
3406 };
3407
3408 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
3409         .name           = "usb_host_hs",
3410         .class          = &omap3xxx_usb_host_hs_hwmod_class,
3411         .clkdm_name     = "l3_init_clkdm",
3412         .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
3413         .main_clk       = "usbhost_48m_fck",
3414         .prcm = {
3415                 .omap2 = {
3416                         .module_offs = OMAP3430ES2_USBHOST_MOD,
3417                         .prcm_reg_id = 1,
3418                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
3419                         .idlest_reg_id = 1,
3420                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
3421                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
3422                 },
3423         },
3424         .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
3425         .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
3426         .slaves         = omap3xxx_usb_host_hs_slaves,
3427         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves),
3428         .masters        = omap3xxx_usb_host_hs_masters,
3429         .masters_cnt    = ARRAY_SIZE(omap3xxx_usb_host_hs_masters),
3430
3431         /*
3432          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3433          * id: i660
3434          *
3435          * Description:
3436          * In the following configuration :
3437          * - USBHOST module is set to smart-idle mode
3438          * - PRCM asserts idle_req to the USBHOST module ( This typically
3439          *   happens when the system is going to a low power mode : all ports
3440          *   have been suspended, the master part of the USBHOST module has
3441          *   entered the standby state, and SW has cut the functional clocks)
3442          * - an USBHOST interrupt occurs before the module is able to answer
3443          *   idle_ack, typically a remote wakeup IRQ.
3444          * Then the USB HOST module will enter a deadlock situation where it
3445          * is no more accessible nor functional.
3446          *
3447          * Workaround:
3448          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3449          */
3450
3451         /*
3452          * Errata: USB host EHCI may stall when entering smart-standby mode
3453          * Id: i571
3454          *
3455          * Description:
3456          * When the USBHOST module is set to smart-standby mode, and when it is
3457          * ready to enter the standby state (i.e. all ports are suspended and
3458          * all attached devices are in suspend mode), then it can wrongly assert
3459          * the Mstandby signal too early while there are still some residual OCP
3460          * transactions ongoing. If this condition occurs, the internal state
3461          * machine may go to an undefined state and the USB link may be stuck
3462          * upon the next resume.
3463          *
3464          * Workaround:
3465          * Don't use smart standby; use only force standby,
3466          * hence HWMOD_SWSUP_MSTANDBY
3467          */
3468
3469         /*
3470          * During system boot; If the hwmod framework resets the module
3471          * the module will have smart idle settings; which can lead to deadlock
3472          * (above Errata Id:i660); so, dont reset the module during boot;
3473          * Use HWMOD_INIT_NO_RESET.
3474          */
3475
3476         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3477                           HWMOD_INIT_NO_RESET,
3478 };
3479
3480 /*
3481  * 'usb_tll_hs' class
3482  * usb_tll_hs module is the adapter on the usb_host_hs ports
3483  */
3484 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
3485         .rev_offs       = 0x0000,
3486         .sysc_offs      = 0x0010,
3487         .syss_offs      = 0x0014,
3488         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3489                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3490                            SYSC_HAS_AUTOIDLE),
3491         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3492         .sysc_fields    = &omap_hwmod_sysc_type1,
3493 };
3494
3495 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
3496         .name = "usb_tll_hs",
3497         .sysc = &omap3xxx_usb_tll_hs_sysc,
3498 };
3499
3500 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
3501         { .name = "tll-irq", .irq = 78 },
3502         { .irq = -1 }
3503 };
3504
3505 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3506         {
3507                 .name           = "tll",
3508                 .pa_start       = 0x48062000,
3509                 .pa_end         = 0x48062fff,
3510                 .flags          = ADDR_TYPE_RT
3511         },
3512         {}
3513 };
3514
3515 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3516         .master         = &omap3xxx_l4_core_hwmod,
3517         .slave          = &omap3xxx_usb_tll_hs_hwmod,
3518         .clk            = "usbtll_ick",
3519         .addr           = omap3xxx_usb_tll_hs_addrs,
3520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3521 };
3522
3523 static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = {
3524         &omap3xxx_l4_core__usb_tll_hs,
3525 };
3526
3527 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
3528         .name           = "usb_tll_hs",
3529         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
3530         .clkdm_name     = "l3_init_clkdm",
3531         .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
3532         .main_clk       = "usbtll_fck",
3533         .prcm = {
3534                 .omap2 = {
3535                         .module_offs = CORE_MOD,
3536                         .prcm_reg_id = 3,
3537                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3538                         .idlest_reg_id = 3,
3539                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
3540                 },
3541         },
3542         .slaves         = omap3xxx_usb_tll_hs_slaves,
3543         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves),
3544 };
3545
3546 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3547         &omap3xxx_l3_main_hwmod,
3548         &omap3xxx_l4_core_hwmod,
3549         &omap3xxx_l4_per_hwmod,
3550         &omap3xxx_l4_wkup_hwmod,
3551         &omap3xxx_mmc3_hwmod,
3552         &omap3xxx_mpu_hwmod,
3553
3554         &omap3xxx_timer1_hwmod,
3555         &omap3xxx_timer2_hwmod,
3556         &omap3xxx_timer3_hwmod,
3557         &omap3xxx_timer4_hwmod,
3558         &omap3xxx_timer5_hwmod,
3559         &omap3xxx_timer6_hwmod,
3560         &omap3xxx_timer7_hwmod,
3561         &omap3xxx_timer8_hwmod,
3562         &omap3xxx_timer9_hwmod,
3563         &omap3xxx_timer10_hwmod,
3564         &omap3xxx_timer11_hwmod,
3565
3566         &omap3xxx_wd_timer2_hwmod,
3567         &omap3xxx_uart1_hwmod,
3568         &omap3xxx_uart2_hwmod,
3569         &omap3xxx_uart3_hwmod,
3570
3571         /* i2c class */
3572         &omap3xxx_i2c1_hwmod,
3573         &omap3xxx_i2c2_hwmod,
3574         &omap3xxx_i2c3_hwmod,
3575
3576         /* gpio class */
3577         &omap3xxx_gpio1_hwmod,
3578         &omap3xxx_gpio2_hwmod,
3579         &omap3xxx_gpio3_hwmod,
3580         &omap3xxx_gpio4_hwmod,
3581         &omap3xxx_gpio5_hwmod,
3582         &omap3xxx_gpio6_hwmod,
3583
3584         /* dma_system class*/
3585         &omap3xxx_dma_system_hwmod,
3586
3587         /* mcbsp class */
3588         &omap3xxx_mcbsp1_hwmod,
3589         &omap3xxx_mcbsp2_hwmod,
3590         &omap3xxx_mcbsp3_hwmod,
3591         &omap3xxx_mcbsp4_hwmod,
3592         &omap3xxx_mcbsp5_hwmod,
3593         &omap3xxx_mcbsp2_sidetone_hwmod,
3594         &omap3xxx_mcbsp3_sidetone_hwmod,
3595
3596
3597         /* mcspi class */
3598         &omap34xx_mcspi1,
3599         &omap34xx_mcspi2,
3600         &omap34xx_mcspi3,
3601         &omap34xx_mcspi4,
3602
3603         NULL,
3604 };
3605
3606 /* GP-only hwmods */
3607 static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
3608         &omap3xxx_timer12_hwmod,
3609         NULL
3610 };
3611
3612 /* 3430ES1-only hwmods */
3613 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
3614         &omap3430es1_dss_core_hwmod,
3615         NULL
3616 };
3617
3618 /* 3430ES2+-only hwmods */
3619 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
3620         &omap3xxx_dss_core_hwmod,
3621         &omap3xxx_usbhsotg_hwmod,
3622         &omap3xxx_usb_host_hs_hwmod,
3623         &omap3xxx_usb_tll_hs_hwmod,
3624         NULL
3625 };
3626
3627 /* <= 3430ES3-only hwmods */
3628 static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
3629         &omap3xxx_pre_es3_mmc1_hwmod,
3630         &omap3xxx_pre_es3_mmc2_hwmod,
3631         NULL
3632 };
3633
3634 /* 3430ES3+-only hwmods */
3635 static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
3636         &omap3xxx_es3plus_mmc1_hwmod,
3637         &omap3xxx_es3plus_mmc2_hwmod,
3638         NULL
3639 };
3640
3641 /* 34xx-only hwmods (all ES revisions) */
3642 static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
3643         &omap3xxx_iva_hwmod,
3644         &omap34xx_sr1_hwmod,
3645         &omap34xx_sr2_hwmod,
3646         &omap3xxx_mailbox_hwmod,
3647         NULL
3648 };
3649
3650 /* 36xx-only hwmods (all ES revisions) */
3651 static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
3652         &omap3xxx_iva_hwmod,
3653         &omap3xxx_uart4_hwmod,
3654         &omap3xxx_dss_core_hwmod,
3655         &omap36xx_sr1_hwmod,
3656         &omap36xx_sr2_hwmod,
3657         &omap3xxx_usbhsotg_hwmod,
3658         &omap3xxx_mailbox_hwmod,
3659         &omap3xxx_usb_host_hs_hwmod,
3660         &omap3xxx_usb_tll_hs_hwmod,
3661         &omap3xxx_es3plus_mmc1_hwmod,
3662         &omap3xxx_es3plus_mmc2_hwmod,
3663         NULL
3664 };
3665
3666 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3667         &omap3xxx_dss_core_hwmod, /* XXX ??? */
3668         &am35xx_usbhsotg_hwmod,
3669         &am35xx_uart4_hwmod,
3670         &omap3xxx_usb_host_hs_hwmod,
3671         &omap3xxx_usb_tll_hs_hwmod,
3672         &omap3xxx_es3plus_mmc1_hwmod,
3673         &omap3xxx_es3plus_mmc2_hwmod,
3674         NULL
3675 };
3676
3677 static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
3678         /* dss class */
3679         &omap3xxx_dss_dispc_hwmod,
3680         &omap3xxx_dss_dsi1_hwmod,
3681         &omap3xxx_dss_rfbi_hwmod,
3682         &omap3xxx_dss_venc_hwmod,
3683         NULL
3684 };
3685
3686 int __init omap3xxx_hwmod_init(void)
3687 {
3688         int r;
3689         struct omap_hwmod **h = NULL;
3690         unsigned int rev;
3691
3692         /* Register hwmods common to all OMAP3 */
3693         r = omap_hwmod_register(omap3xxx_hwmods);
3694         if (r < 0)
3695                 return r;
3696
3697         /* Register GP-only hwmods. */
3698         if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3699                 r = omap_hwmod_register(omap3xxx_gp_hwmods);
3700                 if (r < 0)
3701                         return r;
3702         }
3703
3704         rev = omap_rev();
3705
3706         /*
3707          * Register hwmods common to individual OMAP3 families, all
3708          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3709          * All possible revisions should be included in this conditional.
3710          */
3711         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3712             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3713             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3714                 h = omap34xx_hwmods;
3715         } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3716                 h = am35xx_hwmods;
3717         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3718                    rev == OMAP3630_REV_ES1_2) {
3719                 h = omap36xx_hwmods;
3720         } else {
3721                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3722                 return -EINVAL;
3723         };
3724
3725         r = omap_hwmod_register(h);
3726         if (r < 0)
3727                 return r;
3728
3729         /*
3730          * Register hwmods specific to certain ES levels of a
3731          * particular family of silicon (e.g., 34xx ES1.0)
3732          */
3733         h = NULL;
3734         if (rev == OMAP3430_REV_ES1_0) {
3735                 h = omap3430es1_hwmods;
3736         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3737                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3738                    rev == OMAP3430_REV_ES3_1_2) {
3739                 h = omap3430es2plus_hwmods;
3740         };
3741
3742         if (h) {
3743                 r = omap_hwmod_register(h);
3744                 if (r < 0)
3745                         return r;
3746         }
3747
3748         h = NULL;
3749         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3750             rev == OMAP3430_REV_ES2_1) {
3751                 h = omap3430_pre_es3_hwmods;
3752         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3753                    rev == OMAP3430_REV_ES3_1_2) {
3754                 h = omap3430_es3plus_hwmods;
3755         };
3756
3757         if (h)
3758                 r = omap_hwmod_register(h);
3759         if (r < 0)
3760                 return r;
3761
3762         /*
3763          * DSS code presumes that dss_core hwmod is handled first,
3764          * _before_ any other DSS related hwmods so register common
3765          * DSS hwmods last to ensure that dss_core is already registered.
3766          * Otherwise some change things may happen, for ex. if dispc
3767          * is handled before dss_core and DSS is enabled in bootloader
3768          * DIPSC will be reset with outputs enabled which sometimes leads
3769          * to unrecoverable L3 error.
3770          * XXX The long-term fix to this is to ensure modules are set up
3771          * in dependency order in the hwmod core code.
3772          */
3773         r = omap_hwmod_register(omap3xxx_dss_hwmods);
3774
3775         return r;
3776 }