2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2010 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
14 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
24 #include <plat/gpio.h>
25 #include <plat/mcspi.h>
27 #include "omap_hwmod_common_data.h"
29 #include "prm-regbits-34xx.h"
30 #include "cm-regbits-34xx.h"
32 #include <mach/am35xx.h>
35 * OMAP3xxx hardware module integration data
37 * ALl of the data in this section should be autogeneratable from the
38 * TI hardware database or other technical documentation. Data that
39 * is driver-specific or driver-kernel integration-specific belongs
43 static struct omap_hwmod omap3xxx_mpu_hwmod;
44 static struct omap_hwmod omap3xxx_iva_hwmod;
45 static struct omap_hwmod omap3xxx_l3_main_hwmod;
46 static struct omap_hwmod omap3xxx_l4_core_hwmod;
47 static struct omap_hwmod omap3xxx_l4_per_hwmod;
48 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
49 static struct omap_hwmod omap3430es1_dss_core_hwmod;
50 static struct omap_hwmod omap3xxx_dss_core_hwmod;
51 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
52 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
53 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
54 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
55 static struct omap_hwmod omap3xxx_i2c1_hwmod;
56 static struct omap_hwmod omap3xxx_i2c2_hwmod;
57 static struct omap_hwmod omap3xxx_i2c3_hwmod;
58 static struct omap_hwmod omap3xxx_gpio1_hwmod;
59 static struct omap_hwmod omap3xxx_gpio2_hwmod;
60 static struct omap_hwmod omap3xxx_gpio3_hwmod;
61 static struct omap_hwmod omap3xxx_gpio4_hwmod;
62 static struct omap_hwmod omap3xxx_gpio5_hwmod;
63 static struct omap_hwmod omap3xxx_gpio6_hwmod;
64 static struct omap_hwmod omap34xx_sr1_hwmod;
65 static struct omap_hwmod omap34xx_sr2_hwmod;
66 static struct omap_hwmod omap34xx_mcspi1;
67 static struct omap_hwmod omap34xx_mcspi2;
68 static struct omap_hwmod omap34xx_mcspi3;
69 static struct omap_hwmod omap34xx_mcspi4;
70 static struct omap_hwmod am35xx_usbhsotg_hwmod;
72 static struct omap_hwmod omap3xxx_dma_system_hwmod;
74 /* L3 -> L4_CORE interface */
75 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
76 .master = &omap3xxx_l3_main_hwmod,
77 .slave = &omap3xxx_l4_core_hwmod,
78 .user = OCP_USER_MPU | OCP_USER_SDMA,
81 /* L3 -> L4_PER interface */
82 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
83 .master = &omap3xxx_l3_main_hwmod,
84 .slave = &omap3xxx_l4_per_hwmod,
85 .user = OCP_USER_MPU | OCP_USER_SDMA,
88 /* MPU -> L3 interface */
89 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
90 .master = &omap3xxx_mpu_hwmod,
91 .slave = &omap3xxx_l3_main_hwmod,
95 /* Slave interfaces on the L3 interconnect */
96 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
97 &omap3xxx_mpu__l3_main,
101 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
102 .master = &omap3xxx_dss_core_hwmod,
103 .slave = &omap3xxx_l3_main_hwmod,
106 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
107 .flags = OMAP_FIREWALL_L3,
110 .user = OCP_USER_MPU | OCP_USER_SDMA,
113 /* Master interfaces on the L3 interconnect */
114 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
115 &omap3xxx_l3_main__l4_core,
116 &omap3xxx_l3_main__l4_per,
120 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
122 .class = &l3_hwmod_class,
123 .masters = omap3xxx_l3_main_masters,
124 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
125 .slaves = omap3xxx_l3_main_slaves,
126 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
127 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
128 .flags = HWMOD_NO_IDLEST,
131 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
132 static struct omap_hwmod omap3xxx_uart1_hwmod;
133 static struct omap_hwmod omap3xxx_uart2_hwmod;
134 static struct omap_hwmod omap3xxx_uart3_hwmod;
135 static struct omap_hwmod omap3xxx_uart4_hwmod;
136 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
138 /* l3_core -> usbhsotg interface */
139 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
140 .master = &omap3xxx_usbhsotg_hwmod,
141 .slave = &omap3xxx_l3_main_hwmod,
142 .clk = "core_l3_ick",
143 .user = OCP_USER_MPU,
146 /* l3_core -> am35xx_usbhsotg interface */
147 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
148 .master = &am35xx_usbhsotg_hwmod,
149 .slave = &omap3xxx_l3_main_hwmod,
150 .clk = "core_l3_ick",
151 .user = OCP_USER_MPU,
153 /* L4_CORE -> L4_WKUP interface */
154 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
155 .master = &omap3xxx_l4_core_hwmod,
156 .slave = &omap3xxx_l4_wkup_hwmod,
157 .user = OCP_USER_MPU | OCP_USER_SDMA,
160 /* L4 CORE -> UART1 interface */
161 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
163 .pa_start = OMAP3_UART1_BASE,
164 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
165 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
169 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
170 .master = &omap3xxx_l4_core_hwmod,
171 .slave = &omap3xxx_uart1_hwmod,
173 .addr = omap3xxx_uart1_addr_space,
174 .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
175 .user = OCP_USER_MPU | OCP_USER_SDMA,
178 /* L4 CORE -> UART2 interface */
179 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
181 .pa_start = OMAP3_UART2_BASE,
182 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
183 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
187 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
188 .master = &omap3xxx_l4_core_hwmod,
189 .slave = &omap3xxx_uart2_hwmod,
191 .addr = omap3xxx_uart2_addr_space,
192 .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
193 .user = OCP_USER_MPU | OCP_USER_SDMA,
196 /* L4 PER -> UART3 interface */
197 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
199 .pa_start = OMAP3_UART3_BASE,
200 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
201 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
205 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
206 .master = &omap3xxx_l4_per_hwmod,
207 .slave = &omap3xxx_uart3_hwmod,
209 .addr = omap3xxx_uart3_addr_space,
210 .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
211 .user = OCP_USER_MPU | OCP_USER_SDMA,
214 /* L4 PER -> UART4 interface */
215 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
217 .pa_start = OMAP3_UART4_BASE,
218 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
219 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
223 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
224 .master = &omap3xxx_l4_per_hwmod,
225 .slave = &omap3xxx_uart4_hwmod,
227 .addr = omap3xxx_uart4_addr_space,
228 .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
229 .user = OCP_USER_MPU | OCP_USER_SDMA,
232 /* I2C IP block address space length (in bytes) */
233 #define OMAP2_I2C_AS_LEN 128
235 /* L4 CORE -> I2C1 interface */
236 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
238 .pa_start = 0x48070000,
239 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
240 .flags = ADDR_TYPE_RT,
244 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
245 .master = &omap3xxx_l4_core_hwmod,
246 .slave = &omap3xxx_i2c1_hwmod,
248 .addr = omap3xxx_i2c1_addr_space,
249 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
252 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
254 .flags = OMAP_FIREWALL_L4,
257 .user = OCP_USER_MPU | OCP_USER_SDMA,
260 /* L4 CORE -> I2C2 interface */
261 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
263 .pa_start = 0x48072000,
264 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
265 .flags = ADDR_TYPE_RT,
269 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
270 .master = &omap3xxx_l4_core_hwmod,
271 .slave = &omap3xxx_i2c2_hwmod,
273 .addr = omap3xxx_i2c2_addr_space,
274 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
277 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
279 .flags = OMAP_FIREWALL_L4,
282 .user = OCP_USER_MPU | OCP_USER_SDMA,
285 /* L4 CORE -> I2C3 interface */
286 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
288 .pa_start = 0x48060000,
289 .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
290 .flags = ADDR_TYPE_RT,
294 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
295 .master = &omap3xxx_l4_core_hwmod,
296 .slave = &omap3xxx_i2c3_hwmod,
298 .addr = omap3xxx_i2c3_addr_space,
299 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
302 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
304 .flags = OMAP_FIREWALL_L4,
307 .user = OCP_USER_MPU | OCP_USER_SDMA,
310 /* L4 CORE -> SR1 interface */
311 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
313 .pa_start = OMAP34XX_SR1_BASE,
314 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
315 .flags = ADDR_TYPE_RT,
319 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
320 .master = &omap3xxx_l4_core_hwmod,
321 .slave = &omap34xx_sr1_hwmod,
323 .addr = omap3_sr1_addr_space,
324 .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
325 .user = OCP_USER_MPU,
328 /* L4 CORE -> SR1 interface */
329 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
331 .pa_start = OMAP34XX_SR2_BASE,
332 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
333 .flags = ADDR_TYPE_RT,
337 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
338 .master = &omap3xxx_l4_core_hwmod,
339 .slave = &omap34xx_sr2_hwmod,
341 .addr = omap3_sr2_addr_space,
342 .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
343 .user = OCP_USER_MPU,
347 * usbhsotg interface data
350 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
352 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
353 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
354 .flags = ADDR_TYPE_RT
358 /* l4_core -> usbhsotg */
359 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
360 .master = &omap3xxx_l4_core_hwmod,
361 .slave = &omap3xxx_usbhsotg_hwmod,
363 .addr = omap3xxx_usbhsotg_addrs,
364 .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
365 .user = OCP_USER_MPU,
368 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
369 &omap3xxx_usbhsotg__l3,
372 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
373 &omap3xxx_l4_core__usbhsotg,
376 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
378 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
379 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
380 .flags = ADDR_TYPE_RT
384 /* l4_core -> usbhsotg */
385 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
386 .master = &omap3xxx_l4_core_hwmod,
387 .slave = &am35xx_usbhsotg_hwmod,
389 .addr = am35xx_usbhsotg_addrs,
390 .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
391 .user = OCP_USER_MPU,
394 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
395 &am35xx_usbhsotg__l3,
398 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
399 &am35xx_l4_core__usbhsotg,
401 /* Slave interfaces on the L4_CORE interconnect */
402 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
403 &omap3xxx_l3_main__l4_core,
408 /* Master interfaces on the L4_CORE interconnect */
409 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
410 &omap3xxx_l4_core__l4_wkup,
411 &omap3_l4_core__uart1,
412 &omap3_l4_core__uart2,
413 &omap3_l4_core__i2c1,
414 &omap3_l4_core__i2c2,
415 &omap3_l4_core__i2c3,
419 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
421 .class = &l4_hwmod_class,
422 .masters = omap3xxx_l4_core_masters,
423 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
424 .slaves = omap3xxx_l4_core_slaves,
425 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
426 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
427 .flags = HWMOD_NO_IDLEST,
430 /* Slave interfaces on the L4_PER interconnect */
431 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
432 &omap3xxx_l3_main__l4_per,
435 /* Master interfaces on the L4_PER interconnect */
436 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
437 &omap3_l4_per__uart3,
438 &omap3_l4_per__uart4,
442 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
444 .class = &l4_hwmod_class,
445 .masters = omap3xxx_l4_per_masters,
446 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
447 .slaves = omap3xxx_l4_per_slaves,
448 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
449 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
450 .flags = HWMOD_NO_IDLEST,
453 /* Slave interfaces on the L4_WKUP interconnect */
454 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
455 &omap3xxx_l4_core__l4_wkup,
458 /* Master interfaces on the L4_WKUP interconnect */
459 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
463 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
465 .class = &l4_hwmod_class,
466 .masters = omap3xxx_l4_wkup_masters,
467 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
468 .slaves = omap3xxx_l4_wkup_slaves,
469 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
470 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
471 .flags = HWMOD_NO_IDLEST,
474 /* Master interfaces on the MPU device */
475 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
476 &omap3xxx_mpu__l3_main,
480 static struct omap_hwmod omap3xxx_mpu_hwmod = {
482 .class = &mpu_hwmod_class,
483 .main_clk = "arm_fck",
484 .masters = omap3xxx_mpu_masters,
485 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
486 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
490 * IVA2_2 interface data
493 /* IVA2 <- L3 interface */
494 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
495 .master = &omap3xxx_l3_main_hwmod,
496 .slave = &omap3xxx_iva_hwmod,
498 .user = OCP_USER_MPU | OCP_USER_SDMA,
501 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
509 static struct omap_hwmod omap3xxx_iva_hwmod = {
511 .class = &iva_hwmod_class,
512 .masters = omap3xxx_iva_masters,
513 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
514 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
517 /* l4_wkup -> wd_timer2 */
518 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
520 .pa_start = 0x48314000,
521 .pa_end = 0x4831407f,
522 .flags = ADDR_TYPE_RT
526 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
527 .master = &omap3xxx_l4_wkup_hwmod,
528 .slave = &omap3xxx_wd_timer2_hwmod,
530 .addr = omap3xxx_wd_timer2_addrs,
531 .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
532 .user = OCP_USER_MPU | OCP_USER_SDMA,
537 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
541 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
545 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
546 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
547 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
548 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
549 .sysc_fields = &omap_hwmod_sysc_type1,
553 static struct omap_hwmod_class_sysconfig i2c_sysc = {
557 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
558 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
560 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
561 .sysc_fields = &omap_hwmod_sysc_type1,
564 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
566 .sysc = &omap3xxx_wd_timer_sysc,
567 .pre_shutdown = &omap2_wd_timer_disable
571 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
572 &omap3xxx_l4_wkup__wd_timer2,
575 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
577 .class = &omap3xxx_wd_timer_hwmod_class,
578 .main_clk = "wdt2_fck",
582 .module_bit = OMAP3430_EN_WDT2_SHIFT,
583 .module_offs = WKUP_MOD,
585 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
588 .slaves = omap3xxx_wd_timer2_slaves,
589 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
590 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
595 static struct omap_hwmod_class_sysconfig uart_sysc = {
599 .sysc_flags = (SYSC_HAS_SIDLEMODE |
600 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
602 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
603 .sysc_fields = &omap_hwmod_sysc_type1,
606 static struct omap_hwmod_class uart_class = {
613 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
614 { .irq = INT_24XX_UART1_IRQ, },
617 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
618 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
619 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
622 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
623 &omap3_l4_core__uart1,
626 static struct omap_hwmod omap3xxx_uart1_hwmod = {
628 .mpu_irqs = uart1_mpu_irqs,
629 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
630 .sdma_reqs = uart1_sdma_reqs,
631 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
632 .main_clk = "uart1_fck",
635 .module_offs = CORE_MOD,
637 .module_bit = OMAP3430_EN_UART1_SHIFT,
639 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
642 .slaves = omap3xxx_uart1_slaves,
643 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
644 .class = &uart_class,
645 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
650 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
651 { .irq = INT_24XX_UART2_IRQ, },
654 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
655 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
656 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
659 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
660 &omap3_l4_core__uart2,
663 static struct omap_hwmod omap3xxx_uart2_hwmod = {
665 .mpu_irqs = uart2_mpu_irqs,
666 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
667 .sdma_reqs = uart2_sdma_reqs,
668 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
669 .main_clk = "uart2_fck",
672 .module_offs = CORE_MOD,
674 .module_bit = OMAP3430_EN_UART2_SHIFT,
676 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
679 .slaves = omap3xxx_uart2_slaves,
680 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
681 .class = &uart_class,
682 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
687 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
688 { .irq = INT_24XX_UART3_IRQ, },
691 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
692 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
693 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
696 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
697 &omap3_l4_per__uart3,
700 static struct omap_hwmod omap3xxx_uart3_hwmod = {
702 .mpu_irqs = uart3_mpu_irqs,
703 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
704 .sdma_reqs = uart3_sdma_reqs,
705 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
706 .main_clk = "uart3_fck",
709 .module_offs = OMAP3430_PER_MOD,
711 .module_bit = OMAP3430_EN_UART3_SHIFT,
713 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
716 .slaves = omap3xxx_uart3_slaves,
717 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
718 .class = &uart_class,
719 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
724 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
725 { .irq = INT_36XX_UART4_IRQ, },
728 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
729 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
730 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
733 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
734 &omap3_l4_per__uart4,
737 static struct omap_hwmod omap3xxx_uart4_hwmod = {
739 .mpu_irqs = uart4_mpu_irqs,
740 .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
741 .sdma_reqs = uart4_sdma_reqs,
742 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
743 .main_clk = "uart4_fck",
746 .module_offs = OMAP3430_PER_MOD,
748 .module_bit = OMAP3630_EN_UART4_SHIFT,
750 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
753 .slaves = omap3xxx_uart4_slaves,
754 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
755 .class = &uart_class,
756 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
759 static struct omap_hwmod_class i2c_class = {
769 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
773 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
774 .sysc_fields = &omap_hwmod_sysc_type1,
777 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
779 .sysc = &omap3xxx_dss_sysc,
783 static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = {
787 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
788 { .name = "dispc", .dma_req = 5 },
789 { .name = "dsi1", .dma_req = 74 },
793 /* dss master ports */
794 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
798 static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
800 .pa_start = 0x48050000,
801 .pa_end = 0x480503FF,
802 .flags = ADDR_TYPE_RT
807 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
808 .master = &omap3xxx_l4_core_hwmod,
809 .slave = &omap3430es1_dss_core_hwmod,
811 .addr = omap3xxx_dss_addrs,
812 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
815 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
816 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
817 .flags = OMAP_FIREWALL_L4,
820 .user = OCP_USER_MPU | OCP_USER_SDMA,
823 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
824 .master = &omap3xxx_l4_core_hwmod,
825 .slave = &omap3xxx_dss_core_hwmod,
827 .addr = omap3xxx_dss_addrs,
828 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
831 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
832 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
833 .flags = OMAP_FIREWALL_L4,
836 .user = OCP_USER_MPU | OCP_USER_SDMA,
839 /* dss slave ports */
840 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
841 &omap3430es1_l4_core__dss,
844 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
845 &omap3xxx_l4_core__dss,
848 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
849 { .role = "tv_clk", .clk = "dss_tv_fck" },
850 { .role = "dssclk", .clk = "dss_96m_fck" },
851 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
854 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
856 .class = &omap3xxx_dss_hwmod_class,
857 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
858 .mpu_irqs = omap3xxx_dss_irqs,
859 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
860 .sdma_reqs = omap3xxx_dss_sdma_chs,
861 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
866 .module_bit = OMAP3430_EN_DSS1_SHIFT,
867 .module_offs = OMAP3430_DSS_MOD,
869 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
872 .opt_clks = dss_opt_clks,
873 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
874 .slaves = omap3430es1_dss_slaves,
875 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
876 .masters = omap3xxx_dss_masters,
877 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
878 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
879 .flags = HWMOD_NO_IDLEST,
882 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
884 .class = &omap3xxx_dss_hwmod_class,
885 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
886 .mpu_irqs = omap3xxx_dss_irqs,
887 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
888 .sdma_reqs = omap3xxx_dss_sdma_chs,
889 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
894 .module_bit = OMAP3430_EN_DSS1_SHIFT,
895 .module_offs = OMAP3430_DSS_MOD,
897 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
898 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
901 .opt_clks = dss_opt_clks,
902 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
903 .slaves = omap3xxx_dss_slaves,
904 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
905 .masters = omap3xxx_dss_masters,
906 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
907 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
908 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
916 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
920 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
921 SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
922 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
923 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
924 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
925 .sysc_fields = &omap_hwmod_sysc_type1,
928 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
930 .sysc = &omap3xxx_dispc_sysc,
933 static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
935 .pa_start = 0x48050400,
936 .pa_end = 0x480507FF,
937 .flags = ADDR_TYPE_RT
941 /* l4_core -> dss_dispc */
942 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
943 .master = &omap3xxx_l4_core_hwmod,
944 .slave = &omap3xxx_dss_dispc_hwmod,
946 .addr = omap3xxx_dss_dispc_addrs,
947 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
950 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
951 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
952 .flags = OMAP_FIREWALL_L4,
955 .user = OCP_USER_MPU | OCP_USER_SDMA,
958 /* dss_dispc slave ports */
959 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
960 &omap3xxx_l4_core__dss_dispc,
963 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
965 .class = &omap3xxx_dispc_hwmod_class,
966 .main_clk = "dss1_alwon_fck",
970 .module_bit = OMAP3430_EN_DSS1_SHIFT,
971 .module_offs = OMAP3430_DSS_MOD,
974 .slaves = omap3xxx_dss_dispc_slaves,
975 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
976 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
977 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
978 CHIP_GE_OMAP3630ES1_1),
979 .flags = HWMOD_NO_IDLEST,
984 * display serial interface controller
987 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
992 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
994 .pa_start = 0x4804FC00,
995 .pa_end = 0x4804FFFF,
996 .flags = ADDR_TYPE_RT
1000 /* l4_core -> dss_dsi1 */
1001 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1002 .master = &omap3xxx_l4_core_hwmod,
1003 .slave = &omap3xxx_dss_dsi1_hwmod,
1004 .addr = omap3xxx_dss_dsi1_addrs,
1005 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
1008 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1009 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1010 .flags = OMAP_FIREWALL_L4,
1013 .user = OCP_USER_MPU | OCP_USER_SDMA,
1016 /* dss_dsi1 slave ports */
1017 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1018 &omap3xxx_l4_core__dss_dsi1,
1021 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1023 .class = &omap3xxx_dsi_hwmod_class,
1024 .main_clk = "dss1_alwon_fck",
1028 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1029 .module_offs = OMAP3430_DSS_MOD,
1032 .slaves = omap3xxx_dss_dsi1_slaves,
1033 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1034 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1035 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1036 CHIP_GE_OMAP3630ES1_1),
1037 .flags = HWMOD_NO_IDLEST,
1042 * remote frame buffer interface
1045 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1047 .sysc_offs = 0x0010,
1048 .syss_offs = 0x0014,
1049 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1051 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1052 .sysc_fields = &omap_hwmod_sysc_type1,
1055 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1057 .sysc = &omap3xxx_rfbi_sysc,
1060 static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1062 .pa_start = 0x48050800,
1063 .pa_end = 0x48050BFF,
1064 .flags = ADDR_TYPE_RT
1068 /* l4_core -> dss_rfbi */
1069 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1070 .master = &omap3xxx_l4_core_hwmod,
1071 .slave = &omap3xxx_dss_rfbi_hwmod,
1073 .addr = omap3xxx_dss_rfbi_addrs,
1074 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
1077 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1078 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1079 .flags = OMAP_FIREWALL_L4,
1082 .user = OCP_USER_MPU | OCP_USER_SDMA,
1085 /* dss_rfbi slave ports */
1086 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1087 &omap3xxx_l4_core__dss_rfbi,
1090 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1092 .class = &omap3xxx_rfbi_hwmod_class,
1093 .main_clk = "dss1_alwon_fck",
1097 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1098 .module_offs = OMAP3430_DSS_MOD,
1101 .slaves = omap3xxx_dss_rfbi_slaves,
1102 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1103 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1104 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1105 CHIP_GE_OMAP3630ES1_1),
1106 .flags = HWMOD_NO_IDLEST,
1114 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1119 static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1121 .pa_start = 0x48050C00,
1122 .pa_end = 0x48050FFF,
1123 .flags = ADDR_TYPE_RT
1127 /* l4_core -> dss_venc */
1128 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1129 .master = &omap3xxx_l4_core_hwmod,
1130 .slave = &omap3xxx_dss_venc_hwmod,
1131 .clk = "dss_tv_fck",
1132 .addr = omap3xxx_dss_venc_addrs,
1133 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
1136 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1137 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1138 .flags = OMAP_FIREWALL_L4,
1141 .user = OCP_USER_MPU | OCP_USER_SDMA,
1144 /* dss_venc slave ports */
1145 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1146 &omap3xxx_l4_core__dss_venc,
1149 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1151 .class = &omap3xxx_venc_hwmod_class,
1152 .main_clk = "dss1_alwon_fck",
1156 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1157 .module_offs = OMAP3430_DSS_MOD,
1160 .slaves = omap3xxx_dss_venc_slaves,
1161 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1162 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1163 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1164 CHIP_GE_OMAP3630ES1_1),
1165 .flags = HWMOD_NO_IDLEST,
1170 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1171 .fifo_depth = 8, /* bytes */
1174 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1175 { .irq = INT_24XX_I2C1_IRQ, },
1178 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1179 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1180 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1183 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1184 &omap3_l4_core__i2c1,
1187 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1189 .mpu_irqs = i2c1_mpu_irqs,
1190 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
1191 .sdma_reqs = i2c1_sdma_reqs,
1192 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1193 .main_clk = "i2c1_fck",
1196 .module_offs = CORE_MOD,
1198 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1200 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1203 .slaves = omap3xxx_i2c1_slaves,
1204 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1205 .class = &i2c_class,
1206 .dev_attr = &i2c1_dev_attr,
1207 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1212 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1213 .fifo_depth = 8, /* bytes */
1216 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1217 { .irq = INT_24XX_I2C2_IRQ, },
1220 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1221 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1222 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1225 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1226 &omap3_l4_core__i2c2,
1229 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1231 .mpu_irqs = i2c2_mpu_irqs,
1232 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
1233 .sdma_reqs = i2c2_sdma_reqs,
1234 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1235 .main_clk = "i2c2_fck",
1238 .module_offs = CORE_MOD,
1240 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1242 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1245 .slaves = omap3xxx_i2c2_slaves,
1246 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1247 .class = &i2c_class,
1248 .dev_attr = &i2c2_dev_attr,
1249 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1254 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1255 .fifo_depth = 64, /* bytes */
1258 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1259 { .irq = INT_34XX_I2C3_IRQ, },
1262 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1263 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1264 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1267 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1268 &omap3_l4_core__i2c3,
1271 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1273 .mpu_irqs = i2c3_mpu_irqs,
1274 .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
1275 .sdma_reqs = i2c3_sdma_reqs,
1276 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
1277 .main_clk = "i2c3_fck",
1280 .module_offs = CORE_MOD,
1282 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1284 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1287 .slaves = omap3xxx_i2c3_slaves,
1288 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1289 .class = &i2c_class,
1290 .dev_attr = &i2c3_dev_attr,
1291 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1294 /* l4_wkup -> gpio1 */
1295 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1297 .pa_start = 0x48310000,
1298 .pa_end = 0x483101ff,
1299 .flags = ADDR_TYPE_RT
1303 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1304 .master = &omap3xxx_l4_wkup_hwmod,
1305 .slave = &omap3xxx_gpio1_hwmod,
1306 .addr = omap3xxx_gpio1_addrs,
1307 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
1308 .user = OCP_USER_MPU | OCP_USER_SDMA,
1311 /* l4_per -> gpio2 */
1312 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1314 .pa_start = 0x49050000,
1315 .pa_end = 0x490501ff,
1316 .flags = ADDR_TYPE_RT
1320 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1321 .master = &omap3xxx_l4_per_hwmod,
1322 .slave = &omap3xxx_gpio2_hwmod,
1323 .addr = omap3xxx_gpio2_addrs,
1324 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
1325 .user = OCP_USER_MPU | OCP_USER_SDMA,
1328 /* l4_per -> gpio3 */
1329 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1331 .pa_start = 0x49052000,
1332 .pa_end = 0x490521ff,
1333 .flags = ADDR_TYPE_RT
1337 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1338 .master = &omap3xxx_l4_per_hwmod,
1339 .slave = &omap3xxx_gpio3_hwmod,
1340 .addr = omap3xxx_gpio3_addrs,
1341 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
1342 .user = OCP_USER_MPU | OCP_USER_SDMA,
1345 /* l4_per -> gpio4 */
1346 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1348 .pa_start = 0x49054000,
1349 .pa_end = 0x490541ff,
1350 .flags = ADDR_TYPE_RT
1354 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1355 .master = &omap3xxx_l4_per_hwmod,
1356 .slave = &omap3xxx_gpio4_hwmod,
1357 .addr = omap3xxx_gpio4_addrs,
1358 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
1359 .user = OCP_USER_MPU | OCP_USER_SDMA,
1362 /* l4_per -> gpio5 */
1363 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1365 .pa_start = 0x49056000,
1366 .pa_end = 0x490561ff,
1367 .flags = ADDR_TYPE_RT
1371 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1372 .master = &omap3xxx_l4_per_hwmod,
1373 .slave = &omap3xxx_gpio5_hwmod,
1374 .addr = omap3xxx_gpio5_addrs,
1375 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
1376 .user = OCP_USER_MPU | OCP_USER_SDMA,
1379 /* l4_per -> gpio6 */
1380 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1382 .pa_start = 0x49058000,
1383 .pa_end = 0x490581ff,
1384 .flags = ADDR_TYPE_RT
1388 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1389 .master = &omap3xxx_l4_per_hwmod,
1390 .slave = &omap3xxx_gpio6_hwmod,
1391 .addr = omap3xxx_gpio6_addrs,
1392 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
1393 .user = OCP_USER_MPU | OCP_USER_SDMA,
1398 * general purpose io module
1401 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1403 .sysc_offs = 0x0010,
1404 .syss_offs = 0x0014,
1405 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1406 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1407 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1408 .sysc_fields = &omap_hwmod_sysc_type1,
1411 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1413 .sysc = &omap3xxx_gpio_sysc,
1418 static struct omap_gpio_dev_attr gpio_dev_attr = {
1424 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
1425 { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
1428 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1429 { .role = "dbclk", .clk = "gpio1_dbck", },
1432 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1433 &omap3xxx_l4_wkup__gpio1,
1436 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1438 .mpu_irqs = omap3xxx_gpio1_irqs,
1439 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
1440 .main_clk = "gpio1_ick",
1441 .opt_clks = gpio1_opt_clks,
1442 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1446 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1447 .module_offs = WKUP_MOD,
1449 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1452 .slaves = omap3xxx_gpio1_slaves,
1453 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1454 .class = &omap3xxx_gpio_hwmod_class,
1455 .dev_attr = &gpio_dev_attr,
1456 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1460 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
1461 { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
1464 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1465 { .role = "dbclk", .clk = "gpio2_dbck", },
1468 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1469 &omap3xxx_l4_per__gpio2,
1472 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1474 .mpu_irqs = omap3xxx_gpio2_irqs,
1475 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
1476 .main_clk = "gpio2_ick",
1477 .opt_clks = gpio2_opt_clks,
1478 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1482 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1483 .module_offs = OMAP3430_PER_MOD,
1485 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1488 .slaves = omap3xxx_gpio2_slaves,
1489 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1490 .class = &omap3xxx_gpio_hwmod_class,
1491 .dev_attr = &gpio_dev_attr,
1492 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1496 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
1497 { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
1500 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1501 { .role = "dbclk", .clk = "gpio3_dbck", },
1504 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1505 &omap3xxx_l4_per__gpio3,
1508 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1510 .mpu_irqs = omap3xxx_gpio3_irqs,
1511 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
1512 .main_clk = "gpio3_ick",
1513 .opt_clks = gpio3_opt_clks,
1514 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1518 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1519 .module_offs = OMAP3430_PER_MOD,
1521 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1524 .slaves = omap3xxx_gpio3_slaves,
1525 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1526 .class = &omap3xxx_gpio_hwmod_class,
1527 .dev_attr = &gpio_dev_attr,
1528 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1532 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
1533 { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
1536 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1537 { .role = "dbclk", .clk = "gpio4_dbck", },
1540 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1541 &omap3xxx_l4_per__gpio4,
1544 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1546 .mpu_irqs = omap3xxx_gpio4_irqs,
1547 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
1548 .main_clk = "gpio4_ick",
1549 .opt_clks = gpio4_opt_clks,
1550 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1554 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1555 .module_offs = OMAP3430_PER_MOD,
1557 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1560 .slaves = omap3xxx_gpio4_slaves,
1561 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1562 .class = &omap3xxx_gpio_hwmod_class,
1563 .dev_attr = &gpio_dev_attr,
1564 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1568 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1569 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1572 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1573 { .role = "dbclk", .clk = "gpio5_dbck", },
1576 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
1577 &omap3xxx_l4_per__gpio5,
1580 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1582 .mpu_irqs = omap3xxx_gpio5_irqs,
1583 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
1584 .main_clk = "gpio5_ick",
1585 .opt_clks = gpio5_opt_clks,
1586 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1590 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1591 .module_offs = OMAP3430_PER_MOD,
1593 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1596 .slaves = omap3xxx_gpio5_slaves,
1597 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
1598 .class = &omap3xxx_gpio_hwmod_class,
1599 .dev_attr = &gpio_dev_attr,
1600 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1604 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1605 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
1608 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1609 { .role = "dbclk", .clk = "gpio6_dbck", },
1612 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
1613 &omap3xxx_l4_per__gpio6,
1616 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1618 .mpu_irqs = omap3xxx_gpio6_irqs,
1619 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
1620 .main_clk = "gpio6_ick",
1621 .opt_clks = gpio6_opt_clks,
1622 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1626 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1627 .module_offs = OMAP3430_PER_MOD,
1629 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1632 .slaves = omap3xxx_gpio6_slaves,
1633 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
1634 .class = &omap3xxx_gpio_hwmod_class,
1635 .dev_attr = &gpio_dev_attr,
1636 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1639 /* dma_system -> L3 */
1640 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
1641 .master = &omap3xxx_dma_system_hwmod,
1642 .slave = &omap3xxx_l3_main_hwmod,
1643 .clk = "core_l3_ick",
1644 .user = OCP_USER_MPU | OCP_USER_SDMA,
1647 /* dma attributes */
1648 static struct omap_dma_dev_attr dma_dev_attr = {
1649 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1650 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1654 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1656 .sysc_offs = 0x002c,
1657 .syss_offs = 0x0028,
1658 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1659 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1660 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
1661 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1662 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1663 .sysc_fields = &omap_hwmod_sysc_type1,
1666 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1668 .sysc = &omap3xxx_dma_sysc,
1672 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
1673 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1674 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1675 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1676 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1679 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
1681 .pa_start = 0x48056000,
1682 .pa_end = 0x4a0560ff,
1683 .flags = ADDR_TYPE_RT
1687 /* dma_system master ports */
1688 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
1689 &omap3xxx_dma_system__l3,
1692 /* l4_cfg -> dma_system */
1693 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
1694 .master = &omap3xxx_l4_core_hwmod,
1695 .slave = &omap3xxx_dma_system_hwmod,
1696 .clk = "core_l4_ick",
1697 .addr = omap3xxx_dma_system_addrs,
1698 .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
1699 .user = OCP_USER_MPU | OCP_USER_SDMA,
1702 /* dma_system slave ports */
1703 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
1704 &omap3xxx_l4_core__dma_system,
1707 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1709 .class = &omap3xxx_dma_hwmod_class,
1710 .mpu_irqs = omap3xxx_dma_system_irqs,
1711 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
1712 .main_clk = "core_l3_ick",
1715 .module_offs = CORE_MOD,
1717 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1719 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1722 .slaves = omap3xxx_dma_system_slaves,
1723 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
1724 .masters = omap3xxx_dma_system_masters,
1725 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
1726 .dev_attr = &dma_dev_attr,
1727 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1728 .flags = HWMOD_NO_IDLEST,
1732 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1736 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1738 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1739 .clockact = CLOCKACT_TEST_ICLK,
1740 .sysc_fields = &omap34xx_sr_sysc_fields,
1743 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1744 .name = "smartreflex",
1745 .sysc = &omap34xx_sr_sysc,
1749 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1754 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1756 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1757 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1759 .sysc_fields = &omap36xx_sr_sysc_fields,
1762 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1763 .name = "smartreflex",
1764 .sysc = &omap36xx_sr_sysc,
1769 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
1770 &omap3_l4_core__sr1,
1773 static struct omap_hwmod omap34xx_sr1_hwmod = {
1774 .name = "sr1_hwmod",
1775 .class = &omap34xx_smartreflex_hwmod_class,
1776 .main_clk = "sr1_fck",
1781 .module_bit = OMAP3430_EN_SR1_SHIFT,
1782 .module_offs = WKUP_MOD,
1784 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1787 .slaves = omap3_sr1_slaves,
1788 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
1789 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
1790 CHIP_IS_OMAP3430ES3_0 |
1791 CHIP_IS_OMAP3430ES3_1),
1792 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1795 static struct omap_hwmod omap36xx_sr1_hwmod = {
1796 .name = "sr1_hwmod",
1797 .class = &omap36xx_smartreflex_hwmod_class,
1798 .main_clk = "sr1_fck",
1803 .module_bit = OMAP3430_EN_SR1_SHIFT,
1804 .module_offs = WKUP_MOD,
1806 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1809 .slaves = omap3_sr1_slaves,
1810 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
1811 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1815 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
1816 &omap3_l4_core__sr2,
1819 static struct omap_hwmod omap34xx_sr2_hwmod = {
1820 .name = "sr2_hwmod",
1821 .class = &omap34xx_smartreflex_hwmod_class,
1822 .main_clk = "sr2_fck",
1827 .module_bit = OMAP3430_EN_SR2_SHIFT,
1828 .module_offs = WKUP_MOD,
1830 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1833 .slaves = omap3_sr2_slaves,
1834 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
1835 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
1836 CHIP_IS_OMAP3430ES3_0 |
1837 CHIP_IS_OMAP3430ES3_1),
1838 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1841 static struct omap_hwmod omap36xx_sr2_hwmod = {
1842 .name = "sr2_hwmod",
1843 .class = &omap36xx_smartreflex_hwmod_class,
1844 .main_clk = "sr2_fck",
1849 .module_bit = OMAP3430_EN_SR2_SHIFT,
1850 .module_offs = WKUP_MOD,
1852 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1855 .slaves = omap3_sr2_slaves,
1856 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
1857 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1860 /* l4 core -> mcspi1 interface */
1861 static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
1863 .pa_start = 0x48098000,
1864 .pa_end = 0x480980ff,
1865 .flags = ADDR_TYPE_RT,
1869 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
1870 .master = &omap3xxx_l4_core_hwmod,
1871 .slave = &omap34xx_mcspi1,
1872 .clk = "mcspi1_ick",
1873 .addr = omap34xx_mcspi1_addr_space,
1874 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
1875 .user = OCP_USER_MPU | OCP_USER_SDMA,
1878 /* l4 core -> mcspi2 interface */
1879 static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
1881 .pa_start = 0x4809a000,
1882 .pa_end = 0x4809a0ff,
1883 .flags = ADDR_TYPE_RT,
1887 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
1888 .master = &omap3xxx_l4_core_hwmod,
1889 .slave = &omap34xx_mcspi2,
1890 .clk = "mcspi2_ick",
1891 .addr = omap34xx_mcspi2_addr_space,
1892 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
1893 .user = OCP_USER_MPU | OCP_USER_SDMA,
1896 /* l4 core -> mcspi3 interface */
1897 static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
1899 .pa_start = 0x480b8000,
1900 .pa_end = 0x480b80ff,
1901 .flags = ADDR_TYPE_RT,
1905 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
1906 .master = &omap3xxx_l4_core_hwmod,
1907 .slave = &omap34xx_mcspi3,
1908 .clk = "mcspi3_ick",
1909 .addr = omap34xx_mcspi3_addr_space,
1910 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
1911 .user = OCP_USER_MPU | OCP_USER_SDMA,
1914 /* l4 core -> mcspi4 interface */
1915 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
1917 .pa_start = 0x480ba000,
1918 .pa_end = 0x480ba0ff,
1919 .flags = ADDR_TYPE_RT,
1923 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
1924 .master = &omap3xxx_l4_core_hwmod,
1925 .slave = &omap34xx_mcspi4,
1926 .clk = "mcspi4_ick",
1927 .addr = omap34xx_mcspi4_addr_space,
1928 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
1929 .user = OCP_USER_MPU | OCP_USER_SDMA,
1934 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1938 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1940 .sysc_offs = 0x0010,
1941 .syss_offs = 0x0014,
1942 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1943 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1944 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1945 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1946 .sysc_fields = &omap_hwmod_sysc_type1,
1949 static struct omap_hwmod_class omap34xx_mcspi_class = {
1951 .sysc = &omap34xx_mcspi_sysc,
1952 .rev = OMAP3_MCSPI_REV,
1956 static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
1957 { .name = "irq", .irq = 65 },
1960 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
1961 { .name = "tx0", .dma_req = 35 },
1962 { .name = "rx0", .dma_req = 36 },
1963 { .name = "tx1", .dma_req = 37 },
1964 { .name = "rx1", .dma_req = 38 },
1965 { .name = "tx2", .dma_req = 39 },
1966 { .name = "rx2", .dma_req = 40 },
1967 { .name = "tx3", .dma_req = 41 },
1968 { .name = "rx3", .dma_req = 42 },
1971 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
1972 &omap34xx_l4_core__mcspi1,
1975 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1976 .num_chipselect = 4,
1979 static struct omap_hwmod omap34xx_mcspi1 = {
1981 .mpu_irqs = omap34xx_mcspi1_mpu_irqs,
1982 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
1983 .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
1984 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
1985 .main_clk = "mcspi1_fck",
1988 .module_offs = CORE_MOD,
1990 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1992 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1995 .slaves = omap34xx_mcspi1_slaves,
1996 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
1997 .class = &omap34xx_mcspi_class,
1998 .dev_attr = &omap_mcspi1_dev_attr,
1999 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2003 static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
2004 { .name = "irq", .irq = 66 },
2007 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
2008 { .name = "tx0", .dma_req = 43 },
2009 { .name = "rx0", .dma_req = 44 },
2010 { .name = "tx1", .dma_req = 45 },
2011 { .name = "rx1", .dma_req = 46 },
2014 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2015 &omap34xx_l4_core__mcspi2,
2018 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2019 .num_chipselect = 2,
2022 static struct omap_hwmod omap34xx_mcspi2 = {
2024 .mpu_irqs = omap34xx_mcspi2_mpu_irqs,
2025 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
2026 .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
2027 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
2028 .main_clk = "mcspi2_fck",
2031 .module_offs = CORE_MOD,
2033 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2035 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2038 .slaves = omap34xx_mcspi2_slaves,
2039 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2040 .class = &omap34xx_mcspi_class,
2041 .dev_attr = &omap_mcspi2_dev_attr,
2042 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2046 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2047 { .name = "irq", .irq = 91 }, /* 91 */
2050 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2051 { .name = "tx0", .dma_req = 15 },
2052 { .name = "rx0", .dma_req = 16 },
2053 { .name = "tx1", .dma_req = 23 },
2054 { .name = "rx1", .dma_req = 24 },
2057 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2058 &omap34xx_l4_core__mcspi3,
2061 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2062 .num_chipselect = 2,
2065 static struct omap_hwmod omap34xx_mcspi3 = {
2067 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
2068 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
2069 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
2070 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
2071 .main_clk = "mcspi3_fck",
2074 .module_offs = CORE_MOD,
2076 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2078 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2081 .slaves = omap34xx_mcspi3_slaves,
2082 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2083 .class = &omap34xx_mcspi_class,
2084 .dev_attr = &omap_mcspi3_dev_attr,
2085 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2089 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2090 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2093 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2094 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2095 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2098 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2099 &omap34xx_l4_core__mcspi4,
2102 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2103 .num_chipselect = 1,
2106 static struct omap_hwmod omap34xx_mcspi4 = {
2108 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
2109 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
2110 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
2111 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
2112 .main_clk = "mcspi4_fck",
2115 .module_offs = CORE_MOD,
2117 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2119 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2122 .slaves = omap34xx_mcspi4_slaves,
2123 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2124 .class = &omap34xx_mcspi_class,
2125 .dev_attr = &omap_mcspi4_dev_attr,
2126 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2132 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2134 .sysc_offs = 0x0404,
2135 .syss_offs = 0x0408,
2136 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2137 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2139 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2140 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2141 .sysc_fields = &omap_hwmod_sysc_type1,
2144 static struct omap_hwmod_class usbotg_class = {
2146 .sysc = &omap3xxx_usbhsotg_sysc,
2149 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2151 { .name = "mc", .irq = 92 },
2152 { .name = "dma", .irq = 93 },
2155 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
2156 .name = "usb_otg_hs",
2157 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
2158 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
2159 .main_clk = "hsotgusb_ick",
2163 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
2164 .module_offs = CORE_MOD,
2166 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
2167 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
2170 .masters = omap3xxx_usbhsotg_masters,
2171 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
2172 .slaves = omap3xxx_usbhsotg_slaves,
2173 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
2174 .class = &usbotg_class,
2177 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
2178 * broken when autoidle is enabled
2179 * workaround is to disable the autoidle bit at module level.
2181 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
2182 | HWMOD_SWSUP_MSTANDBY,
2183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
2187 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
2189 { .name = "mc", .irq = 71 },
2192 static struct omap_hwmod_class am35xx_usbotg_class = {
2193 .name = "am35xx_usbotg",
2197 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
2198 .name = "am35x_otg_hs",
2199 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
2200 .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
2206 .masters = am35xx_usbhsotg_masters,
2207 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
2208 .slaves = am35xx_usbhsotg_slaves,
2209 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
2210 .class = &am35xx_usbotg_class,
2211 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
2214 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
2215 &omap3xxx_l3_main_hwmod,
2216 &omap3xxx_l4_core_hwmod,
2217 &omap3xxx_l4_per_hwmod,
2218 &omap3xxx_l4_wkup_hwmod,
2219 &omap3xxx_mpu_hwmod,
2220 &omap3xxx_iva_hwmod,
2221 &omap3xxx_wd_timer2_hwmod,
2222 &omap3xxx_uart1_hwmod,
2223 &omap3xxx_uart2_hwmod,
2224 &omap3xxx_uart3_hwmod,
2225 &omap3xxx_uart4_hwmod,
2227 &omap3430es1_dss_core_hwmod,
2228 &omap3xxx_dss_core_hwmod,
2229 &omap3xxx_dss_dispc_hwmod,
2230 &omap3xxx_dss_dsi1_hwmod,
2231 &omap3xxx_dss_rfbi_hwmod,
2232 &omap3xxx_dss_venc_hwmod,
2235 &omap3xxx_i2c1_hwmod,
2236 &omap3xxx_i2c2_hwmod,
2237 &omap3xxx_i2c3_hwmod,
2238 &omap34xx_sr1_hwmod,
2239 &omap34xx_sr2_hwmod,
2240 &omap36xx_sr1_hwmod,
2241 &omap36xx_sr2_hwmod,
2245 &omap3xxx_gpio1_hwmod,
2246 &omap3xxx_gpio2_hwmod,
2247 &omap3xxx_gpio3_hwmod,
2248 &omap3xxx_gpio4_hwmod,
2249 &omap3xxx_gpio5_hwmod,
2250 &omap3xxx_gpio6_hwmod,
2252 /* dma_system class*/
2253 &omap3xxx_dma_system_hwmod,
2262 &omap3xxx_usbhsotg_hwmod,
2264 /* usbotg for am35x */
2265 &am35xx_usbhsotg_hwmod,
2270 int __init omap3xxx_hwmod_init(void)
2272 return omap_hwmod_init(omap3xxx_hwmods);