arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l4_3xxx.h>
  22 #include <plat/i2c.h>
  23 #include <plat/gpio.h>
  24
  25 #include "omap_hwmod_common_data.h"
  26
  27 #include "prm-regbits-34xx.h"
  28 #include "cm-regbits-34xx.h"
  29
  30 /*
  31  * OMAP3xxx hardware module integration data
  32  *
  33  * ALl of the data in this section should be autogeneratable from the
  34  * TI hardware database or other technical documentation.  Data that
  35  * is driver-specific or driver-kernel integration-specific belongs
  36  * elsewhere.
  37  */
  38
  39 static struct omap_hwmod omap3xxx_mpu_hwmod;
  40 static struct omap_hwmod omap3xxx_iva_hwmod;
  41 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  42 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  43 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  44 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  45 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  46 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  47 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  48 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  49 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  50 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  51 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  52 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  53 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  54
  55 /* L3 -> L4_CORE interface */
  56 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  57         .master = &omap3xxx_l3_main_hwmod,
  58         .slave  = &omap3xxx_l4_core_hwmod,
  59         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  60 };
  61
  62 /* L3 -> L4_PER interface */
  63 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  64         .master = &omap3xxx_l3_main_hwmod,
  65         .slave  = &omap3xxx_l4_per_hwmod,
  66         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  67 };
  68
  69 /* MPU -> L3 interface */
  70 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
  71         .master = &omap3xxx_mpu_hwmod,
  72         .slave  = &omap3xxx_l3_main_hwmod,
  73         .user   = OCP_USER_MPU,
  74 };
  75
  76 /* Slave interfaces on the L3 interconnect */
  77 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
  78         &omap3xxx_mpu__l3_main,
  79 };
  80
  81 /* Master interfaces on the L3 interconnect */
  82 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
  83         &omap3xxx_l3_main__l4_core,
  84         &omap3xxx_l3_main__l4_per,
  85 };
  86
  87 /* L3 */
  88 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  89         .name           = "l3_main",
  90         .class          = &l3_hwmod_class,
  91         .masters        = omap3xxx_l3_main_masters,
  92         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
  93         .slaves         = omap3xxx_l3_main_slaves,
  94         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
  95         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  96         .flags          = HWMOD_NO_IDLEST,
  97 };
  98
  99 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 100 static struct omap_hwmod omap3xxx_uart1_hwmod;
 101 static struct omap_hwmod omap3xxx_uart2_hwmod;
 102 static struct omap_hwmod omap3xxx_uart3_hwmod;
 103 static struct omap_hwmod omap3xxx_uart4_hwmod;
 104
 105 /* L4_CORE -> L4_WKUP interface */
 106 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 107         .master = &omap3xxx_l4_core_hwmod,
 108         .slave  = &omap3xxx_l4_wkup_hwmod,
 109         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 110 };
 111
 112 /* L4 CORE -> UART1 interface */
 113 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 114         {
 115                 .pa_start       = OMAP3_UART1_BASE,
 116                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 117                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 118         },
 119 };
 120
 121 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 122         .master         = &omap3xxx_l4_core_hwmod,
 123         .slave          = &omap3xxx_uart1_hwmod,
 124         .clk            = "uart1_ick",
 125         .addr           = omap3xxx_uart1_addr_space,
 126         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart1_addr_space),
 127         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 128 };
 129
 130 /* L4 CORE -> UART2 interface */
 131 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 132         {
 133                 .pa_start       = OMAP3_UART2_BASE,
 134                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 135                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 136         },
 137 };
 138
 139 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 140         .master         = &omap3xxx_l4_core_hwmod,
 141         .slave          = &omap3xxx_uart2_hwmod,
 142         .clk            = "uart2_ick",
 143         .addr           = omap3xxx_uart2_addr_space,
 144         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart2_addr_space),
 145         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 146 };
 147
 148 /* L4 PER -> UART3 interface */
 149 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 150         {
 151                 .pa_start       = OMAP3_UART3_BASE,
 152                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 153                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 154         },
 155 };
 156
 157 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 158         .master         = &omap3xxx_l4_per_hwmod,
 159         .slave          = &omap3xxx_uart3_hwmod,
 160         .clk            = "uart3_ick",
 161         .addr           = omap3xxx_uart3_addr_space,
 162         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart3_addr_space),
 163         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 164 };
 165
 166 /* L4 PER -> UART4 interface */
 167 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 168         {
 169                 .pa_start       = OMAP3_UART4_BASE,
 170                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 171                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 172         },
 173 };
 174
 175 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 176         .master         = &omap3xxx_l4_per_hwmod,
 177         .slave          = &omap3xxx_uart4_hwmod,
 178         .clk            = "uart4_ick",
 179         .addr           = omap3xxx_uart4_addr_space,
 180         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart4_addr_space),
 181         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 182 };
 183
 184 /* I2C IP block address space length (in bytes) */
 185 #define OMAP2_I2C_AS_LEN                128
 186
 187 /* L4 CORE -> I2C1 interface */
 188 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
 189         {
 190                 .pa_start       = 0x48070000,
 191                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
 192                 .flags          = ADDR_TYPE_RT,
 193         },
 194 };
 195
 196 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 197         .master         = &omap3xxx_l4_core_hwmod,
 198         .slave          = &omap3xxx_i2c1_hwmod,
 199         .clk            = "i2c1_ick",
 200         .addr           = omap3xxx_i2c1_addr_space,
 201         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
 202         .fw = {
 203                 .omap2 = {
 204                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 205                         .l4_prot_group = 7,
 206                         .flags  = OMAP_FIREWALL_L4,
 207                 }
 208         },
 209         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 210 };
 211
 212 /* L4 CORE -> I2C2 interface */
 213 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
 214         {
 215                 .pa_start       = 0x48072000,
 216                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 217                 .flags          = ADDR_TYPE_RT,
 218         },
 219 };
 220
 221 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 222         .master         = &omap3xxx_l4_core_hwmod,
 223         .slave          = &omap3xxx_i2c2_hwmod,
 224         .clk            = "i2c2_ick",
 225         .addr           = omap3xxx_i2c2_addr_space,
 226         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
 227         .fw = {
 228                 .omap2 = {
 229                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 230                         .l4_prot_group = 7,
 231                         .flags = OMAP_FIREWALL_L4,
 232                 }
 233         },
 234         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 235 };
 236
 237 /* L4 CORE -> I2C3 interface */
 238 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 239         {
 240                 .pa_start       = 0x48060000,
 241                 .pa_end         = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
 242                 .flags          = ADDR_TYPE_RT,
 243         },
 244 };
 245
 246 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 247         .master         = &omap3xxx_l4_core_hwmod,
 248         .slave          = &omap3xxx_i2c3_hwmod,
 249         .clk            = "i2c3_ick",
 250         .addr           = omap3xxx_i2c3_addr_space,
 251         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
 252         .fw = {
 253                 .omap2 = {
 254                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 255                         .l4_prot_group = 7,
 256                         .flags = OMAP_FIREWALL_L4,
 257                 }
 258         },
 259         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 260 };
 261
 262 /* Slave interfaces on the L4_CORE interconnect */
 263 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 264         &omap3xxx_l3_main__l4_core,
 265 };
 266
 267 /* Master interfaces on the L4_CORE interconnect */
 268 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
 269         &omap3xxx_l4_core__l4_wkup,
 270         &omap3_l4_core__uart1,
 271         &omap3_l4_core__uart2,
 272         &omap3_l4_core__i2c1,
 273         &omap3_l4_core__i2c2,
 274         &omap3_l4_core__i2c3,
 275 };
 276
 277 /* L4 CORE */
 278 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 279         .name           = "l4_core",
 280         .class          = &l4_hwmod_class,
 281         .masters        = omap3xxx_l4_core_masters,
 282         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_core_masters),
 283         .slaves         = omap3xxx_l4_core_slaves,
 284         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 285         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 286         .flags          = HWMOD_NO_IDLEST,
 287 };
 288
 289 /* Slave interfaces on the L4_PER interconnect */
 290 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 291         &omap3xxx_l3_main__l4_per,
 292 };
 293
 294 /* Master interfaces on the L4_PER interconnect */
 295 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
 296         &omap3_l4_per__uart3,
 297         &omap3_l4_per__uart4,
 298 };
 299
 300 /* L4 PER */
 301 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 302         .name           = "l4_per",
 303         .class          = &l4_hwmod_class,
 304         .masters        = omap3xxx_l4_per_masters,
 305         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_per_masters),
 306         .slaves         = omap3xxx_l4_per_slaves,
 307         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 308         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 309         .flags          = HWMOD_NO_IDLEST,
 310 };
 311
 312 /* Slave interfaces on the L4_WKUP interconnect */
 313 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 314         &omap3xxx_l4_core__l4_wkup,
 315 };
 316
 317 /* Master interfaces on the L4_WKUP interconnect */
 318 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
 319 };
 320
 321 /* L4 WKUP */
 322 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 323         .name           = "l4_wkup",
 324         .class          = &l4_hwmod_class,
 325         .masters        = omap3xxx_l4_wkup_masters,
 326         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
 327         .slaves         = omap3xxx_l4_wkup_slaves,
 328         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 329         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 330         .flags          = HWMOD_NO_IDLEST,
 331 };
 332
 333 /* Master interfaces on the MPU device */
 334 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 335         &omap3xxx_mpu__l3_main,
 336 };
 337
 338 /* MPU */
 339 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 340         .name           = "mpu",
 341         .class          = &mpu_hwmod_class,
 342         .main_clk       = "arm_fck",
 343         .masters        = omap3xxx_mpu_masters,
 344         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 345         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 346 };
 347
 348 /*
 349  * IVA2_2 interface data
 350  */
 351
 352 /* IVA2 <- L3 interface */
 353 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 354         .master         = &omap3xxx_l3_main_hwmod,
 355         .slave          = &omap3xxx_iva_hwmod,
 356         .clk            = "iva2_ck",
 357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 358 };
 359
 360 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 361         &omap3xxx_l3__iva,
 362 };
 363
 364 /*
 365  * IVA2 (IVA2)
 366  */
 367
 368 static struct omap_hwmod omap3xxx_iva_hwmod = {
 369         .name           = "iva",
 370         .class          = &iva_hwmod_class,
 371         .masters        = omap3xxx_iva_masters,
 372         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 373         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 374 };
 375
 376 /* l4_wkup -> wd_timer2 */
 377 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
 378         {
 379                 .pa_start       = 0x48314000,
 380                 .pa_end         = 0x4831407f,
 381                 .flags          = ADDR_TYPE_RT
 382         },
 383 };
 384
 385 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
 386         .master         = &omap3xxx_l4_wkup_hwmod,
 387         .slave          = &omap3xxx_wd_timer2_hwmod,
 388         .clk            = "wdt2_ick",
 389         .addr           = omap3xxx_wd_timer2_addrs,
 390         .addr_cnt       = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
 391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 392 };
 393
 394 /*
 395  * 'wd_timer' class
 396  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 397  * overflow condition
 398  */
 399
 400 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 401         .rev_offs       = 0x0000,
 402         .sysc_offs      = 0x0010,
 403         .syss_offs      = 0x0014,
 404         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 405                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 406                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
 407         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 408         .sysc_fields    = &omap_hwmod_sysc_type1,
 409 };
 410
 411 /* I2C common */
 412 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 413         .rev_offs       = 0x00,
 414         .sysc_offs      = 0x20,
 415         .syss_offs      = 0x10,
 416         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 417                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 418                            SYSC_HAS_AUTOIDLE),
 419         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 420         .sysc_fields    = &omap_hwmod_sysc_type1,
 421 };
 422
 423 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 424         .name = "wd_timer",
 425         .sysc = &omap3xxx_wd_timer_sysc,
 426 };
 427
 428 /* wd_timer2 */
 429 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
 430         &omap3xxx_l4_wkup__wd_timer2,
 431 };
 432
 433 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 434         .name           = "wd_timer2",
 435         .class          = &omap3xxx_wd_timer_hwmod_class,
 436         .main_clk       = "wdt2_fck",
 437         .prcm           = {
 438                 .omap2 = {
 439                         .prcm_reg_id = 1,
 440                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 441                         .module_offs = WKUP_MOD,
 442                         .idlest_reg_id = 1,
 443                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 444                 },
 445         },
 446         .slaves         = omap3xxx_wd_timer2_slaves,
 447         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
 448         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 449 };
 450
 451 /* UART common */
 452
 453 static struct omap_hwmod_class_sysconfig uart_sysc = {
 454         .rev_offs       = 0x50,
 455         .sysc_offs      = 0x54,
 456         .syss_offs      = 0x58,
 457         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
 458                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 459                            SYSC_HAS_AUTOIDLE),
 460         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 461         .sysc_fields    = &omap_hwmod_sysc_type1,
 462 };
 463
 464 static struct omap_hwmod_class uart_class = {
 465         .name = "uart",
 466         .sysc = &uart_sysc,
 467 };
 468
 469 /* UART1 */
 470
 471 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
 472         { .irq = INT_24XX_UART1_IRQ, },
 473 };
 474
 475 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
 476         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
 477         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
 478 };
 479
 480 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
 481         &omap3_l4_core__uart1,
 482 };
 483
 484 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 485         .name           = "uart1",
 486         .mpu_irqs       = uart1_mpu_irqs,
 487         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
 488         .sdma_reqs      = uart1_sdma_reqs,
 489         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
 490         .main_clk       = "uart1_fck",
 491         .prcm           = {
 492                 .omap2 = {
 493                         .module_offs = CORE_MOD,
 494                         .prcm_reg_id = 1,
 495                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 496                         .idlest_reg_id = 1,
 497                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 498                 },
 499         },
 500         .slaves         = omap3xxx_uart1_slaves,
 501         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
 502         .class          = &uart_class,
 503         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 504 };
 505
 506 /* UART2 */
 507
 508 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
 509         { .irq = INT_24XX_UART2_IRQ, },
 510 };
 511
 512 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
 513         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 514         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 515 };
 516
 517 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
 518         &omap3_l4_core__uart2,
 519 };
 520
 521 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 522         .name           = "uart2",
 523         .mpu_irqs       = uart2_mpu_irqs,
 524         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
 525         .sdma_reqs      = uart2_sdma_reqs,
 526         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
 527         .main_clk       = "uart2_fck",
 528         .prcm           = {
 529                 .omap2 = {
 530                         .module_offs = CORE_MOD,
 531                         .prcm_reg_id = 1,
 532                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 533                         .idlest_reg_id = 1,
 534                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 535                 },
 536         },
 537         .slaves         = omap3xxx_uart2_slaves,
 538         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
 539         .class          = &uart_class,
 540         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 541 };
 542
 543 /* UART3 */
 544
 545 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
 546         { .irq = INT_24XX_UART3_IRQ, },
 547 };
 548
 549 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
 550         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
 551         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
 552 };
 553
 554 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
 555         &omap3_l4_per__uart3,
 556 };
 557
 558 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 559         .name           = "uart3",
 560         .mpu_irqs       = uart3_mpu_irqs,
 561         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
 562         .sdma_reqs      = uart3_sdma_reqs,
 563         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
 564         .main_clk       = "uart3_fck",
 565         .prcm           = {
 566                 .omap2 = {
 567                         .module_offs = OMAP3430_PER_MOD,
 568                         .prcm_reg_id = 1,
 569                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 570                         .idlest_reg_id = 1,
 571                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 572                 },
 573         },
 574         .slaves         = omap3xxx_uart3_slaves,
 575         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
 576         .class          = &uart_class,
 577         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 578 };
 579
 580 /* UART4 */
 581
 582 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 583         { .irq = INT_36XX_UART4_IRQ, },
 584 };
 585
 586 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 587         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
 588         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
 589 };
 590
 591 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
 592         &omap3_l4_per__uart4,
 593 };
 594
 595 static struct omap_hwmod omap3xxx_uart4_hwmod = {
 596         .name           = "uart4",
 597         .mpu_irqs       = uart4_mpu_irqs,
 598         .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
 599         .sdma_reqs      = uart4_sdma_reqs,
 600         .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
 601         .main_clk       = "uart4_fck",
 602         .prcm           = {
 603                 .omap2 = {
 604                         .module_offs = OMAP3430_PER_MOD,
 605                         .prcm_reg_id = 1,
 606                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 607                         .idlest_reg_id = 1,
 608                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 609                 },
 610         },
 611         .slaves         = omap3xxx_uart4_slaves,
 612         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
 613         .class          = &uart_class,
 614         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 615 };
 616
 617 static struct omap_hwmod_class i2c_class = {
 618         .name = "i2c",
 619         .sysc = &i2c_sysc,
 620 };
 621
 622 /* I2C1 */
 623
 624 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 625         .fifo_depth     = 8, /* bytes */
 626 };
 627
 628 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
 629         { .irq = INT_24XX_I2C1_IRQ, },
 630 };
 631
 632 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
 633         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
 634         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
 635 };
 636
 637 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
 638         &omap3_l4_core__i2c1,
 639 };
 640
 641 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 642         .name           = "i2c1",
 643         .mpu_irqs       = i2c1_mpu_irqs,
 644         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
 645         .sdma_reqs      = i2c1_sdma_reqs,
 646         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
 647         .main_clk       = "i2c1_fck",
 648         .prcm           = {
 649                 .omap2 = {
 650                         .module_offs = CORE_MOD,
 651                         .prcm_reg_id = 1,
 652                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 653                         .idlest_reg_id = 1,
 654                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 655                 },
 656         },
 657         .slaves         = omap3xxx_i2c1_slaves,
 658         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
 659         .class          = &i2c_class,
 660         .dev_attr       = &i2c1_dev_attr,
 661         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 662 };
 663
 664 /* I2C2 */
 665
 666 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 667         .fifo_depth     = 8, /* bytes */
 668 };
 669
 670 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
 671         { .irq = INT_24XX_I2C2_IRQ, },
 672 };
 673
 674 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
 675         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
 676         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
 677 };
 678
 679 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
 680         &omap3_l4_core__i2c2,
 681 };
 682
 683 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 684         .name           = "i2c2",
 685         .mpu_irqs       = i2c2_mpu_irqs,
 686         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
 687         .sdma_reqs      = i2c2_sdma_reqs,
 688         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
 689         .main_clk       = "i2c2_fck",
 690         .prcm           = {
 691                 .omap2 = {
 692                         .module_offs = CORE_MOD,
 693                         .prcm_reg_id = 1,
 694                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 695                         .idlest_reg_id = 1,
 696                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 697                 },
 698         },
 699         .slaves         = omap3xxx_i2c2_slaves,
 700         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
 701         .class          = &i2c_class,
 702         .dev_attr       = &i2c2_dev_attr,
 703         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 704 };
 705
 706 /* I2C3 */
 707
 708 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 709         .fifo_depth     = 64, /* bytes */
 710 };
 711
 712 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 713         { .irq = INT_34XX_I2C3_IRQ, },
 714 };
 715
 716 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 717         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
 718         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
 719 };
 720
 721 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
 722         &omap3_l4_core__i2c3,
 723 };
 724
 725 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 726         .name           = "i2c3",
 727         .mpu_irqs       = i2c3_mpu_irqs,
 728         .mpu_irqs_cnt   = ARRAY_SIZE(i2c3_mpu_irqs),
 729         .sdma_reqs      = i2c3_sdma_reqs,
 730         .sdma_reqs_cnt  = ARRAY_SIZE(i2c3_sdma_reqs),
 731         .main_clk       = "i2c3_fck",
 732         .prcm           = {
 733                 .omap2 = {
 734                         .module_offs = CORE_MOD,
 735                         .prcm_reg_id = 1,
 736                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 737                         .idlest_reg_id = 1,
 738                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 739                 },
 740         },
 741         .slaves         = omap3xxx_i2c3_slaves,
 742         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
 743         .class          = &i2c_class,
 744         .dev_attr       = &i2c3_dev_attr,
 745         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 746 };
 747
 748 /* l4_wkup -> gpio1 */
 749 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
 750         {
 751                 .pa_start       = 0x48310000,
 752                 .pa_end         = 0x483101ff,
 753                 .flags          = ADDR_TYPE_RT
 754         },
 755 };
 756
 757 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
 758         .master         = &omap3xxx_l4_wkup_hwmod,
 759         .slave          = &omap3xxx_gpio1_hwmod,
 760         .addr           = omap3xxx_gpio1_addrs,
 761         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio1_addrs),
 762         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 763 };
 764
 765 /* l4_per -> gpio2 */
 766 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
 767         {
 768                 .pa_start       = 0x49050000,
 769                 .pa_end         = 0x490501ff,
 770                 .flags          = ADDR_TYPE_RT
 771         },
 772 };
 773
 774 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
 775         .master         = &omap3xxx_l4_per_hwmod,
 776         .slave          = &omap3xxx_gpio2_hwmod,
 777         .addr           = omap3xxx_gpio2_addrs,
 778         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio2_addrs),
 779         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 780 };
 781
 782 /* l4_per -> gpio3 */
 783 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
 784         {
 785                 .pa_start       = 0x49052000,
 786                 .pa_end         = 0x490521ff,
 787                 .flags          = ADDR_TYPE_RT
 788         },
 789 };
 790
 791 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
 792         .master         = &omap3xxx_l4_per_hwmod,
 793         .slave          = &omap3xxx_gpio3_hwmod,
 794         .addr           = omap3xxx_gpio3_addrs,
 795         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio3_addrs),
 796         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 797 };
 798
 799 /* l4_per -> gpio4 */
 800 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
 801         {
 802                 .pa_start       = 0x49054000,
 803                 .pa_end         = 0x490541ff,
 804                 .flags          = ADDR_TYPE_RT
 805         },
 806 };
 807
 808 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
 809         .master         = &omap3xxx_l4_per_hwmod,
 810         .slave          = &omap3xxx_gpio4_hwmod,
 811         .addr           = omap3xxx_gpio4_addrs,
 812         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio4_addrs),
 813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 814 };
 815
 816 /* l4_per -> gpio5 */
 817 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
 818         {
 819                 .pa_start       = 0x49056000,
 820                 .pa_end         = 0x490561ff,
 821                 .flags          = ADDR_TYPE_RT
 822         },
 823 };
 824
 825 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
 826         .master         = &omap3xxx_l4_per_hwmod,
 827         .slave          = &omap3xxx_gpio5_hwmod,
 828         .addr           = omap3xxx_gpio5_addrs,
 829         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio5_addrs),
 830         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 831 };
 832
 833 /* l4_per -> gpio6 */
 834 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
 835         {
 836                 .pa_start       = 0x49058000,
 837                 .pa_end         = 0x490581ff,
 838                 .flags          = ADDR_TYPE_RT
 839         },
 840 };
 841
 842 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
 843         .master         = &omap3xxx_l4_per_hwmod,
 844         .slave          = &omap3xxx_gpio6_hwmod,
 845         .addr           = omap3xxx_gpio6_addrs,
 846         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio6_addrs),
 847         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 848 };
 849
 850 /*
 851  * 'gpio' class
 852  * general purpose io module
 853  */
 854
 855 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 856         .rev_offs       = 0x0000,
 857         .sysc_offs      = 0x0010,
 858         .syss_offs      = 0x0014,
 859         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 860                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 861         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 862         .sysc_fields    = &omap_hwmod_sysc_type1,
 863 };
 864
 865 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 866         .name = "gpio",
 867         .sysc = &omap3xxx_gpio_sysc,
 868         .rev = 1,
 869 };
 870
 871 /* gpio_dev_attr*/
 872 static struct omap_gpio_dev_attr gpio_dev_attr = {
 873         .bank_width = 32,
 874         .dbck_flag = true,
 875 };
 876
 877 /* gpio1 */
 878 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
 879         { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
 880 };
 881
 882 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 883         { .role = "dbclk", .clk = "gpio1_dbck", },
 884 };
 885
 886 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
 887         &omap3xxx_l4_wkup__gpio1,
 888 };
 889
 890 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 891         .name           = "gpio1",
 892         .mpu_irqs       = omap3xxx_gpio1_irqs,
 893         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio1_irqs),
 894         .main_clk       = "gpio1_ick",
 895         .opt_clks       = gpio1_opt_clks,
 896         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 897         .prcm           = {
 898                 .omap2 = {
 899                         .prcm_reg_id = 1,
 900                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 901                         .module_offs = WKUP_MOD,
 902                         .idlest_reg_id = 1,
 903                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 904                 },
 905         },
 906         .slaves         = omap3xxx_gpio1_slaves,
 907         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
 908         .class          = &omap3xxx_gpio_hwmod_class,
 909         .dev_attr       = &gpio_dev_attr,
 910         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 911 };
 912
 913 /* gpio2 */
 914 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
 915         { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
 916 };
 917
 918 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 919         { .role = "dbclk", .clk = "gpio2_dbck", },
 920 };
 921
 922 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
 923         &omap3xxx_l4_per__gpio2,
 924 };
 925
 926 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 927         .name           = "gpio2",
 928         .mpu_irqs       = omap3xxx_gpio2_irqs,
 929         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio2_irqs),
 930         .main_clk       = "gpio2_ick",
 931         .opt_clks       = gpio2_opt_clks,
 932         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 933         .prcm           = {
 934                 .omap2 = {
 935                         .prcm_reg_id = 1,
 936                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 937                         .module_offs = OMAP3430_PER_MOD,
 938                         .idlest_reg_id = 1,
 939                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 940                 },
 941         },
 942         .slaves         = omap3xxx_gpio2_slaves,
 943         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
 944         .class          = &omap3xxx_gpio_hwmod_class,
 945         .dev_attr       = &gpio_dev_attr,
 946         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 947 };
 948
 949 /* gpio3 */
 950 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
 951         { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
 952 };
 953
 954 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 955         { .role = "dbclk", .clk = "gpio3_dbck", },
 956 };
 957
 958 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
 959         &omap3xxx_l4_per__gpio3,
 960 };
 961
 962 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 963         .name           = "gpio3",
 964         .mpu_irqs       = omap3xxx_gpio3_irqs,
 965         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio3_irqs),
 966         .main_clk       = "gpio3_ick",
 967         .opt_clks       = gpio3_opt_clks,
 968         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 969         .prcm           = {
 970                 .omap2 = {
 971                         .prcm_reg_id = 1,
 972                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 973                         .module_offs = OMAP3430_PER_MOD,
 974                         .idlest_reg_id = 1,
 975                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 976                 },
 977         },
 978         .slaves         = omap3xxx_gpio3_slaves,
 979         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
 980         .class          = &omap3xxx_gpio_hwmod_class,
 981         .dev_attr       = &gpio_dev_attr,
 982         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 983 };
 984
 985 /* gpio4 */
 986 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
 987         { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
 988 };
 989
 990 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 991         { .role = "dbclk", .clk = "gpio4_dbck", },
 992 };
 993
 994 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
 995         &omap3xxx_l4_per__gpio4,
 996 };
 997
 998 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 999         .name           = "gpio4",
1000         .mpu_irqs       = omap3xxx_gpio4_irqs,
1001         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio4_irqs),
1002         .main_clk       = "gpio4_ick",
1003         .opt_clks       = gpio4_opt_clks,
1004         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1005         .prcm           = {
1006                 .omap2 = {
1007                         .prcm_reg_id = 1,
1008                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1009                         .module_offs = OMAP3430_PER_MOD,
1010                         .idlest_reg_id = 1,
1011                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1012                 },
1013         },
1014         .slaves         = omap3xxx_gpio4_slaves,
1015         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1016         .class          = &omap3xxx_gpio_hwmod_class,
1017         .dev_attr       = &gpio_dev_attr,
1018         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1019 };
1020
1021 /* gpio5 */
1022 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1023         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1024 };
1025
1026 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1027         { .role = "dbclk", .clk = "gpio5_dbck", },
1028 };
1029
1030 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
1031         &omap3xxx_l4_per__gpio5,
1032 };
1033
1034 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1035         .name           = "gpio5",
1036         .mpu_irqs       = omap3xxx_gpio5_irqs,
1037         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio5_irqs),
1038         .main_clk       = "gpio5_ick",
1039         .opt_clks       = gpio5_opt_clks,
1040         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1041         .prcm           = {
1042                 .omap2 = {
1043                         .prcm_reg_id = 1,
1044                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1045                         .module_offs = OMAP3430_PER_MOD,
1046                         .idlest_reg_id = 1,
1047                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1048                 },
1049         },
1050         .slaves         = omap3xxx_gpio5_slaves,
1051         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
1052         .class          = &omap3xxx_gpio_hwmod_class,
1053         .dev_attr       = &gpio_dev_attr,
1054         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1055 };
1056
1057 /* gpio6 */
1058 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1059         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
1060 };
1061
1062 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1063         { .role = "dbclk", .clk = "gpio6_dbck", },
1064 };
1065
1066 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
1067         &omap3xxx_l4_per__gpio6,
1068 };
1069
1070 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1071         .name           = "gpio6",
1072         .mpu_irqs       = omap3xxx_gpio6_irqs,
1073         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio6_irqs),
1074         .main_clk       = "gpio6_ick",
1075         .opt_clks       = gpio6_opt_clks,
1076         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1077         .prcm           = {
1078                 .omap2 = {
1079                         .prcm_reg_id = 1,
1080                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1081                         .module_offs = OMAP3430_PER_MOD,
1082                         .idlest_reg_id = 1,
1083                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1084                 },
1085         },
1086         .slaves         = omap3xxx_gpio6_slaves,
1087         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
1088         .class          = &omap3xxx_gpio_hwmod_class,
1089         .dev_attr       = &gpio_dev_attr,
1090         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1091 };
1092
1093 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
1094         &omap3xxx_l3_main_hwmod,
1095         &omap3xxx_l4_core_hwmod,
1096         &omap3xxx_l4_per_hwmod,
1097         &omap3xxx_l4_wkup_hwmod,
1098         &omap3xxx_mpu_hwmod,
1099         &omap3xxx_iva_hwmod,
1100         &omap3xxx_wd_timer2_hwmod,
1101         &omap3xxx_uart1_hwmod,
1102         &omap3xxx_uart2_hwmod,
1103         &omap3xxx_uart3_hwmod,
1104         &omap3xxx_uart4_hwmod,
1105         &omap3xxx_i2c1_hwmod,
1106         &omap3xxx_i2c2_hwmod,
1107         &omap3xxx_i2c3_hwmod,
1108
1109         /* gpio class */
1110         &omap3xxx_gpio1_hwmod,
1111         &omap3xxx_gpio2_hwmod,
1112         &omap3xxx_gpio3_hwmod,
1113         &omap3xxx_gpio4_hwmod,
1114         &omap3xxx_gpio5_hwmod,
1115         &omap3xxx_gpio6_hwmod,
1116         NULL,
1117 };
1118
1119 int __init omap3xxx_hwmod_init(void)
1120 {
1121         return omap_hwmod_init(omap3xxx_hwmods);
1122 }