2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2010 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
14 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
20 #include <plat/serial.h>
21 #include <plat/l4_3xxx.h>
23 #include <plat/omap34xx.h>
25 #include "omap_hwmod_common_data.h"
27 #include "prm-regbits-34xx.h"
28 #include "cm-regbits-34xx.h"
31 * OMAP3xxx hardware module integration data
33 * ALl of the data in this section should be autogeneratable from the
34 * TI hardware database or other technical documentation. Data that
35 * is driver-specific or driver-kernel integration-specific belongs
39 static struct omap_hwmod omap3xxx_mpu_hwmod;
40 static struct omap_hwmod omap3xxx_iva_hwmod;
41 static struct omap_hwmod omap3xxx_l3_main_hwmod;
42 static struct omap_hwmod omap3xxx_l4_core_hwmod;
43 static struct omap_hwmod omap3xxx_l4_per_hwmod;
44 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
45 static struct omap_hwmod omap3xxx_i2c1_hwmod;
46 static struct omap_hwmod omap3xxx_i2c2_hwmod;
47 static struct omap_hwmod omap3xxx_i2c3_hwmod;
49 /* L3 -> L4_CORE interface */
50 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
51 .master = &omap3xxx_l3_main_hwmod,
52 .slave = &omap3xxx_l4_core_hwmod,
53 .user = OCP_USER_MPU | OCP_USER_SDMA,
56 /* L3 -> L4_PER interface */
57 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
58 .master = &omap3xxx_l3_main_hwmod,
59 .slave = &omap3xxx_l4_per_hwmod,
60 .user = OCP_USER_MPU | OCP_USER_SDMA,
63 /* MPU -> L3 interface */
64 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
65 .master = &omap3xxx_mpu_hwmod,
66 .slave = &omap3xxx_l3_main_hwmod,
70 /* Slave interfaces on the L3 interconnect */
71 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
72 &omap3xxx_mpu__l3_main,
75 /* Master interfaces on the L3 interconnect */
76 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
77 &omap3xxx_l3_main__l4_core,
78 &omap3xxx_l3_main__l4_per,
82 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
84 .class = &l3_hwmod_class,
85 .masters = omap3xxx_l3_main_masters,
86 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
87 .slaves = omap3xxx_l3_main_slaves,
88 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
89 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
90 .flags = HWMOD_NO_IDLEST,
93 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
94 static struct omap_hwmod omap3xxx_uart1_hwmod;
95 static struct omap_hwmod omap3xxx_uart2_hwmod;
96 static struct omap_hwmod omap3xxx_uart3_hwmod;
97 static struct omap_hwmod omap3xxx_uart4_hwmod;
99 /* L4_CORE -> L4_WKUP interface */
100 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
101 .master = &omap3xxx_l4_core_hwmod,
102 .slave = &omap3xxx_l4_wkup_hwmod,
103 .user = OCP_USER_MPU | OCP_USER_SDMA,
106 /* L4 CORE -> UART1 interface */
107 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
109 .pa_start = OMAP3_UART1_BASE,
110 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
111 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
115 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
116 .master = &omap3xxx_l4_core_hwmod,
117 .slave = &omap3xxx_uart1_hwmod,
119 .addr = omap3xxx_uart1_addr_space,
120 .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
121 .user = OCP_USER_MPU | OCP_USER_SDMA,
124 /* L4 CORE -> UART2 interface */
125 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
127 .pa_start = OMAP3_UART2_BASE,
128 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
129 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
133 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
134 .master = &omap3xxx_l4_core_hwmod,
135 .slave = &omap3xxx_uart2_hwmod,
137 .addr = omap3xxx_uart2_addr_space,
138 .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
139 .user = OCP_USER_MPU | OCP_USER_SDMA,
142 /* L4 PER -> UART3 interface */
143 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
145 .pa_start = OMAP3_UART3_BASE,
146 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
147 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
151 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
152 .master = &omap3xxx_l4_per_hwmod,
153 .slave = &omap3xxx_uart3_hwmod,
155 .addr = omap3xxx_uart3_addr_space,
156 .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
157 .user = OCP_USER_MPU | OCP_USER_SDMA,
160 /* L4 PER -> UART4 interface */
161 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
163 .pa_start = OMAP3_UART4_BASE,
164 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
165 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
169 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
170 .master = &omap3xxx_l4_per_hwmod,
171 .slave = &omap3xxx_uart4_hwmod,
173 .addr = omap3xxx_uart4_addr_space,
174 .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
175 .user = OCP_USER_MPU | OCP_USER_SDMA,
178 /* I2C IP block address space length (in bytes) */
179 #define OMAP2_I2C_AS_LEN 128
181 /* L4 CORE -> I2C1 interface */
182 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
184 .pa_start = 0x48070000,
185 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
186 .flags = ADDR_TYPE_RT,
190 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
191 .master = &omap3xxx_l4_core_hwmod,
192 .slave = &omap3xxx_i2c1_hwmod,
194 .addr = omap3xxx_i2c1_addr_space,
195 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
198 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
200 .flags = OMAP_FIREWALL_L4,
203 .user = OCP_USER_MPU | OCP_USER_SDMA,
206 /* L4 CORE -> I2C2 interface */
207 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
209 .pa_start = 0x48072000,
210 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
211 .flags = ADDR_TYPE_RT,
215 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
216 .master = &omap3xxx_l4_core_hwmod,
217 .slave = &omap3xxx_i2c2_hwmod,
219 .addr = omap3xxx_i2c2_addr_space,
220 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
223 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
225 .flags = OMAP_FIREWALL_L4,
228 .user = OCP_USER_MPU | OCP_USER_SDMA,
231 /* L4 CORE -> I2C3 interface */
232 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
234 .pa_start = 0x48060000,
235 .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
236 .flags = ADDR_TYPE_RT,
240 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
241 .master = &omap3xxx_l4_core_hwmod,
242 .slave = &omap3xxx_i2c3_hwmod,
244 .addr = omap3xxx_i2c3_addr_space,
245 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
248 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
250 .flags = OMAP_FIREWALL_L4,
253 .user = OCP_USER_MPU | OCP_USER_SDMA,
256 /* Slave interfaces on the L4_CORE interconnect */
257 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
258 &omap3xxx_l3_main__l4_core,
261 /* Master interfaces on the L4_CORE interconnect */
262 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
263 &omap3xxx_l4_core__l4_wkup,
264 &omap3_l4_core__uart1,
265 &omap3_l4_core__uart2,
266 &omap3_l4_core__i2c1,
267 &omap3_l4_core__i2c2,
268 &omap3_l4_core__i2c3,
272 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
274 .class = &l4_hwmod_class,
275 .masters = omap3xxx_l4_core_masters,
276 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
277 .slaves = omap3xxx_l4_core_slaves,
278 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
279 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
280 .flags = HWMOD_NO_IDLEST,
283 /* Slave interfaces on the L4_PER interconnect */
284 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
285 &omap3xxx_l3_main__l4_per,
288 /* Master interfaces on the L4_PER interconnect */
289 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
290 &omap3_l4_per__uart3,
291 &omap3_l4_per__uart4,
295 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
297 .class = &l4_hwmod_class,
298 .masters = omap3xxx_l4_per_masters,
299 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
300 .slaves = omap3xxx_l4_per_slaves,
301 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
303 .flags = HWMOD_NO_IDLEST,
306 /* Slave interfaces on the L4_WKUP interconnect */
307 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
308 &omap3xxx_l4_core__l4_wkup,
311 /* Master interfaces on the L4_WKUP interconnect */
312 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
316 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
318 .class = &l4_hwmod_class,
319 .masters = omap3xxx_l4_wkup_masters,
320 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
321 .slaves = omap3xxx_l4_wkup_slaves,
322 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
323 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
324 .flags = HWMOD_NO_IDLEST,
327 /* Master interfaces on the MPU device */
328 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
329 &omap3xxx_mpu__l3_main,
333 static struct omap_hwmod omap3xxx_mpu_hwmod = {
335 .class = &mpu_hwmod_class,
336 .main_clk = "arm_fck",
337 .masters = omap3xxx_mpu_masters,
338 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
339 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
343 * IVA2_2 interface data
346 /* IVA2 <- L3 interface */
347 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
348 .master = &omap3xxx_l3_main_hwmod,
349 .slave = &omap3xxx_iva_hwmod,
351 .user = OCP_USER_MPU | OCP_USER_SDMA,
354 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
362 static struct omap_hwmod omap3xxx_iva_hwmod = {
364 .class = &iva_hwmod_class,
365 .masters = omap3xxx_iva_masters,
366 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
367 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
370 /* l4_wkup -> wd_timer2 */
371 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
373 .pa_start = 0x48314000,
374 .pa_end = 0x4831407f,
375 .flags = ADDR_TYPE_RT
379 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
380 .master = &omap3xxx_l4_wkup_hwmod,
381 .slave = &omap3xxx_wd_timer2_hwmod,
383 .addr = omap3xxx_wd_timer2_addrs,
384 .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
385 .user = OCP_USER_MPU | OCP_USER_SDMA,
390 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
394 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
398 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
399 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
400 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
401 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
402 .sysc_fields = &omap_hwmod_sysc_type1,
406 static struct omap_hwmod_class_sysconfig i2c_sysc = {
410 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
411 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
413 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
414 .sysc_fields = &omap_hwmod_sysc_type1,
417 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
419 .sysc = &omap3xxx_wd_timer_sysc,
423 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
424 &omap3xxx_l4_wkup__wd_timer2,
427 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
429 .class = &omap3xxx_wd_timer_hwmod_class,
430 .main_clk = "wdt2_fck",
434 .module_bit = OMAP3430_EN_WDT2_SHIFT,
435 .module_offs = WKUP_MOD,
437 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
440 .slaves = omap3xxx_wd_timer2_slaves,
441 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
442 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
447 static struct omap_hwmod_class_sysconfig uart_sysc = {
451 .sysc_flags = (SYSC_HAS_SIDLEMODE |
452 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
454 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
455 .sysc_fields = &omap_hwmod_sysc_type1,
458 static struct omap_hwmod_class uart_class = {
465 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
466 { .irq = INT_24XX_UART1_IRQ, },
469 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
470 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
471 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
474 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
475 &omap3_l4_core__uart1,
478 static struct omap_hwmod omap3xxx_uart1_hwmod = {
480 .mpu_irqs = uart1_mpu_irqs,
481 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
482 .sdma_reqs = uart1_sdma_reqs,
483 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
484 .main_clk = "uart1_fck",
487 .module_offs = CORE_MOD,
489 .module_bit = OMAP3430_EN_UART1_SHIFT,
491 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
494 .slaves = omap3xxx_uart1_slaves,
495 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
496 .class = &uart_class,
497 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
502 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
503 { .irq = INT_24XX_UART2_IRQ, },
506 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
507 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
508 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
511 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
512 &omap3_l4_core__uart2,
515 static struct omap_hwmod omap3xxx_uart2_hwmod = {
517 .mpu_irqs = uart2_mpu_irqs,
518 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
519 .sdma_reqs = uart2_sdma_reqs,
520 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
521 .main_clk = "uart2_fck",
524 .module_offs = CORE_MOD,
526 .module_bit = OMAP3430_EN_UART2_SHIFT,
528 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
531 .slaves = omap3xxx_uart2_slaves,
532 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
533 .class = &uart_class,
534 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
539 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
540 { .irq = INT_24XX_UART3_IRQ, },
543 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
544 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
545 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
548 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
549 &omap3_l4_per__uart3,
552 static struct omap_hwmod omap3xxx_uart3_hwmod = {
554 .mpu_irqs = uart3_mpu_irqs,
555 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
556 .sdma_reqs = uart3_sdma_reqs,
557 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
558 .main_clk = "uart3_fck",
561 .module_offs = OMAP3430_PER_MOD,
563 .module_bit = OMAP3430_EN_UART3_SHIFT,
565 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
568 .slaves = omap3xxx_uart3_slaves,
569 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
570 .class = &uart_class,
571 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
576 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
577 { .irq = INT_36XX_UART4_IRQ, },
580 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
581 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
582 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
585 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
586 &omap3_l4_per__uart4,
589 static struct omap_hwmod omap3xxx_uart4_hwmod = {
591 .mpu_irqs = uart4_mpu_irqs,
592 .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
593 .sdma_reqs = uart4_sdma_reqs,
594 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
595 .main_clk = "uart4_fck",
598 .module_offs = OMAP3430_PER_MOD,
600 .module_bit = OMAP3630_EN_UART4_SHIFT,
602 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
605 .slaves = omap3xxx_uart4_slaves,
606 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
607 .class = &uart_class,
608 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
611 static struct omap_hwmod_class i2c_class = {
618 static struct omap_i2c_dev_attr i2c1_dev_attr = {
619 .fifo_depth = 8, /* bytes */
622 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
623 { .irq = INT_24XX_I2C1_IRQ, },
626 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
627 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
628 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
631 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
632 &omap3_l4_core__i2c1,
635 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
637 .mpu_irqs = i2c1_mpu_irqs,
638 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
639 .sdma_reqs = i2c1_sdma_reqs,
640 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
641 .main_clk = "i2c1_fck",
644 .module_offs = CORE_MOD,
646 .module_bit = OMAP3430_EN_I2C1_SHIFT,
648 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
651 .slaves = omap3xxx_i2c1_slaves,
652 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
654 .dev_attr = &i2c1_dev_attr,
655 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
660 static struct omap_i2c_dev_attr i2c2_dev_attr = {
661 .fifo_depth = 8, /* bytes */
664 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
665 { .irq = INT_24XX_I2C2_IRQ, },
668 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
669 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
670 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
673 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
674 &omap3_l4_core__i2c2,
677 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
679 .mpu_irqs = i2c2_mpu_irqs,
680 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
681 .sdma_reqs = i2c2_sdma_reqs,
682 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
683 .main_clk = "i2c2_fck",
686 .module_offs = CORE_MOD,
688 .module_bit = OMAP3430_EN_I2C2_SHIFT,
690 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
693 .slaves = omap3xxx_i2c2_slaves,
694 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
696 .dev_attr = &i2c2_dev_attr,
697 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
702 static struct omap_i2c_dev_attr i2c3_dev_attr = {
703 .fifo_depth = 64, /* bytes */
706 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
707 { .irq = INT_34XX_I2C3_IRQ, },
710 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
711 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
712 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
715 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
716 &omap3_l4_core__i2c3,
719 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
721 .mpu_irqs = i2c3_mpu_irqs,
722 .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
723 .sdma_reqs = i2c3_sdma_reqs,
724 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
725 .main_clk = "i2c3_fck",
728 .module_offs = CORE_MOD,
730 .module_bit = OMAP3430_EN_I2C3_SHIFT,
732 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
735 .slaves = omap3xxx_i2c3_slaves,
736 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
738 .dev_attr = &i2c3_dev_attr,
739 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
742 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
743 &omap3xxx_l3_main_hwmod,
744 &omap3xxx_l4_core_hwmod,
745 &omap3xxx_l4_per_hwmod,
746 &omap3xxx_l4_wkup_hwmod,
749 &omap3xxx_wd_timer2_hwmod,
750 &omap3xxx_uart1_hwmod,
751 &omap3xxx_uart2_hwmod,
752 &omap3xxx_uart3_hwmod,
753 &omap3xxx_uart4_hwmod,
754 &omap3xxx_i2c1_hwmod,
755 &omap3xxx_i2c2_hwmod,
756 &omap3xxx_i2c3_hwmod,
760 int __init omap3xxx_hwmod_init(void)
762 return omap_hwmod_init(omap3xxx_hwmods);