arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/smartreflex.h>
  27 #include <plat/mcbsp.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod_common_data.h"
  32
  33 #include "prm-regbits-34xx.h"
  34 #include "cm-regbits-34xx.h"
  35 #include "wd_timer.h"
  36 #include <mach/am35xx.h>
  37
  38 /*
  39  * OMAP3xxx hardware module integration data
  40  *
  41  * ALl of the data in this section should be autogeneratable from the
  42  * TI hardware database or other technical documentation.  Data that
  43  * is driver-specific or driver-kernel integration-specific belongs
  44  * elsewhere.
  45  */
  46
  47 static struct omap_hwmod omap3xxx_mpu_hwmod;
  48 static struct omap_hwmod omap3xxx_iva_hwmod;
  49 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  51 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  52 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  53 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  58 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  61 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  67 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  68 static struct omap_hwmod omap34xx_sr1_hwmod;
  69 static struct omap_hwmod omap34xx_sr2_hwmod;
  70 static struct omap_hwmod omap34xx_mcspi1;
  71 static struct omap_hwmod omap34xx_mcspi2;
  72 static struct omap_hwmod omap34xx_mcspi3;
  73 static struct omap_hwmod omap34xx_mcspi4;
  74 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  75 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  76 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  77 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  78
  79 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  80
  81 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  83 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  87 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  88
  89 /* L3 -> L4_CORE interface */
  90 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  91         .master = &omap3xxx_l3_main_hwmod,
  92         .slave  = &omap3xxx_l4_core_hwmod,
  93         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  94 };
  95
  96 /* L3 -> L4_PER interface */
  97 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  98         .master = &omap3xxx_l3_main_hwmod,
  99         .slave  = &omap3xxx_l4_per_hwmod,
 100         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 101 };
 102
 103 /* L3 taret configuration and error log registers */
 104 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 105         { .irq = INT_34XX_L3_DBG_IRQ },
 106         { .irq = INT_34XX_L3_APP_IRQ },
 107 };
 108
 109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 110         {
 111                 .pa_start       = 0x68000000,
 112                 .pa_end         = 0x6800ffff,
 113                 .flags          = ADDR_TYPE_RT,
 114         },
 115 };
 116
 117 /* MPU -> L3 interface */
 118 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 119         .master   = &omap3xxx_mpu_hwmod,
 120         .slave    = &omap3xxx_l3_main_hwmod,
 121         .addr     = omap3xxx_l3_main_addrs,
 122         .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
 123         .user   = OCP_USER_MPU,
 124 };
 125
 126 /* Slave interfaces on the L3 interconnect */
 127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 128         &omap3xxx_mpu__l3_main,
 129 };
 130
 131 /* DSS -> l3 */
 132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 133         .master         = &omap3xxx_dss_core_hwmod,
 134         .slave          = &omap3xxx_l3_main_hwmod,
 135         .fw = {
 136                 .omap2 = {
 137                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 138                         .flags  = OMAP_FIREWALL_L3,
 139                 }
 140         },
 141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 142 };
 143
 144 /* Master interfaces on the L3 interconnect */
 145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 146         &omap3xxx_l3_main__l4_core,
 147         &omap3xxx_l3_main__l4_per,
 148 };
 149
 150 /* L3 */
 151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 152         .name           = "l3_main",
 153         .class          = &l3_hwmod_class,
 154         .mpu_irqs       = omap3xxx_l3_main_irqs,
 155         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_l3_main_irqs),
 156         .masters        = omap3xxx_l3_main_masters,
 157         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 158         .slaves         = omap3xxx_l3_main_slaves,
 159         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 160         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 161         .flags          = HWMOD_NO_IDLEST,
 162 };
 163
 164 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 165 static struct omap_hwmod omap3xxx_uart1_hwmod;
 166 static struct omap_hwmod omap3xxx_uart2_hwmod;
 167 static struct omap_hwmod omap3xxx_uart3_hwmod;
 168 static struct omap_hwmod omap3xxx_uart4_hwmod;
 169 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 170
 171 /* l3_core -> usbhsotg interface */
 172 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 173         .master         = &omap3xxx_usbhsotg_hwmod,
 174         .slave          = &omap3xxx_l3_main_hwmod,
 175         .clk            = "core_l3_ick",
 176         .user           = OCP_USER_MPU,
 177 };
 178
 179 /* l3_core -> am35xx_usbhsotg interface */
 180 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 181         .master         = &am35xx_usbhsotg_hwmod,
 182         .slave          = &omap3xxx_l3_main_hwmod,
 183         .clk            = "core_l3_ick",
 184         .user           = OCP_USER_MPU,
 185 };
 186 /* L4_CORE -> L4_WKUP interface */
 187 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 188         .master = &omap3xxx_l4_core_hwmod,
 189         .slave  = &omap3xxx_l4_wkup_hwmod,
 190         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 191 };
 192
 193 /* L4 CORE -> MMC1 interface */
 194 static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
 195         {
 196                 .pa_start       = 0x4809c000,
 197                 .pa_end         = 0x4809c1ff,
 198                 .flags          = ADDR_TYPE_RT,
 199         },
 200 };
 201
 202 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 203         .master         = &omap3xxx_l4_core_hwmod,
 204         .slave          = &omap3xxx_mmc1_hwmod,
 205         .clk            = "mmchs1_ick",
 206         .addr           = omap3xxx_mmc1_addr_space,
 207         .addr_cnt       = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
 208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 209         .flags          = OMAP_FIREWALL_L4
 210 };
 211
 212 /* L4 CORE -> MMC2 interface */
 213 static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
 214         {
 215                 .pa_start       = 0x480b4000,
 216                 .pa_end         = 0x480b41ff,
 217                 .flags          = ADDR_TYPE_RT,
 218         },
 219 };
 220
 221 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 222         .master         = &omap3xxx_l4_core_hwmod,
 223         .slave          = &omap3xxx_mmc2_hwmod,
 224         .clk            = "mmchs2_ick",
 225         .addr           = omap3xxx_mmc2_addr_space,
 226         .addr_cnt       = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
 227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 228         .flags          = OMAP_FIREWALL_L4
 229 };
 230
 231 /* L4 CORE -> MMC3 interface */
 232 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 233         {
 234                 .pa_start       = 0x480ad000,
 235                 .pa_end         = 0x480ad1ff,
 236                 .flags          = ADDR_TYPE_RT,
 237         },
 238 };
 239
 240 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 241         .master         = &omap3xxx_l4_core_hwmod,
 242         .slave          = &omap3xxx_mmc3_hwmod,
 243         .clk            = "mmchs3_ick",
 244         .addr           = omap3xxx_mmc3_addr_space,
 245         .addr_cnt       = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
 246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 247         .flags          = OMAP_FIREWALL_L4
 248 };
 249
 250 /* L4 CORE -> UART1 interface */
 251 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 252         {
 253                 .pa_start       = OMAP3_UART1_BASE,
 254                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 255                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 256         },
 257 };
 258
 259 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 260         .master         = &omap3xxx_l4_core_hwmod,
 261         .slave          = &omap3xxx_uart1_hwmod,
 262         .clk            = "uart1_ick",
 263         .addr           = omap3xxx_uart1_addr_space,
 264         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart1_addr_space),
 265         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 266 };
 267
 268 /* L4 CORE -> UART2 interface */
 269 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 270         {
 271                 .pa_start       = OMAP3_UART2_BASE,
 272                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 273                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 274         },
 275 };
 276
 277 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 278         .master         = &omap3xxx_l4_core_hwmod,
 279         .slave          = &omap3xxx_uart2_hwmod,
 280         .clk            = "uart2_ick",
 281         .addr           = omap3xxx_uart2_addr_space,
 282         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart2_addr_space),
 283         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 284 };
 285
 286 /* L4 PER -> UART3 interface */
 287 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 288         {
 289                 .pa_start       = OMAP3_UART3_BASE,
 290                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 291                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 292         },
 293 };
 294
 295 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 296         .master         = &omap3xxx_l4_per_hwmod,
 297         .slave          = &omap3xxx_uart3_hwmod,
 298         .clk            = "uart3_ick",
 299         .addr           = omap3xxx_uart3_addr_space,
 300         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart3_addr_space),
 301         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 302 };
 303
 304 /* L4 PER -> UART4 interface */
 305 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 306         {
 307                 .pa_start       = OMAP3_UART4_BASE,
 308                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 309                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 310         },
 311 };
 312
 313 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 314         .master         = &omap3xxx_l4_per_hwmod,
 315         .slave          = &omap3xxx_uart4_hwmod,
 316         .clk            = "uart4_ick",
 317         .addr           = omap3xxx_uart4_addr_space,
 318         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart4_addr_space),
 319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 320 };
 321
 322 /* I2C IP block address space length (in bytes) */
 323 #define OMAP2_I2C_AS_LEN                128
 324
 325 /* L4 CORE -> I2C1 interface */
 326 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
 327         {
 328                 .pa_start       = 0x48070000,
 329                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
 330                 .flags          = ADDR_TYPE_RT,
 331         },
 332 };
 333
 334 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 335         .master         = &omap3xxx_l4_core_hwmod,
 336         .slave          = &omap3xxx_i2c1_hwmod,
 337         .clk            = "i2c1_ick",
 338         .addr           = omap3xxx_i2c1_addr_space,
 339         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
 340         .fw = {
 341                 .omap2 = {
 342                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 343                         .l4_prot_group = 7,
 344                         .flags  = OMAP_FIREWALL_L4,
 345                 }
 346         },
 347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 348 };
 349
 350 /* L4 CORE -> I2C2 interface */
 351 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
 352         {
 353                 .pa_start       = 0x48072000,
 354                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 355                 .flags          = ADDR_TYPE_RT,
 356         },
 357 };
 358
 359 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 360         .master         = &omap3xxx_l4_core_hwmod,
 361         .slave          = &omap3xxx_i2c2_hwmod,
 362         .clk            = "i2c2_ick",
 363         .addr           = omap3xxx_i2c2_addr_space,
 364         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
 365         .fw = {
 366                 .omap2 = {
 367                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 368                         .l4_prot_group = 7,
 369                         .flags = OMAP_FIREWALL_L4,
 370                 }
 371         },
 372         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 373 };
 374
 375 /* L4 CORE -> I2C3 interface */
 376 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 377         {
 378                 .pa_start       = 0x48060000,
 379                 .pa_end         = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
 380                 .flags          = ADDR_TYPE_RT,
 381         },
 382 };
 383
 384 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 385         .master         = &omap3xxx_l4_core_hwmod,
 386         .slave          = &omap3xxx_i2c3_hwmod,
 387         .clk            = "i2c3_ick",
 388         .addr           = omap3xxx_i2c3_addr_space,
 389         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
 390         .fw = {
 391                 .omap2 = {
 392                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 393                         .l4_prot_group = 7,
 394                         .flags = OMAP_FIREWALL_L4,
 395                 }
 396         },
 397         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 398 };
 399
 400 /* L4 CORE -> SR1 interface */
 401 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 402         {
 403                 .pa_start       = OMAP34XX_SR1_BASE,
 404                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 405                 .flags          = ADDR_TYPE_RT,
 406         },
 407 };
 408
 409 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 410         .master         = &omap3xxx_l4_core_hwmod,
 411         .slave          = &omap34xx_sr1_hwmod,
 412         .clk            = "sr_l4_ick",
 413         .addr           = omap3_sr1_addr_space,
 414         .addr_cnt       = ARRAY_SIZE(omap3_sr1_addr_space),
 415         .user           = OCP_USER_MPU,
 416 };
 417
 418 /* L4 CORE -> SR1 interface */
 419 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 420         {
 421                 .pa_start       = OMAP34XX_SR2_BASE,
 422                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 423                 .flags          = ADDR_TYPE_RT,
 424         },
 425 };
 426
 427 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 428         .master         = &omap3xxx_l4_core_hwmod,
 429         .slave          = &omap34xx_sr2_hwmod,
 430         .clk            = "sr_l4_ick",
 431         .addr           = omap3_sr2_addr_space,
 432         .addr_cnt       = ARRAY_SIZE(omap3_sr2_addr_space),
 433         .user           = OCP_USER_MPU,
 434 };
 435
 436 /*
 437 * usbhsotg interface data
 438 */
 439
 440 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 441         {
 442                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 443                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 444                 .flags          = ADDR_TYPE_RT
 445         },
 446 };
 447
 448 /* l4_core -> usbhsotg  */
 449 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 450         .master         = &omap3xxx_l4_core_hwmod,
 451         .slave          = &omap3xxx_usbhsotg_hwmod,
 452         .clk            = "l4_ick",
 453         .addr           = omap3xxx_usbhsotg_addrs,
 454         .addr_cnt       = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
 455         .user           = OCP_USER_MPU,
 456 };
 457
 458 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 459         &omap3xxx_usbhsotg__l3,
 460 };
 461
 462 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 463         &omap3xxx_l4_core__usbhsotg,
 464 };
 465
 466 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 467         {
 468                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 469                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 470                 .flags          = ADDR_TYPE_RT
 471         },
 472 };
 473
 474 /* l4_core -> usbhsotg  */
 475 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 476         .master         = &omap3xxx_l4_core_hwmod,
 477         .slave          = &am35xx_usbhsotg_hwmod,
 478         .clk            = "l4_ick",
 479         .addr           = am35xx_usbhsotg_addrs,
 480         .addr_cnt       = ARRAY_SIZE(am35xx_usbhsotg_addrs),
 481         .user           = OCP_USER_MPU,
 482 };
 483
 484 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 485         &am35xx_usbhsotg__l3,
 486 };
 487
 488 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 489         &am35xx_l4_core__usbhsotg,
 490 };
 491 /* Slave interfaces on the L4_CORE interconnect */
 492 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 493         &omap3xxx_l3_main__l4_core,
 494 };
 495
 496 /* L4 CORE */
 497 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 498         .name           = "l4_core",
 499         .class          = &l4_hwmod_class,
 500         .slaves         = omap3xxx_l4_core_slaves,
 501         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 502         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 503         .flags          = HWMOD_NO_IDLEST,
 504 };
 505
 506 /* Slave interfaces on the L4_PER interconnect */
 507 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 508         &omap3xxx_l3_main__l4_per,
 509 };
 510
 511 /* L4 PER */
 512 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 513         .name           = "l4_per",
 514         .class          = &l4_hwmod_class,
 515         .slaves         = omap3xxx_l4_per_slaves,
 516         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 517         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 518         .flags          = HWMOD_NO_IDLEST,
 519 };
 520
 521 /* Slave interfaces on the L4_WKUP interconnect */
 522 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 523         &omap3xxx_l4_core__l4_wkup,
 524 };
 525
 526 /* L4 WKUP */
 527 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 528         .name           = "l4_wkup",
 529         .class          = &l4_hwmod_class,
 530         .slaves         = omap3xxx_l4_wkup_slaves,
 531         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 532         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 533         .flags          = HWMOD_NO_IDLEST,
 534 };
 535
 536 /* Master interfaces on the MPU device */
 537 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 538         &omap3xxx_mpu__l3_main,
 539 };
 540
 541 /* MPU */
 542 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 543         .name           = "mpu",
 544         .class          = &mpu_hwmod_class,
 545         .main_clk       = "arm_fck",
 546         .masters        = omap3xxx_mpu_masters,
 547         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 548         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 549 };
 550
 551 /*
 552  * IVA2_2 interface data
 553  */
 554
 555 /* IVA2 <- L3 interface */
 556 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 557         .master         = &omap3xxx_l3_main_hwmod,
 558         .slave          = &omap3xxx_iva_hwmod,
 559         .clk            = "iva2_ck",
 560         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 561 };
 562
 563 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 564         &omap3xxx_l3__iva,
 565 };
 566
 567 /*
 568  * IVA2 (IVA2)
 569  */
 570
 571 static struct omap_hwmod omap3xxx_iva_hwmod = {
 572         .name           = "iva",
 573         .class          = &iva_hwmod_class,
 574         .masters        = omap3xxx_iva_masters,
 575         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 576         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 577 };
 578
 579 /* timer class */
 580 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 581         .rev_offs       = 0x0000,
 582         .sysc_offs      = 0x0010,
 583         .syss_offs      = 0x0014,
 584         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 585                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 586                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 587         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 588         .sysc_fields    = &omap_hwmod_sysc_type1,
 589 };
 590
 591 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 592         .name = "timer",
 593         .sysc = &omap3xxx_timer_1ms_sysc,
 594         .rev = OMAP_TIMER_IP_VERSION_1,
 595 };
 596
 597 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 598         .rev_offs       = 0x0000,
 599         .sysc_offs      = 0x0010,
 600         .syss_offs      = 0x0014,
 601         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 602                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 603         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 604         .sysc_fields    = &omap_hwmod_sysc_type1,
 605 };
 606
 607 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 608         .name = "timer",
 609         .sysc = &omap3xxx_timer_sysc,
 610         .rev =  OMAP_TIMER_IP_VERSION_1,
 611 };
 612
 613 /* timer1 */
 614 static struct omap_hwmod omap3xxx_timer1_hwmod;
 615 static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
 616         { .irq = 37, },
 617 };
 618
 619 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 620         {
 621                 .pa_start       = 0x48318000,
 622                 .pa_end         = 0x48318000 + SZ_1K - 1,
 623                 .flags          = ADDR_TYPE_RT
 624         },
 625 };
 626
 627 /* l4_wkup -> timer1 */
 628 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 629         .master         = &omap3xxx_l4_wkup_hwmod,
 630         .slave          = &omap3xxx_timer1_hwmod,
 631         .clk            = "gpt1_ick",
 632         .addr           = omap3xxx_timer1_addrs,
 633         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer1_addrs),
 634         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 635 };
 636
 637 /* timer1 slave port */
 638 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 639         &omap3xxx_l4_wkup__timer1,
 640 };
 641
 642 /* timer1 hwmod */
 643 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 644         .name           = "timer1",
 645         .mpu_irqs       = omap3xxx_timer1_mpu_irqs,
 646         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
 647         .main_clk       = "gpt1_fck",
 648         .prcm           = {
 649                 .omap2 = {
 650                         .prcm_reg_id = 1,
 651                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 652                         .module_offs = WKUP_MOD,
 653                         .idlest_reg_id = 1,
 654                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 655                 },
 656         },
 657         .slaves         = omap3xxx_timer1_slaves,
 658         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 659         .class          = &omap3xxx_timer_1ms_hwmod_class,
 660         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 661 };
 662
 663 /* timer2 */
 664 static struct omap_hwmod omap3xxx_timer2_hwmod;
 665 static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
 666         { .irq = 38, },
 667 };
 668
 669 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 670         {
 671                 .pa_start       = 0x49032000,
 672                 .pa_end         = 0x49032000 + SZ_1K - 1,
 673                 .flags          = ADDR_TYPE_RT
 674         },
 675 };
 676
 677 /* l4_per -> timer2 */
 678 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 679         .master         = &omap3xxx_l4_per_hwmod,
 680         .slave          = &omap3xxx_timer2_hwmod,
 681         .clk            = "gpt2_ick",
 682         .addr           = omap3xxx_timer2_addrs,
 683         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer2_addrs),
 684         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 685 };
 686
 687 /* timer2 slave port */
 688 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 689         &omap3xxx_l4_per__timer2,
 690 };
 691
 692 /* timer2 hwmod */
 693 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 694         .name           = "timer2",
 695         .mpu_irqs       = omap3xxx_timer2_mpu_irqs,
 696         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
 697         .main_clk       = "gpt2_fck",
 698         .prcm           = {
 699                 .omap2 = {
 700                         .prcm_reg_id = 1,
 701                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 702                         .module_offs = OMAP3430_PER_MOD,
 703                         .idlest_reg_id = 1,
 704                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 705                 },
 706         },
 707         .slaves         = omap3xxx_timer2_slaves,
 708         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 709         .class          = &omap3xxx_timer_1ms_hwmod_class,
 710         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 711 };
 712
 713 /* timer3 */
 714 static struct omap_hwmod omap3xxx_timer3_hwmod;
 715 static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
 716         { .irq = 39, },
 717 };
 718
 719 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 720         {
 721                 .pa_start       = 0x49034000,
 722                 .pa_end         = 0x49034000 + SZ_1K - 1,
 723                 .flags          = ADDR_TYPE_RT
 724         },
 725 };
 726
 727 /* l4_per -> timer3 */
 728 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 729         .master         = &omap3xxx_l4_per_hwmod,
 730         .slave          = &omap3xxx_timer3_hwmod,
 731         .clk            = "gpt3_ick",
 732         .addr           = omap3xxx_timer3_addrs,
 733         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer3_addrs),
 734         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 735 };
 736
 737 /* timer3 slave port */
 738 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 739         &omap3xxx_l4_per__timer3,
 740 };
 741
 742 /* timer3 hwmod */
 743 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 744         .name           = "timer3",
 745         .mpu_irqs       = omap3xxx_timer3_mpu_irqs,
 746         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
 747         .main_clk       = "gpt3_fck",
 748         .prcm           = {
 749                 .omap2 = {
 750                         .prcm_reg_id = 1,
 751                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 752                         .module_offs = OMAP3430_PER_MOD,
 753                         .idlest_reg_id = 1,
 754                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 755                 },
 756         },
 757         .slaves         = omap3xxx_timer3_slaves,
 758         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 759         .class          = &omap3xxx_timer_hwmod_class,
 760         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 761 };
 762
 763 /* timer4 */
 764 static struct omap_hwmod omap3xxx_timer4_hwmod;
 765 static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
 766         { .irq = 40, },
 767 };
 768
 769 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 770         {
 771                 .pa_start       = 0x49036000,
 772                 .pa_end         = 0x49036000 + SZ_1K - 1,
 773                 .flags          = ADDR_TYPE_RT
 774         },
 775 };
 776
 777 /* l4_per -> timer4 */
 778 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 779         .master         = &omap3xxx_l4_per_hwmod,
 780         .slave          = &omap3xxx_timer4_hwmod,
 781         .clk            = "gpt4_ick",
 782         .addr           = omap3xxx_timer4_addrs,
 783         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer4_addrs),
 784         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 785 };
 786
 787 /* timer4 slave port */
 788 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 789         &omap3xxx_l4_per__timer4,
 790 };
 791
 792 /* timer4 hwmod */
 793 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 794         .name           = "timer4",
 795         .mpu_irqs       = omap3xxx_timer4_mpu_irqs,
 796         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
 797         .main_clk       = "gpt4_fck",
 798         .prcm           = {
 799                 .omap2 = {
 800                         .prcm_reg_id = 1,
 801                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 802                         .module_offs = OMAP3430_PER_MOD,
 803                         .idlest_reg_id = 1,
 804                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 805                 },
 806         },
 807         .slaves         = omap3xxx_timer4_slaves,
 808         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 809         .class          = &omap3xxx_timer_hwmod_class,
 810         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 811 };
 812
 813 /* timer5 */
 814 static struct omap_hwmod omap3xxx_timer5_hwmod;
 815 static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
 816         { .irq = 41, },
 817 };
 818
 819 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 820         {
 821                 .pa_start       = 0x49038000,
 822                 .pa_end         = 0x49038000 + SZ_1K - 1,
 823                 .flags          = ADDR_TYPE_RT
 824         },
 825 };
 826
 827 /* l4_per -> timer5 */
 828 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 829         .master         = &omap3xxx_l4_per_hwmod,
 830         .slave          = &omap3xxx_timer5_hwmod,
 831         .clk            = "gpt5_ick",
 832         .addr           = omap3xxx_timer5_addrs,
 833         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer5_addrs),
 834         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 835 };
 836
 837 /* timer5 slave port */
 838 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 839         &omap3xxx_l4_per__timer5,
 840 };
 841
 842 /* timer5 hwmod */
 843 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 844         .name           = "timer5",
 845         .mpu_irqs       = omap3xxx_timer5_mpu_irqs,
 846         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
 847         .main_clk       = "gpt5_fck",
 848         .prcm           = {
 849                 .omap2 = {
 850                         .prcm_reg_id = 1,
 851                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 852                         .module_offs = OMAP3430_PER_MOD,
 853                         .idlest_reg_id = 1,
 854                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 855                 },
 856         },
 857         .slaves         = omap3xxx_timer5_slaves,
 858         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 859         .class          = &omap3xxx_timer_hwmod_class,
 860         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 861 };
 862
 863 /* timer6 */
 864 static struct omap_hwmod omap3xxx_timer6_hwmod;
 865 static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
 866         { .irq = 42, },
 867 };
 868
 869 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 870         {
 871                 .pa_start       = 0x4903A000,
 872                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 873                 .flags          = ADDR_TYPE_RT
 874         },
 875 };
 876
 877 /* l4_per -> timer6 */
 878 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 879         .master         = &omap3xxx_l4_per_hwmod,
 880         .slave          = &omap3xxx_timer6_hwmod,
 881         .clk            = "gpt6_ick",
 882         .addr           = omap3xxx_timer6_addrs,
 883         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer6_addrs),
 884         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 885 };
 886
 887 /* timer6 slave port */
 888 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 889         &omap3xxx_l4_per__timer6,
 890 };
 891
 892 /* timer6 hwmod */
 893 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 894         .name           = "timer6",
 895         .mpu_irqs       = omap3xxx_timer6_mpu_irqs,
 896         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
 897         .main_clk       = "gpt6_fck",
 898         .prcm           = {
 899                 .omap2 = {
 900                         .prcm_reg_id = 1,
 901                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 902                         .module_offs = OMAP3430_PER_MOD,
 903                         .idlest_reg_id = 1,
 904                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 905                 },
 906         },
 907         .slaves         = omap3xxx_timer6_slaves,
 908         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 909         .class          = &omap3xxx_timer_hwmod_class,
 910         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 911 };
 912
 913 /* timer7 */
 914 static struct omap_hwmod omap3xxx_timer7_hwmod;
 915 static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
 916         { .irq = 43, },
 917 };
 918
 919 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 920         {
 921                 .pa_start       = 0x4903C000,
 922                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 923                 .flags          = ADDR_TYPE_RT
 924         },
 925 };
 926
 927 /* l4_per -> timer7 */
 928 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 929         .master         = &omap3xxx_l4_per_hwmod,
 930         .slave          = &omap3xxx_timer7_hwmod,
 931         .clk            = "gpt7_ick",
 932         .addr           = omap3xxx_timer7_addrs,
 933         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer7_addrs),
 934         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 935 };
 936
 937 /* timer7 slave port */
 938 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 939         &omap3xxx_l4_per__timer7,
 940 };
 941
 942 /* timer7 hwmod */
 943 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 944         .name           = "timer7",
 945         .mpu_irqs       = omap3xxx_timer7_mpu_irqs,
 946         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
 947         .main_clk       = "gpt7_fck",
 948         .prcm           = {
 949                 .omap2 = {
 950                         .prcm_reg_id = 1,
 951                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 952                         .module_offs = OMAP3430_PER_MOD,
 953                         .idlest_reg_id = 1,
 954                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 955                 },
 956         },
 957         .slaves         = omap3xxx_timer7_slaves,
 958         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 959         .class          = &omap3xxx_timer_hwmod_class,
 960         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 961 };
 962
 963 /* timer8 */
 964 static struct omap_hwmod omap3xxx_timer8_hwmod;
 965 static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
 966         { .irq = 44, },
 967 };
 968
 969 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 970         {
 971                 .pa_start       = 0x4903E000,
 972                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 973                 .flags          = ADDR_TYPE_RT
 974         },
 975 };
 976
 977 /* l4_per -> timer8 */
 978 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 979         .master         = &omap3xxx_l4_per_hwmod,
 980         .slave          = &omap3xxx_timer8_hwmod,
 981         .clk            = "gpt8_ick",
 982         .addr           = omap3xxx_timer8_addrs,
 983         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer8_addrs),
 984         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 985 };
 986
 987 /* timer8 slave port */
 988 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 989         &omap3xxx_l4_per__timer8,
 990 };
 991
 992 /* timer8 hwmod */
 993 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 994         .name           = "timer8",
 995         .mpu_irqs       = omap3xxx_timer8_mpu_irqs,
 996         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
 997         .main_clk       = "gpt8_fck",
 998         .prcm           = {
 999                 .omap2 = {
1000                         .prcm_reg_id = 1,
1001                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
1002                         .module_offs = OMAP3430_PER_MOD,
1003                         .idlest_reg_id = 1,
1004                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
1005                 },
1006         },
1007         .slaves         = omap3xxx_timer8_slaves,
1008         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
1009         .class          = &omap3xxx_timer_hwmod_class,
1010         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1011 };
1012
1013 /* timer9 */
1014 static struct omap_hwmod omap3xxx_timer9_hwmod;
1015 static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
1016         { .irq = 45, },
1017 };
1018
1019 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
1020         {
1021                 .pa_start       = 0x49040000,
1022                 .pa_end         = 0x49040000 + SZ_1K - 1,
1023                 .flags          = ADDR_TYPE_RT
1024         },
1025 };
1026
1027 /* l4_per -> timer9 */
1028 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1029         .master         = &omap3xxx_l4_per_hwmod,
1030         .slave          = &omap3xxx_timer9_hwmod,
1031         .clk            = "gpt9_ick",
1032         .addr           = omap3xxx_timer9_addrs,
1033         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer9_addrs),
1034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1035 };
1036
1037 /* timer9 slave port */
1038 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1039         &omap3xxx_l4_per__timer9,
1040 };
1041
1042 /* timer9 hwmod */
1043 static struct omap_hwmod omap3xxx_timer9_hwmod = {
1044         .name           = "timer9",
1045         .mpu_irqs       = omap3xxx_timer9_mpu_irqs,
1046         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
1047         .main_clk       = "gpt9_fck",
1048         .prcm           = {
1049                 .omap2 = {
1050                         .prcm_reg_id = 1,
1051                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
1052                         .module_offs = OMAP3430_PER_MOD,
1053                         .idlest_reg_id = 1,
1054                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1055                 },
1056         },
1057         .slaves         = omap3xxx_timer9_slaves,
1058         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
1059         .class          = &omap3xxx_timer_hwmod_class,
1060         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1061 };
1062
1063 /* timer10 */
1064 static struct omap_hwmod omap3xxx_timer10_hwmod;
1065 static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1066         { .irq = 46, },
1067 };
1068
1069 static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
1070         {
1071                 .pa_start       = 0x48086000,
1072                 .pa_end         = 0x48086000 + SZ_1K - 1,
1073                 .flags          = ADDR_TYPE_RT
1074         },
1075 };
1076
1077 /* l4_core -> timer10 */
1078 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1079         .master         = &omap3xxx_l4_core_hwmod,
1080         .slave          = &omap3xxx_timer10_hwmod,
1081         .clk            = "gpt10_ick",
1082         .addr           = omap3xxx_timer10_addrs,
1083         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer10_addrs),
1084         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1085 };
1086
1087 /* timer10 slave port */
1088 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1089         &omap3xxx_l4_core__timer10,
1090 };
1091
1092 /* timer10 hwmod */
1093 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1094         .name           = "timer10",
1095         .mpu_irqs       = omap3xxx_timer10_mpu_irqs,
1096         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
1097         .main_clk       = "gpt10_fck",
1098         .prcm           = {
1099                 .omap2 = {
1100                         .prcm_reg_id = 1,
1101                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1102                         .module_offs = CORE_MOD,
1103                         .idlest_reg_id = 1,
1104                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1105                 },
1106         },
1107         .slaves         = omap3xxx_timer10_slaves,
1108         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1109         .class          = &omap3xxx_timer_1ms_hwmod_class,
1110         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1111 };
1112
1113 /* timer11 */
1114 static struct omap_hwmod omap3xxx_timer11_hwmod;
1115 static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1116         { .irq = 47, },
1117 };
1118
1119 static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
1120         {
1121                 .pa_start       = 0x48088000,
1122                 .pa_end         = 0x48088000 + SZ_1K - 1,
1123                 .flags          = ADDR_TYPE_RT
1124         },
1125 };
1126
1127 /* l4_core -> timer11 */
1128 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1129         .master         = &omap3xxx_l4_core_hwmod,
1130         .slave          = &omap3xxx_timer11_hwmod,
1131         .clk            = "gpt11_ick",
1132         .addr           = omap3xxx_timer11_addrs,
1133         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer11_addrs),
1134         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1135 };
1136
1137 /* timer11 slave port */
1138 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1139         &omap3xxx_l4_core__timer11,
1140 };
1141
1142 /* timer11 hwmod */
1143 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1144         .name           = "timer11",
1145         .mpu_irqs       = omap3xxx_timer11_mpu_irqs,
1146         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
1147         .main_clk       = "gpt11_fck",
1148         .prcm           = {
1149                 .omap2 = {
1150                         .prcm_reg_id = 1,
1151                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1152                         .module_offs = CORE_MOD,
1153                         .idlest_reg_id = 1,
1154                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1155                 },
1156         },
1157         .slaves         = omap3xxx_timer11_slaves,
1158         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1159         .class          = &omap3xxx_timer_hwmod_class,
1160         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1161 };
1162
1163 /* timer12*/
1164 static struct omap_hwmod omap3xxx_timer12_hwmod;
1165 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1166         { .irq = 95, },
1167 };
1168
1169 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1170         {
1171                 .pa_start       = 0x48304000,
1172                 .pa_end         = 0x48304000 + SZ_1K - 1,
1173                 .flags          = ADDR_TYPE_RT
1174         },
1175 };
1176
1177 /* l4_core -> timer12 */
1178 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1179         .master         = &omap3xxx_l4_core_hwmod,
1180         .slave          = &omap3xxx_timer12_hwmod,
1181         .clk            = "gpt12_ick",
1182         .addr           = omap3xxx_timer12_addrs,
1183         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer12_addrs),
1184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1185 };
1186
1187 /* timer12 slave port */
1188 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1189         &omap3xxx_l4_core__timer12,
1190 };
1191
1192 /* timer12 hwmod */
1193 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1194         .name           = "timer12",
1195         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1196         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
1197         .main_clk       = "gpt12_fck",
1198         .prcm           = {
1199                 .omap2 = {
1200                         .prcm_reg_id = 1,
1201                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1202                         .module_offs = WKUP_MOD,
1203                         .idlest_reg_id = 1,
1204                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1205                 },
1206         },
1207         .slaves         = omap3xxx_timer12_slaves,
1208         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1209         .class          = &omap3xxx_timer_hwmod_class,
1210         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1211 };
1212
1213 /* l4_wkup -> wd_timer2 */
1214 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1215         {
1216                 .pa_start       = 0x48314000,
1217                 .pa_end         = 0x4831407f,
1218                 .flags          = ADDR_TYPE_RT
1219         },
1220 };
1221
1222 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1223         .master         = &omap3xxx_l4_wkup_hwmod,
1224         .slave          = &omap3xxx_wd_timer2_hwmod,
1225         .clk            = "wdt2_ick",
1226         .addr           = omap3xxx_wd_timer2_addrs,
1227         .addr_cnt       = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
1228         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1229 };
1230
1231 /*
1232  * 'wd_timer' class
1233  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1234  * overflow condition
1235  */
1236
1237 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1238         .rev_offs       = 0x0000,
1239         .sysc_offs      = 0x0010,
1240         .syss_offs      = 0x0014,
1241         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1242                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1243                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1244                            SYSS_HAS_RESET_STATUS),
1245         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1246         .sysc_fields    = &omap_hwmod_sysc_type1,
1247 };
1248
1249 /* I2C common */
1250 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1251         .rev_offs       = 0x00,
1252         .sysc_offs      = 0x20,
1253         .syss_offs      = 0x10,
1254         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1255                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1256                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1257         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1258         .sysc_fields    = &omap_hwmod_sysc_type1,
1259 };
1260
1261 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1262         .name           = "wd_timer",
1263         .sysc           = &omap3xxx_wd_timer_sysc,
1264         .pre_shutdown   = &omap2_wd_timer_disable
1265 };
1266
1267 /* wd_timer2 */
1268 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1269         &omap3xxx_l4_wkup__wd_timer2,
1270 };
1271
1272 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1273         .name           = "wd_timer2",
1274         .class          = &omap3xxx_wd_timer_hwmod_class,
1275         .main_clk       = "wdt2_fck",
1276         .prcm           = {
1277                 .omap2 = {
1278                         .prcm_reg_id = 1,
1279                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1280                         .module_offs = WKUP_MOD,
1281                         .idlest_reg_id = 1,
1282                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1283                 },
1284         },
1285         .slaves         = omap3xxx_wd_timer2_slaves,
1286         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1287         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1288         /*
1289          * XXX: Use software supervised mode, HW supervised smartidle seems to
1290          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1291          */
1292         .flags          = HWMOD_SWSUP_SIDLE,
1293 };
1294
1295 /* UART common */
1296
1297 static struct omap_hwmod_class_sysconfig uart_sysc = {
1298         .rev_offs       = 0x50,
1299         .sysc_offs      = 0x54,
1300         .syss_offs      = 0x58,
1301         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
1302                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1303                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1304         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1305         .sysc_fields    = &omap_hwmod_sysc_type1,
1306 };
1307
1308 static struct omap_hwmod_class uart_class = {
1309         .name = "uart",
1310         .sysc = &uart_sysc,
1311 };
1312
1313 /* UART1 */
1314
1315 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1316         { .irq = INT_24XX_UART1_IRQ, },
1317 };
1318
1319 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1320         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1321         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1322 };
1323
1324 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1325         &omap3_l4_core__uart1,
1326 };
1327
1328 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1329         .name           = "uart1",
1330         .mpu_irqs       = uart1_mpu_irqs,
1331         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
1332         .sdma_reqs      = uart1_sdma_reqs,
1333         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
1334         .main_clk       = "uart1_fck",
1335         .prcm           = {
1336                 .omap2 = {
1337                         .module_offs = CORE_MOD,
1338                         .prcm_reg_id = 1,
1339                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1340                         .idlest_reg_id = 1,
1341                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1342                 },
1343         },
1344         .slaves         = omap3xxx_uart1_slaves,
1345         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1346         .class          = &uart_class,
1347         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1348 };
1349
1350 /* UART2 */
1351
1352 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1353         { .irq = INT_24XX_UART2_IRQ, },
1354 };
1355
1356 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1357         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1358         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1359 };
1360
1361 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1362         &omap3_l4_core__uart2,
1363 };
1364
1365 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1366         .name           = "uart2",
1367         .mpu_irqs       = uart2_mpu_irqs,
1368         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
1369         .sdma_reqs      = uart2_sdma_reqs,
1370         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
1371         .main_clk       = "uart2_fck",
1372         .prcm           = {
1373                 .omap2 = {
1374                         .module_offs = CORE_MOD,
1375                         .prcm_reg_id = 1,
1376                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1377                         .idlest_reg_id = 1,
1378                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1379                 },
1380         },
1381         .slaves         = omap3xxx_uart2_slaves,
1382         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1383         .class          = &uart_class,
1384         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1385 };
1386
1387 /* UART3 */
1388
1389 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1390         { .irq = INT_24XX_UART3_IRQ, },
1391 };
1392
1393 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1394         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1395         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1396 };
1397
1398 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1399         &omap3_l4_per__uart3,
1400 };
1401
1402 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1403         .name           = "uart3",
1404         .mpu_irqs       = uart3_mpu_irqs,
1405         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
1406         .sdma_reqs      = uart3_sdma_reqs,
1407         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
1408         .main_clk       = "uart3_fck",
1409         .prcm           = {
1410                 .omap2 = {
1411                         .module_offs = OMAP3430_PER_MOD,
1412                         .prcm_reg_id = 1,
1413                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1414                         .idlest_reg_id = 1,
1415                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1416                 },
1417         },
1418         .slaves         = omap3xxx_uart3_slaves,
1419         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1420         .class          = &uart_class,
1421         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1422 };
1423
1424 /* UART4 */
1425
1426 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1427         { .irq = INT_36XX_UART4_IRQ, },
1428 };
1429
1430 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1431         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1432         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1433 };
1434
1435 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1436         &omap3_l4_per__uart4,
1437 };
1438
1439 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1440         .name           = "uart4",
1441         .mpu_irqs       = uart4_mpu_irqs,
1442         .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
1443         .sdma_reqs      = uart4_sdma_reqs,
1444         .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
1445         .main_clk       = "uart4_fck",
1446         .prcm           = {
1447                 .omap2 = {
1448                         .module_offs = OMAP3430_PER_MOD,
1449                         .prcm_reg_id = 1,
1450                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1451                         .idlest_reg_id = 1,
1452                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1453                 },
1454         },
1455         .slaves         = omap3xxx_uart4_slaves,
1456         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1457         .class          = &uart_class,
1458         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1459 };
1460
1461 static struct omap_hwmod_class i2c_class = {
1462         .name = "i2c",
1463         .sysc = &i2c_sysc,
1464 };
1465
1466 /*
1467  * 'dss' class
1468  * display sub-system
1469  */
1470
1471 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1472         .rev_offs       = 0x0000,
1473         .sysc_offs      = 0x0010,
1474         .syss_offs      = 0x0014,
1475         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1476         .sysc_fields    = &omap_hwmod_sysc_type1,
1477 };
1478
1479 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1480         .name = "dss",
1481         .sysc = &omap3xxx_dss_sysc,
1482 };
1483
1484 /* dss */
1485 static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = {
1486         { .irq = 25 },
1487 };
1488
1489 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1490         { .name = "dispc", .dma_req = 5 },
1491         { .name = "dsi1", .dma_req = 74 },
1492 };
1493
1494 /* dss */
1495 /* dss master ports */
1496 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1497         &omap3xxx_dss__l3,
1498 };
1499
1500 static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
1501         {
1502                 .pa_start       = 0x48050000,
1503                 .pa_end         = 0x480503FF,
1504                 .flags          = ADDR_TYPE_RT
1505         },
1506 };
1507
1508 /* l4_core -> dss */
1509 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1510         .master         = &omap3xxx_l4_core_hwmod,
1511         .slave          = &omap3430es1_dss_core_hwmod,
1512         .clk            = "dss_ick",
1513         .addr           = omap3xxx_dss_addrs,
1514         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
1515         .fw = {
1516                 .omap2 = {
1517                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1518                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1519                         .flags  = OMAP_FIREWALL_L4,
1520                 }
1521         },
1522         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1523 };
1524
1525 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1526         .master         = &omap3xxx_l4_core_hwmod,
1527         .slave          = &omap3xxx_dss_core_hwmod,
1528         .clk            = "dss_ick",
1529         .addr           = omap3xxx_dss_addrs,
1530         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
1531         .fw = {
1532                 .omap2 = {
1533                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1534                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1535                         .flags  = OMAP_FIREWALL_L4,
1536                 }
1537         },
1538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1539 };
1540
1541 /* dss slave ports */
1542 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1543         &omap3430es1_l4_core__dss,
1544 };
1545
1546 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1547         &omap3xxx_l4_core__dss,
1548 };
1549
1550 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1551         { .role = "tv_clk", .clk = "dss_tv_fck" },
1552         { .role = "dssclk", .clk = "dss_96m_fck" },
1553         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1554 };
1555
1556 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1557         .name           = "dss_core",
1558         .class          = &omap3xxx_dss_hwmod_class,
1559         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1560         .mpu_irqs       = omap3xxx_dss_irqs,
1561         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dss_irqs),
1562         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1563         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1564
1565         .prcm           = {
1566                 .omap2 = {
1567                         .prcm_reg_id = 1,
1568                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1569                         .module_offs = OMAP3430_DSS_MOD,
1570                         .idlest_reg_id = 1,
1571                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1572                 },
1573         },
1574         .opt_clks       = dss_opt_clks,
1575         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1576         .slaves         = omap3430es1_dss_slaves,
1577         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1578         .masters        = omap3xxx_dss_masters,
1579         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1580         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1581         .flags          = HWMOD_NO_IDLEST,
1582 };
1583
1584 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1585         .name           = "dss_core",
1586         .class          = &omap3xxx_dss_hwmod_class,
1587         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1588         .mpu_irqs       = omap3xxx_dss_irqs,
1589         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dss_irqs),
1590         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1591         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1592
1593         .prcm           = {
1594                 .omap2 = {
1595                         .prcm_reg_id = 1,
1596                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1597                         .module_offs = OMAP3430_DSS_MOD,
1598                         .idlest_reg_id = 1,
1599                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1600                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1601                 },
1602         },
1603         .opt_clks       = dss_opt_clks,
1604         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1605         .slaves         = omap3xxx_dss_slaves,
1606         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1607         .masters        = omap3xxx_dss_masters,
1608         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1609         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1610                                 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1611 };
1612
1613 /*
1614  * 'dispc' class
1615  * display controller
1616  */
1617
1618 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1619         .rev_offs       = 0x0000,
1620         .sysc_offs      = 0x0010,
1621         .syss_offs      = 0x0014,
1622         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1623                            SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1624                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1625         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1626                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1627         .sysc_fields    = &omap_hwmod_sysc_type1,
1628 };
1629
1630 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1631         .name = "dispc",
1632         .sysc = &omap3xxx_dispc_sysc,
1633 };
1634
1635 static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
1636         {
1637                 .pa_start       = 0x48050400,
1638                 .pa_end         = 0x480507FF,
1639                 .flags          = ADDR_TYPE_RT
1640         },
1641 };
1642
1643 /* l4_core -> dss_dispc */
1644 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1645         .master         = &omap3xxx_l4_core_hwmod,
1646         .slave          = &omap3xxx_dss_dispc_hwmod,
1647         .clk            = "dss_ick",
1648         .addr           = omap3xxx_dss_dispc_addrs,
1649         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
1650         .fw = {
1651                 .omap2 = {
1652                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1653                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1654                         .flags  = OMAP_FIREWALL_L4,
1655                 }
1656         },
1657         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1658 };
1659
1660 /* dss_dispc slave ports */
1661 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1662         &omap3xxx_l4_core__dss_dispc,
1663 };
1664
1665 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1666         .name           = "dss_dispc",
1667         .class          = &omap3xxx_dispc_hwmod_class,
1668         .main_clk       = "dss1_alwon_fck",
1669         .prcm           = {
1670                 .omap2 = {
1671                         .prcm_reg_id = 1,
1672                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1673                         .module_offs = OMAP3430_DSS_MOD,
1674                 },
1675         },
1676         .slaves         = omap3xxx_dss_dispc_slaves,
1677         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1678         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1679                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1680                                 CHIP_GE_OMAP3630ES1_1),
1681         .flags          = HWMOD_NO_IDLEST,
1682 };
1683
1684 /*
1685  * 'dsi' class
1686  * display serial interface controller
1687  */
1688
1689 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1690         .name = "dsi",
1691 };
1692
1693 /* dss_dsi1 */
1694 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1695         {
1696                 .pa_start       = 0x4804FC00,
1697                 .pa_end         = 0x4804FFFF,
1698                 .flags          = ADDR_TYPE_RT
1699         },
1700 };
1701
1702 /* l4_core -> dss_dsi1 */
1703 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1704         .master         = &omap3xxx_l4_core_hwmod,
1705         .slave          = &omap3xxx_dss_dsi1_hwmod,
1706         .addr           = omap3xxx_dss_dsi1_addrs,
1707         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
1708         .fw = {
1709                 .omap2 = {
1710                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1711                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1712                         .flags  = OMAP_FIREWALL_L4,
1713                 }
1714         },
1715         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1716 };
1717
1718 /* dss_dsi1 slave ports */
1719 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1720         &omap3xxx_l4_core__dss_dsi1,
1721 };
1722
1723 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1724         .name           = "dss_dsi1",
1725         .class          = &omap3xxx_dsi_hwmod_class,
1726         .main_clk       = "dss1_alwon_fck",
1727         .prcm           = {
1728                 .omap2 = {
1729                         .prcm_reg_id = 1,
1730                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1731                         .module_offs = OMAP3430_DSS_MOD,
1732                 },
1733         },
1734         .slaves         = omap3xxx_dss_dsi1_slaves,
1735         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1736         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1737                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1738                                 CHIP_GE_OMAP3630ES1_1),
1739         .flags          = HWMOD_NO_IDLEST,
1740 };
1741
1742 /*
1743  * 'rfbi' class
1744  * remote frame buffer interface
1745  */
1746
1747 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1748         .rev_offs       = 0x0000,
1749         .sysc_offs      = 0x0010,
1750         .syss_offs      = 0x0014,
1751         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1752                            SYSC_HAS_AUTOIDLE),
1753         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1754         .sysc_fields    = &omap_hwmod_sysc_type1,
1755 };
1756
1757 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1758         .name = "rfbi",
1759         .sysc = &omap3xxx_rfbi_sysc,
1760 };
1761
1762 static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1763         {
1764                 .pa_start       = 0x48050800,
1765                 .pa_end         = 0x48050BFF,
1766                 .flags          = ADDR_TYPE_RT
1767         },
1768 };
1769
1770 /* l4_core -> dss_rfbi */
1771 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1772         .master         = &omap3xxx_l4_core_hwmod,
1773         .slave          = &omap3xxx_dss_rfbi_hwmod,
1774         .clk            = "dss_ick",
1775         .addr           = omap3xxx_dss_rfbi_addrs,
1776         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
1777         .fw = {
1778                 .omap2 = {
1779                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1780                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1781                         .flags  = OMAP_FIREWALL_L4,
1782                 }
1783         },
1784         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1785 };
1786
1787 /* dss_rfbi slave ports */
1788 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1789         &omap3xxx_l4_core__dss_rfbi,
1790 };
1791
1792 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1793         .name           = "dss_rfbi",
1794         .class          = &omap3xxx_rfbi_hwmod_class,
1795         .main_clk       = "dss1_alwon_fck",
1796         .prcm           = {
1797                 .omap2 = {
1798                         .prcm_reg_id = 1,
1799                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1800                         .module_offs = OMAP3430_DSS_MOD,
1801                 },
1802         },
1803         .slaves         = omap3xxx_dss_rfbi_slaves,
1804         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1805         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1806                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1807                                 CHIP_GE_OMAP3630ES1_1),
1808         .flags          = HWMOD_NO_IDLEST,
1809 };
1810
1811 /*
1812  * 'venc' class
1813  * video encoder
1814  */
1815
1816 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1817         .name = "venc",
1818 };
1819
1820 /* dss_venc */
1821 static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1822         {
1823                 .pa_start       = 0x48050C00,
1824                 .pa_end         = 0x48050FFF,
1825                 .flags          = ADDR_TYPE_RT
1826         },
1827 };
1828
1829 /* l4_core -> dss_venc */
1830 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1831         .master         = &omap3xxx_l4_core_hwmod,
1832         .slave          = &omap3xxx_dss_venc_hwmod,
1833         .clk            = "dss_tv_fck",
1834         .addr           = omap3xxx_dss_venc_addrs,
1835         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
1836         .fw = {
1837                 .omap2 = {
1838                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1839                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1840                         .flags  = OMAP_FIREWALL_L4,
1841                 }
1842         },
1843         .flags          = OCPIF_SWSUP_IDLE,
1844         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1845 };
1846
1847 /* dss_venc slave ports */
1848 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1849         &omap3xxx_l4_core__dss_venc,
1850 };
1851
1852 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1853         .name           = "dss_venc",
1854         .class          = &omap3xxx_venc_hwmod_class,
1855         .main_clk       = "dss1_alwon_fck",
1856         .prcm           = {
1857                 .omap2 = {
1858                         .prcm_reg_id = 1,
1859                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1860                         .module_offs = OMAP3430_DSS_MOD,
1861                 },
1862         },
1863         .slaves         = omap3xxx_dss_venc_slaves,
1864         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1865         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1866                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1867                                 CHIP_GE_OMAP3630ES1_1),
1868         .flags          = HWMOD_NO_IDLEST,
1869 };
1870
1871 /* I2C1 */
1872
1873 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1874         .fifo_depth     = 8, /* bytes */
1875 };
1876
1877 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1878         { .irq = INT_24XX_I2C1_IRQ, },
1879 };
1880
1881 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1882         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1883         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1884 };
1885
1886 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1887         &omap3_l4_core__i2c1,
1888 };
1889
1890 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1891         .name           = "i2c1",
1892         .mpu_irqs       = i2c1_mpu_irqs,
1893         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
1894         .sdma_reqs      = i2c1_sdma_reqs,
1895         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
1896         .main_clk       = "i2c1_fck",
1897         .prcm           = {
1898                 .omap2 = {
1899                         .module_offs = CORE_MOD,
1900                         .prcm_reg_id = 1,
1901                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1902                         .idlest_reg_id = 1,
1903                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1904                 },
1905         },
1906         .slaves         = omap3xxx_i2c1_slaves,
1907         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1908         .class          = &i2c_class,
1909         .dev_attr       = &i2c1_dev_attr,
1910         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1911 };
1912
1913 /* I2C2 */
1914
1915 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1916         .fifo_depth     = 8, /* bytes */
1917 };
1918
1919 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1920         { .irq = INT_24XX_I2C2_IRQ, },
1921 };
1922
1923 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1924         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1925         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1926 };
1927
1928 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1929         &omap3_l4_core__i2c2,
1930 };
1931
1932 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1933         .name           = "i2c2",
1934         .mpu_irqs       = i2c2_mpu_irqs,
1935         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
1936         .sdma_reqs      = i2c2_sdma_reqs,
1937         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
1938         .main_clk       = "i2c2_fck",
1939         .prcm           = {
1940                 .omap2 = {
1941                         .module_offs = CORE_MOD,
1942                         .prcm_reg_id = 1,
1943                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1944                         .idlest_reg_id = 1,
1945                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1946                 },
1947         },
1948         .slaves         = omap3xxx_i2c2_slaves,
1949         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1950         .class          = &i2c_class,
1951         .dev_attr       = &i2c2_dev_attr,
1952         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1953 };
1954
1955 /* I2C3 */
1956
1957 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1958         .fifo_depth     = 64, /* bytes */
1959 };
1960
1961 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1962         { .irq = INT_34XX_I2C3_IRQ, },
1963 };
1964
1965 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1966         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1967         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1968 };
1969
1970 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1971         &omap3_l4_core__i2c3,
1972 };
1973
1974 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1975         .name           = "i2c3",
1976         .mpu_irqs       = i2c3_mpu_irqs,
1977         .mpu_irqs_cnt   = ARRAY_SIZE(i2c3_mpu_irqs),
1978         .sdma_reqs      = i2c3_sdma_reqs,
1979         .sdma_reqs_cnt  = ARRAY_SIZE(i2c3_sdma_reqs),
1980         .main_clk       = "i2c3_fck",
1981         .prcm           = {
1982                 .omap2 = {
1983                         .module_offs = CORE_MOD,
1984                         .prcm_reg_id = 1,
1985                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1986                         .idlest_reg_id = 1,
1987                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1988                 },
1989         },
1990         .slaves         = omap3xxx_i2c3_slaves,
1991         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1992         .class          = &i2c_class,
1993         .dev_attr       = &i2c3_dev_attr,
1994         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1995 };
1996
1997 /* l4_wkup -> gpio1 */
1998 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1999         {
2000                 .pa_start       = 0x48310000,
2001                 .pa_end         = 0x483101ff,
2002                 .flags          = ADDR_TYPE_RT
2003         },
2004 };
2005
2006 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2007         .master         = &omap3xxx_l4_wkup_hwmod,
2008         .slave          = &omap3xxx_gpio1_hwmod,
2009         .addr           = omap3xxx_gpio1_addrs,
2010         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio1_addrs),
2011         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2012 };
2013
2014 /* l4_per -> gpio2 */
2015 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2016         {
2017                 .pa_start       = 0x49050000,
2018                 .pa_end         = 0x490501ff,
2019                 .flags          = ADDR_TYPE_RT
2020         },
2021 };
2022
2023 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2024         .master         = &omap3xxx_l4_per_hwmod,
2025         .slave          = &omap3xxx_gpio2_hwmod,
2026         .addr           = omap3xxx_gpio2_addrs,
2027         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio2_addrs),
2028         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2029 };
2030
2031 /* l4_per -> gpio3 */
2032 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2033         {
2034                 .pa_start       = 0x49052000,
2035                 .pa_end         = 0x490521ff,
2036                 .flags          = ADDR_TYPE_RT
2037         },
2038 };
2039
2040 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2041         .master         = &omap3xxx_l4_per_hwmod,
2042         .slave          = &omap3xxx_gpio3_hwmod,
2043         .addr           = omap3xxx_gpio3_addrs,
2044         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio3_addrs),
2045         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2046 };
2047
2048 /* l4_per -> gpio4 */
2049 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2050         {
2051                 .pa_start       = 0x49054000,
2052                 .pa_end         = 0x490541ff,
2053                 .flags          = ADDR_TYPE_RT
2054         },
2055 };
2056
2057 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2058         .master         = &omap3xxx_l4_per_hwmod,
2059         .slave          = &omap3xxx_gpio4_hwmod,
2060         .addr           = omap3xxx_gpio4_addrs,
2061         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio4_addrs),
2062         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2063 };
2064
2065 /* l4_per -> gpio5 */
2066 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2067         {
2068                 .pa_start       = 0x49056000,
2069                 .pa_end         = 0x490561ff,
2070                 .flags          = ADDR_TYPE_RT
2071         },
2072 };
2073
2074 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2075         .master         = &omap3xxx_l4_per_hwmod,
2076         .slave          = &omap3xxx_gpio5_hwmod,
2077         .addr           = omap3xxx_gpio5_addrs,
2078         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio5_addrs),
2079         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2080 };
2081
2082 /* l4_per -> gpio6 */
2083 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2084         {
2085                 .pa_start       = 0x49058000,
2086                 .pa_end         = 0x490581ff,
2087                 .flags          = ADDR_TYPE_RT
2088         },
2089 };
2090
2091 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2092         .master         = &omap3xxx_l4_per_hwmod,
2093         .slave          = &omap3xxx_gpio6_hwmod,
2094         .addr           = omap3xxx_gpio6_addrs,
2095         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio6_addrs),
2096         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2097 };
2098
2099 /*
2100  * 'gpio' class
2101  * general purpose io module
2102  */
2103
2104 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
2105         .rev_offs       = 0x0000,
2106         .sysc_offs      = 0x0010,
2107         .syss_offs      = 0x0014,
2108         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2109                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
2110                            SYSS_HAS_RESET_STATUS),
2111         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2112         .sysc_fields    = &omap_hwmod_sysc_type1,
2113 };
2114
2115 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
2116         .name = "gpio",
2117         .sysc = &omap3xxx_gpio_sysc,
2118         .rev = 1,
2119 };
2120
2121 /* gpio_dev_attr*/
2122 static struct omap_gpio_dev_attr gpio_dev_attr = {
2123         .bank_width = 32,
2124         .dbck_flag = true,
2125 };
2126
2127 /* gpio1 */
2128 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
2129         { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
2130 };
2131
2132 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
2133         { .role = "dbclk", .clk = "gpio1_dbck", },
2134 };
2135
2136 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
2137         &omap3xxx_l4_wkup__gpio1,
2138 };
2139
2140 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2141         .name           = "gpio1",
2142         .mpu_irqs       = omap3xxx_gpio1_irqs,
2143         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio1_irqs),
2144         .main_clk       = "gpio1_ick",
2145         .opt_clks       = gpio1_opt_clks,
2146         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
2147         .prcm           = {
2148                 .omap2 = {
2149                         .prcm_reg_id = 1,
2150                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
2151                         .module_offs = WKUP_MOD,
2152                         .idlest_reg_id = 1,
2153                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
2154                 },
2155         },
2156         .slaves         = omap3xxx_gpio1_slaves,
2157         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
2158         .class          = &omap3xxx_gpio_hwmod_class,
2159         .dev_attr       = &gpio_dev_attr,
2160         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2161 };
2162
2163 /* gpio2 */
2164 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
2165         { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
2166 };
2167
2168 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
2169         { .role = "dbclk", .clk = "gpio2_dbck", },
2170 };
2171
2172 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
2173         &omap3xxx_l4_per__gpio2,
2174 };
2175
2176 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2177         .name           = "gpio2",
2178         .mpu_irqs       = omap3xxx_gpio2_irqs,
2179         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio2_irqs),
2180         .main_clk       = "gpio2_ick",
2181         .opt_clks       = gpio2_opt_clks,
2182         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
2183         .prcm           = {
2184                 .omap2 = {
2185                         .prcm_reg_id = 1,
2186                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
2187                         .module_offs = OMAP3430_PER_MOD,
2188                         .idlest_reg_id = 1,
2189                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2190                 },
2191         },
2192         .slaves         = omap3xxx_gpio2_slaves,
2193         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2194         .class          = &omap3xxx_gpio_hwmod_class,
2195         .dev_attr       = &gpio_dev_attr,
2196         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2197 };
2198
2199 /* gpio3 */
2200 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
2201         { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
2202 };
2203
2204 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2205         { .role = "dbclk", .clk = "gpio3_dbck", },
2206 };
2207
2208 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2209         &omap3xxx_l4_per__gpio3,
2210 };
2211
2212 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2213         .name           = "gpio3",
2214         .mpu_irqs       = omap3xxx_gpio3_irqs,
2215         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio3_irqs),
2216         .main_clk       = "gpio3_ick",
2217         .opt_clks       = gpio3_opt_clks,
2218         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
2219         .prcm           = {
2220                 .omap2 = {
2221                         .prcm_reg_id = 1,
2222                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2223                         .module_offs = OMAP3430_PER_MOD,
2224                         .idlest_reg_id = 1,
2225                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2226                 },
2227         },
2228         .slaves         = omap3xxx_gpio3_slaves,
2229         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2230         .class          = &omap3xxx_gpio_hwmod_class,
2231         .dev_attr       = &gpio_dev_attr,
2232         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2233 };
2234
2235 /* gpio4 */
2236 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
2237         { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
2238 };
2239
2240 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2241         { .role = "dbclk", .clk = "gpio4_dbck", },
2242 };
2243
2244 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2245         &omap3xxx_l4_per__gpio4,
2246 };
2247
2248 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2249         .name           = "gpio4",
2250         .mpu_irqs       = omap3xxx_gpio4_irqs,
2251         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio4_irqs),
2252         .main_clk       = "gpio4_ick",
2253         .opt_clks       = gpio4_opt_clks,
2254         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2255         .prcm           = {
2256                 .omap2 = {
2257                         .prcm_reg_id = 1,
2258                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2259                         .module_offs = OMAP3430_PER_MOD,
2260                         .idlest_reg_id = 1,
2261                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2262                 },
2263         },
2264         .slaves         = omap3xxx_gpio4_slaves,
2265         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2266         .class          = &omap3xxx_gpio_hwmod_class,
2267         .dev_attr       = &gpio_dev_attr,
2268         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2269 };
2270
2271 /* gpio5 */
2272 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2273         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2274 };
2275
2276 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2277         { .role = "dbclk", .clk = "gpio5_dbck", },
2278 };
2279
2280 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2281         &omap3xxx_l4_per__gpio5,
2282 };
2283
2284 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2285         .name           = "gpio5",
2286         .mpu_irqs       = omap3xxx_gpio5_irqs,
2287         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio5_irqs),
2288         .main_clk       = "gpio5_ick",
2289         .opt_clks       = gpio5_opt_clks,
2290         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2291         .prcm           = {
2292                 .omap2 = {
2293                         .prcm_reg_id = 1,
2294                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2295                         .module_offs = OMAP3430_PER_MOD,
2296                         .idlest_reg_id = 1,
2297                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2298                 },
2299         },
2300         .slaves         = omap3xxx_gpio5_slaves,
2301         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2302         .class          = &omap3xxx_gpio_hwmod_class,
2303         .dev_attr       = &gpio_dev_attr,
2304         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2305 };
2306
2307 /* gpio6 */
2308 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2309         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2310 };
2311
2312 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2313         { .role = "dbclk", .clk = "gpio6_dbck", },
2314 };
2315
2316 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2317         &omap3xxx_l4_per__gpio6,
2318 };
2319
2320 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2321         .name           = "gpio6",
2322         .mpu_irqs       = omap3xxx_gpio6_irqs,
2323         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio6_irqs),
2324         .main_clk       = "gpio6_ick",
2325         .opt_clks       = gpio6_opt_clks,
2326         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2327         .prcm           = {
2328                 .omap2 = {
2329                         .prcm_reg_id = 1,
2330                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2331                         .module_offs = OMAP3430_PER_MOD,
2332                         .idlest_reg_id = 1,
2333                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2334                 },
2335         },
2336         .slaves         = omap3xxx_gpio6_slaves,
2337         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2338         .class          = &omap3xxx_gpio_hwmod_class,
2339         .dev_attr       = &gpio_dev_attr,
2340         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2341 };
2342
2343 /* dma_system -> L3 */
2344 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2345         .master         = &omap3xxx_dma_system_hwmod,
2346         .slave          = &omap3xxx_l3_main_hwmod,
2347         .clk            = "core_l3_ick",
2348         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2349 };
2350
2351 /* dma attributes */
2352 static struct omap_dma_dev_attr dma_dev_attr = {
2353         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2354                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2355         .lch_count = 32,
2356 };
2357
2358 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2359         .rev_offs       = 0x0000,
2360         .sysc_offs      = 0x002c,
2361         .syss_offs      = 0x0028,
2362         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2363                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2364                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2365                            SYSS_HAS_RESET_STATUS),
2366         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2367                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2368         .sysc_fields    = &omap_hwmod_sysc_type1,
2369 };
2370
2371 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2372         .name = "dma",
2373         .sysc = &omap3xxx_dma_sysc,
2374 };
2375
2376 /* dma_system */
2377 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
2378         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
2379         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
2380         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
2381         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
2382 };
2383
2384 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2385         {
2386                 .pa_start       = 0x48056000,
2387                 .pa_end         = 0x4a0560ff,
2388                 .flags          = ADDR_TYPE_RT
2389         },
2390 };
2391
2392 /* dma_system master ports */
2393 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2394         &omap3xxx_dma_system__l3,
2395 };
2396
2397 /* l4_cfg -> dma_system */
2398 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2399         .master         = &omap3xxx_l4_core_hwmod,
2400         .slave          = &omap3xxx_dma_system_hwmod,
2401         .clk            = "core_l4_ick",
2402         .addr           = omap3xxx_dma_system_addrs,
2403         .addr_cnt       = ARRAY_SIZE(omap3xxx_dma_system_addrs),
2404         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2405 };
2406
2407 /* dma_system slave ports */
2408 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2409         &omap3xxx_l4_core__dma_system,
2410 };
2411
2412 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2413         .name           = "dma",
2414         .class          = &omap3xxx_dma_hwmod_class,
2415         .mpu_irqs       = omap3xxx_dma_system_irqs,
2416         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dma_system_irqs),
2417         .main_clk       = "core_l3_ick",
2418         .prcm = {
2419                 .omap2 = {
2420                         .module_offs            = CORE_MOD,
2421                         .prcm_reg_id            = 1,
2422                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2423                         .idlest_reg_id          = 1,
2424                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2425                 },
2426         },
2427         .slaves         = omap3xxx_dma_system_slaves,
2428         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2429         .masters        = omap3xxx_dma_system_masters,
2430         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2431         .dev_attr       = &dma_dev_attr,
2432         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2433         .flags          = HWMOD_NO_IDLEST,
2434 };
2435
2436 /*
2437  * 'mcbsp' class
2438  * multi channel buffered serial port controller
2439  */
2440
2441 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2442         .sysc_offs      = 0x008c,
2443         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2444                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2445         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2446         .sysc_fields    = &omap_hwmod_sysc_type1,
2447         .clockact       = 0x2,
2448 };
2449
2450 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2451         .name = "mcbsp",
2452         .sysc = &omap3xxx_mcbsp_sysc,
2453         .rev  = MCBSP_CONFIG_TYPE3,
2454 };
2455
2456 /* mcbsp1 */
2457 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2458         { .name = "irq", .irq = 16 },
2459         { .name = "tx", .irq = 59 },
2460         { .name = "rx", .irq = 60 },
2461 };
2462
2463 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2464         { .name = "rx", .dma_req = 32 },
2465         { .name = "tx", .dma_req = 31 },
2466 };
2467
2468 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2469         {
2470                 .name           = "mpu",
2471                 .pa_start       = 0x48074000,
2472                 .pa_end         = 0x480740ff,
2473                 .flags          = ADDR_TYPE_RT
2474         },
2475 };
2476
2477 /* l4_core -> mcbsp1 */
2478 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2479         .master         = &omap3xxx_l4_core_hwmod,
2480         .slave          = &omap3xxx_mcbsp1_hwmod,
2481         .clk            = "mcbsp1_ick",
2482         .addr           = omap3xxx_mcbsp1_addrs,
2483         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
2484         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2485 };
2486
2487 /* mcbsp1 slave ports */
2488 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2489         &omap3xxx_l4_core__mcbsp1,
2490 };
2491
2492 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2493         .name           = "mcbsp1",
2494         .class          = &omap3xxx_mcbsp_hwmod_class,
2495         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2496         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
2497         .sdma_reqs      = omap3xxx_mcbsp1_sdma_chs,
2498         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2499         .main_clk       = "mcbsp1_fck",
2500         .prcm           = {
2501                 .omap2 = {
2502                         .prcm_reg_id = 1,
2503                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2504                         .module_offs = CORE_MOD,
2505                         .idlest_reg_id = 1,
2506                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2507                 },
2508         },
2509         .slaves         = omap3xxx_mcbsp1_slaves,
2510         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2511         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2512 };
2513
2514 /* mcbsp2 */
2515 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2516         { .name = "irq", .irq = 17 },
2517         { .name = "tx", .irq = 62 },
2518         { .name = "rx", .irq = 63 },
2519 };
2520
2521 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2522         { .name = "rx", .dma_req = 34 },
2523         { .name = "tx", .dma_req = 33 },
2524 };
2525
2526 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2527         {
2528                 .name           = "mpu",
2529                 .pa_start       = 0x49022000,
2530                 .pa_end         = 0x490220ff,
2531                 .flags          = ADDR_TYPE_RT
2532         },
2533 };
2534
2535 /* l4_per -> mcbsp2 */
2536 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2537         .master         = &omap3xxx_l4_per_hwmod,
2538         .slave          = &omap3xxx_mcbsp2_hwmod,
2539         .clk            = "mcbsp2_ick",
2540         .addr           = omap3xxx_mcbsp2_addrs,
2541         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
2542         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2543 };
2544
2545 /* mcbsp2 slave ports */
2546 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2547         &omap3xxx_l4_per__mcbsp2,
2548 };
2549
2550 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2551         .sidetone       = "mcbsp2_sidetone",
2552 };
2553
2554 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2555         .name           = "mcbsp2",
2556         .class          = &omap3xxx_mcbsp_hwmod_class,
2557         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2558         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
2559         .sdma_reqs      = omap3xxx_mcbsp2_sdma_chs,
2560         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2561         .main_clk       = "mcbsp2_fck",
2562         .prcm           = {
2563                 .omap2 = {
2564                         .prcm_reg_id = 1,
2565                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2566                         .module_offs = OMAP3430_PER_MOD,
2567                         .idlest_reg_id = 1,
2568                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2569                 },
2570         },
2571         .slaves         = omap3xxx_mcbsp2_slaves,
2572         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2573         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2574         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2575 };
2576
2577 /* mcbsp3 */
2578 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2579         { .name = "irq", .irq = 22 },
2580         { .name = "tx", .irq = 89 },
2581         { .name = "rx", .irq = 90 },
2582 };
2583
2584 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2585         { .name = "rx", .dma_req = 18 },
2586         { .name = "tx", .dma_req = 17 },
2587 };
2588
2589 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2590         {
2591                 .name           = "mpu",
2592                 .pa_start       = 0x49024000,
2593                 .pa_end         = 0x490240ff,
2594                 .flags          = ADDR_TYPE_RT
2595         },
2596 };
2597
2598 /* l4_per -> mcbsp3 */
2599 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2600         .master         = &omap3xxx_l4_per_hwmod,
2601         .slave          = &omap3xxx_mcbsp3_hwmod,
2602         .clk            = "mcbsp3_ick",
2603         .addr           = omap3xxx_mcbsp3_addrs,
2604         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
2605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2606 };
2607
2608 /* mcbsp3 slave ports */
2609 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2610         &omap3xxx_l4_per__mcbsp3,
2611 };
2612
2613 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2614         .sidetone       = "mcbsp3_sidetone",
2615 };
2616
2617 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2618         .name           = "mcbsp3",
2619         .class          = &omap3xxx_mcbsp_hwmod_class,
2620         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2621         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
2622         .sdma_reqs      = omap3xxx_mcbsp3_sdma_chs,
2623         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2624         .main_clk       = "mcbsp3_fck",
2625         .prcm           = {
2626                 .omap2 = {
2627                         .prcm_reg_id = 1,
2628                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2629                         .module_offs = OMAP3430_PER_MOD,
2630                         .idlest_reg_id = 1,
2631                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2632                 },
2633         },
2634         .slaves         = omap3xxx_mcbsp3_slaves,
2635         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2636         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2637         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2638 };
2639
2640 /* mcbsp4 */
2641 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2642         { .name = "irq", .irq = 23 },
2643         { .name = "tx", .irq = 54 },
2644         { .name = "rx", .irq = 55 },
2645 };
2646
2647 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2648         { .name = "rx", .dma_req = 20 },
2649         { .name = "tx", .dma_req = 19 },
2650 };
2651
2652 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2653         {
2654                 .name           = "mpu",
2655                 .pa_start       = 0x49026000,
2656                 .pa_end         = 0x490260ff,
2657                 .flags          = ADDR_TYPE_RT
2658         },
2659 };
2660
2661 /* l4_per -> mcbsp4 */
2662 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2663         .master         = &omap3xxx_l4_per_hwmod,
2664         .slave          = &omap3xxx_mcbsp4_hwmod,
2665         .clk            = "mcbsp4_ick",
2666         .addr           = omap3xxx_mcbsp4_addrs,
2667         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
2668         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2669 };
2670
2671 /* mcbsp4 slave ports */
2672 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2673         &omap3xxx_l4_per__mcbsp4,
2674 };
2675
2676 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2677         .name           = "mcbsp4",
2678         .class          = &omap3xxx_mcbsp_hwmod_class,
2679         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2680         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
2681         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2682         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2683         .main_clk       = "mcbsp4_fck",
2684         .prcm           = {
2685                 .omap2 = {
2686                         .prcm_reg_id = 1,
2687                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2688                         .module_offs = OMAP3430_PER_MOD,
2689                         .idlest_reg_id = 1,
2690                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2691                 },
2692         },
2693         .slaves         = omap3xxx_mcbsp4_slaves,
2694         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2695         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2696 };
2697
2698 /* mcbsp5 */
2699 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2700         { .name = "irq", .irq = 27 },
2701         { .name = "tx", .irq = 81 },
2702         { .name = "rx", .irq = 82 },
2703 };
2704
2705 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2706         { .name = "rx", .dma_req = 22 },
2707         { .name = "tx", .dma_req = 21 },
2708 };
2709
2710 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2711         {
2712                 .name           = "mpu",
2713                 .pa_start       = 0x48096000,
2714                 .pa_end         = 0x480960ff,
2715                 .flags          = ADDR_TYPE_RT
2716         },
2717 };
2718
2719 /* l4_core -> mcbsp5 */
2720 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2721         .master         = &omap3xxx_l4_core_hwmod,
2722         .slave          = &omap3xxx_mcbsp5_hwmod,
2723         .clk            = "mcbsp5_ick",
2724         .addr           = omap3xxx_mcbsp5_addrs,
2725         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
2726         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2727 };
2728
2729 /* mcbsp5 slave ports */
2730 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2731         &omap3xxx_l4_core__mcbsp5,
2732 };
2733
2734 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2735         .name           = "mcbsp5",
2736         .class          = &omap3xxx_mcbsp_hwmod_class,
2737         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2738         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
2739         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2740         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2741         .main_clk       = "mcbsp5_fck",
2742         .prcm           = {
2743                 .omap2 = {
2744                         .prcm_reg_id = 1,
2745                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2746                         .module_offs = CORE_MOD,
2747                         .idlest_reg_id = 1,
2748                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2749                 },
2750         },
2751         .slaves         = omap3xxx_mcbsp5_slaves,
2752         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2753         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2754 };
2755 /* 'mcbsp sidetone' class */
2756
2757 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2758         .sysc_offs      = 0x0010,
2759         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2760         .sysc_fields    = &omap_hwmod_sysc_type1,
2761 };
2762
2763 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2764         .name = "mcbsp_sidetone",
2765         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2766 };
2767
2768 /* mcbsp2_sidetone */
2769 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2770         { .name = "irq", .irq = 4 },
2771 };
2772
2773 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2774         {
2775                 .name           = "sidetone",
2776                 .pa_start       = 0x49028000,
2777                 .pa_end         = 0x490280ff,
2778                 .flags          = ADDR_TYPE_RT
2779         },
2780 };
2781
2782 /* l4_per -> mcbsp2_sidetone */
2783 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2784         .master         = &omap3xxx_l4_per_hwmod,
2785         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2786         .clk            = "mcbsp2_ick",
2787         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2788         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
2789         .user           = OCP_USER_MPU,
2790 };
2791
2792 /* mcbsp2_sidetone slave ports */
2793 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2794         &omap3xxx_l4_per__mcbsp2_sidetone,
2795 };
2796
2797 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2798         .name           = "mcbsp2_sidetone",
2799         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2800         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2801         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
2802         .main_clk       = "mcbsp2_fck",
2803         .prcm           = {
2804                 .omap2 = {
2805                         .prcm_reg_id = 1,
2806                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2807                         .module_offs = OMAP3430_PER_MOD,
2808                         .idlest_reg_id = 1,
2809                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2810                 },
2811         },
2812         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2813         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2814         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2815 };
2816
2817 /* mcbsp3_sidetone */
2818 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2819         { .name = "irq", .irq = 5 },
2820 };
2821
2822 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2823         {
2824                 .name           = "sidetone",
2825                 .pa_start       = 0x4902A000,
2826                 .pa_end         = 0x4902A0ff,
2827                 .flags          = ADDR_TYPE_RT
2828         },
2829 };
2830
2831 /* l4_per -> mcbsp3_sidetone */
2832 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2833         .master         = &omap3xxx_l4_per_hwmod,
2834         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2835         .clk            = "mcbsp3_ick",
2836         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2837         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
2838         .user           = OCP_USER_MPU,
2839 };
2840
2841 /* mcbsp3_sidetone slave ports */
2842 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2843         &omap3xxx_l4_per__mcbsp3_sidetone,
2844 };
2845
2846 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2847         .name           = "mcbsp3_sidetone",
2848         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2849         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2850         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
2851         .main_clk       = "mcbsp3_fck",
2852         .prcm           = {
2853                 .omap2 = {
2854                         .prcm_reg_id = 1,
2855                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2856                         .module_offs = OMAP3430_PER_MOD,
2857                         .idlest_reg_id = 1,
2858                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2859                 },
2860         },
2861         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2862         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2863         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2864 };
2865
2866
2867 /* SR common */
2868 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2869         .clkact_shift   = 20,
2870 };
2871
2872 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2873         .sysc_offs      = 0x24,
2874         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2875         .clockact       = CLOCKACT_TEST_ICLK,
2876         .sysc_fields    = &omap34xx_sr_sysc_fields,
2877 };
2878
2879 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2880         .name = "smartreflex",
2881         .sysc = &omap34xx_sr_sysc,
2882         .rev  = 1,
2883 };
2884
2885 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2886         .sidle_shift    = 24,
2887         .enwkup_shift   = 26
2888 };
2889
2890 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2891         .sysc_offs      = 0x38,
2892         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2893         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2894                         SYSC_NO_CACHE),
2895         .sysc_fields    = &omap36xx_sr_sysc_fields,
2896 };
2897
2898 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2899         .name = "smartreflex",
2900         .sysc = &omap36xx_sr_sysc,
2901         .rev  = 2,
2902 };
2903
2904 /* SR1 */
2905 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2906         &omap3_l4_core__sr1,
2907 };
2908
2909 static struct omap_hwmod omap34xx_sr1_hwmod = {
2910         .name           = "sr1_hwmod",
2911         .class          = &omap34xx_smartreflex_hwmod_class,
2912         .main_clk       = "sr1_fck",
2913         .vdd_name       = "mpu",
2914         .prcm           = {
2915                 .omap2 = {
2916                         .prcm_reg_id = 1,
2917                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2918                         .module_offs = WKUP_MOD,
2919                         .idlest_reg_id = 1,
2920                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2921                 },
2922         },
2923         .slaves         = omap3_sr1_slaves,
2924         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2925         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2926                                         CHIP_IS_OMAP3430ES3_0 |
2927                                         CHIP_IS_OMAP3430ES3_1),
2928         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2929 };
2930
2931 static struct omap_hwmod omap36xx_sr1_hwmod = {
2932         .name           = "sr1_hwmod",
2933         .class          = &omap36xx_smartreflex_hwmod_class,
2934         .main_clk       = "sr1_fck",
2935         .vdd_name       = "mpu",
2936         .prcm           = {
2937                 .omap2 = {
2938                         .prcm_reg_id = 1,
2939                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2940                         .module_offs = WKUP_MOD,
2941                         .idlest_reg_id = 1,
2942                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2943                 },
2944         },
2945         .slaves         = omap3_sr1_slaves,
2946         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2947         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2948 };
2949
2950 /* SR2 */
2951 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2952         &omap3_l4_core__sr2,
2953 };
2954
2955 static struct omap_hwmod omap34xx_sr2_hwmod = {
2956         .name           = "sr2_hwmod",
2957         .class          = &omap34xx_smartreflex_hwmod_class,
2958         .main_clk       = "sr2_fck",
2959         .vdd_name       = "core",
2960         .prcm           = {
2961                 .omap2 = {
2962                         .prcm_reg_id = 1,
2963                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2964                         .module_offs = WKUP_MOD,
2965                         .idlest_reg_id = 1,
2966                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2967                 },
2968         },
2969         .slaves         = omap3_sr2_slaves,
2970         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2971         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2972                                         CHIP_IS_OMAP3430ES3_0 |
2973                                         CHIP_IS_OMAP3430ES3_1),
2974         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2975 };
2976
2977 static struct omap_hwmod omap36xx_sr2_hwmod = {
2978         .name           = "sr2_hwmod",
2979         .class          = &omap36xx_smartreflex_hwmod_class,
2980         .main_clk       = "sr2_fck",
2981         .vdd_name       = "core",
2982         .prcm           = {
2983                 .omap2 = {
2984                         .prcm_reg_id = 1,
2985                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2986                         .module_offs = WKUP_MOD,
2987                         .idlest_reg_id = 1,
2988                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2989                 },
2990         },
2991         .slaves         = omap3_sr2_slaves,
2992         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2993         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2994 };
2995
2996 /*
2997  * 'mailbox' class
2998  * mailbox module allowing communication between the on-chip processors
2999  * using a queued mailbox-interrupt mechanism.
3000  */
3001
3002 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
3003         .rev_offs       = 0x000,
3004         .sysc_offs      = 0x010,
3005         .syss_offs      = 0x014,
3006         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3007                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
3008         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3009         .sysc_fields    = &omap_hwmod_sysc_type1,
3010 };
3011
3012 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
3013         .name = "mailbox",
3014         .sysc = &omap3xxx_mailbox_sysc,
3015 };
3016
3017 static struct omap_hwmod omap3xxx_mailbox_hwmod;
3018 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
3019         { .irq = 26 },
3020 };
3021
3022 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3023         {
3024                 .pa_start       = 0x48094000,
3025                 .pa_end         = 0x480941ff,
3026                 .flags          = ADDR_TYPE_RT,
3027         },
3028 };
3029
3030 /* l4_core -> mailbox */
3031 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3032         .master         = &omap3xxx_l4_core_hwmod,
3033         .slave          = &omap3xxx_mailbox_hwmod,
3034         .addr           = omap3xxx_mailbox_addrs,
3035         .addr_cnt       = ARRAY_SIZE(omap3xxx_mailbox_addrs),
3036         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3037 };
3038
3039 /* mailbox slave ports */
3040 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
3041         &omap3xxx_l4_core__mailbox,
3042 };
3043
3044 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
3045         .name           = "mailbox",
3046         .class          = &omap3xxx_mailbox_hwmod_class,
3047         .mpu_irqs       = omap3xxx_mailbox_irqs,
3048         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mailbox_irqs),
3049         .main_clk       = "mailboxes_ick",
3050         .prcm           = {
3051                 .omap2 = {
3052                         .prcm_reg_id = 1,
3053                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
3054                         .module_offs = CORE_MOD,
3055                         .idlest_reg_id = 1,
3056                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
3057                 },
3058         },
3059         .slaves         = omap3xxx_mailbox_slaves,
3060         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
3061         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3062 };
3063
3064 /* l4 core -> mcspi1 interface */
3065 static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
3066         {
3067                 .pa_start       = 0x48098000,
3068                 .pa_end         = 0x480980ff,
3069                 .flags          = ADDR_TYPE_RT,
3070         },
3071 };
3072
3073 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3074         .master         = &omap3xxx_l4_core_hwmod,
3075         .slave          = &omap34xx_mcspi1,
3076         .clk            = "mcspi1_ick",
3077         .addr           = omap34xx_mcspi1_addr_space,
3078         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
3079         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3080 };
3081
3082 /* l4 core -> mcspi2 interface */
3083 static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
3084         {
3085                 .pa_start       = 0x4809a000,
3086                 .pa_end         = 0x4809a0ff,
3087                 .flags          = ADDR_TYPE_RT,
3088         },
3089 };
3090
3091 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3092         .master         = &omap3xxx_l4_core_hwmod,
3093         .slave          = &omap34xx_mcspi2,
3094         .clk            = "mcspi2_ick",
3095         .addr           = omap34xx_mcspi2_addr_space,
3096         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
3097         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3098 };
3099
3100 /* l4 core -> mcspi3 interface */
3101 static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
3102         {
3103                 .pa_start       = 0x480b8000,
3104                 .pa_end         = 0x480b80ff,
3105                 .flags          = ADDR_TYPE_RT,
3106         },
3107 };
3108
3109 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3110         .master         = &omap3xxx_l4_core_hwmod,
3111         .slave          = &omap34xx_mcspi3,
3112         .clk            = "mcspi3_ick",
3113         .addr           = omap34xx_mcspi3_addr_space,
3114         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
3115         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3116 };
3117
3118 /* l4 core -> mcspi4 interface */
3119 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3120         {
3121                 .pa_start       = 0x480ba000,
3122                 .pa_end         = 0x480ba0ff,
3123                 .flags          = ADDR_TYPE_RT,
3124         },
3125 };
3126
3127 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3128         .master         = &omap3xxx_l4_core_hwmod,
3129         .slave          = &omap34xx_mcspi4,
3130         .clk            = "mcspi4_ick",
3131         .addr           = omap34xx_mcspi4_addr_space,
3132         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
3133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3134 };
3135
3136 /*
3137  * 'mcspi' class
3138  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3139  * bus
3140  */
3141
3142 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
3143         .rev_offs       = 0x0000,
3144         .sysc_offs      = 0x0010,
3145         .syss_offs      = 0x0014,
3146         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3147                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3148                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3149         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3150         .sysc_fields    = &omap_hwmod_sysc_type1,
3151 };
3152
3153 static struct omap_hwmod_class omap34xx_mcspi_class = {
3154         .name = "mcspi",
3155         .sysc = &omap34xx_mcspi_sysc,
3156         .rev = OMAP3_MCSPI_REV,
3157 };
3158
3159 /* mcspi1 */
3160 static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
3161         { .name = "irq", .irq = 65 },
3162 };
3163
3164 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
3165         { .name = "tx0", .dma_req = 35 },
3166         { .name = "rx0", .dma_req = 36 },
3167         { .name = "tx1", .dma_req = 37 },
3168         { .name = "rx1", .dma_req = 38 },
3169         { .name = "tx2", .dma_req = 39 },
3170         { .name = "rx2", .dma_req = 40 },
3171         { .name = "tx3", .dma_req = 41 },
3172         { .name = "rx3", .dma_req = 42 },
3173 };
3174
3175 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
3176         &omap34xx_l4_core__mcspi1,
3177 };
3178
3179 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
3180         .num_chipselect = 4,
3181 };
3182
3183 static struct omap_hwmod omap34xx_mcspi1 = {
3184         .name           = "mcspi1",
3185         .mpu_irqs       = omap34xx_mcspi1_mpu_irqs,
3186         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
3187         .sdma_reqs      = omap34xx_mcspi1_sdma_reqs,
3188         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
3189         .main_clk       = "mcspi1_fck",
3190         .prcm           = {
3191                 .omap2 = {
3192                         .module_offs = CORE_MOD,
3193                         .prcm_reg_id = 1,
3194                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
3195                         .idlest_reg_id = 1,
3196                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
3197                 },
3198         },
3199         .slaves         = omap34xx_mcspi1_slaves,
3200         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
3201         .class          = &omap34xx_mcspi_class,
3202         .dev_attr       = &omap_mcspi1_dev_attr,
3203         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3204 };
3205
3206 /* mcspi2 */
3207 static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
3208         { .name = "irq", .irq = 66 },
3209 };
3210
3211 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
3212         { .name = "tx0", .dma_req = 43 },
3213         { .name = "rx0", .dma_req = 44 },
3214         { .name = "tx1", .dma_req = 45 },
3215         { .name = "rx1", .dma_req = 46 },
3216 };
3217
3218 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
3219         &omap34xx_l4_core__mcspi2,
3220 };
3221
3222 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
3223         .num_chipselect = 2,
3224 };
3225
3226 static struct omap_hwmod omap34xx_mcspi2 = {
3227         .name           = "mcspi2",
3228         .mpu_irqs       = omap34xx_mcspi2_mpu_irqs,
3229         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
3230         .sdma_reqs      = omap34xx_mcspi2_sdma_reqs,
3231         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
3232         .main_clk       = "mcspi2_fck",
3233         .prcm           = {
3234                 .omap2 = {
3235                         .module_offs = CORE_MOD,
3236                         .prcm_reg_id = 1,
3237                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
3238                         .idlest_reg_id = 1,
3239                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
3240                 },
3241         },
3242         .slaves         = omap34xx_mcspi2_slaves,
3243         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
3244         .class          = &omap34xx_mcspi_class,
3245         .dev_attr       = &omap_mcspi2_dev_attr,
3246         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3247 };
3248
3249 /* mcspi3 */
3250 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
3251         { .name = "irq", .irq = 91 }, /* 91 */
3252 };
3253
3254 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
3255         { .name = "tx0", .dma_req = 15 },
3256         { .name = "rx0", .dma_req = 16 },
3257         { .name = "tx1", .dma_req = 23 },
3258         { .name = "rx1", .dma_req = 24 },
3259 };
3260
3261 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
3262         &omap34xx_l4_core__mcspi3,
3263 };
3264
3265 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
3266         .num_chipselect = 2,
3267 };
3268
3269 static struct omap_hwmod omap34xx_mcspi3 = {
3270         .name           = "mcspi3",
3271         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
3272         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
3273         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
3274         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
3275         .main_clk       = "mcspi3_fck",
3276         .prcm           = {
3277                 .omap2 = {
3278                         .module_offs = CORE_MOD,
3279                         .prcm_reg_id = 1,
3280                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
3281                         .idlest_reg_id = 1,
3282                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
3283                 },
3284         },
3285         .slaves         = omap34xx_mcspi3_slaves,
3286         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3287         .class          = &omap34xx_mcspi_class,
3288         .dev_attr       = &omap_mcspi3_dev_attr,
3289         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3290 };
3291
3292 /* SPI4 */
3293 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3294         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3295 };
3296
3297 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3298         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3299         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3300 };
3301
3302 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3303         &omap34xx_l4_core__mcspi4,
3304 };
3305
3306 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3307         .num_chipselect = 1,
3308 };
3309
3310 static struct omap_hwmod omap34xx_mcspi4 = {
3311         .name           = "mcspi4",
3312         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
3313         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
3314         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
3315         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
3316         .main_clk       = "mcspi4_fck",
3317         .prcm           = {
3318                 .omap2 = {
3319                         .module_offs = CORE_MOD,
3320                         .prcm_reg_id = 1,
3321                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3322                         .idlest_reg_id = 1,
3323                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3324                 },
3325         },
3326         .slaves         = omap34xx_mcspi4_slaves,
3327         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3328         .class          = &omap34xx_mcspi_class,
3329         .dev_attr       = &omap_mcspi4_dev_attr,
3330         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3331 };
3332
3333 /*
3334  * usbhsotg
3335  */
3336 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3337         .rev_offs       = 0x0400,
3338         .sysc_offs      = 0x0404,
3339         .syss_offs      = 0x0408,
3340         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3341                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3342                           SYSC_HAS_AUTOIDLE),
3343         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3344                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3345         .sysc_fields    = &omap_hwmod_sysc_type1,
3346 };
3347
3348 static struct omap_hwmod_class usbotg_class = {
3349         .name = "usbotg",
3350         .sysc = &omap3xxx_usbhsotg_sysc,
3351 };
3352 /* usb_otg_hs */
3353 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3354
3355         { .name = "mc", .irq = 92 },
3356         { .name = "dma", .irq = 93 },
3357 };
3358
3359 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3360         .name           = "usb_otg_hs",
3361         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
3362         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
3363         .main_clk       = "hsotgusb_ick",
3364         .prcm           = {
3365                 .omap2 = {
3366                         .prcm_reg_id = 1,
3367                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3368                         .module_offs = CORE_MOD,
3369                         .idlest_reg_id = 1,
3370                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3371                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3372                 },
3373         },
3374         .masters        = omap3xxx_usbhsotg_masters,
3375         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3376         .slaves         = omap3xxx_usbhsotg_slaves,
3377         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3378         .class          = &usbotg_class,
3379
3380         /*
3381          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
3382          * broken when autoidle is enabled
3383          * workaround is to disable the autoidle bit at module level.
3384          */
3385         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3386                                 | HWMOD_SWSUP_MSTANDBY,
3387         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3388 };
3389
3390 /* usb_otg_hs */
3391 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3392
3393         { .name = "mc", .irq = 71 },
3394 };
3395
3396 static struct omap_hwmod_class am35xx_usbotg_class = {
3397         .name = "am35xx_usbotg",
3398         .sysc = NULL,
3399 };
3400
3401 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3402         .name           = "am35x_otg_hs",
3403         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3404         .mpu_irqs_cnt   = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
3405         .main_clk       = NULL,
3406         .prcm = {
3407                 .omap2 = {
3408                 },
3409         },
3410         .masters        = am35xx_usbhsotg_masters,
3411         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3412         .slaves         = am35xx_usbhsotg_slaves,
3413         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3414         .class          = &am35xx_usbotg_class,
3415         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3416 };
3417
3418 /* MMC/SD/SDIO common */
3419
3420 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3421         .rev_offs       = 0x1fc,
3422         .sysc_offs      = 0x10,
3423         .syss_offs      = 0x14,
3424         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3425                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3426                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3427         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3428         .sysc_fields    = &omap_hwmod_sysc_type1,
3429 };
3430
3431 static struct omap_hwmod_class omap34xx_mmc_class = {
3432         .name = "mmc",
3433         .sysc = &omap34xx_mmc_sysc,
3434 };
3435
3436 /* MMC/SD/SDIO1 */
3437
3438 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3439         { .irq = 83, },
3440 };
3441
3442 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3443         { .name = "tx", .dma_req = 61, },
3444         { .name = "rx", .dma_req = 62, },
3445 };
3446
3447 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3448         { .role = "dbck", .clk = "omap_32k_fck", },
3449 };
3450
3451 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3452         &omap3xxx_l4_core__mmc1,
3453 };
3454
3455 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3456         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3457 };
3458
3459 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3460         .name           = "mmc1",
3461         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3462         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
3463         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3464         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3465         .opt_clks       = omap34xx_mmc1_opt_clks,
3466         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3467         .main_clk       = "mmchs1_fck",
3468         .prcm           = {
3469                 .omap2 = {
3470                         .module_offs = CORE_MOD,
3471                         .prcm_reg_id = 1,
3472                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3473                         .idlest_reg_id = 1,
3474                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3475                 },
3476         },
3477         .dev_attr       = &mmc1_dev_attr,
3478         .slaves         = omap3xxx_mmc1_slaves,
3479         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3480         .class          = &omap34xx_mmc_class,
3481         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3482 };
3483
3484 /* MMC/SD/SDIO2 */
3485
3486 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3487         { .irq = INT_24XX_MMC2_IRQ, },
3488 };
3489
3490 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3491         { .name = "tx", .dma_req = 47, },
3492         { .name = "rx", .dma_req = 48, },
3493 };
3494
3495 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3496         { .role = "dbck", .clk = "omap_32k_fck", },
3497 };
3498
3499 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3500         &omap3xxx_l4_core__mmc2,
3501 };
3502
3503 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3504         .name           = "mmc2",
3505         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3506         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
3507         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3508         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3509         .opt_clks       = omap34xx_mmc2_opt_clks,
3510         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3511         .main_clk       = "mmchs2_fck",
3512         .prcm           = {
3513                 .omap2 = {
3514                         .module_offs = CORE_MOD,
3515                         .prcm_reg_id = 1,
3516                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3517                         .idlest_reg_id = 1,
3518                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3519                 },
3520         },
3521         .slaves         = omap3xxx_mmc2_slaves,
3522         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3523         .class          = &omap34xx_mmc_class,
3524         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3525 };
3526
3527 /* MMC/SD/SDIO3 */
3528
3529 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3530         { .irq = 94, },
3531 };
3532
3533 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3534         { .name = "tx", .dma_req = 77, },
3535         { .name = "rx", .dma_req = 78, },
3536 };
3537
3538 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3539         { .role = "dbck", .clk = "omap_32k_fck", },
3540 };
3541
3542 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3543         &omap3xxx_l4_core__mmc3,
3544 };
3545
3546 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3547         .name           = "mmc3",
3548         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3549         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
3550         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3551         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3552         .opt_clks       = omap34xx_mmc3_opt_clks,
3553         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3554         .main_clk       = "mmchs3_fck",
3555         .prcm           = {
3556                 .omap2 = {
3557                         .prcm_reg_id = 1,
3558                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3559                         .idlest_reg_id = 1,
3560                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3561                 },
3562         },
3563         .slaves         = omap3xxx_mmc3_slaves,
3564         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3565         .class          = &omap34xx_mmc_class,
3566         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3567 };
3568
3569 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3570         &omap3xxx_l3_main_hwmod,
3571         &omap3xxx_l4_core_hwmod,
3572         &omap3xxx_l4_per_hwmod,
3573         &omap3xxx_l4_wkup_hwmod,
3574         &omap3xxx_mmc1_hwmod,
3575         &omap3xxx_mmc2_hwmod,
3576         &omap3xxx_mmc3_hwmod,
3577         &omap3xxx_mpu_hwmod,
3578         &omap3xxx_iva_hwmod,
3579
3580         &omap3xxx_timer1_hwmod,
3581         &omap3xxx_timer2_hwmod,
3582         &omap3xxx_timer3_hwmod,
3583         &omap3xxx_timer4_hwmod,
3584         &omap3xxx_timer5_hwmod,
3585         &omap3xxx_timer6_hwmod,
3586         &omap3xxx_timer7_hwmod,
3587         &omap3xxx_timer8_hwmod,
3588         &omap3xxx_timer9_hwmod,
3589         &omap3xxx_timer10_hwmod,
3590         &omap3xxx_timer11_hwmod,
3591         &omap3xxx_timer12_hwmod,
3592
3593         &omap3xxx_wd_timer2_hwmod,
3594         &omap3xxx_uart1_hwmod,
3595         &omap3xxx_uart2_hwmod,
3596         &omap3xxx_uart3_hwmod,
3597         &omap3xxx_uart4_hwmod,
3598         /* dss class */
3599         &omap3430es1_dss_core_hwmod,
3600         &omap3xxx_dss_core_hwmod,
3601         &omap3xxx_dss_dispc_hwmod,
3602         &omap3xxx_dss_dsi1_hwmod,
3603         &omap3xxx_dss_rfbi_hwmod,
3604         &omap3xxx_dss_venc_hwmod,
3605
3606         /* i2c class */
3607         &omap3xxx_i2c1_hwmod,
3608         &omap3xxx_i2c2_hwmod,
3609         &omap3xxx_i2c3_hwmod,
3610         &omap34xx_sr1_hwmod,
3611         &omap34xx_sr2_hwmod,
3612         &omap36xx_sr1_hwmod,
3613         &omap36xx_sr2_hwmod,
3614
3615
3616         /* gpio class */
3617         &omap3xxx_gpio1_hwmod,
3618         &omap3xxx_gpio2_hwmod,
3619         &omap3xxx_gpio3_hwmod,
3620         &omap3xxx_gpio4_hwmod,
3621         &omap3xxx_gpio5_hwmod,
3622         &omap3xxx_gpio6_hwmod,
3623
3624         /* dma_system class*/
3625         &omap3xxx_dma_system_hwmod,
3626
3627         /* mcbsp class */
3628         &omap3xxx_mcbsp1_hwmod,
3629         &omap3xxx_mcbsp2_hwmod,
3630         &omap3xxx_mcbsp3_hwmod,
3631         &omap3xxx_mcbsp4_hwmod,
3632         &omap3xxx_mcbsp5_hwmod,
3633         &omap3xxx_mcbsp2_sidetone_hwmod,
3634         &omap3xxx_mcbsp3_sidetone_hwmod,
3635
3636         /* mailbox class */
3637         &omap3xxx_mailbox_hwmod,
3638
3639         /* mcspi class */
3640         &omap34xx_mcspi1,
3641         &omap34xx_mcspi2,
3642         &omap34xx_mcspi3,
3643         &omap34xx_mcspi4,
3644
3645         /* usbotg class */
3646         &omap3xxx_usbhsotg_hwmod,
3647
3648         /* usbotg for am35x */
3649         &am35xx_usbhsotg_hwmod,
3650
3651         NULL,
3652 };
3653
3654 int __init omap3xxx_hwmod_init(void)
3655 {
3656         return omap_hwmod_register(omap3xxx_hwmods);
3657 }