arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/smartreflex.h>
  26 #include <plat/mcspi.h>
  27
  28 #include "omap_hwmod_common_data.h"
  29
  30 #include "prm-regbits-34xx.h"
  31 #include "cm-regbits-34xx.h"
  32 #include "wd_timer.h"
  33 #include <mach/am35xx.h>
  34
  35 /*
  36  * OMAP3xxx hardware module integration data
  37  *
  38  * ALl of the data in this section should be autogeneratable from the
  39  * TI hardware database or other technical documentation.  Data that
  40  * is driver-specific or driver-kernel integration-specific belongs
  41  * elsewhere.
  42  */
  43
  44 static struct omap_hwmod omap3xxx_mpu_hwmod;
  45 static struct omap_hwmod omap3xxx_iva_hwmod;
  46 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  47 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  48 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  49 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  50 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  51 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  52 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  53 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  56 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  57 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  58 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  59 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  60 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  61 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  65 static struct omap_hwmod omap34xx_sr1_hwmod;
  66 static struct omap_hwmod omap34xx_sr2_hwmod;
  67 static struct omap_hwmod omap34xx_mcspi1;
  68 static struct omap_hwmod omap34xx_mcspi2;
  69 static struct omap_hwmod omap34xx_mcspi3;
  70 static struct omap_hwmod omap34xx_mcspi4;
  71 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  72
  73 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  74
  75 /* L3 -> L4_CORE interface */
  76 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  77         .master = &omap3xxx_l3_main_hwmod,
  78         .slave  = &omap3xxx_l4_core_hwmod,
  79         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  80 };
  81
  82 /* L3 -> L4_PER interface */
  83 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  84         .master = &omap3xxx_l3_main_hwmod,
  85         .slave  = &omap3xxx_l4_per_hwmod,
  86         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  87 };
  88
  89 /* MPU -> L3 interface */
  90 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
  91         .master = &omap3xxx_mpu_hwmod,
  92         .slave  = &omap3xxx_l3_main_hwmod,
  93         .user   = OCP_USER_MPU,
  94 };
  95
  96 /* Slave interfaces on the L3 interconnect */
  97 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
  98         &omap3xxx_mpu__l3_main,
  99 };
 100
 101 /* DSS -> l3 */
 102 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 103         .master         = &omap3xxx_dss_core_hwmod,
 104         .slave          = &omap3xxx_l3_main_hwmod,
 105         .fw = {
 106                 .omap2 = {
 107                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 108                         .flags  = OMAP_FIREWALL_L3,
 109                 }
 110         },
 111         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 112 };
 113
 114 /* Master interfaces on the L3 interconnect */
 115 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 116         &omap3xxx_l3_main__l4_core,
 117         &omap3xxx_l3_main__l4_per,
 118 };
 119
 120 /* L3 */
 121 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 122         .name           = "l3_main",
 123         .class          = &l3_hwmod_class,
 124         .masters        = omap3xxx_l3_main_masters,
 125         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 126         .slaves         = omap3xxx_l3_main_slaves,
 127         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 128         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 129         .flags          = HWMOD_NO_IDLEST,
 130 };
 131
 132 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 133 static struct omap_hwmod omap3xxx_uart1_hwmod;
 134 static struct omap_hwmod omap3xxx_uart2_hwmod;
 135 static struct omap_hwmod omap3xxx_uart3_hwmod;
 136 static struct omap_hwmod omap3xxx_uart4_hwmod;
 137 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 138
 139 /* l3_core -> usbhsotg interface */
 140 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 141         .master         = &omap3xxx_usbhsotg_hwmod,
 142         .slave          = &omap3xxx_l3_main_hwmod,
 143         .clk            = "core_l3_ick",
 144         .user           = OCP_USER_MPU,
 145 };
 146
 147 /* l3_core -> am35xx_usbhsotg interface */
 148 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 149         .master         = &am35xx_usbhsotg_hwmod,
 150         .slave          = &omap3xxx_l3_main_hwmod,
 151         .clk            = "core_l3_ick",
 152         .user           = OCP_USER_MPU,
 153 };
 154 /* L4_CORE -> L4_WKUP interface */
 155 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 156         .master = &omap3xxx_l4_core_hwmod,
 157         .slave  = &omap3xxx_l4_wkup_hwmod,
 158         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 159 };
 160
 161 /* L4 CORE -> UART1 interface */
 162 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 163         {
 164                 .pa_start       = OMAP3_UART1_BASE,
 165                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 166                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 167         },
 168 };
 169
 170 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 171         .master         = &omap3xxx_l4_core_hwmod,
 172         .slave          = &omap3xxx_uart1_hwmod,
 173         .clk            = "uart1_ick",
 174         .addr           = omap3xxx_uart1_addr_space,
 175         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart1_addr_space),
 176         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 177 };
 178
 179 /* L4 CORE -> UART2 interface */
 180 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 181         {
 182                 .pa_start       = OMAP3_UART2_BASE,
 183                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 184                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 185         },
 186 };
 187
 188 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 189         .master         = &omap3xxx_l4_core_hwmod,
 190         .slave          = &omap3xxx_uart2_hwmod,
 191         .clk            = "uart2_ick",
 192         .addr           = omap3xxx_uart2_addr_space,
 193         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart2_addr_space),
 194         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 195 };
 196
 197 /* L4 PER -> UART3 interface */
 198 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 199         {
 200                 .pa_start       = OMAP3_UART3_BASE,
 201                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 202                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 203         },
 204 };
 205
 206 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 207         .master         = &omap3xxx_l4_per_hwmod,
 208         .slave          = &omap3xxx_uart3_hwmod,
 209         .clk            = "uart3_ick",
 210         .addr           = omap3xxx_uart3_addr_space,
 211         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart3_addr_space),
 212         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 213 };
 214
 215 /* L4 PER -> UART4 interface */
 216 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 217         {
 218                 .pa_start       = OMAP3_UART4_BASE,
 219                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 220                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 221         },
 222 };
 223
 224 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 225         .master         = &omap3xxx_l4_per_hwmod,
 226         .slave          = &omap3xxx_uart4_hwmod,
 227         .clk            = "uart4_ick",
 228         .addr           = omap3xxx_uart4_addr_space,
 229         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart4_addr_space),
 230         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 231 };
 232
 233 /* I2C IP block address space length (in bytes) */
 234 #define OMAP2_I2C_AS_LEN                128
 235
 236 /* L4 CORE -> I2C1 interface */
 237 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
 238         {
 239                 .pa_start       = 0x48070000,
 240                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
 241                 .flags          = ADDR_TYPE_RT,
 242         },
 243 };
 244
 245 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 246         .master         = &omap3xxx_l4_core_hwmod,
 247         .slave          = &omap3xxx_i2c1_hwmod,
 248         .clk            = "i2c1_ick",
 249         .addr           = omap3xxx_i2c1_addr_space,
 250         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
 251         .fw = {
 252                 .omap2 = {
 253                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 254                         .l4_prot_group = 7,
 255                         .flags  = OMAP_FIREWALL_L4,
 256                 }
 257         },
 258         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 259 };
 260
 261 /* L4 CORE -> I2C2 interface */
 262 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
 263         {
 264                 .pa_start       = 0x48072000,
 265                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 266                 .flags          = ADDR_TYPE_RT,
 267         },
 268 };
 269
 270 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 271         .master         = &omap3xxx_l4_core_hwmod,
 272         .slave          = &omap3xxx_i2c2_hwmod,
 273         .clk            = "i2c2_ick",
 274         .addr           = omap3xxx_i2c2_addr_space,
 275         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
 276         .fw = {
 277                 .omap2 = {
 278                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 279                         .l4_prot_group = 7,
 280                         .flags = OMAP_FIREWALL_L4,
 281                 }
 282         },
 283         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 284 };
 285
 286 /* L4 CORE -> I2C3 interface */
 287 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 288         {
 289                 .pa_start       = 0x48060000,
 290                 .pa_end         = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
 291                 .flags          = ADDR_TYPE_RT,
 292         },
 293 };
 294
 295 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 296         .master         = &omap3xxx_l4_core_hwmod,
 297         .slave          = &omap3xxx_i2c3_hwmod,
 298         .clk            = "i2c3_ick",
 299         .addr           = omap3xxx_i2c3_addr_space,
 300         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
 301         .fw = {
 302                 .omap2 = {
 303                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 304                         .l4_prot_group = 7,
 305                         .flags = OMAP_FIREWALL_L4,
 306                 }
 307         },
 308         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 309 };
 310
 311 /* L4 CORE -> SR1 interface */
 312 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 313         {
 314                 .pa_start       = OMAP34XX_SR1_BASE,
 315                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 316                 .flags          = ADDR_TYPE_RT,
 317         },
 318 };
 319
 320 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 321         .master         = &omap3xxx_l4_core_hwmod,
 322         .slave          = &omap34xx_sr1_hwmod,
 323         .clk            = "sr_l4_ick",
 324         .addr           = omap3_sr1_addr_space,
 325         .addr_cnt       = ARRAY_SIZE(omap3_sr1_addr_space),
 326         .user           = OCP_USER_MPU,
 327 };
 328
 329 /* L4 CORE -> SR1 interface */
 330 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 331         {
 332                 .pa_start       = OMAP34XX_SR2_BASE,
 333                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 334                 .flags          = ADDR_TYPE_RT,
 335         },
 336 };
 337
 338 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 339         .master         = &omap3xxx_l4_core_hwmod,
 340         .slave          = &omap34xx_sr2_hwmod,
 341         .clk            = "sr_l4_ick",
 342         .addr           = omap3_sr2_addr_space,
 343         .addr_cnt       = ARRAY_SIZE(omap3_sr2_addr_space),
 344         .user           = OCP_USER_MPU,
 345 };
 346
 347 /*
 348 * usbhsotg interface data
 349 */
 350
 351 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 352         {
 353                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 354                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 355                 .flags          = ADDR_TYPE_RT
 356         },
 357 };
 358
 359 /* l4_core -> usbhsotg  */
 360 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 361         .master         = &omap3xxx_l4_core_hwmod,
 362         .slave          = &omap3xxx_usbhsotg_hwmod,
 363         .clk            = "l4_ick",
 364         .addr           = omap3xxx_usbhsotg_addrs,
 365         .addr_cnt       = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
 366         .user           = OCP_USER_MPU,
 367 };
 368
 369 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 370         &omap3xxx_usbhsotg__l3,
 371 };
 372
 373 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 374         &omap3xxx_l4_core__usbhsotg,
 375 };
 376
 377 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 378         {
 379                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 380                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 381                 .flags          = ADDR_TYPE_RT
 382         },
 383 };
 384
 385 /* l4_core -> usbhsotg  */
 386 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 387         .master         = &omap3xxx_l4_core_hwmod,
 388         .slave          = &am35xx_usbhsotg_hwmod,
 389         .clk            = "l4_ick",
 390         .addr           = am35xx_usbhsotg_addrs,
 391         .addr_cnt       = ARRAY_SIZE(am35xx_usbhsotg_addrs),
 392         .user           = OCP_USER_MPU,
 393 };
 394
 395 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 396         &am35xx_usbhsotg__l3,
 397 };
 398
 399 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 400         &am35xx_l4_core__usbhsotg,
 401 };
 402 /* Slave interfaces on the L4_CORE interconnect */
 403 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 404         &omap3xxx_l3_main__l4_core,
 405         &omap3_l4_core__sr1,
 406         &omap3_l4_core__sr2,
 407 };
 408
 409 /* Master interfaces on the L4_CORE interconnect */
 410 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
 411         &omap3xxx_l4_core__l4_wkup,
 412         &omap3_l4_core__uart1,
 413         &omap3_l4_core__uart2,
 414         &omap3_l4_core__i2c1,
 415         &omap3_l4_core__i2c2,
 416         &omap3_l4_core__i2c3,
 417 };
 418
 419 /* L4 CORE */
 420 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 421         .name           = "l4_core",
 422         .class          = &l4_hwmod_class,
 423         .masters        = omap3xxx_l4_core_masters,
 424         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_core_masters),
 425         .slaves         = omap3xxx_l4_core_slaves,
 426         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 427         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 428         .flags          = HWMOD_NO_IDLEST,
 429 };
 430
 431 /* Slave interfaces on the L4_PER interconnect */
 432 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 433         &omap3xxx_l3_main__l4_per,
 434 };
 435
 436 /* Master interfaces on the L4_PER interconnect */
 437 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
 438         &omap3_l4_per__uart3,
 439         &omap3_l4_per__uart4,
 440 };
 441
 442 /* L4 PER */
 443 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 444         .name           = "l4_per",
 445         .class          = &l4_hwmod_class,
 446         .masters        = omap3xxx_l4_per_masters,
 447         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_per_masters),
 448         .slaves         = omap3xxx_l4_per_slaves,
 449         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 450         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 451         .flags          = HWMOD_NO_IDLEST,
 452 };
 453
 454 /* Slave interfaces on the L4_WKUP interconnect */
 455 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 456         &omap3xxx_l4_core__l4_wkup,
 457 };
 458
 459 /* Master interfaces on the L4_WKUP interconnect */
 460 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
 461 };
 462
 463 /* L4 WKUP */
 464 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 465         .name           = "l4_wkup",
 466         .class          = &l4_hwmod_class,
 467         .masters        = omap3xxx_l4_wkup_masters,
 468         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
 469         .slaves         = omap3xxx_l4_wkup_slaves,
 470         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 471         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 472         .flags          = HWMOD_NO_IDLEST,
 473 };
 474
 475 /* Master interfaces on the MPU device */
 476 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 477         &omap3xxx_mpu__l3_main,
 478 };
 479
 480 /* MPU */
 481 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 482         .name           = "mpu",
 483         .class          = &mpu_hwmod_class,
 484         .main_clk       = "arm_fck",
 485         .masters        = omap3xxx_mpu_masters,
 486         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 487         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 488 };
 489
 490 /*
 491  * IVA2_2 interface data
 492  */
 493
 494 /* IVA2 <- L3 interface */
 495 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 496         .master         = &omap3xxx_l3_main_hwmod,
 497         .slave          = &omap3xxx_iva_hwmod,
 498         .clk            = "iva2_ck",
 499         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 500 };
 501
 502 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 503         &omap3xxx_l3__iva,
 504 };
 505
 506 /*
 507  * IVA2 (IVA2)
 508  */
 509
 510 static struct omap_hwmod omap3xxx_iva_hwmod = {
 511         .name           = "iva",
 512         .class          = &iva_hwmod_class,
 513         .masters        = omap3xxx_iva_masters,
 514         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 515         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 516 };
 517
 518 /* l4_wkup -> wd_timer2 */
 519 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
 520         {
 521                 .pa_start       = 0x48314000,
 522                 .pa_end         = 0x4831407f,
 523                 .flags          = ADDR_TYPE_RT
 524         },
 525 };
 526
 527 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
 528         .master         = &omap3xxx_l4_wkup_hwmod,
 529         .slave          = &omap3xxx_wd_timer2_hwmod,
 530         .clk            = "wdt2_ick",
 531         .addr           = omap3xxx_wd_timer2_addrs,
 532         .addr_cnt       = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
 533         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 534 };
 535
 536 /*
 537  * 'wd_timer' class
 538  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 539  * overflow condition
 540  */
 541
 542 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 543         .rev_offs       = 0x0000,
 544         .sysc_offs      = 0x0010,
 545         .syss_offs      = 0x0014,
 546         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 547                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 548                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
 549         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 550         .sysc_fields    = &omap_hwmod_sysc_type1,
 551 };
 552
 553 /* I2C common */
 554 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 555         .rev_offs       = 0x00,
 556         .sysc_offs      = 0x20,
 557         .syss_offs      = 0x10,
 558         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 559                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 560                            SYSC_HAS_AUTOIDLE),
 561         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 562         .sysc_fields    = &omap_hwmod_sysc_type1,
 563 };
 564
 565 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 566         .name           = "wd_timer",
 567         .sysc           = &omap3xxx_wd_timer_sysc,
 568         .pre_shutdown   = &omap2_wd_timer_disable
 569 };
 570
 571 /* wd_timer2 */
 572 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
 573         &omap3xxx_l4_wkup__wd_timer2,
 574 };
 575
 576 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 577         .name           = "wd_timer2",
 578         .class          = &omap3xxx_wd_timer_hwmod_class,
 579         .main_clk       = "wdt2_fck",
 580         .prcm           = {
 581                 .omap2 = {
 582                         .prcm_reg_id = 1,
 583                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 584                         .module_offs = WKUP_MOD,
 585                         .idlest_reg_id = 1,
 586                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 587                 },
 588         },
 589         .slaves         = omap3xxx_wd_timer2_slaves,
 590         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
 591         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 592 };
 593
 594 /* UART common */
 595
 596 static struct omap_hwmod_class_sysconfig uart_sysc = {
 597         .rev_offs       = 0x50,
 598         .sysc_offs      = 0x54,
 599         .syss_offs      = 0x58,
 600         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
 601                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 602                            SYSC_HAS_AUTOIDLE),
 603         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 604         .sysc_fields    = &omap_hwmod_sysc_type1,
 605 };
 606
 607 static struct omap_hwmod_class uart_class = {
 608         .name = "uart",
 609         .sysc = &uart_sysc,
 610 };
 611
 612 /* UART1 */
 613
 614 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
 615         { .irq = INT_24XX_UART1_IRQ, },
 616 };
 617
 618 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
 619         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
 620         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
 621 };
 622
 623 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
 624         &omap3_l4_core__uart1,
 625 };
 626
 627 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 628         .name           = "uart1",
 629         .mpu_irqs       = uart1_mpu_irqs,
 630         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
 631         .sdma_reqs      = uart1_sdma_reqs,
 632         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
 633         .main_clk       = "uart1_fck",
 634         .prcm           = {
 635                 .omap2 = {
 636                         .module_offs = CORE_MOD,
 637                         .prcm_reg_id = 1,
 638                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 639                         .idlest_reg_id = 1,
 640                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 641                 },
 642         },
 643         .slaves         = omap3xxx_uart1_slaves,
 644         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
 645         .class          = &uart_class,
 646         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 647 };
 648
 649 /* UART2 */
 650
 651 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
 652         { .irq = INT_24XX_UART2_IRQ, },
 653 };
 654
 655 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
 656         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 657         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 658 };
 659
 660 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
 661         &omap3_l4_core__uart2,
 662 };
 663
 664 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 665         .name           = "uart2",
 666         .mpu_irqs       = uart2_mpu_irqs,
 667         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
 668         .sdma_reqs      = uart2_sdma_reqs,
 669         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
 670         .main_clk       = "uart2_fck",
 671         .prcm           = {
 672                 .omap2 = {
 673                         .module_offs = CORE_MOD,
 674                         .prcm_reg_id = 1,
 675                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 676                         .idlest_reg_id = 1,
 677                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 678                 },
 679         },
 680         .slaves         = omap3xxx_uart2_slaves,
 681         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
 682         .class          = &uart_class,
 683         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 684 };
 685
 686 /* UART3 */
 687
 688 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
 689         { .irq = INT_24XX_UART3_IRQ, },
 690 };
 691
 692 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
 693         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
 694         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
 695 };
 696
 697 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
 698         &omap3_l4_per__uart3,
 699 };
 700
 701 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 702         .name           = "uart3",
 703         .mpu_irqs       = uart3_mpu_irqs,
 704         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
 705         .sdma_reqs      = uart3_sdma_reqs,
 706         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
 707         .main_clk       = "uart3_fck",
 708         .prcm           = {
 709                 .omap2 = {
 710                         .module_offs = OMAP3430_PER_MOD,
 711                         .prcm_reg_id = 1,
 712                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 713                         .idlest_reg_id = 1,
 714                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 715                 },
 716         },
 717         .slaves         = omap3xxx_uart3_slaves,
 718         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
 719         .class          = &uart_class,
 720         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 721 };
 722
 723 /* UART4 */
 724
 725 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 726         { .irq = INT_36XX_UART4_IRQ, },
 727 };
 728
 729 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 730         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
 731         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
 732 };
 733
 734 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
 735         &omap3_l4_per__uart4,
 736 };
 737
 738 static struct omap_hwmod omap3xxx_uart4_hwmod = {
 739         .name           = "uart4",
 740         .mpu_irqs       = uart4_mpu_irqs,
 741         .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
 742         .sdma_reqs      = uart4_sdma_reqs,
 743         .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
 744         .main_clk       = "uart4_fck",
 745         .prcm           = {
 746                 .omap2 = {
 747                         .module_offs = OMAP3430_PER_MOD,
 748                         .prcm_reg_id = 1,
 749                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 750                         .idlest_reg_id = 1,
 751                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 752                 },
 753         },
 754         .slaves         = omap3xxx_uart4_slaves,
 755         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
 756         .class          = &uart_class,
 757         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 758 };
 759
 760 static struct omap_hwmod_class i2c_class = {
 761         .name = "i2c",
 762         .sysc = &i2c_sysc,
 763 };
 764
 765 /*
 766  * 'dss' class
 767  * display sub-system
 768  */
 769
 770 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
 771         .rev_offs       = 0x0000,
 772         .sysc_offs      = 0x0010,
 773         .syss_offs      = 0x0014,
 774         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 775         .sysc_fields    = &omap_hwmod_sysc_type1,
 776 };
 777
 778 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
 779         .name = "dss",
 780         .sysc = &omap3xxx_dss_sysc,
 781 };
 782
 783 /* dss */
 784 static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = {
 785         { .irq = 25 },
 786 };
 787
 788 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 789         { .name = "dispc", .dma_req = 5 },
 790         { .name = "dsi1", .dma_req = 74 },
 791 };
 792
 793 /* dss */
 794 /* dss master ports */
 795 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
 796         &omap3xxx_dss__l3,
 797 };
 798
 799 static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
 800         {
 801                 .pa_start       = 0x48050000,
 802                 .pa_end         = 0x480503FF,
 803                 .flags          = ADDR_TYPE_RT
 804         },
 805 };
 806
 807 /* l4_core -> dss */
 808 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
 809         .master         = &omap3xxx_l4_core_hwmod,
 810         .slave          = &omap3430es1_dss_core_hwmod,
 811         .clk            = "dss_ick",
 812         .addr           = omap3xxx_dss_addrs,
 813         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
 814         .fw = {
 815                 .omap2 = {
 816                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
 817                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
 818                         .flags  = OMAP_FIREWALL_L4,
 819                 }
 820         },
 821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 822 };
 823
 824 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
 825         .master         = &omap3xxx_l4_core_hwmod,
 826         .slave          = &omap3xxx_dss_core_hwmod,
 827         .clk            = "dss_ick",
 828         .addr           = omap3xxx_dss_addrs,
 829         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
 830         .fw = {
 831                 .omap2 = {
 832                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
 833                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
 834                         .flags  = OMAP_FIREWALL_L4,
 835                 }
 836         },
 837         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 838 };
 839
 840 /* dss slave ports */
 841 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
 842         &omap3430es1_l4_core__dss,
 843 };
 844
 845 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
 846         &omap3xxx_l4_core__dss,
 847 };
 848
 849 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 850         { .role = "tv_clk", .clk = "dss_tv_fck" },
 851         { .role = "dssclk", .clk = "dss_96m_fck" },
 852         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 853 };
 854
 855 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 856         .name           = "dss_core",
 857         .class          = &omap3xxx_dss_hwmod_class,
 858         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 859         .mpu_irqs       = omap3xxx_dss_irqs,
 860         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dss_irqs),
 861         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 862         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
 863
 864         .prcm           = {
 865                 .omap2 = {
 866                         .prcm_reg_id = 1,
 867                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 868                         .module_offs = OMAP3430_DSS_MOD,
 869                         .idlest_reg_id = 1,
 870                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 871                 },
 872         },
 873         .opt_clks       = dss_opt_clks,
 874         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 875         .slaves         = omap3430es1_dss_slaves,
 876         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
 877         .masters        = omap3xxx_dss_masters,
 878         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
 879         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
 880         .flags          = HWMOD_NO_IDLEST,
 881 };
 882
 883 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 884         .name           = "dss_core",
 885         .class          = &omap3xxx_dss_hwmod_class,
 886         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 887         .mpu_irqs       = omap3xxx_dss_irqs,
 888         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dss_irqs),
 889         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 890         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
 891
 892         .prcm           = {
 893                 .omap2 = {
 894                         .prcm_reg_id = 1,
 895                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 896                         .module_offs = OMAP3430_DSS_MOD,
 897                         .idlest_reg_id = 1,
 898                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 899                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 900                 },
 901         },
 902         .opt_clks       = dss_opt_clks,
 903         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 904         .slaves         = omap3xxx_dss_slaves,
 905         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
 906         .masters        = omap3xxx_dss_masters,
 907         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
 908         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
 909                                 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
 910 };
 911
 912 /*
 913  * 'dispc' class
 914  * display controller
 915  */
 916
 917 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
 918         .rev_offs       = 0x0000,
 919         .sysc_offs      = 0x0010,
 920         .syss_offs      = 0x0014,
 921         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 922                            SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
 923                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 924         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 925                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 926         .sysc_fields    = &omap_hwmod_sysc_type1,
 927 };
 928
 929 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
 930         .name = "dispc",
 931         .sysc = &omap3xxx_dispc_sysc,
 932 };
 933
 934 static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
 935         {
 936                 .pa_start       = 0x48050400,
 937                 .pa_end         = 0x480507FF,
 938                 .flags          = ADDR_TYPE_RT
 939         },
 940 };
 941
 942 /* l4_core -> dss_dispc */
 943 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
 944         .master         = &omap3xxx_l4_core_hwmod,
 945         .slave          = &omap3xxx_dss_dispc_hwmod,
 946         .clk            = "dss_ick",
 947         .addr           = omap3xxx_dss_dispc_addrs,
 948         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
 949         .fw = {
 950                 .omap2 = {
 951                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
 952                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
 953                         .flags  = OMAP_FIREWALL_L4,
 954                 }
 955         },
 956         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 957 };
 958
 959 /* dss_dispc slave ports */
 960 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
 961         &omap3xxx_l4_core__dss_dispc,
 962 };
 963
 964 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 965         .name           = "dss_dispc",
 966         .class          = &omap3xxx_dispc_hwmod_class,
 967         .main_clk       = "dss1_alwon_fck",
 968         .prcm           = {
 969                 .omap2 = {
 970                         .prcm_reg_id = 1,
 971                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 972                         .module_offs = OMAP3430_DSS_MOD,
 973                 },
 974         },
 975         .slaves         = omap3xxx_dss_dispc_slaves,
 976         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
 977         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
 978                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
 979                                 CHIP_GE_OMAP3630ES1_1),
 980         .flags          = HWMOD_NO_IDLEST,
 981 };
 982
 983 /*
 984  * 'dsi' class
 985  * display serial interface controller
 986  */
 987
 988 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 989         .name = "dsi",
 990 };
 991
 992 /* dss_dsi1 */
 993 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
 994         {
 995                 .pa_start       = 0x4804FC00,
 996                 .pa_end         = 0x4804FFFF,
 997                 .flags          = ADDR_TYPE_RT
 998         },
 999 };
1000
1001 /* l4_core -> dss_dsi1 */
1002 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1003         .master         = &omap3xxx_l4_core_hwmod,
1004         .slave          = &omap3xxx_dss_dsi1_hwmod,
1005         .addr           = omap3xxx_dss_dsi1_addrs,
1006         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
1007         .fw = {
1008                 .omap2 = {
1009                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1010                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1011                         .flags  = OMAP_FIREWALL_L4,
1012                 }
1013         },
1014         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1015 };
1016
1017 /* dss_dsi1 slave ports */
1018 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1019         &omap3xxx_l4_core__dss_dsi1,
1020 };
1021
1022 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1023         .name           = "dss_dsi1",
1024         .class          = &omap3xxx_dsi_hwmod_class,
1025         .main_clk       = "dss1_alwon_fck",
1026         .prcm           = {
1027                 .omap2 = {
1028                         .prcm_reg_id = 1,
1029                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1030                         .module_offs = OMAP3430_DSS_MOD,
1031                 },
1032         },
1033         .slaves         = omap3xxx_dss_dsi1_slaves,
1034         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1035         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1036                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1037                                 CHIP_GE_OMAP3630ES1_1),
1038         .flags          = HWMOD_NO_IDLEST,
1039 };
1040
1041 /*
1042  * 'rfbi' class
1043  * remote frame buffer interface
1044  */
1045
1046 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1047         .rev_offs       = 0x0000,
1048         .sysc_offs      = 0x0010,
1049         .syss_offs      = 0x0014,
1050         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1051                            SYSC_HAS_AUTOIDLE),
1052         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1053         .sysc_fields    = &omap_hwmod_sysc_type1,
1054 };
1055
1056 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1057         .name = "rfbi",
1058         .sysc = &omap3xxx_rfbi_sysc,
1059 };
1060
1061 static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1062         {
1063                 .pa_start       = 0x48050800,
1064                 .pa_end         = 0x48050BFF,
1065                 .flags          = ADDR_TYPE_RT
1066         },
1067 };
1068
1069 /* l4_core -> dss_rfbi */
1070 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1071         .master         = &omap3xxx_l4_core_hwmod,
1072         .slave          = &omap3xxx_dss_rfbi_hwmod,
1073         .clk            = "dss_ick",
1074         .addr           = omap3xxx_dss_rfbi_addrs,
1075         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
1076         .fw = {
1077                 .omap2 = {
1078                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1079                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1080                         .flags  = OMAP_FIREWALL_L4,
1081                 }
1082         },
1083         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1084 };
1085
1086 /* dss_rfbi slave ports */
1087 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1088         &omap3xxx_l4_core__dss_rfbi,
1089 };
1090
1091 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1092         .name           = "dss_rfbi",
1093         .class          = &omap3xxx_rfbi_hwmod_class,
1094         .main_clk       = "dss1_alwon_fck",
1095         .prcm           = {
1096                 .omap2 = {
1097                         .prcm_reg_id = 1,
1098                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1099                         .module_offs = OMAP3430_DSS_MOD,
1100                 },
1101         },
1102         .slaves         = omap3xxx_dss_rfbi_slaves,
1103         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1104         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1105                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1106                                 CHIP_GE_OMAP3630ES1_1),
1107         .flags          = HWMOD_NO_IDLEST,
1108 };
1109
1110 /*
1111  * 'venc' class
1112  * video encoder
1113  */
1114
1115 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1116         .name = "venc",
1117 };
1118
1119 /* dss_venc */
1120 static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1121         {
1122                 .pa_start       = 0x48050C00,
1123                 .pa_end         = 0x48050FFF,
1124                 .flags          = ADDR_TYPE_RT
1125         },
1126 };
1127
1128 /* l4_core -> dss_venc */
1129 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1130         .master         = &omap3xxx_l4_core_hwmod,
1131         .slave          = &omap3xxx_dss_venc_hwmod,
1132         .clk            = "dss_tv_fck",
1133         .addr           = omap3xxx_dss_venc_addrs,
1134         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
1135         .fw = {
1136                 .omap2 = {
1137                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1138                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1139                         .flags  = OMAP_FIREWALL_L4,
1140                 }
1141         },
1142         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1143 };
1144
1145 /* dss_venc slave ports */
1146 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1147         &omap3xxx_l4_core__dss_venc,
1148 };
1149
1150 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1151         .name           = "dss_venc",
1152         .class          = &omap3xxx_venc_hwmod_class,
1153         .main_clk       = "dss1_alwon_fck",
1154         .prcm           = {
1155                 .omap2 = {
1156                         .prcm_reg_id = 1,
1157                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1158                         .module_offs = OMAP3430_DSS_MOD,
1159                 },
1160         },
1161         .slaves         = omap3xxx_dss_venc_slaves,
1162         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1163         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1164                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1165                                 CHIP_GE_OMAP3630ES1_1),
1166         .flags          = HWMOD_NO_IDLEST,
1167 };
1168
1169 /* I2C1 */
1170
1171 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1172         .fifo_depth     = 8, /* bytes */
1173 };
1174
1175 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1176         { .irq = INT_24XX_I2C1_IRQ, },
1177 };
1178
1179 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1180         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1181         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1182 };
1183
1184 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1185         &omap3_l4_core__i2c1,
1186 };
1187
1188 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1189         .name           = "i2c1",
1190         .mpu_irqs       = i2c1_mpu_irqs,
1191         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
1192         .sdma_reqs      = i2c1_sdma_reqs,
1193         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
1194         .main_clk       = "i2c1_fck",
1195         .prcm           = {
1196                 .omap2 = {
1197                         .module_offs = CORE_MOD,
1198                         .prcm_reg_id = 1,
1199                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1200                         .idlest_reg_id = 1,
1201                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1202                 },
1203         },
1204         .slaves         = omap3xxx_i2c1_slaves,
1205         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1206         .class          = &i2c_class,
1207         .dev_attr       = &i2c1_dev_attr,
1208         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1209 };
1210
1211 /* I2C2 */
1212
1213 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1214         .fifo_depth     = 8, /* bytes */
1215 };
1216
1217 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1218         { .irq = INT_24XX_I2C2_IRQ, },
1219 };
1220
1221 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1222         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1223         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1224 };
1225
1226 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1227         &omap3_l4_core__i2c2,
1228 };
1229
1230 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1231         .name           = "i2c2",
1232         .mpu_irqs       = i2c2_mpu_irqs,
1233         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
1234         .sdma_reqs      = i2c2_sdma_reqs,
1235         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
1236         .main_clk       = "i2c2_fck",
1237         .prcm           = {
1238                 .omap2 = {
1239                         .module_offs = CORE_MOD,
1240                         .prcm_reg_id = 1,
1241                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1242                         .idlest_reg_id = 1,
1243                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1244                 },
1245         },
1246         .slaves         = omap3xxx_i2c2_slaves,
1247         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1248         .class          = &i2c_class,
1249         .dev_attr       = &i2c2_dev_attr,
1250         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1251 };
1252
1253 /* I2C3 */
1254
1255 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1256         .fifo_depth     = 64, /* bytes */
1257 };
1258
1259 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1260         { .irq = INT_34XX_I2C3_IRQ, },
1261 };
1262
1263 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1264         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1265         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1266 };
1267
1268 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1269         &omap3_l4_core__i2c3,
1270 };
1271
1272 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1273         .name           = "i2c3",
1274         .mpu_irqs       = i2c3_mpu_irqs,
1275         .mpu_irqs_cnt   = ARRAY_SIZE(i2c3_mpu_irqs),
1276         .sdma_reqs      = i2c3_sdma_reqs,
1277         .sdma_reqs_cnt  = ARRAY_SIZE(i2c3_sdma_reqs),
1278         .main_clk       = "i2c3_fck",
1279         .prcm           = {
1280                 .omap2 = {
1281                         .module_offs = CORE_MOD,
1282                         .prcm_reg_id = 1,
1283                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1284                         .idlest_reg_id = 1,
1285                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1286                 },
1287         },
1288         .slaves         = omap3xxx_i2c3_slaves,
1289         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1290         .class          = &i2c_class,
1291         .dev_attr       = &i2c3_dev_attr,
1292         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1293 };
1294
1295 /* l4_wkup -> gpio1 */
1296 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1297         {
1298                 .pa_start       = 0x48310000,
1299                 .pa_end         = 0x483101ff,
1300                 .flags          = ADDR_TYPE_RT
1301         },
1302 };
1303
1304 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1305         .master         = &omap3xxx_l4_wkup_hwmod,
1306         .slave          = &omap3xxx_gpio1_hwmod,
1307         .addr           = omap3xxx_gpio1_addrs,
1308         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio1_addrs),
1309         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1310 };
1311
1312 /* l4_per -> gpio2 */
1313 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1314         {
1315                 .pa_start       = 0x49050000,
1316                 .pa_end         = 0x490501ff,
1317                 .flags          = ADDR_TYPE_RT
1318         },
1319 };
1320
1321 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1322         .master         = &omap3xxx_l4_per_hwmod,
1323         .slave          = &omap3xxx_gpio2_hwmod,
1324         .addr           = omap3xxx_gpio2_addrs,
1325         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio2_addrs),
1326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1327 };
1328
1329 /* l4_per -> gpio3 */
1330 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1331         {
1332                 .pa_start       = 0x49052000,
1333                 .pa_end         = 0x490521ff,
1334                 .flags          = ADDR_TYPE_RT
1335         },
1336 };
1337
1338 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1339         .master         = &omap3xxx_l4_per_hwmod,
1340         .slave          = &omap3xxx_gpio3_hwmod,
1341         .addr           = omap3xxx_gpio3_addrs,
1342         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio3_addrs),
1343         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1344 };
1345
1346 /* l4_per -> gpio4 */
1347 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1348         {
1349                 .pa_start       = 0x49054000,
1350                 .pa_end         = 0x490541ff,
1351                 .flags          = ADDR_TYPE_RT
1352         },
1353 };
1354
1355 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1356         .master         = &omap3xxx_l4_per_hwmod,
1357         .slave          = &omap3xxx_gpio4_hwmod,
1358         .addr           = omap3xxx_gpio4_addrs,
1359         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio4_addrs),
1360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1361 };
1362
1363 /* l4_per -> gpio5 */
1364 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1365         {
1366                 .pa_start       = 0x49056000,
1367                 .pa_end         = 0x490561ff,
1368                 .flags          = ADDR_TYPE_RT
1369         },
1370 };
1371
1372 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1373         .master         = &omap3xxx_l4_per_hwmod,
1374         .slave          = &omap3xxx_gpio5_hwmod,
1375         .addr           = omap3xxx_gpio5_addrs,
1376         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio5_addrs),
1377         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1378 };
1379
1380 /* l4_per -> gpio6 */
1381 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1382         {
1383                 .pa_start       = 0x49058000,
1384                 .pa_end         = 0x490581ff,
1385                 .flags          = ADDR_TYPE_RT
1386         },
1387 };
1388
1389 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1390         .master         = &omap3xxx_l4_per_hwmod,
1391         .slave          = &omap3xxx_gpio6_hwmod,
1392         .addr           = omap3xxx_gpio6_addrs,
1393         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio6_addrs),
1394         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1395 };
1396
1397 /*
1398  * 'gpio' class
1399  * general purpose io module
1400  */
1401
1402 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1403         .rev_offs       = 0x0000,
1404         .sysc_offs      = 0x0010,
1405         .syss_offs      = 0x0014,
1406         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1407                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1408         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1409         .sysc_fields    = &omap_hwmod_sysc_type1,
1410 };
1411
1412 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1413         .name = "gpio",
1414         .sysc = &omap3xxx_gpio_sysc,
1415         .rev = 1,
1416 };
1417
1418 /* gpio_dev_attr*/
1419 static struct omap_gpio_dev_attr gpio_dev_attr = {
1420         .bank_width = 32,
1421         .dbck_flag = true,
1422 };
1423
1424 /* gpio1 */
1425 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
1426         { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
1427 };
1428
1429 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1430         { .role = "dbclk", .clk = "gpio1_dbck", },
1431 };
1432
1433 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1434         &omap3xxx_l4_wkup__gpio1,
1435 };
1436
1437 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1438         .name           = "gpio1",
1439         .mpu_irqs       = omap3xxx_gpio1_irqs,
1440         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio1_irqs),
1441         .main_clk       = "gpio1_ick",
1442         .opt_clks       = gpio1_opt_clks,
1443         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1444         .prcm           = {
1445                 .omap2 = {
1446                         .prcm_reg_id = 1,
1447                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1448                         .module_offs = WKUP_MOD,
1449                         .idlest_reg_id = 1,
1450                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1451                 },
1452         },
1453         .slaves         = omap3xxx_gpio1_slaves,
1454         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1455         .class          = &omap3xxx_gpio_hwmod_class,
1456         .dev_attr       = &gpio_dev_attr,
1457         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1458 };
1459
1460 /* gpio2 */
1461 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
1462         { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
1463 };
1464
1465 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1466         { .role = "dbclk", .clk = "gpio2_dbck", },
1467 };
1468
1469 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1470         &omap3xxx_l4_per__gpio2,
1471 };
1472
1473 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1474         .name           = "gpio2",
1475         .mpu_irqs       = omap3xxx_gpio2_irqs,
1476         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio2_irqs),
1477         .main_clk       = "gpio2_ick",
1478         .opt_clks       = gpio2_opt_clks,
1479         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1480         .prcm           = {
1481                 .omap2 = {
1482                         .prcm_reg_id = 1,
1483                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1484                         .module_offs = OMAP3430_PER_MOD,
1485                         .idlest_reg_id = 1,
1486                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1487                 },
1488         },
1489         .slaves         = omap3xxx_gpio2_slaves,
1490         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1491         .class          = &omap3xxx_gpio_hwmod_class,
1492         .dev_attr       = &gpio_dev_attr,
1493         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1494 };
1495
1496 /* gpio3 */
1497 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
1498         { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
1499 };
1500
1501 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1502         { .role = "dbclk", .clk = "gpio3_dbck", },
1503 };
1504
1505 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1506         &omap3xxx_l4_per__gpio3,
1507 };
1508
1509 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1510         .name           = "gpio3",
1511         .mpu_irqs       = omap3xxx_gpio3_irqs,
1512         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio3_irqs),
1513         .main_clk       = "gpio3_ick",
1514         .opt_clks       = gpio3_opt_clks,
1515         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1516         .prcm           = {
1517                 .omap2 = {
1518                         .prcm_reg_id = 1,
1519                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1520                         .module_offs = OMAP3430_PER_MOD,
1521                         .idlest_reg_id = 1,
1522                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1523                 },
1524         },
1525         .slaves         = omap3xxx_gpio3_slaves,
1526         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1527         .class          = &omap3xxx_gpio_hwmod_class,
1528         .dev_attr       = &gpio_dev_attr,
1529         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1530 };
1531
1532 /* gpio4 */
1533 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
1534         { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
1535 };
1536
1537 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1538         { .role = "dbclk", .clk = "gpio4_dbck", },
1539 };
1540
1541 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1542         &omap3xxx_l4_per__gpio4,
1543 };
1544
1545 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1546         .name           = "gpio4",
1547         .mpu_irqs       = omap3xxx_gpio4_irqs,
1548         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio4_irqs),
1549         .main_clk       = "gpio4_ick",
1550         .opt_clks       = gpio4_opt_clks,
1551         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1552         .prcm           = {
1553                 .omap2 = {
1554                         .prcm_reg_id = 1,
1555                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1556                         .module_offs = OMAP3430_PER_MOD,
1557                         .idlest_reg_id = 1,
1558                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1559                 },
1560         },
1561         .slaves         = omap3xxx_gpio4_slaves,
1562         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1563         .class          = &omap3xxx_gpio_hwmod_class,
1564         .dev_attr       = &gpio_dev_attr,
1565         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1566 };
1567
1568 /* gpio5 */
1569 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1570         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1571 };
1572
1573 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1574         { .role = "dbclk", .clk = "gpio5_dbck", },
1575 };
1576
1577 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
1578         &omap3xxx_l4_per__gpio5,
1579 };
1580
1581 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1582         .name           = "gpio5",
1583         .mpu_irqs       = omap3xxx_gpio5_irqs,
1584         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio5_irqs),
1585         .main_clk       = "gpio5_ick",
1586         .opt_clks       = gpio5_opt_clks,
1587         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1588         .prcm           = {
1589                 .omap2 = {
1590                         .prcm_reg_id = 1,
1591                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1592                         .module_offs = OMAP3430_PER_MOD,
1593                         .idlest_reg_id = 1,
1594                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1595                 },
1596         },
1597         .slaves         = omap3xxx_gpio5_slaves,
1598         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
1599         .class          = &omap3xxx_gpio_hwmod_class,
1600         .dev_attr       = &gpio_dev_attr,
1601         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1602 };
1603
1604 /* gpio6 */
1605 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1606         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
1607 };
1608
1609 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1610         { .role = "dbclk", .clk = "gpio6_dbck", },
1611 };
1612
1613 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
1614         &omap3xxx_l4_per__gpio6,
1615 };
1616
1617 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1618         .name           = "gpio6",
1619         .mpu_irqs       = omap3xxx_gpio6_irqs,
1620         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio6_irqs),
1621         .main_clk       = "gpio6_ick",
1622         .opt_clks       = gpio6_opt_clks,
1623         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1624         .prcm           = {
1625                 .omap2 = {
1626                         .prcm_reg_id = 1,
1627                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1628                         .module_offs = OMAP3430_PER_MOD,
1629                         .idlest_reg_id = 1,
1630                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1631                 },
1632         },
1633         .slaves         = omap3xxx_gpio6_slaves,
1634         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
1635         .class          = &omap3xxx_gpio_hwmod_class,
1636         .dev_attr       = &gpio_dev_attr,
1637         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1638 };
1639
1640 /* dma_system -> L3 */
1641 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
1642         .master         = &omap3xxx_dma_system_hwmod,
1643         .slave          = &omap3xxx_l3_main_hwmod,
1644         .clk            = "core_l3_ick",
1645         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1646 };
1647
1648 /* dma attributes */
1649 static struct omap_dma_dev_attr dma_dev_attr = {
1650         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1651                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1652         .lch_count = 32,
1653 };
1654
1655 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1656         .rev_offs       = 0x0000,
1657         .sysc_offs      = 0x002c,
1658         .syss_offs      = 0x0028,
1659         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1660                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1661                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
1662         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1663                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1664         .sysc_fields    = &omap_hwmod_sysc_type1,
1665 };
1666
1667 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1668         .name = "dma",
1669         .sysc = &omap3xxx_dma_sysc,
1670 };
1671
1672 /* dma_system */
1673 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
1674         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1675         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1676         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1677         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1678 };
1679
1680 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
1681         {
1682                 .pa_start       = 0x48056000,
1683                 .pa_end         = 0x4a0560ff,
1684                 .flags          = ADDR_TYPE_RT
1685         },
1686 };
1687
1688 /* dma_system master ports */
1689 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
1690         &omap3xxx_dma_system__l3,
1691 };
1692
1693 /* l4_cfg -> dma_system */
1694 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
1695         .master         = &omap3xxx_l4_core_hwmod,
1696         .slave          = &omap3xxx_dma_system_hwmod,
1697         .clk            = "core_l4_ick",
1698         .addr           = omap3xxx_dma_system_addrs,
1699         .addr_cnt       = ARRAY_SIZE(omap3xxx_dma_system_addrs),
1700         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1701 };
1702
1703 /* dma_system slave ports */
1704 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
1705         &omap3xxx_l4_core__dma_system,
1706 };
1707
1708 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1709         .name           = "dma",
1710         .class          = &omap3xxx_dma_hwmod_class,
1711         .mpu_irqs       = omap3xxx_dma_system_irqs,
1712         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dma_system_irqs),
1713         .main_clk       = "core_l3_ick",
1714         .prcm = {
1715                 .omap2 = {
1716                         .module_offs            = CORE_MOD,
1717                         .prcm_reg_id            = 1,
1718                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1719                         .idlest_reg_id          = 1,
1720                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1721                 },
1722         },
1723         .slaves         = omap3xxx_dma_system_slaves,
1724         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
1725         .masters        = omap3xxx_dma_system_masters,
1726         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
1727         .dev_attr       = &dma_dev_attr,
1728         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1729         .flags          = HWMOD_NO_IDLEST,
1730 };
1731
1732 /* SR common */
1733 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1734         .clkact_shift   = 20,
1735 };
1736
1737 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1738         .sysc_offs      = 0x24,
1739         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1740         .clockact       = CLOCKACT_TEST_ICLK,
1741         .sysc_fields    = &omap34xx_sr_sysc_fields,
1742 };
1743
1744 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1745         .name = "smartreflex",
1746         .sysc = &omap34xx_sr_sysc,
1747         .rev  = 1,
1748 };
1749
1750 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1751         .sidle_shift    = 24,
1752         .enwkup_shift   = 26
1753 };
1754
1755 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1756         .sysc_offs      = 0x38,
1757         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1758         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1759                         SYSC_NO_CACHE),
1760         .sysc_fields    = &omap36xx_sr_sysc_fields,
1761 };
1762
1763 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1764         .name = "smartreflex",
1765         .sysc = &omap36xx_sr_sysc,
1766         .rev  = 2,
1767 };
1768
1769 /* SR1 */
1770 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
1771         &omap3_l4_core__sr1,
1772 };
1773
1774 static struct omap_hwmod omap34xx_sr1_hwmod = {
1775         .name           = "sr1_hwmod",
1776         .class          = &omap34xx_smartreflex_hwmod_class,
1777         .main_clk       = "sr1_fck",
1778         .vdd_name       = "mpu",
1779         .prcm           = {
1780                 .omap2 = {
1781                         .prcm_reg_id = 1,
1782                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1783                         .module_offs = WKUP_MOD,
1784                         .idlest_reg_id = 1,
1785                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1786                 },
1787         },
1788         .slaves         = omap3_sr1_slaves,
1789         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
1790         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
1791                                         CHIP_IS_OMAP3430ES3_0 |
1792                                         CHIP_IS_OMAP3430ES3_1),
1793         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1794 };
1795
1796 static struct omap_hwmod omap36xx_sr1_hwmod = {
1797         .name           = "sr1_hwmod",
1798         .class          = &omap36xx_smartreflex_hwmod_class,
1799         .main_clk       = "sr1_fck",
1800         .vdd_name       = "mpu",
1801         .prcm           = {
1802                 .omap2 = {
1803                         .prcm_reg_id = 1,
1804                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1805                         .module_offs = WKUP_MOD,
1806                         .idlest_reg_id = 1,
1807                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1808                 },
1809         },
1810         .slaves         = omap3_sr1_slaves,
1811         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
1812         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1813 };
1814
1815 /* SR2 */
1816 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
1817         &omap3_l4_core__sr2,
1818 };
1819
1820 static struct omap_hwmod omap34xx_sr2_hwmod = {
1821         .name           = "sr2_hwmod",
1822         .class          = &omap34xx_smartreflex_hwmod_class,
1823         .main_clk       = "sr2_fck",
1824         .vdd_name       = "core",
1825         .prcm           = {
1826                 .omap2 = {
1827                         .prcm_reg_id = 1,
1828                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1829                         .module_offs = WKUP_MOD,
1830                         .idlest_reg_id = 1,
1831                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1832                 },
1833         },
1834         .slaves         = omap3_sr2_slaves,
1835         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
1836         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
1837                                         CHIP_IS_OMAP3430ES3_0 |
1838                                         CHIP_IS_OMAP3430ES3_1),
1839         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1840 };
1841
1842 static struct omap_hwmod omap36xx_sr2_hwmod = {
1843         .name           = "sr2_hwmod",
1844         .class          = &omap36xx_smartreflex_hwmod_class,
1845         .main_clk       = "sr2_fck",
1846         .vdd_name       = "core",
1847         .prcm           = {
1848                 .omap2 = {
1849                         .prcm_reg_id = 1,
1850                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1851                         .module_offs = WKUP_MOD,
1852                         .idlest_reg_id = 1,
1853                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1854                 },
1855         },
1856         .slaves         = omap3_sr2_slaves,
1857         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
1858         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1859 };
1860
1861 /*
1862  * 'mailbox' class
1863  * mailbox module allowing communication between the on-chip processors
1864  * using a queued mailbox-interrupt mechanism.
1865  */
1866
1867 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1868         .rev_offs       = 0x000,
1869         .sysc_offs      = 0x010,
1870         .syss_offs      = 0x014,
1871         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1872                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1873         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1874         .sysc_fields    = &omap_hwmod_sysc_type1,
1875 };
1876
1877 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1878         .name = "mailbox",
1879         .sysc = &omap3xxx_mailbox_sysc,
1880 };
1881
1882 static struct omap_hwmod omap3xxx_mailbox_hwmod;
1883 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1884         { .irq = 26 },
1885 };
1886
1887 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
1888         {
1889                 .pa_start       = 0x48094000,
1890                 .pa_end         = 0x480941ff,
1891                 .flags          = ADDR_TYPE_RT,
1892         },
1893 };
1894
1895 /* l4_core -> mailbox */
1896 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
1897         .master         = &omap3xxx_l4_core_hwmod,
1898         .slave          = &omap3xxx_mailbox_hwmod,
1899         .addr           = omap3xxx_mailbox_addrs,
1900         .addr_cnt       = ARRAY_SIZE(omap3xxx_mailbox_addrs),
1901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1902 };
1903
1904 /* mailbox slave ports */
1905 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
1906         &omap3xxx_l4_core__mailbox,
1907 };
1908
1909 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1910         .name           = "mailbox",
1911         .class          = &omap3xxx_mailbox_hwmod_class,
1912         .mpu_irqs       = omap3xxx_mailbox_irqs,
1913         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mailbox_irqs),
1914         .main_clk       = "mailboxes_ick",
1915         .prcm           = {
1916                 .omap2 = {
1917                         .prcm_reg_id = 1,
1918                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1919                         .module_offs = CORE_MOD,
1920                         .idlest_reg_id = 1,
1921                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1922                 },
1923         },
1924         .slaves         = omap3xxx_mailbox_slaves,
1925         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
1926         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1927 };
1928
1929 /* l4 core -> mcspi1 interface */
1930 static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
1931         {
1932                 .pa_start       = 0x48098000,
1933                 .pa_end         = 0x480980ff,
1934                 .flags          = ADDR_TYPE_RT,
1935         },
1936 };
1937
1938 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
1939         .master         = &omap3xxx_l4_core_hwmod,
1940         .slave          = &omap34xx_mcspi1,
1941         .clk            = "mcspi1_ick",
1942         .addr           = omap34xx_mcspi1_addr_space,
1943         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
1944         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1945 };
1946
1947 /* l4 core -> mcspi2 interface */
1948 static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
1949         {
1950                 .pa_start       = 0x4809a000,
1951                 .pa_end         = 0x4809a0ff,
1952                 .flags          = ADDR_TYPE_RT,
1953         },
1954 };
1955
1956 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
1957         .master         = &omap3xxx_l4_core_hwmod,
1958         .slave          = &omap34xx_mcspi2,
1959         .clk            = "mcspi2_ick",
1960         .addr           = omap34xx_mcspi2_addr_space,
1961         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
1962         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1963 };
1964
1965 /* l4 core -> mcspi3 interface */
1966 static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
1967         {
1968                 .pa_start       = 0x480b8000,
1969                 .pa_end         = 0x480b80ff,
1970                 .flags          = ADDR_TYPE_RT,
1971         },
1972 };
1973
1974 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
1975         .master         = &omap3xxx_l4_core_hwmod,
1976         .slave          = &omap34xx_mcspi3,
1977         .clk            = "mcspi3_ick",
1978         .addr           = omap34xx_mcspi3_addr_space,
1979         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
1980         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1981 };
1982
1983 /* l4 core -> mcspi4 interface */
1984 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
1985         {
1986                 .pa_start       = 0x480ba000,
1987                 .pa_end         = 0x480ba0ff,
1988                 .flags          = ADDR_TYPE_RT,
1989         },
1990 };
1991
1992 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
1993         .master         = &omap3xxx_l4_core_hwmod,
1994         .slave          = &omap34xx_mcspi4,
1995         .clk            = "mcspi4_ick",
1996         .addr           = omap34xx_mcspi4_addr_space,
1997         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
1998         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1999 };
2000
2001 /*
2002  * 'mcspi' class
2003  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2004  * bus
2005  */
2006
2007 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2008         .rev_offs       = 0x0000,
2009         .sysc_offs      = 0x0010,
2010         .syss_offs      = 0x0014,
2011         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2012                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2013                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2014         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2015         .sysc_fields    = &omap_hwmod_sysc_type1,
2016 };
2017
2018 static struct omap_hwmod_class omap34xx_mcspi_class = {
2019         .name = "mcspi",
2020         .sysc = &omap34xx_mcspi_sysc,
2021         .rev = OMAP3_MCSPI_REV,
2022 };
2023
2024 /* mcspi1 */
2025 static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
2026         { .name = "irq", .irq = 65 },
2027 };
2028
2029 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
2030         { .name = "tx0", .dma_req = 35 },
2031         { .name = "rx0", .dma_req = 36 },
2032         { .name = "tx1", .dma_req = 37 },
2033         { .name = "rx1", .dma_req = 38 },
2034         { .name = "tx2", .dma_req = 39 },
2035         { .name = "rx2", .dma_req = 40 },
2036         { .name = "tx3", .dma_req = 41 },
2037         { .name = "rx3", .dma_req = 42 },
2038 };
2039
2040 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2041         &omap34xx_l4_core__mcspi1,
2042 };
2043
2044 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2045         .num_chipselect = 4,
2046 };
2047
2048 static struct omap_hwmod omap34xx_mcspi1 = {
2049         .name           = "mcspi1",
2050         .mpu_irqs       = omap34xx_mcspi1_mpu_irqs,
2051         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
2052         .sdma_reqs      = omap34xx_mcspi1_sdma_reqs,
2053         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
2054         .main_clk       = "mcspi1_fck",
2055         .prcm           = {
2056                 .omap2 = {
2057                         .module_offs = CORE_MOD,
2058                         .prcm_reg_id = 1,
2059                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2060                         .idlest_reg_id = 1,
2061                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2062                 },
2063         },
2064         .slaves         = omap34xx_mcspi1_slaves,
2065         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2066         .class          = &omap34xx_mcspi_class,
2067         .dev_attr       = &omap_mcspi1_dev_attr,
2068         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2069 };
2070
2071 /* mcspi2 */
2072 static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
2073         { .name = "irq", .irq = 66 },
2074 };
2075
2076 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
2077         { .name = "tx0", .dma_req = 43 },
2078         { .name = "rx0", .dma_req = 44 },
2079         { .name = "tx1", .dma_req = 45 },
2080         { .name = "rx1", .dma_req = 46 },
2081 };
2082
2083 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2084         &omap34xx_l4_core__mcspi2,
2085 };
2086
2087 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2088         .num_chipselect = 2,
2089 };
2090
2091 static struct omap_hwmod omap34xx_mcspi2 = {
2092         .name           = "mcspi2",
2093         .mpu_irqs       = omap34xx_mcspi2_mpu_irqs,
2094         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
2095         .sdma_reqs      = omap34xx_mcspi2_sdma_reqs,
2096         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
2097         .main_clk       = "mcspi2_fck",
2098         .prcm           = {
2099                 .omap2 = {
2100                         .module_offs = CORE_MOD,
2101                         .prcm_reg_id = 1,
2102                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2103                         .idlest_reg_id = 1,
2104                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2105                 },
2106         },
2107         .slaves         = omap34xx_mcspi2_slaves,
2108         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2109         .class          = &omap34xx_mcspi_class,
2110         .dev_attr       = &omap_mcspi2_dev_attr,
2111         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2112 };
2113
2114 /* mcspi3 */
2115 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2116         { .name = "irq", .irq = 91 }, /* 91 */
2117 };
2118
2119 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2120         { .name = "tx0", .dma_req = 15 },
2121         { .name = "rx0", .dma_req = 16 },
2122         { .name = "tx1", .dma_req = 23 },
2123         { .name = "rx1", .dma_req = 24 },
2124 };
2125
2126 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2127         &omap34xx_l4_core__mcspi3,
2128 };
2129
2130 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2131         .num_chipselect = 2,
2132 };
2133
2134 static struct omap_hwmod omap34xx_mcspi3 = {
2135         .name           = "mcspi3",
2136         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
2137         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
2138         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
2139         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
2140         .main_clk       = "mcspi3_fck",
2141         .prcm           = {
2142                 .omap2 = {
2143                         .module_offs = CORE_MOD,
2144                         .prcm_reg_id = 1,
2145                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2146                         .idlest_reg_id = 1,
2147                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2148                 },
2149         },
2150         .slaves         = omap34xx_mcspi3_slaves,
2151         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2152         .class          = &omap34xx_mcspi_class,
2153         .dev_attr       = &omap_mcspi3_dev_attr,
2154         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2155 };
2156
2157 /* SPI4 */
2158 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2159         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2160 };
2161
2162 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2163         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2164         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2165 };
2166
2167 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2168         &omap34xx_l4_core__mcspi4,
2169 };
2170
2171 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2172         .num_chipselect = 1,
2173 };
2174
2175 static struct omap_hwmod omap34xx_mcspi4 = {
2176         .name           = "mcspi4",
2177         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
2178         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
2179         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
2180         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
2181         .main_clk       = "mcspi4_fck",
2182         .prcm           = {
2183                 .omap2 = {
2184                         .module_offs = CORE_MOD,
2185                         .prcm_reg_id = 1,
2186                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2187                         .idlest_reg_id = 1,
2188                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2189                 },
2190         },
2191         .slaves         = omap34xx_mcspi4_slaves,
2192         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2193         .class          = &omap34xx_mcspi_class,
2194         .dev_attr       = &omap_mcspi4_dev_attr,
2195         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2196 };
2197
2198 /*
2199  * usbhsotg
2200  */
2201 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2202         .rev_offs       = 0x0400,
2203         .sysc_offs      = 0x0404,
2204         .syss_offs      = 0x0408,
2205         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2206                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2207                           SYSC_HAS_AUTOIDLE),
2208         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2209                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2210         .sysc_fields    = &omap_hwmod_sysc_type1,
2211 };
2212
2213 static struct omap_hwmod_class usbotg_class = {
2214         .name = "usbotg",
2215         .sysc = &omap3xxx_usbhsotg_sysc,
2216 };
2217 /* usb_otg_hs */
2218 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2219
2220         { .name = "mc", .irq = 92 },
2221         { .name = "dma", .irq = 93 },
2222 };
2223
2224 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
2225         .name           = "usb_otg_hs",
2226         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
2227         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
2228         .main_clk       = "hsotgusb_ick",
2229         .prcm           = {
2230                 .omap2 = {
2231                         .prcm_reg_id = 1,
2232                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
2233                         .module_offs = CORE_MOD,
2234                         .idlest_reg_id = 1,
2235                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
2236                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
2237                 },
2238         },
2239         .masters        = omap3xxx_usbhsotg_masters,
2240         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
2241         .slaves         = omap3xxx_usbhsotg_slaves,
2242         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
2243         .class          = &usbotg_class,
2244
2245         /*
2246          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
2247          * broken when autoidle is enabled
2248          * workaround is to disable the autoidle bit at module level.
2249          */
2250         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
2251                                 | HWMOD_SWSUP_MSTANDBY,
2252         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
2253 };
2254
2255 /* usb_otg_hs */
2256 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
2257
2258         { .name = "mc", .irq = 71 },
2259 };
2260
2261 static struct omap_hwmod_class am35xx_usbotg_class = {
2262         .name = "am35xx_usbotg",
2263         .sysc = NULL,
2264 };
2265
2266 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
2267         .name           = "am35x_otg_hs",
2268         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
2269         .mpu_irqs_cnt   = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
2270         .main_clk       = NULL,
2271         .prcm = {
2272                 .omap2 = {
2273                 },
2274         },
2275         .masters        = am35xx_usbhsotg_masters,
2276         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
2277         .slaves         = am35xx_usbhsotg_slaves,
2278         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
2279         .class          = &am35xx_usbotg_class,
2280         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
2281 };
2282
2283 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
2284         &omap3xxx_l3_main_hwmod,
2285         &omap3xxx_l4_core_hwmod,
2286         &omap3xxx_l4_per_hwmod,
2287         &omap3xxx_l4_wkup_hwmod,
2288         &omap3xxx_mpu_hwmod,
2289         &omap3xxx_iva_hwmod,
2290         &omap3xxx_wd_timer2_hwmod,
2291         &omap3xxx_uart1_hwmod,
2292         &omap3xxx_uart2_hwmod,
2293         &omap3xxx_uart3_hwmod,
2294         &omap3xxx_uart4_hwmod,
2295         /* dss class */
2296         &omap3430es1_dss_core_hwmod,
2297         &omap3xxx_dss_core_hwmod,
2298         &omap3xxx_dss_dispc_hwmod,
2299         &omap3xxx_dss_dsi1_hwmod,
2300         &omap3xxx_dss_rfbi_hwmod,
2301         &omap3xxx_dss_venc_hwmod,
2302
2303         /* i2c class */
2304         &omap3xxx_i2c1_hwmod,
2305         &omap3xxx_i2c2_hwmod,
2306         &omap3xxx_i2c3_hwmod,
2307         &omap34xx_sr1_hwmod,
2308         &omap34xx_sr2_hwmod,
2309         &omap36xx_sr1_hwmod,
2310         &omap36xx_sr2_hwmod,
2311
2312
2313         /* gpio class */
2314         &omap3xxx_gpio1_hwmod,
2315         &omap3xxx_gpio2_hwmod,
2316         &omap3xxx_gpio3_hwmod,
2317         &omap3xxx_gpio4_hwmod,
2318         &omap3xxx_gpio5_hwmod,
2319         &omap3xxx_gpio6_hwmod,
2320
2321         /* dma_system class*/
2322         &omap3xxx_dma_system_hwmod,
2323
2324         /* mailbox class */
2325         &omap3xxx_mailbox_hwmod,
2326
2327         /* mcspi class */
2328         &omap34xx_mcspi1,
2329         &omap34xx_mcspi2,
2330         &omap34xx_mcspi3,
2331         &omap34xx_mcspi4,
2332
2333         /* usbotg class */
2334         &omap3xxx_usbhsotg_hwmod,
2335
2336         /* usbotg for am35x */
2337         &am35xx_usbhsotg_hwmod,
2338
2339         NULL,
2340 };
2341
2342 int __init omap3xxx_hwmod_init(void)
2343 {
2344         return omap_hwmod_init(omap3xxx_hwmods);
2345 }