arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "prm-regbits-34xx.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "wd_timer.h"
  35 #include <mach/am35xx.h>
  36
  37 /*
  38  * OMAP3xxx hardware module integration data
  39  *
  40  * ALl of the data in this section should be autogeneratable from the
  41  * TI hardware database or other technical documentation.  Data that
  42  * is driver-specific or driver-kernel integration-specific belongs
  43  * elsewhere.
  44  */
  45
  46 static struct omap_hwmod omap3xxx_mpu_hwmod;
  47 static struct omap_hwmod omap3xxx_iva_hwmod;
  48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  67 static struct omap_hwmod omap34xx_sr1_hwmod;
  68 static struct omap_hwmod omap34xx_sr2_hwmod;
  69 static struct omap_hwmod omap34xx_mcspi1;
  70 static struct omap_hwmod omap34xx_mcspi2;
  71 static struct omap_hwmod omap34xx_mcspi3;
  72 static struct omap_hwmod omap34xx_mcspi4;
  73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  77
  78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  79
  80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  87
  88 /* L3 -> L4_CORE interface */
  89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  90         .master = &omap3xxx_l3_main_hwmod,
  91         .slave  = &omap3xxx_l4_core_hwmod,
  92         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  93 };
  94
  95 /* L3 -> L4_PER interface */
  96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  97         .master = &omap3xxx_l3_main_hwmod,
  98         .slave  = &omap3xxx_l4_per_hwmod,
  99         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 100 };
 101
 102 /* L3 taret configuration and error log registers */
 103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 104         { .irq = INT_34XX_L3_DBG_IRQ },
 105         { .irq = INT_34XX_L3_APP_IRQ },
 106         { .irq = -1 }
 107 };
 108
 109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 110         {
 111                 .pa_start       = 0x68000000,
 112                 .pa_end         = 0x6800ffff,
 113                 .flags          = ADDR_TYPE_RT,
 114         },
 115         { }
 116 };
 117
 118 /* MPU -> L3 interface */
 119 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 120         .master   = &omap3xxx_mpu_hwmod,
 121         .slave    = &omap3xxx_l3_main_hwmod,
 122         .addr     = omap3xxx_l3_main_addrs,
 123         .user   = OCP_USER_MPU,
 124 };
 125
 126 /* Slave interfaces on the L3 interconnect */
 127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 128         &omap3xxx_mpu__l3_main,
 129 };
 130
 131 /* DSS -> l3 */
 132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 133         .master         = &omap3xxx_dss_core_hwmod,
 134         .slave          = &omap3xxx_l3_main_hwmod,
 135         .fw = {
 136                 .omap2 = {
 137                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 138                         .flags  = OMAP_FIREWALL_L3,
 139                 }
 140         },
 141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 142 };
 143
 144 /* Master interfaces on the L3 interconnect */
 145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 146         &omap3xxx_l3_main__l4_core,
 147         &omap3xxx_l3_main__l4_per,
 148 };
 149
 150 /* L3 */
 151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 152         .name           = "l3_main",
 153         .class          = &l3_hwmod_class,
 154         .mpu_irqs       = omap3xxx_l3_main_irqs,
 155         .masters        = omap3xxx_l3_main_masters,
 156         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 157         .slaves         = omap3xxx_l3_main_slaves,
 158         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 159         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 160         .flags          = HWMOD_NO_IDLEST,
 161 };
 162
 163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 164 static struct omap_hwmod omap3xxx_uart1_hwmod;
 165 static struct omap_hwmod omap3xxx_uart2_hwmod;
 166 static struct omap_hwmod omap3xxx_uart3_hwmod;
 167 static struct omap_hwmod omap3xxx_uart4_hwmod;
 168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 169
 170 /* l3_core -> usbhsotg interface */
 171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 172         .master         = &omap3xxx_usbhsotg_hwmod,
 173         .slave          = &omap3xxx_l3_main_hwmod,
 174         .clk            = "core_l3_ick",
 175         .user           = OCP_USER_MPU,
 176 };
 177
 178 /* l3_core -> am35xx_usbhsotg interface */
 179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 180         .master         = &am35xx_usbhsotg_hwmod,
 181         .slave          = &omap3xxx_l3_main_hwmod,
 182         .clk            = "core_l3_ick",
 183         .user           = OCP_USER_MPU,
 184 };
 185 /* L4_CORE -> L4_WKUP interface */
 186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 187         .master = &omap3xxx_l4_core_hwmod,
 188         .slave  = &omap3xxx_l4_wkup_hwmod,
 189         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 190 };
 191
 192 /* L4 CORE -> MMC1 interface */
 193 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 194         .master         = &omap3xxx_l4_core_hwmod,
 195         .slave          = &omap3xxx_mmc1_hwmod,
 196         .clk            = "mmchs1_ick",
 197         .addr           = omap2430_mmc1_addr_space,
 198         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 199         .flags          = OMAP_FIREWALL_L4
 200 };
 201
 202 /* L4 CORE -> MMC2 interface */
 203 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 204         .master         = &omap3xxx_l4_core_hwmod,
 205         .slave          = &omap3xxx_mmc2_hwmod,
 206         .clk            = "mmchs2_ick",
 207         .addr           = omap2430_mmc2_addr_space,
 208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 209         .flags          = OMAP_FIREWALL_L4
 210 };
 211
 212 /* L4 CORE -> MMC3 interface */
 213 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 214         {
 215                 .pa_start       = 0x480ad000,
 216                 .pa_end         = 0x480ad1ff,
 217                 .flags          = ADDR_TYPE_RT,
 218         },
 219         { }
 220 };
 221
 222 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 223         .master         = &omap3xxx_l4_core_hwmod,
 224         .slave          = &omap3xxx_mmc3_hwmod,
 225         .clk            = "mmchs3_ick",
 226         .addr           = omap3xxx_mmc3_addr_space,
 227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 228         .flags          = OMAP_FIREWALL_L4
 229 };
 230
 231 /* L4 CORE -> UART1 interface */
 232 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 233         {
 234                 .pa_start       = OMAP3_UART1_BASE,
 235                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 236                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 237         },
 238         { }
 239 };
 240
 241 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 242         .master         = &omap3xxx_l4_core_hwmod,
 243         .slave          = &omap3xxx_uart1_hwmod,
 244         .clk            = "uart1_ick",
 245         .addr           = omap3xxx_uart1_addr_space,
 246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 247 };
 248
 249 /* L4 CORE -> UART2 interface */
 250 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 251         {
 252                 .pa_start       = OMAP3_UART2_BASE,
 253                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 254                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 255         },
 256         { }
 257 };
 258
 259 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 260         .master         = &omap3xxx_l4_core_hwmod,
 261         .slave          = &omap3xxx_uart2_hwmod,
 262         .clk            = "uart2_ick",
 263         .addr           = omap3xxx_uart2_addr_space,
 264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 265 };
 266
 267 /* L4 PER -> UART3 interface */
 268 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 269         {
 270                 .pa_start       = OMAP3_UART3_BASE,
 271                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 272                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 273         },
 274         { }
 275 };
 276
 277 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 278         .master         = &omap3xxx_l4_per_hwmod,
 279         .slave          = &omap3xxx_uart3_hwmod,
 280         .clk            = "uart3_ick",
 281         .addr           = omap3xxx_uart3_addr_space,
 282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 283 };
 284
 285 /* L4 PER -> UART4 interface */
 286 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 287         {
 288                 .pa_start       = OMAP3_UART4_BASE,
 289                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 290                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 291         },
 292         { }
 293 };
 294
 295 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 296         .master         = &omap3xxx_l4_per_hwmod,
 297         .slave          = &omap3xxx_uart4_hwmod,
 298         .clk            = "uart4_ick",
 299         .addr           = omap3xxx_uart4_addr_space,
 300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 301 };
 302
 303 /* L4 CORE -> I2C1 interface */
 304 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 305         .master         = &omap3xxx_l4_core_hwmod,
 306         .slave          = &omap3xxx_i2c1_hwmod,
 307         .clk            = "i2c1_ick",
 308         .addr           = omap2_i2c1_addr_space,
 309         .fw = {
 310                 .omap2 = {
 311                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 312                         .l4_prot_group = 7,
 313                         .flags  = OMAP_FIREWALL_L4,
 314                 }
 315         },
 316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 317 };
 318
 319 /* L4 CORE -> I2C2 interface */
 320 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 321         .master         = &omap3xxx_l4_core_hwmod,
 322         .slave          = &omap3xxx_i2c2_hwmod,
 323         .clk            = "i2c2_ick",
 324         .addr           = omap2_i2c2_addr_space,
 325         .fw = {
 326                 .omap2 = {
 327                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 328                         .l4_prot_group = 7,
 329                         .flags = OMAP_FIREWALL_L4,
 330                 }
 331         },
 332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 333 };
 334
 335 /* L4 CORE -> I2C3 interface */
 336 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 337         {
 338                 .pa_start       = 0x48060000,
 339                 .pa_end         = 0x48060000 + SZ_128 - 1,
 340                 .flags          = ADDR_TYPE_RT,
 341         },
 342         { }
 343 };
 344
 345 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 346         .master         = &omap3xxx_l4_core_hwmod,
 347         .slave          = &omap3xxx_i2c3_hwmod,
 348         .clk            = "i2c3_ick",
 349         .addr           = omap3xxx_i2c3_addr_space,
 350         .fw = {
 351                 .omap2 = {
 352                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 353                         .l4_prot_group = 7,
 354                         .flags = OMAP_FIREWALL_L4,
 355                 }
 356         },
 357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 358 };
 359
 360 /* L4 CORE -> SR1 interface */
 361 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 362         {
 363                 .pa_start       = OMAP34XX_SR1_BASE,
 364                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 365                 .flags          = ADDR_TYPE_RT,
 366         },
 367         { }
 368 };
 369
 370 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 371         .master         = &omap3xxx_l4_core_hwmod,
 372         .slave          = &omap34xx_sr1_hwmod,
 373         .clk            = "sr_l4_ick",
 374         .addr           = omap3_sr1_addr_space,
 375         .user           = OCP_USER_MPU,
 376 };
 377
 378 /* L4 CORE -> SR1 interface */
 379 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 380         {
 381                 .pa_start       = OMAP34XX_SR2_BASE,
 382                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 383                 .flags          = ADDR_TYPE_RT,
 384         },
 385         { }
 386 };
 387
 388 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 389         .master         = &omap3xxx_l4_core_hwmod,
 390         .slave          = &omap34xx_sr2_hwmod,
 391         .clk            = "sr_l4_ick",
 392         .addr           = omap3_sr2_addr_space,
 393         .user           = OCP_USER_MPU,
 394 };
 395
 396 /*
 397 * usbhsotg interface data
 398 */
 399
 400 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 401         {
 402                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 403                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 404                 .flags          = ADDR_TYPE_RT
 405         },
 406         { }
 407 };
 408
 409 /* l4_core -> usbhsotg  */
 410 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 411         .master         = &omap3xxx_l4_core_hwmod,
 412         .slave          = &omap3xxx_usbhsotg_hwmod,
 413         .clk            = "l4_ick",
 414         .addr           = omap3xxx_usbhsotg_addrs,
 415         .user           = OCP_USER_MPU,
 416 };
 417
 418 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 419         &omap3xxx_usbhsotg__l3,
 420 };
 421
 422 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 423         &omap3xxx_l4_core__usbhsotg,
 424 };
 425
 426 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 427         {
 428                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 429                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 430                 .flags          = ADDR_TYPE_RT
 431         },
 432         { }
 433 };
 434
 435 /* l4_core -> usbhsotg  */
 436 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 437         .master         = &omap3xxx_l4_core_hwmod,
 438         .slave          = &am35xx_usbhsotg_hwmod,
 439         .clk            = "l4_ick",
 440         .addr           = am35xx_usbhsotg_addrs,
 441         .user           = OCP_USER_MPU,
 442 };
 443
 444 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 445         &am35xx_usbhsotg__l3,
 446 };
 447
 448 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 449         &am35xx_l4_core__usbhsotg,
 450 };
 451 /* Slave interfaces on the L4_CORE interconnect */
 452 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 453         &omap3xxx_l3_main__l4_core,
 454 };
 455
 456 /* L4 CORE */
 457 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 458         .name           = "l4_core",
 459         .class          = &l4_hwmod_class,
 460         .slaves         = omap3xxx_l4_core_slaves,
 461         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 462         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 463         .flags          = HWMOD_NO_IDLEST,
 464 };
 465
 466 /* Slave interfaces on the L4_PER interconnect */
 467 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 468         &omap3xxx_l3_main__l4_per,
 469 };
 470
 471 /* L4 PER */
 472 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 473         .name           = "l4_per",
 474         .class          = &l4_hwmod_class,
 475         .slaves         = omap3xxx_l4_per_slaves,
 476         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 477         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 478         .flags          = HWMOD_NO_IDLEST,
 479 };
 480
 481 /* Slave interfaces on the L4_WKUP interconnect */
 482 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 483         &omap3xxx_l4_core__l4_wkup,
 484 };
 485
 486 /* L4 WKUP */
 487 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 488         .name           = "l4_wkup",
 489         .class          = &l4_hwmod_class,
 490         .slaves         = omap3xxx_l4_wkup_slaves,
 491         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 492         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 493         .flags          = HWMOD_NO_IDLEST,
 494 };
 495
 496 /* Master interfaces on the MPU device */
 497 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 498         &omap3xxx_mpu__l3_main,
 499 };
 500
 501 /* MPU */
 502 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 503         .name           = "mpu",
 504         .class          = &mpu_hwmod_class,
 505         .main_clk       = "arm_fck",
 506         .masters        = omap3xxx_mpu_masters,
 507         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 508         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 509 };
 510
 511 /*
 512  * IVA2_2 interface data
 513  */
 514
 515 /* IVA2 <- L3 interface */
 516 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 517         .master         = &omap3xxx_l3_main_hwmod,
 518         .slave          = &omap3xxx_iva_hwmod,
 519         .clk            = "iva2_ck",
 520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 521 };
 522
 523 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 524         &omap3xxx_l3__iva,
 525 };
 526
 527 /*
 528  * IVA2 (IVA2)
 529  */
 530
 531 static struct omap_hwmod omap3xxx_iva_hwmod = {
 532         .name           = "iva",
 533         .class          = &iva_hwmod_class,
 534         .masters        = omap3xxx_iva_masters,
 535         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 536         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 537 };
 538
 539 /* timer class */
 540 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 541         .rev_offs       = 0x0000,
 542         .sysc_offs      = 0x0010,
 543         .syss_offs      = 0x0014,
 544         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 545                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 546                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 547         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 548         .sysc_fields    = &omap_hwmod_sysc_type1,
 549 };
 550
 551 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 552         .name = "timer",
 553         .sysc = &omap3xxx_timer_1ms_sysc,
 554         .rev = OMAP_TIMER_IP_VERSION_1,
 555 };
 556
 557 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 558         .rev_offs       = 0x0000,
 559         .sysc_offs      = 0x0010,
 560         .syss_offs      = 0x0014,
 561         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 562                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 563         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 564         .sysc_fields    = &omap_hwmod_sysc_type1,
 565 };
 566
 567 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 568         .name = "timer",
 569         .sysc = &omap3xxx_timer_sysc,
 570         .rev =  OMAP_TIMER_IP_VERSION_1,
 571 };
 572
 573 /* timer1 */
 574 static struct omap_hwmod omap3xxx_timer1_hwmod;
 575
 576 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 577         {
 578                 .pa_start       = 0x48318000,
 579                 .pa_end         = 0x48318000 + SZ_1K - 1,
 580                 .flags          = ADDR_TYPE_RT
 581         },
 582         { }
 583 };
 584
 585 /* l4_wkup -> timer1 */
 586 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 587         .master         = &omap3xxx_l4_wkup_hwmod,
 588         .slave          = &omap3xxx_timer1_hwmod,
 589         .clk            = "gpt1_ick",
 590         .addr           = omap3xxx_timer1_addrs,
 591         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 592 };
 593
 594 /* timer1 slave port */
 595 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 596         &omap3xxx_l4_wkup__timer1,
 597 };
 598
 599 /* timer1 hwmod */
 600 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 601         .name           = "timer1",
 602         .mpu_irqs       = omap2_timer1_mpu_irqs,
 603         .main_clk       = "gpt1_fck",
 604         .prcm           = {
 605                 .omap2 = {
 606                         .prcm_reg_id = 1,
 607                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 608                         .module_offs = WKUP_MOD,
 609                         .idlest_reg_id = 1,
 610                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 611                 },
 612         },
 613         .slaves         = omap3xxx_timer1_slaves,
 614         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 615         .class          = &omap3xxx_timer_1ms_hwmod_class,
 616         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 617 };
 618
 619 /* timer2 */
 620 static struct omap_hwmod omap3xxx_timer2_hwmod;
 621
 622 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 623         {
 624                 .pa_start       = 0x49032000,
 625                 .pa_end         = 0x49032000 + SZ_1K - 1,
 626                 .flags          = ADDR_TYPE_RT
 627         },
 628         { }
 629 };
 630
 631 /* l4_per -> timer2 */
 632 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 633         .master         = &omap3xxx_l4_per_hwmod,
 634         .slave          = &omap3xxx_timer2_hwmod,
 635         .clk            = "gpt2_ick",
 636         .addr           = omap3xxx_timer2_addrs,
 637         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 638 };
 639
 640 /* timer2 slave port */
 641 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 642         &omap3xxx_l4_per__timer2,
 643 };
 644
 645 /* timer2 hwmod */
 646 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 647         .name           = "timer2",
 648         .mpu_irqs       = omap2_timer2_mpu_irqs,
 649         .main_clk       = "gpt2_fck",
 650         .prcm           = {
 651                 .omap2 = {
 652                         .prcm_reg_id = 1,
 653                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 654                         .module_offs = OMAP3430_PER_MOD,
 655                         .idlest_reg_id = 1,
 656                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 657                 },
 658         },
 659         .slaves         = omap3xxx_timer2_slaves,
 660         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 661         .class          = &omap3xxx_timer_1ms_hwmod_class,
 662         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 663 };
 664
 665 /* timer3 */
 666 static struct omap_hwmod omap3xxx_timer3_hwmod;
 667
 668 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 669         {
 670                 .pa_start       = 0x49034000,
 671                 .pa_end         = 0x49034000 + SZ_1K - 1,
 672                 .flags          = ADDR_TYPE_RT
 673         },
 674         { }
 675 };
 676
 677 /* l4_per -> timer3 */
 678 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 679         .master         = &omap3xxx_l4_per_hwmod,
 680         .slave          = &omap3xxx_timer3_hwmod,
 681         .clk            = "gpt3_ick",
 682         .addr           = omap3xxx_timer3_addrs,
 683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 684 };
 685
 686 /* timer3 slave port */
 687 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 688         &omap3xxx_l4_per__timer3,
 689 };
 690
 691 /* timer3 hwmod */
 692 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 693         .name           = "timer3",
 694         .mpu_irqs       = omap2_timer3_mpu_irqs,
 695         .main_clk       = "gpt3_fck",
 696         .prcm           = {
 697                 .omap2 = {
 698                         .prcm_reg_id = 1,
 699                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 700                         .module_offs = OMAP3430_PER_MOD,
 701                         .idlest_reg_id = 1,
 702                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 703                 },
 704         },
 705         .slaves         = omap3xxx_timer3_slaves,
 706         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 707         .class          = &omap3xxx_timer_hwmod_class,
 708         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 709 };
 710
 711 /* timer4 */
 712 static struct omap_hwmod omap3xxx_timer4_hwmod;
 713
 714 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 715         {
 716                 .pa_start       = 0x49036000,
 717                 .pa_end         = 0x49036000 + SZ_1K - 1,
 718                 .flags          = ADDR_TYPE_RT
 719         },
 720         { }
 721 };
 722
 723 /* l4_per -> timer4 */
 724 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 725         .master         = &omap3xxx_l4_per_hwmod,
 726         .slave          = &omap3xxx_timer4_hwmod,
 727         .clk            = "gpt4_ick",
 728         .addr           = omap3xxx_timer4_addrs,
 729         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 730 };
 731
 732 /* timer4 slave port */
 733 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 734         &omap3xxx_l4_per__timer4,
 735 };
 736
 737 /* timer4 hwmod */
 738 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 739         .name           = "timer4",
 740         .mpu_irqs       = omap2_timer4_mpu_irqs,
 741         .main_clk       = "gpt4_fck",
 742         .prcm           = {
 743                 .omap2 = {
 744                         .prcm_reg_id = 1,
 745                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 746                         .module_offs = OMAP3430_PER_MOD,
 747                         .idlest_reg_id = 1,
 748                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 749                 },
 750         },
 751         .slaves         = omap3xxx_timer4_slaves,
 752         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 753         .class          = &omap3xxx_timer_hwmod_class,
 754         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 755 };
 756
 757 /* timer5 */
 758 static struct omap_hwmod omap3xxx_timer5_hwmod;
 759
 760 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 761         {
 762                 .pa_start       = 0x49038000,
 763                 .pa_end         = 0x49038000 + SZ_1K - 1,
 764                 .flags          = ADDR_TYPE_RT
 765         },
 766         { }
 767 };
 768
 769 /* l4_per -> timer5 */
 770 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 771         .master         = &omap3xxx_l4_per_hwmod,
 772         .slave          = &omap3xxx_timer5_hwmod,
 773         .clk            = "gpt5_ick",
 774         .addr           = omap3xxx_timer5_addrs,
 775         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 776 };
 777
 778 /* timer5 slave port */
 779 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 780         &omap3xxx_l4_per__timer5,
 781 };
 782
 783 /* timer5 hwmod */
 784 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 785         .name           = "timer5",
 786         .mpu_irqs       = omap2_timer5_mpu_irqs,
 787         .main_clk       = "gpt5_fck",
 788         .prcm           = {
 789                 .omap2 = {
 790                         .prcm_reg_id = 1,
 791                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 792                         .module_offs = OMAP3430_PER_MOD,
 793                         .idlest_reg_id = 1,
 794                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 795                 },
 796         },
 797         .slaves         = omap3xxx_timer5_slaves,
 798         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 799         .class          = &omap3xxx_timer_hwmod_class,
 800         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 801 };
 802
 803 /* timer6 */
 804 static struct omap_hwmod omap3xxx_timer6_hwmod;
 805
 806 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 807         {
 808                 .pa_start       = 0x4903A000,
 809                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 810                 .flags          = ADDR_TYPE_RT
 811         },
 812         { }
 813 };
 814
 815 /* l4_per -> timer6 */
 816 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 817         .master         = &omap3xxx_l4_per_hwmod,
 818         .slave          = &omap3xxx_timer6_hwmod,
 819         .clk            = "gpt6_ick",
 820         .addr           = omap3xxx_timer6_addrs,
 821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 822 };
 823
 824 /* timer6 slave port */
 825 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 826         &omap3xxx_l4_per__timer6,
 827 };
 828
 829 /* timer6 hwmod */
 830 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 831         .name           = "timer6",
 832         .mpu_irqs       = omap2_timer6_mpu_irqs,
 833         .main_clk       = "gpt6_fck",
 834         .prcm           = {
 835                 .omap2 = {
 836                         .prcm_reg_id = 1,
 837                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 838                         .module_offs = OMAP3430_PER_MOD,
 839                         .idlest_reg_id = 1,
 840                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 841                 },
 842         },
 843         .slaves         = omap3xxx_timer6_slaves,
 844         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 845         .class          = &omap3xxx_timer_hwmod_class,
 846         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 847 };
 848
 849 /* timer7 */
 850 static struct omap_hwmod omap3xxx_timer7_hwmod;
 851
 852 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 853         {
 854                 .pa_start       = 0x4903C000,
 855                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 856                 .flags          = ADDR_TYPE_RT
 857         },
 858         { }
 859 };
 860
 861 /* l4_per -> timer7 */
 862 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 863         .master         = &omap3xxx_l4_per_hwmod,
 864         .slave          = &omap3xxx_timer7_hwmod,
 865         .clk            = "gpt7_ick",
 866         .addr           = omap3xxx_timer7_addrs,
 867         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 868 };
 869
 870 /* timer7 slave port */
 871 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 872         &omap3xxx_l4_per__timer7,
 873 };
 874
 875 /* timer7 hwmod */
 876 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 877         .name           = "timer7",
 878         .mpu_irqs       = omap2_timer7_mpu_irqs,
 879         .main_clk       = "gpt7_fck",
 880         .prcm           = {
 881                 .omap2 = {
 882                         .prcm_reg_id = 1,
 883                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 884                         .module_offs = OMAP3430_PER_MOD,
 885                         .idlest_reg_id = 1,
 886                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 887                 },
 888         },
 889         .slaves         = omap3xxx_timer7_slaves,
 890         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 891         .class          = &omap3xxx_timer_hwmod_class,
 892         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 893 };
 894
 895 /* timer8 */
 896 static struct omap_hwmod omap3xxx_timer8_hwmod;
 897
 898 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 899         {
 900                 .pa_start       = 0x4903E000,
 901                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 902                 .flags          = ADDR_TYPE_RT
 903         },
 904         { }
 905 };
 906
 907 /* l4_per -> timer8 */
 908 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 909         .master         = &omap3xxx_l4_per_hwmod,
 910         .slave          = &omap3xxx_timer8_hwmod,
 911         .clk            = "gpt8_ick",
 912         .addr           = omap3xxx_timer8_addrs,
 913         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 914 };
 915
 916 /* timer8 slave port */
 917 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 918         &omap3xxx_l4_per__timer8,
 919 };
 920
 921 /* timer8 hwmod */
 922 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 923         .name           = "timer8",
 924         .mpu_irqs       = omap2_timer8_mpu_irqs,
 925         .main_clk       = "gpt8_fck",
 926         .prcm           = {
 927                 .omap2 = {
 928                         .prcm_reg_id = 1,
 929                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 930                         .module_offs = OMAP3430_PER_MOD,
 931                         .idlest_reg_id = 1,
 932                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 933                 },
 934         },
 935         .slaves         = omap3xxx_timer8_slaves,
 936         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
 937         .class          = &omap3xxx_timer_hwmod_class,
 938         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 939 };
 940
 941 /* timer9 */
 942 static struct omap_hwmod omap3xxx_timer9_hwmod;
 943
 944 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
 945         {
 946                 .pa_start       = 0x49040000,
 947                 .pa_end         = 0x49040000 + SZ_1K - 1,
 948                 .flags          = ADDR_TYPE_RT
 949         },
 950         { }
 951 };
 952
 953 /* l4_per -> timer9 */
 954 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
 955         .master         = &omap3xxx_l4_per_hwmod,
 956         .slave          = &omap3xxx_timer9_hwmod,
 957         .clk            = "gpt9_ick",
 958         .addr           = omap3xxx_timer9_addrs,
 959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 960 };
 961
 962 /* timer9 slave port */
 963 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
 964         &omap3xxx_l4_per__timer9,
 965 };
 966
 967 /* timer9 hwmod */
 968 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 969         .name           = "timer9",
 970         .mpu_irqs       = omap2_timer9_mpu_irqs,
 971         .main_clk       = "gpt9_fck",
 972         .prcm           = {
 973                 .omap2 = {
 974                         .prcm_reg_id = 1,
 975                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 976                         .module_offs = OMAP3430_PER_MOD,
 977                         .idlest_reg_id = 1,
 978                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 979                 },
 980         },
 981         .slaves         = omap3xxx_timer9_slaves,
 982         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
 983         .class          = &omap3xxx_timer_hwmod_class,
 984         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 985 };
 986
 987 /* timer10 */
 988 static struct omap_hwmod omap3xxx_timer10_hwmod;
 989
 990 /* l4_core -> timer10 */
 991 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
 992         .master         = &omap3xxx_l4_core_hwmod,
 993         .slave          = &omap3xxx_timer10_hwmod,
 994         .clk            = "gpt10_ick",
 995         .addr           = omap2_timer10_addrs,
 996         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 997 };
 998
 999 /* timer10 slave port */
1000 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1001         &omap3xxx_l4_core__timer10,
1002 };
1003
1004 /* timer10 hwmod */
1005 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1006         .name           = "timer10",
1007         .mpu_irqs       = omap2_timer10_mpu_irqs,
1008         .main_clk       = "gpt10_fck",
1009         .prcm           = {
1010                 .omap2 = {
1011                         .prcm_reg_id = 1,
1012                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1013                         .module_offs = CORE_MOD,
1014                         .idlest_reg_id = 1,
1015                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1016                 },
1017         },
1018         .slaves         = omap3xxx_timer10_slaves,
1019         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1020         .class          = &omap3xxx_timer_1ms_hwmod_class,
1021         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1022 };
1023
1024 /* timer11 */
1025 static struct omap_hwmod omap3xxx_timer11_hwmod;
1026
1027 /* l4_core -> timer11 */
1028 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1029         .master         = &omap3xxx_l4_core_hwmod,
1030         .slave          = &omap3xxx_timer11_hwmod,
1031         .clk            = "gpt11_ick",
1032         .addr           = omap2_timer11_addrs,
1033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1034 };
1035
1036 /* timer11 slave port */
1037 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1038         &omap3xxx_l4_core__timer11,
1039 };
1040
1041 /* timer11 hwmod */
1042 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1043         .name           = "timer11",
1044         .mpu_irqs       = omap2_timer11_mpu_irqs,
1045         .main_clk       = "gpt11_fck",
1046         .prcm           = {
1047                 .omap2 = {
1048                         .prcm_reg_id = 1,
1049                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1050                         .module_offs = CORE_MOD,
1051                         .idlest_reg_id = 1,
1052                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1053                 },
1054         },
1055         .slaves         = omap3xxx_timer11_slaves,
1056         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1057         .class          = &omap3xxx_timer_hwmod_class,
1058         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1059 };
1060
1061 /* timer12*/
1062 static struct omap_hwmod omap3xxx_timer12_hwmod;
1063 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1064         { .irq = 95, },
1065         { .irq = -1 }
1066 };
1067
1068 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1069         {
1070                 .pa_start       = 0x48304000,
1071                 .pa_end         = 0x48304000 + SZ_1K - 1,
1072                 .flags          = ADDR_TYPE_RT
1073         },
1074         { }
1075 };
1076
1077 /* l4_core -> timer12 */
1078 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1079         .master         = &omap3xxx_l4_core_hwmod,
1080         .slave          = &omap3xxx_timer12_hwmod,
1081         .clk            = "gpt12_ick",
1082         .addr           = omap3xxx_timer12_addrs,
1083         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1084 };
1085
1086 /* timer12 slave port */
1087 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1088         &omap3xxx_l4_core__timer12,
1089 };
1090
1091 /* timer12 hwmod */
1092 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1093         .name           = "timer12",
1094         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1095         .main_clk       = "gpt12_fck",
1096         .prcm           = {
1097                 .omap2 = {
1098                         .prcm_reg_id = 1,
1099                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1100                         .module_offs = WKUP_MOD,
1101                         .idlest_reg_id = 1,
1102                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1103                 },
1104         },
1105         .slaves         = omap3xxx_timer12_slaves,
1106         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1107         .class          = &omap3xxx_timer_hwmod_class,
1108         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1109 };
1110
1111 /* l4_wkup -> wd_timer2 */
1112 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1113         {
1114                 .pa_start       = 0x48314000,
1115                 .pa_end         = 0x4831407f,
1116                 .flags          = ADDR_TYPE_RT
1117         },
1118         { }
1119 };
1120
1121 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1122         .master         = &omap3xxx_l4_wkup_hwmod,
1123         .slave          = &omap3xxx_wd_timer2_hwmod,
1124         .clk            = "wdt2_ick",
1125         .addr           = omap3xxx_wd_timer2_addrs,
1126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1127 };
1128
1129 /*
1130  * 'wd_timer' class
1131  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1132  * overflow condition
1133  */
1134
1135 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1136         .rev_offs       = 0x0000,
1137         .sysc_offs      = 0x0010,
1138         .syss_offs      = 0x0014,
1139         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1140                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1141                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1142                            SYSS_HAS_RESET_STATUS),
1143         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1144         .sysc_fields    = &omap_hwmod_sysc_type1,
1145 };
1146
1147 /* I2C common */
1148 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1149         .rev_offs       = 0x00,
1150         .sysc_offs      = 0x20,
1151         .syss_offs      = 0x10,
1152         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1153                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1154                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1155         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1156         .sysc_fields    = &omap_hwmod_sysc_type1,
1157 };
1158
1159 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1160         .name           = "wd_timer",
1161         .sysc           = &omap3xxx_wd_timer_sysc,
1162         .pre_shutdown   = &omap2_wd_timer_disable
1163 };
1164
1165 /* wd_timer2 */
1166 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1167         &omap3xxx_l4_wkup__wd_timer2,
1168 };
1169
1170 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1171         .name           = "wd_timer2",
1172         .class          = &omap3xxx_wd_timer_hwmod_class,
1173         .main_clk       = "wdt2_fck",
1174         .prcm           = {
1175                 .omap2 = {
1176                         .prcm_reg_id = 1,
1177                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1178                         .module_offs = WKUP_MOD,
1179                         .idlest_reg_id = 1,
1180                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1181                 },
1182         },
1183         .slaves         = omap3xxx_wd_timer2_slaves,
1184         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1185         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1186         /*
1187          * XXX: Use software supervised mode, HW supervised smartidle seems to
1188          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1189          */
1190         .flags          = HWMOD_SWSUP_SIDLE,
1191 };
1192
1193 /* UART common */
1194
1195 static struct omap_hwmod_class_sysconfig uart_sysc = {
1196         .rev_offs       = 0x50,
1197         .sysc_offs      = 0x54,
1198         .syss_offs      = 0x58,
1199         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
1200                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1201                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1202         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1203         .sysc_fields    = &omap_hwmod_sysc_type1,
1204 };
1205
1206 static struct omap_hwmod_class uart_class = {
1207         .name = "uart",
1208         .sysc = &uart_sysc,
1209 };
1210
1211 /* UART1 */
1212
1213 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1214         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1215         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1216 };
1217
1218 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1219         &omap3_l4_core__uart1,
1220 };
1221
1222 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1223         .name           = "uart1",
1224         .mpu_irqs       = omap2_uart1_mpu_irqs,
1225         .sdma_reqs      = uart1_sdma_reqs,
1226         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
1227         .main_clk       = "uart1_fck",
1228         .prcm           = {
1229                 .omap2 = {
1230                         .module_offs = CORE_MOD,
1231                         .prcm_reg_id = 1,
1232                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1233                         .idlest_reg_id = 1,
1234                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1235                 },
1236         },
1237         .slaves         = omap3xxx_uart1_slaves,
1238         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1239         .class          = &uart_class,
1240         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1241 };
1242
1243 /* UART2 */
1244
1245 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1246         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1247         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1248 };
1249
1250 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1251         &omap3_l4_core__uart2,
1252 };
1253
1254 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1255         .name           = "uart2",
1256         .mpu_irqs       = omap2_uart2_mpu_irqs,
1257         .sdma_reqs      = uart2_sdma_reqs,
1258         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
1259         .main_clk       = "uart2_fck",
1260         .prcm           = {
1261                 .omap2 = {
1262                         .module_offs = CORE_MOD,
1263                         .prcm_reg_id = 1,
1264                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1265                         .idlest_reg_id = 1,
1266                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1267                 },
1268         },
1269         .slaves         = omap3xxx_uart2_slaves,
1270         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1271         .class          = &uart_class,
1272         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1273 };
1274
1275 /* UART3 */
1276
1277 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1278         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1279         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1280 };
1281
1282 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1283         &omap3_l4_per__uart3,
1284 };
1285
1286 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1287         .name           = "uart3",
1288         .mpu_irqs       = omap2_uart3_mpu_irqs,
1289         .sdma_reqs      = uart3_sdma_reqs,
1290         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
1291         .main_clk       = "uart3_fck",
1292         .prcm           = {
1293                 .omap2 = {
1294                         .module_offs = OMAP3430_PER_MOD,
1295                         .prcm_reg_id = 1,
1296                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1297                         .idlest_reg_id = 1,
1298                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1299                 },
1300         },
1301         .slaves         = omap3xxx_uart3_slaves,
1302         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1303         .class          = &uart_class,
1304         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1305 };
1306
1307 /* UART4 */
1308
1309 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1310         { .irq = INT_36XX_UART4_IRQ, },
1311         { .irq = -1 }
1312 };
1313
1314 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1315         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1316         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1317 };
1318
1319 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1320         &omap3_l4_per__uart4,
1321 };
1322
1323 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1324         .name           = "uart4",
1325         .mpu_irqs       = uart4_mpu_irqs,
1326         .sdma_reqs      = uart4_sdma_reqs,
1327         .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
1328         .main_clk       = "uart4_fck",
1329         .prcm           = {
1330                 .omap2 = {
1331                         .module_offs = OMAP3430_PER_MOD,
1332                         .prcm_reg_id = 1,
1333                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1334                         .idlest_reg_id = 1,
1335                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1336                 },
1337         },
1338         .slaves         = omap3xxx_uart4_slaves,
1339         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1340         .class          = &uart_class,
1341         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1342 };
1343
1344 static struct omap_hwmod_class i2c_class = {
1345         .name = "i2c",
1346         .sysc = &i2c_sysc,
1347 };
1348
1349 /*
1350  * 'dss' class
1351  * display sub-system
1352  */
1353
1354 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1355         .rev_offs       = 0x0000,
1356         .sysc_offs      = 0x0010,
1357         .syss_offs      = 0x0014,
1358         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1359         .sysc_fields    = &omap_hwmod_sysc_type1,
1360 };
1361
1362 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1363         .name = "dss",
1364         .sysc = &omap3xxx_dss_sysc,
1365 };
1366
1367 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1368         { .name = "dispc", .dma_req = 5 },
1369         { .name = "dsi1", .dma_req = 74 },
1370 };
1371
1372 /* dss */
1373 /* dss master ports */
1374 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1375         &omap3xxx_dss__l3,
1376 };
1377
1378 /* l4_core -> dss */
1379 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1380         .master         = &omap3xxx_l4_core_hwmod,
1381         .slave          = &omap3430es1_dss_core_hwmod,
1382         .clk            = "dss_ick",
1383         .addr           = omap2_dss_addrs,
1384         .fw = {
1385                 .omap2 = {
1386                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1387                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1388                         .flags  = OMAP_FIREWALL_L4,
1389                 }
1390         },
1391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1392 };
1393
1394 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1395         .master         = &omap3xxx_l4_core_hwmod,
1396         .slave          = &omap3xxx_dss_core_hwmod,
1397         .clk            = "dss_ick",
1398         .addr           = omap2_dss_addrs,
1399         .fw = {
1400                 .omap2 = {
1401                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1402                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1403                         .flags  = OMAP_FIREWALL_L4,
1404                 }
1405         },
1406         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1407 };
1408
1409 /* dss slave ports */
1410 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1411         &omap3430es1_l4_core__dss,
1412 };
1413
1414 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1415         &omap3xxx_l4_core__dss,
1416 };
1417
1418 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1419         { .role = "tv_clk", .clk = "dss_tv_fck" },
1420         { .role = "video_clk", .clk = "dss_96m_fck" },
1421         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1422 };
1423
1424 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1425         .name           = "dss_core",
1426         .class          = &omap3xxx_dss_hwmod_class,
1427         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1428         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1429         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1430
1431         .prcm           = {
1432                 .omap2 = {
1433                         .prcm_reg_id = 1,
1434                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1435                         .module_offs = OMAP3430_DSS_MOD,
1436                         .idlest_reg_id = 1,
1437                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1438                 },
1439         },
1440         .opt_clks       = dss_opt_clks,
1441         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1442         .slaves         = omap3430es1_dss_slaves,
1443         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1444         .masters        = omap3xxx_dss_masters,
1445         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1446         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1447         .flags          = HWMOD_NO_IDLEST,
1448 };
1449
1450 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1451         .name           = "dss_core",
1452         .class          = &omap3xxx_dss_hwmod_class,
1453         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1454         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1455         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1456
1457         .prcm           = {
1458                 .omap2 = {
1459                         .prcm_reg_id = 1,
1460                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1461                         .module_offs = OMAP3430_DSS_MOD,
1462                         .idlest_reg_id = 1,
1463                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1464                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1465                 },
1466         },
1467         .opt_clks       = dss_opt_clks,
1468         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1469         .slaves         = omap3xxx_dss_slaves,
1470         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1471         .masters        = omap3xxx_dss_masters,
1472         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1473         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1474                                 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1475 };
1476
1477 /*
1478  * 'dispc' class
1479  * display controller
1480  */
1481
1482 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1483         .rev_offs       = 0x0000,
1484         .sysc_offs      = 0x0010,
1485         .syss_offs      = 0x0014,
1486         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1487                            SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1488                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1489         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1490                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1491         .sysc_fields    = &omap_hwmod_sysc_type1,
1492 };
1493
1494 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1495         .name = "dispc",
1496         .sysc = &omap3xxx_dispc_sysc,
1497 };
1498
1499 /* l4_core -> dss_dispc */
1500 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1501         .master         = &omap3xxx_l4_core_hwmod,
1502         .slave          = &omap3xxx_dss_dispc_hwmod,
1503         .clk            = "dss_ick",
1504         .addr           = omap2_dss_dispc_addrs,
1505         .fw = {
1506                 .omap2 = {
1507                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1508                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1509                         .flags  = OMAP_FIREWALL_L4,
1510                 }
1511         },
1512         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1513 };
1514
1515 /* dss_dispc slave ports */
1516 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1517         &omap3xxx_l4_core__dss_dispc,
1518 };
1519
1520 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1521         .name           = "dss_dispc",
1522         .class          = &omap3xxx_dispc_hwmod_class,
1523         .mpu_irqs       = omap2_dispc_irqs,
1524         .main_clk       = "dss1_alwon_fck",
1525         .prcm           = {
1526                 .omap2 = {
1527                         .prcm_reg_id = 1,
1528                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1529                         .module_offs = OMAP3430_DSS_MOD,
1530                 },
1531         },
1532         .slaves         = omap3xxx_dss_dispc_slaves,
1533         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1534         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1535                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1536                                 CHIP_GE_OMAP3630ES1_1),
1537         .flags          = HWMOD_NO_IDLEST,
1538 };
1539
1540 /*
1541  * 'dsi' class
1542  * display serial interface controller
1543  */
1544
1545 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1546         .name = "dsi",
1547 };
1548
1549 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1550         { .irq = 25 },
1551         { .irq = -1 }
1552 };
1553
1554 /* dss_dsi1 */
1555 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1556         {
1557                 .pa_start       = 0x4804FC00,
1558                 .pa_end         = 0x4804FFFF,
1559                 .flags          = ADDR_TYPE_RT
1560         },
1561         { }
1562 };
1563
1564 /* l4_core -> dss_dsi1 */
1565 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1566         .master         = &omap3xxx_l4_core_hwmod,
1567         .slave          = &omap3xxx_dss_dsi1_hwmod,
1568         .addr           = omap3xxx_dss_dsi1_addrs,
1569         .fw = {
1570                 .omap2 = {
1571                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1572                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1573                         .flags  = OMAP_FIREWALL_L4,
1574                 }
1575         },
1576         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1577 };
1578
1579 /* dss_dsi1 slave ports */
1580 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1581         &omap3xxx_l4_core__dss_dsi1,
1582 };
1583
1584 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1585         .name           = "dss_dsi1",
1586         .class          = &omap3xxx_dsi_hwmod_class,
1587         .mpu_irqs       = omap3xxx_dsi1_irqs,
1588         .main_clk       = "dss1_alwon_fck",
1589         .prcm           = {
1590                 .omap2 = {
1591                         .prcm_reg_id = 1,
1592                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1593                         .module_offs = OMAP3430_DSS_MOD,
1594                 },
1595         },
1596         .slaves         = omap3xxx_dss_dsi1_slaves,
1597         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1598         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1599                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1600                                 CHIP_GE_OMAP3630ES1_1),
1601         .flags          = HWMOD_NO_IDLEST,
1602 };
1603
1604 /*
1605  * 'rfbi' class
1606  * remote frame buffer interface
1607  */
1608
1609 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1610         .rev_offs       = 0x0000,
1611         .sysc_offs      = 0x0010,
1612         .syss_offs      = 0x0014,
1613         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1614                            SYSC_HAS_AUTOIDLE),
1615         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1616         .sysc_fields    = &omap_hwmod_sysc_type1,
1617 };
1618
1619 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1620         .name = "rfbi",
1621         .sysc = &omap3xxx_rfbi_sysc,
1622 };
1623
1624 /* l4_core -> dss_rfbi */
1625 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1626         .master         = &omap3xxx_l4_core_hwmod,
1627         .slave          = &omap3xxx_dss_rfbi_hwmod,
1628         .clk            = "dss_ick",
1629         .addr           = omap2_dss_rfbi_addrs,
1630         .fw = {
1631                 .omap2 = {
1632                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1633                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1634                         .flags  = OMAP_FIREWALL_L4,
1635                 }
1636         },
1637         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1638 };
1639
1640 /* dss_rfbi slave ports */
1641 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1642         &omap3xxx_l4_core__dss_rfbi,
1643 };
1644
1645 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1646         .name           = "dss_rfbi",
1647         .class          = &omap3xxx_rfbi_hwmod_class,
1648         .main_clk       = "dss1_alwon_fck",
1649         .prcm           = {
1650                 .omap2 = {
1651                         .prcm_reg_id = 1,
1652                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1653                         .module_offs = OMAP3430_DSS_MOD,
1654                 },
1655         },
1656         .slaves         = omap3xxx_dss_rfbi_slaves,
1657         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1658         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1659                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1660                                 CHIP_GE_OMAP3630ES1_1),
1661         .flags          = HWMOD_NO_IDLEST,
1662 };
1663
1664 /*
1665  * 'venc' class
1666  * video encoder
1667  */
1668
1669 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1670         .name = "venc",
1671 };
1672
1673 /* l4_core -> dss_venc */
1674 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1675         .master         = &omap3xxx_l4_core_hwmod,
1676         .slave          = &omap3xxx_dss_venc_hwmod,
1677         .clk            = "dss_tv_fck",
1678         .addr           = omap2_dss_venc_addrs,
1679         .fw = {
1680                 .omap2 = {
1681                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1682                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1683                         .flags  = OMAP_FIREWALL_L4,
1684                 }
1685         },
1686         .flags          = OCPIF_SWSUP_IDLE,
1687         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1688 };
1689
1690 /* dss_venc slave ports */
1691 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1692         &omap3xxx_l4_core__dss_venc,
1693 };
1694
1695 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1696         .name           = "dss_venc",
1697         .class          = &omap3xxx_venc_hwmod_class,
1698         .main_clk       = "dss1_alwon_fck",
1699         .prcm           = {
1700                 .omap2 = {
1701                         .prcm_reg_id = 1,
1702                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1703                         .module_offs = OMAP3430_DSS_MOD,
1704                 },
1705         },
1706         .slaves         = omap3xxx_dss_venc_slaves,
1707         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1708         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1709                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1710                                 CHIP_GE_OMAP3630ES1_1),
1711         .flags          = HWMOD_NO_IDLEST,
1712 };
1713
1714 /* I2C1 */
1715
1716 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1717         .fifo_depth     = 8, /* bytes */
1718 };
1719
1720 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1721         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1722         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1723 };
1724
1725 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1726         &omap3_l4_core__i2c1,
1727 };
1728
1729 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1730         .name           = "i2c1",
1731         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1732         .sdma_reqs      = i2c1_sdma_reqs,
1733         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
1734         .main_clk       = "i2c1_fck",
1735         .prcm           = {
1736                 .omap2 = {
1737                         .module_offs = CORE_MOD,
1738                         .prcm_reg_id = 1,
1739                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1740                         .idlest_reg_id = 1,
1741                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1742                 },
1743         },
1744         .slaves         = omap3xxx_i2c1_slaves,
1745         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1746         .class          = &i2c_class,
1747         .dev_attr       = &i2c1_dev_attr,
1748         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1749 };
1750
1751 /* I2C2 */
1752
1753 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1754         .fifo_depth     = 8, /* bytes */
1755 };
1756
1757 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1758         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1759         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1760 };
1761
1762 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1763         &omap3_l4_core__i2c2,
1764 };
1765
1766 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1767         .name           = "i2c2",
1768         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1769         .sdma_reqs      = i2c2_sdma_reqs,
1770         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
1771         .main_clk       = "i2c2_fck",
1772         .prcm           = {
1773                 .omap2 = {
1774                         .module_offs = CORE_MOD,
1775                         .prcm_reg_id = 1,
1776                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1777                         .idlest_reg_id = 1,
1778                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1779                 },
1780         },
1781         .slaves         = omap3xxx_i2c2_slaves,
1782         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1783         .class          = &i2c_class,
1784         .dev_attr       = &i2c2_dev_attr,
1785         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1786 };
1787
1788 /* I2C3 */
1789
1790 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1791         .fifo_depth     = 64, /* bytes */
1792 };
1793
1794 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1795         { .irq = INT_34XX_I2C3_IRQ, },
1796         { .irq = -1 }
1797 };
1798
1799 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1800         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1801         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1802 };
1803
1804 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1805         &omap3_l4_core__i2c3,
1806 };
1807
1808 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1809         .name           = "i2c3",
1810         .mpu_irqs       = i2c3_mpu_irqs,
1811         .sdma_reqs      = i2c3_sdma_reqs,
1812         .sdma_reqs_cnt  = ARRAY_SIZE(i2c3_sdma_reqs),
1813         .main_clk       = "i2c3_fck",
1814         .prcm           = {
1815                 .omap2 = {
1816                         .module_offs = CORE_MOD,
1817                         .prcm_reg_id = 1,
1818                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1819                         .idlest_reg_id = 1,
1820                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1821                 },
1822         },
1823         .slaves         = omap3xxx_i2c3_slaves,
1824         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1825         .class          = &i2c_class,
1826         .dev_attr       = &i2c3_dev_attr,
1827         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1828 };
1829
1830 /* l4_wkup -> gpio1 */
1831 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1832         {
1833                 .pa_start       = 0x48310000,
1834                 .pa_end         = 0x483101ff,
1835                 .flags          = ADDR_TYPE_RT
1836         },
1837         { }
1838 };
1839
1840 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1841         .master         = &omap3xxx_l4_wkup_hwmod,
1842         .slave          = &omap3xxx_gpio1_hwmod,
1843         .addr           = omap3xxx_gpio1_addrs,
1844         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1845 };
1846
1847 /* l4_per -> gpio2 */
1848 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1849         {
1850                 .pa_start       = 0x49050000,
1851                 .pa_end         = 0x490501ff,
1852                 .flags          = ADDR_TYPE_RT
1853         },
1854         { }
1855 };
1856
1857 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1858         .master         = &omap3xxx_l4_per_hwmod,
1859         .slave          = &omap3xxx_gpio2_hwmod,
1860         .addr           = omap3xxx_gpio2_addrs,
1861         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1862 };
1863
1864 /* l4_per -> gpio3 */
1865 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1866         {
1867                 .pa_start       = 0x49052000,
1868                 .pa_end         = 0x490521ff,
1869                 .flags          = ADDR_TYPE_RT
1870         },
1871         { }
1872 };
1873
1874 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1875         .master         = &omap3xxx_l4_per_hwmod,
1876         .slave          = &omap3xxx_gpio3_hwmod,
1877         .addr           = omap3xxx_gpio3_addrs,
1878         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1879 };
1880
1881 /* l4_per -> gpio4 */
1882 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1883         {
1884                 .pa_start       = 0x49054000,
1885                 .pa_end         = 0x490541ff,
1886                 .flags          = ADDR_TYPE_RT
1887         },
1888         { }
1889 };
1890
1891 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1892         .master         = &omap3xxx_l4_per_hwmod,
1893         .slave          = &omap3xxx_gpio4_hwmod,
1894         .addr           = omap3xxx_gpio4_addrs,
1895         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1896 };
1897
1898 /* l4_per -> gpio5 */
1899 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1900         {
1901                 .pa_start       = 0x49056000,
1902                 .pa_end         = 0x490561ff,
1903                 .flags          = ADDR_TYPE_RT
1904         },
1905         { }
1906 };
1907
1908 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1909         .master         = &omap3xxx_l4_per_hwmod,
1910         .slave          = &omap3xxx_gpio5_hwmod,
1911         .addr           = omap3xxx_gpio5_addrs,
1912         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1913 };
1914
1915 /* l4_per -> gpio6 */
1916 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1917         {
1918                 .pa_start       = 0x49058000,
1919                 .pa_end         = 0x490581ff,
1920                 .flags          = ADDR_TYPE_RT
1921         },
1922         { }
1923 };
1924
1925 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1926         .master         = &omap3xxx_l4_per_hwmod,
1927         .slave          = &omap3xxx_gpio6_hwmod,
1928         .addr           = omap3xxx_gpio6_addrs,
1929         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1930 };
1931
1932 /*
1933  * 'gpio' class
1934  * general purpose io module
1935  */
1936
1937 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1938         .rev_offs       = 0x0000,
1939         .sysc_offs      = 0x0010,
1940         .syss_offs      = 0x0014,
1941         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1942                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1943                            SYSS_HAS_RESET_STATUS),
1944         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1945         .sysc_fields    = &omap_hwmod_sysc_type1,
1946 };
1947
1948 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1949         .name = "gpio",
1950         .sysc = &omap3xxx_gpio_sysc,
1951         .rev = 1,
1952 };
1953
1954 /* gpio_dev_attr*/
1955 static struct omap_gpio_dev_attr gpio_dev_attr = {
1956         .bank_width = 32,
1957         .dbck_flag = true,
1958 };
1959
1960 /* gpio1 */
1961 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1962         { .role = "dbclk", .clk = "gpio1_dbck", },
1963 };
1964
1965 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1966         &omap3xxx_l4_wkup__gpio1,
1967 };
1968
1969 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1970         .name           = "gpio1",
1971         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1972         .mpu_irqs       = omap2_gpio1_irqs,
1973         .main_clk       = "gpio1_ick",
1974         .opt_clks       = gpio1_opt_clks,
1975         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1976         .prcm           = {
1977                 .omap2 = {
1978                         .prcm_reg_id = 1,
1979                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1980                         .module_offs = WKUP_MOD,
1981                         .idlest_reg_id = 1,
1982                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1983                 },
1984         },
1985         .slaves         = omap3xxx_gpio1_slaves,
1986         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1987         .class          = &omap3xxx_gpio_hwmod_class,
1988         .dev_attr       = &gpio_dev_attr,
1989         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1990 };
1991
1992 /* gpio2 */
1993 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1994         { .role = "dbclk", .clk = "gpio2_dbck", },
1995 };
1996
1997 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1998         &omap3xxx_l4_per__gpio2,
1999 };
2000
2001 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2002         .name           = "gpio2",
2003         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2004         .mpu_irqs       = omap2_gpio2_irqs,
2005         .main_clk       = "gpio2_ick",
2006         .opt_clks       = gpio2_opt_clks,
2007         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
2008         .prcm           = {
2009                 .omap2 = {
2010                         .prcm_reg_id = 1,
2011                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
2012                         .module_offs = OMAP3430_PER_MOD,
2013                         .idlest_reg_id = 1,
2014                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2015                 },
2016         },
2017         .slaves         = omap3xxx_gpio2_slaves,
2018         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2019         .class          = &omap3xxx_gpio_hwmod_class,
2020         .dev_attr       = &gpio_dev_attr,
2021         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2022 };
2023
2024 /* gpio3 */
2025 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2026         { .role = "dbclk", .clk = "gpio3_dbck", },
2027 };
2028
2029 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2030         &omap3xxx_l4_per__gpio3,
2031 };
2032
2033 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2034         .name           = "gpio3",
2035         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2036         .mpu_irqs       = omap2_gpio3_irqs,
2037         .main_clk       = "gpio3_ick",
2038         .opt_clks       = gpio3_opt_clks,
2039         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
2040         .prcm           = {
2041                 .omap2 = {
2042                         .prcm_reg_id = 1,
2043                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2044                         .module_offs = OMAP3430_PER_MOD,
2045                         .idlest_reg_id = 1,
2046                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2047                 },
2048         },
2049         .slaves         = omap3xxx_gpio3_slaves,
2050         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2051         .class          = &omap3xxx_gpio_hwmod_class,
2052         .dev_attr       = &gpio_dev_attr,
2053         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2054 };
2055
2056 /* gpio4 */
2057 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2058         { .role = "dbclk", .clk = "gpio4_dbck", },
2059 };
2060
2061 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2062         &omap3xxx_l4_per__gpio4,
2063 };
2064
2065 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2066         .name           = "gpio4",
2067         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2068         .mpu_irqs       = omap2_gpio4_irqs,
2069         .main_clk       = "gpio4_ick",
2070         .opt_clks       = gpio4_opt_clks,
2071         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2072         .prcm           = {
2073                 .omap2 = {
2074                         .prcm_reg_id = 1,
2075                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2076                         .module_offs = OMAP3430_PER_MOD,
2077                         .idlest_reg_id = 1,
2078                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2079                 },
2080         },
2081         .slaves         = omap3xxx_gpio4_slaves,
2082         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2083         .class          = &omap3xxx_gpio_hwmod_class,
2084         .dev_attr       = &gpio_dev_attr,
2085         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2086 };
2087
2088 /* gpio5 */
2089 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2090         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2091         { .irq = -1 }
2092 };
2093
2094 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2095         { .role = "dbclk", .clk = "gpio5_dbck", },
2096 };
2097
2098 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2099         &omap3xxx_l4_per__gpio5,
2100 };
2101
2102 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2103         .name           = "gpio5",
2104         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2105         .mpu_irqs       = omap3xxx_gpio5_irqs,
2106         .main_clk       = "gpio5_ick",
2107         .opt_clks       = gpio5_opt_clks,
2108         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2109         .prcm           = {
2110                 .omap2 = {
2111                         .prcm_reg_id = 1,
2112                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2113                         .module_offs = OMAP3430_PER_MOD,
2114                         .idlest_reg_id = 1,
2115                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2116                 },
2117         },
2118         .slaves         = omap3xxx_gpio5_slaves,
2119         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2120         .class          = &omap3xxx_gpio_hwmod_class,
2121         .dev_attr       = &gpio_dev_attr,
2122         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2123 };
2124
2125 /* gpio6 */
2126 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2127         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2128         { .irq = -1 }
2129 };
2130
2131 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2132         { .role = "dbclk", .clk = "gpio6_dbck", },
2133 };
2134
2135 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2136         &omap3xxx_l4_per__gpio6,
2137 };
2138
2139 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2140         .name           = "gpio6",
2141         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2142         .mpu_irqs       = omap3xxx_gpio6_irqs,
2143         .main_clk       = "gpio6_ick",
2144         .opt_clks       = gpio6_opt_clks,
2145         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2146         .prcm           = {
2147                 .omap2 = {
2148                         .prcm_reg_id = 1,
2149                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2150                         .module_offs = OMAP3430_PER_MOD,
2151                         .idlest_reg_id = 1,
2152                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2153                 },
2154         },
2155         .slaves         = omap3xxx_gpio6_slaves,
2156         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2157         .class          = &omap3xxx_gpio_hwmod_class,
2158         .dev_attr       = &gpio_dev_attr,
2159         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2160 };
2161
2162 /* dma_system -> L3 */
2163 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2164         .master         = &omap3xxx_dma_system_hwmod,
2165         .slave          = &omap3xxx_l3_main_hwmod,
2166         .clk            = "core_l3_ick",
2167         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2168 };
2169
2170 /* dma attributes */
2171 static struct omap_dma_dev_attr dma_dev_attr = {
2172         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2173                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2174         .lch_count = 32,
2175 };
2176
2177 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2178         .rev_offs       = 0x0000,
2179         .sysc_offs      = 0x002c,
2180         .syss_offs      = 0x0028,
2181         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2182                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2183                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2184                            SYSS_HAS_RESET_STATUS),
2185         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2186                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2187         .sysc_fields    = &omap_hwmod_sysc_type1,
2188 };
2189
2190 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2191         .name = "dma",
2192         .sysc = &omap3xxx_dma_sysc,
2193 };
2194
2195 /* dma_system */
2196 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2197         {
2198                 .pa_start       = 0x48056000,
2199                 .pa_end         = 0x48056fff,
2200                 .flags          = ADDR_TYPE_RT
2201         },
2202         { }
2203 };
2204
2205 /* dma_system master ports */
2206 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2207         &omap3xxx_dma_system__l3,
2208 };
2209
2210 /* l4_cfg -> dma_system */
2211 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2212         .master         = &omap3xxx_l4_core_hwmod,
2213         .slave          = &omap3xxx_dma_system_hwmod,
2214         .clk            = "core_l4_ick",
2215         .addr           = omap3xxx_dma_system_addrs,
2216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2217 };
2218
2219 /* dma_system slave ports */
2220 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2221         &omap3xxx_l4_core__dma_system,
2222 };
2223
2224 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2225         .name           = "dma",
2226         .class          = &omap3xxx_dma_hwmod_class,
2227         .mpu_irqs       = omap2_dma_system_irqs,
2228         .main_clk       = "core_l3_ick",
2229         .prcm = {
2230                 .omap2 = {
2231                         .module_offs            = CORE_MOD,
2232                         .prcm_reg_id            = 1,
2233                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2234                         .idlest_reg_id          = 1,
2235                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2236                 },
2237         },
2238         .slaves         = omap3xxx_dma_system_slaves,
2239         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2240         .masters        = omap3xxx_dma_system_masters,
2241         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2242         .dev_attr       = &dma_dev_attr,
2243         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2244         .flags          = HWMOD_NO_IDLEST,
2245 };
2246
2247 /*
2248  * 'mcbsp' class
2249  * multi channel buffered serial port controller
2250  */
2251
2252 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2253         .sysc_offs      = 0x008c,
2254         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2255                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2256         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2257         .sysc_fields    = &omap_hwmod_sysc_type1,
2258         .clockact       = 0x2,
2259 };
2260
2261 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2262         .name = "mcbsp",
2263         .sysc = &omap3xxx_mcbsp_sysc,
2264         .rev  = MCBSP_CONFIG_TYPE3,
2265 };
2266
2267 /* mcbsp1 */
2268 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2269         { .name = "irq", .irq = 16 },
2270         { .name = "tx", .irq = 59 },
2271         { .name = "rx", .irq = 60 },
2272         { .irq = -1 }
2273 };
2274
2275 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2276         { .name = "rx", .dma_req = 32 },
2277         { .name = "tx", .dma_req = 31 },
2278 };
2279
2280 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2281         {
2282                 .name           = "mpu",
2283                 .pa_start       = 0x48074000,
2284                 .pa_end         = 0x480740ff,
2285                 .flags          = ADDR_TYPE_RT
2286         },
2287         { }
2288 };
2289
2290 /* l4_core -> mcbsp1 */
2291 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2292         .master         = &omap3xxx_l4_core_hwmod,
2293         .slave          = &omap3xxx_mcbsp1_hwmod,
2294         .clk            = "mcbsp1_ick",
2295         .addr           = omap3xxx_mcbsp1_addrs,
2296         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2297 };
2298
2299 /* mcbsp1 slave ports */
2300 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2301         &omap3xxx_l4_core__mcbsp1,
2302 };
2303
2304 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2305         .name           = "mcbsp1",
2306         .class          = &omap3xxx_mcbsp_hwmod_class,
2307         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2308         .sdma_reqs      = omap3xxx_mcbsp1_sdma_chs,
2309         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2310         .main_clk       = "mcbsp1_fck",
2311         .prcm           = {
2312                 .omap2 = {
2313                         .prcm_reg_id = 1,
2314                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2315                         .module_offs = CORE_MOD,
2316                         .idlest_reg_id = 1,
2317                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2318                 },
2319         },
2320         .slaves         = omap3xxx_mcbsp1_slaves,
2321         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2322         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2323 };
2324
2325 /* mcbsp2 */
2326 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2327         { .name = "irq", .irq = 17 },
2328         { .name = "tx", .irq = 62 },
2329         { .name = "rx", .irq = 63 },
2330         { .irq = -1 }
2331 };
2332
2333 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2334         { .name = "rx", .dma_req = 34 },
2335         { .name = "tx", .dma_req = 33 },
2336 };
2337
2338 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2339         {
2340                 .name           = "mpu",
2341                 .pa_start       = 0x49022000,
2342                 .pa_end         = 0x490220ff,
2343                 .flags          = ADDR_TYPE_RT
2344         },
2345         { }
2346 };
2347
2348 /* l4_per -> mcbsp2 */
2349 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2350         .master         = &omap3xxx_l4_per_hwmod,
2351         .slave          = &omap3xxx_mcbsp2_hwmod,
2352         .clk            = "mcbsp2_ick",
2353         .addr           = omap3xxx_mcbsp2_addrs,
2354
2355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2356 };
2357
2358 /* mcbsp2 slave ports */
2359 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2360         &omap3xxx_l4_per__mcbsp2,
2361 };
2362
2363 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2364         .sidetone       = "mcbsp2_sidetone",
2365 };
2366
2367 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2368         .name           = "mcbsp2",
2369         .class          = &omap3xxx_mcbsp_hwmod_class,
2370         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2371         .sdma_reqs      = omap3xxx_mcbsp2_sdma_chs,
2372         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2373         .main_clk       = "mcbsp2_fck",
2374         .prcm           = {
2375                 .omap2 = {
2376                         .prcm_reg_id = 1,
2377                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2378                         .module_offs = OMAP3430_PER_MOD,
2379                         .idlest_reg_id = 1,
2380                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2381                 },
2382         },
2383         .slaves         = omap3xxx_mcbsp2_slaves,
2384         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2385         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2386         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2387 };
2388
2389 /* mcbsp3 */
2390 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2391         { .name = "irq", .irq = 22 },
2392         { .name = "tx", .irq = 89 },
2393         { .name = "rx", .irq = 90 },
2394         { .irq = -1 }
2395 };
2396
2397 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2398         { .name = "rx", .dma_req = 18 },
2399         { .name = "tx", .dma_req = 17 },
2400 };
2401
2402 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2403         {
2404                 .name           = "mpu",
2405                 .pa_start       = 0x49024000,
2406                 .pa_end         = 0x490240ff,
2407                 .flags          = ADDR_TYPE_RT
2408         },
2409         { }
2410 };
2411
2412 /* l4_per -> mcbsp3 */
2413 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2414         .master         = &omap3xxx_l4_per_hwmod,
2415         .slave          = &omap3xxx_mcbsp3_hwmod,
2416         .clk            = "mcbsp3_ick",
2417         .addr           = omap3xxx_mcbsp3_addrs,
2418         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2419 };
2420
2421 /* mcbsp3 slave ports */
2422 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2423         &omap3xxx_l4_per__mcbsp3,
2424 };
2425
2426 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2427         .sidetone       = "mcbsp3_sidetone",
2428 };
2429
2430 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2431         .name           = "mcbsp3",
2432         .class          = &omap3xxx_mcbsp_hwmod_class,
2433         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2434         .sdma_reqs      = omap3xxx_mcbsp3_sdma_chs,
2435         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2436         .main_clk       = "mcbsp3_fck",
2437         .prcm           = {
2438                 .omap2 = {
2439                         .prcm_reg_id = 1,
2440                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2441                         .module_offs = OMAP3430_PER_MOD,
2442                         .idlest_reg_id = 1,
2443                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2444                 },
2445         },
2446         .slaves         = omap3xxx_mcbsp3_slaves,
2447         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2448         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2449         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2450 };
2451
2452 /* mcbsp4 */
2453 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2454         { .name = "irq", .irq = 23 },
2455         { .name = "tx", .irq = 54 },
2456         { .name = "rx", .irq = 55 },
2457         { .irq = -1 }
2458 };
2459
2460 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2461         { .name = "rx", .dma_req = 20 },
2462         { .name = "tx", .dma_req = 19 },
2463 };
2464
2465 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2466         {
2467                 .name           = "mpu",
2468                 .pa_start       = 0x49026000,
2469                 .pa_end         = 0x490260ff,
2470                 .flags          = ADDR_TYPE_RT
2471         },
2472         { }
2473 };
2474
2475 /* l4_per -> mcbsp4 */
2476 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2477         .master         = &omap3xxx_l4_per_hwmod,
2478         .slave          = &omap3xxx_mcbsp4_hwmod,
2479         .clk            = "mcbsp4_ick",
2480         .addr           = omap3xxx_mcbsp4_addrs,
2481         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2482 };
2483
2484 /* mcbsp4 slave ports */
2485 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2486         &omap3xxx_l4_per__mcbsp4,
2487 };
2488
2489 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2490         .name           = "mcbsp4",
2491         .class          = &omap3xxx_mcbsp_hwmod_class,
2492         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2493         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2494         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2495         .main_clk       = "mcbsp4_fck",
2496         .prcm           = {
2497                 .omap2 = {
2498                         .prcm_reg_id = 1,
2499                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2500                         .module_offs = OMAP3430_PER_MOD,
2501                         .idlest_reg_id = 1,
2502                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2503                 },
2504         },
2505         .slaves         = omap3xxx_mcbsp4_slaves,
2506         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2507         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2508 };
2509
2510 /* mcbsp5 */
2511 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2512         { .name = "irq", .irq = 27 },
2513         { .name = "tx", .irq = 81 },
2514         { .name = "rx", .irq = 82 },
2515         { .irq = -1 }
2516 };
2517
2518 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2519         { .name = "rx", .dma_req = 22 },
2520         { .name = "tx", .dma_req = 21 },
2521 };
2522
2523 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2524         {
2525                 .name           = "mpu",
2526                 .pa_start       = 0x48096000,
2527                 .pa_end         = 0x480960ff,
2528                 .flags          = ADDR_TYPE_RT
2529         },
2530         { }
2531 };
2532
2533 /* l4_core -> mcbsp5 */
2534 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2535         .master         = &omap3xxx_l4_core_hwmod,
2536         .slave          = &omap3xxx_mcbsp5_hwmod,
2537         .clk            = "mcbsp5_ick",
2538         .addr           = omap3xxx_mcbsp5_addrs,
2539         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2540 };
2541
2542 /* mcbsp5 slave ports */
2543 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2544         &omap3xxx_l4_core__mcbsp5,
2545 };
2546
2547 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2548         .name           = "mcbsp5",
2549         .class          = &omap3xxx_mcbsp_hwmod_class,
2550         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2551         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2552         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2553         .main_clk       = "mcbsp5_fck",
2554         .prcm           = {
2555                 .omap2 = {
2556                         .prcm_reg_id = 1,
2557                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2558                         .module_offs = CORE_MOD,
2559                         .idlest_reg_id = 1,
2560                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2561                 },
2562         },
2563         .slaves         = omap3xxx_mcbsp5_slaves,
2564         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2565         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2566 };
2567 /* 'mcbsp sidetone' class */
2568
2569 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2570         .sysc_offs      = 0x0010,
2571         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2572         .sysc_fields    = &omap_hwmod_sysc_type1,
2573 };
2574
2575 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2576         .name = "mcbsp_sidetone",
2577         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2578 };
2579
2580 /* mcbsp2_sidetone */
2581 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2582         { .name = "irq", .irq = 4 },
2583         { .irq = -1 }
2584 };
2585
2586 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2587         {
2588                 .name           = "sidetone",
2589                 .pa_start       = 0x49028000,
2590                 .pa_end         = 0x490280ff,
2591                 .flags          = ADDR_TYPE_RT
2592         },
2593         { }
2594 };
2595
2596 /* l4_per -> mcbsp2_sidetone */
2597 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2598         .master         = &omap3xxx_l4_per_hwmod,
2599         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2600         .clk            = "mcbsp2_ick",
2601         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2602         .user           = OCP_USER_MPU,
2603 };
2604
2605 /* mcbsp2_sidetone slave ports */
2606 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2607         &omap3xxx_l4_per__mcbsp2_sidetone,
2608 };
2609
2610 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2611         .name           = "mcbsp2_sidetone",
2612         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2613         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2614         .main_clk       = "mcbsp2_fck",
2615         .prcm           = {
2616                 .omap2 = {
2617                         .prcm_reg_id = 1,
2618                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2619                         .module_offs = OMAP3430_PER_MOD,
2620                         .idlest_reg_id = 1,
2621                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2622                 },
2623         },
2624         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2625         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2626         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2627 };
2628
2629 /* mcbsp3_sidetone */
2630 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2631         { .name = "irq", .irq = 5 },
2632         { .irq = -1 }
2633 };
2634
2635 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2636         {
2637                 .name           = "sidetone",
2638                 .pa_start       = 0x4902A000,
2639                 .pa_end         = 0x4902A0ff,
2640                 .flags          = ADDR_TYPE_RT
2641         },
2642         { }
2643 };
2644
2645 /* l4_per -> mcbsp3_sidetone */
2646 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2647         .master         = &omap3xxx_l4_per_hwmod,
2648         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2649         .clk            = "mcbsp3_ick",
2650         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2651         .user           = OCP_USER_MPU,
2652 };
2653
2654 /* mcbsp3_sidetone slave ports */
2655 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2656         &omap3xxx_l4_per__mcbsp3_sidetone,
2657 };
2658
2659 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2660         .name           = "mcbsp3_sidetone",
2661         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2662         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2663         .main_clk       = "mcbsp3_fck",
2664         .prcm           = {
2665                 .omap2 = {
2666                         .prcm_reg_id = 1,
2667                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2668                         .module_offs = OMAP3430_PER_MOD,
2669                         .idlest_reg_id = 1,
2670                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2671                 },
2672         },
2673         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2674         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2675         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2676 };
2677
2678
2679 /* SR common */
2680 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2681         .clkact_shift   = 20,
2682 };
2683
2684 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2685         .sysc_offs      = 0x24,
2686         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2687         .clockact       = CLOCKACT_TEST_ICLK,
2688         .sysc_fields    = &omap34xx_sr_sysc_fields,
2689 };
2690
2691 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2692         .name = "smartreflex",
2693         .sysc = &omap34xx_sr_sysc,
2694         .rev  = 1,
2695 };
2696
2697 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2698         .sidle_shift    = 24,
2699         .enwkup_shift   = 26
2700 };
2701
2702 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2703         .sysc_offs      = 0x38,
2704         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2705         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2706                         SYSC_NO_CACHE),
2707         .sysc_fields    = &omap36xx_sr_sysc_fields,
2708 };
2709
2710 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2711         .name = "smartreflex",
2712         .sysc = &omap36xx_sr_sysc,
2713         .rev  = 2,
2714 };
2715
2716 /* SR1 */
2717 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2718         &omap3_l4_core__sr1,
2719 };
2720
2721 static struct omap_hwmod omap34xx_sr1_hwmod = {
2722         .name           = "sr1_hwmod",
2723         .class          = &omap34xx_smartreflex_hwmod_class,
2724         .main_clk       = "sr1_fck",
2725         .vdd_name       = "mpu",
2726         .prcm           = {
2727                 .omap2 = {
2728                         .prcm_reg_id = 1,
2729                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2730                         .module_offs = WKUP_MOD,
2731                         .idlest_reg_id = 1,
2732                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2733                 },
2734         },
2735         .slaves         = omap3_sr1_slaves,
2736         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2737         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2738                                         CHIP_IS_OMAP3430ES3_0 |
2739                                         CHIP_IS_OMAP3430ES3_1),
2740         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2741 };
2742
2743 static struct omap_hwmod omap36xx_sr1_hwmod = {
2744         .name           = "sr1_hwmod",
2745         .class          = &omap36xx_smartreflex_hwmod_class,
2746         .main_clk       = "sr1_fck",
2747         .vdd_name       = "mpu",
2748         .prcm           = {
2749                 .omap2 = {
2750                         .prcm_reg_id = 1,
2751                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2752                         .module_offs = WKUP_MOD,
2753                         .idlest_reg_id = 1,
2754                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2755                 },
2756         },
2757         .slaves         = omap3_sr1_slaves,
2758         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2759         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2760 };
2761
2762 /* SR2 */
2763 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2764         &omap3_l4_core__sr2,
2765 };
2766
2767 static struct omap_hwmod omap34xx_sr2_hwmod = {
2768         .name           = "sr2_hwmod",
2769         .class          = &omap34xx_smartreflex_hwmod_class,
2770         .main_clk       = "sr2_fck",
2771         .vdd_name       = "core",
2772         .prcm           = {
2773                 .omap2 = {
2774                         .prcm_reg_id = 1,
2775                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2776                         .module_offs = WKUP_MOD,
2777                         .idlest_reg_id = 1,
2778                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2779                 },
2780         },
2781         .slaves         = omap3_sr2_slaves,
2782         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2783         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2784                                         CHIP_IS_OMAP3430ES3_0 |
2785                                         CHIP_IS_OMAP3430ES3_1),
2786         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2787 };
2788
2789 static struct omap_hwmod omap36xx_sr2_hwmod = {
2790         .name           = "sr2_hwmod",
2791         .class          = &omap36xx_smartreflex_hwmod_class,
2792         .main_clk       = "sr2_fck",
2793         .vdd_name       = "core",
2794         .prcm           = {
2795                 .omap2 = {
2796                         .prcm_reg_id = 1,
2797                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2798                         .module_offs = WKUP_MOD,
2799                         .idlest_reg_id = 1,
2800                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2801                 },
2802         },
2803         .slaves         = omap3_sr2_slaves,
2804         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2805         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2806 };
2807
2808 /*
2809  * 'mailbox' class
2810  * mailbox module allowing communication between the on-chip processors
2811  * using a queued mailbox-interrupt mechanism.
2812  */
2813
2814 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2815         .rev_offs       = 0x000,
2816         .sysc_offs      = 0x010,
2817         .syss_offs      = 0x014,
2818         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2819                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2820         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2821         .sysc_fields    = &omap_hwmod_sysc_type1,
2822 };
2823
2824 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2825         .name = "mailbox",
2826         .sysc = &omap3xxx_mailbox_sysc,
2827 };
2828
2829 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2830 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2831         { .irq = 26 },
2832         { .irq = -1 }
2833 };
2834
2835 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2836         {
2837                 .pa_start       = 0x48094000,
2838                 .pa_end         = 0x480941ff,
2839                 .flags          = ADDR_TYPE_RT,
2840         },
2841         { }
2842 };
2843
2844 /* l4_core -> mailbox */
2845 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2846         .master         = &omap3xxx_l4_core_hwmod,
2847         .slave          = &omap3xxx_mailbox_hwmod,
2848         .addr           = omap3xxx_mailbox_addrs,
2849         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2850 };
2851
2852 /* mailbox slave ports */
2853 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2854         &omap3xxx_l4_core__mailbox,
2855 };
2856
2857 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2858         .name           = "mailbox",
2859         .class          = &omap3xxx_mailbox_hwmod_class,
2860         .mpu_irqs       = omap3xxx_mailbox_irqs,
2861         .main_clk       = "mailboxes_ick",
2862         .prcm           = {
2863                 .omap2 = {
2864                         .prcm_reg_id = 1,
2865                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2866                         .module_offs = CORE_MOD,
2867                         .idlest_reg_id = 1,
2868                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2869                 },
2870         },
2871         .slaves         = omap3xxx_mailbox_slaves,
2872         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2873         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2874 };
2875
2876 /* l4 core -> mcspi1 interface */
2877 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2878         .master         = &omap3xxx_l4_core_hwmod,
2879         .slave          = &omap34xx_mcspi1,
2880         .clk            = "mcspi1_ick",
2881         .addr           = omap2_mcspi1_addr_space,
2882         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2883 };
2884
2885 /* l4 core -> mcspi2 interface */
2886 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2887         .master         = &omap3xxx_l4_core_hwmod,
2888         .slave          = &omap34xx_mcspi2,
2889         .clk            = "mcspi2_ick",
2890         .addr           = omap2_mcspi2_addr_space,
2891         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2892 };
2893
2894 /* l4 core -> mcspi3 interface */
2895 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2896         .master         = &omap3xxx_l4_core_hwmod,
2897         .slave          = &omap34xx_mcspi3,
2898         .clk            = "mcspi3_ick",
2899         .addr           = omap2430_mcspi3_addr_space,
2900         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2901 };
2902
2903 /* l4 core -> mcspi4 interface */
2904 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2905         {
2906                 .pa_start       = 0x480ba000,
2907                 .pa_end         = 0x480ba0ff,
2908                 .flags          = ADDR_TYPE_RT,
2909         },
2910         { }
2911 };
2912
2913 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2914         .master         = &omap3xxx_l4_core_hwmod,
2915         .slave          = &omap34xx_mcspi4,
2916         .clk            = "mcspi4_ick",
2917         .addr           = omap34xx_mcspi4_addr_space,
2918         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2919 };
2920
2921 /*
2922  * 'mcspi' class
2923  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2924  * bus
2925  */
2926
2927 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2928         .rev_offs       = 0x0000,
2929         .sysc_offs      = 0x0010,
2930         .syss_offs      = 0x0014,
2931         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2932                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2933                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2934         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2935         .sysc_fields    = &omap_hwmod_sysc_type1,
2936 };
2937
2938 static struct omap_hwmod_class omap34xx_mcspi_class = {
2939         .name = "mcspi",
2940         .sysc = &omap34xx_mcspi_sysc,
2941         .rev = OMAP3_MCSPI_REV,
2942 };
2943
2944 /* mcspi1 */
2945 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
2946         { .name = "tx0", .dma_req = 35 },
2947         { .name = "rx0", .dma_req = 36 },
2948         { .name = "tx1", .dma_req = 37 },
2949         { .name = "rx1", .dma_req = 38 },
2950         { .name = "tx2", .dma_req = 39 },
2951         { .name = "rx2", .dma_req = 40 },
2952         { .name = "tx3", .dma_req = 41 },
2953         { .name = "rx3", .dma_req = 42 },
2954 };
2955
2956 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2957         &omap34xx_l4_core__mcspi1,
2958 };
2959
2960 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2961         .num_chipselect = 4,
2962 };
2963
2964 static struct omap_hwmod omap34xx_mcspi1 = {
2965         .name           = "mcspi1",
2966         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
2967         .sdma_reqs      = omap34xx_mcspi1_sdma_reqs,
2968         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
2969         .main_clk       = "mcspi1_fck",
2970         .prcm           = {
2971                 .omap2 = {
2972                         .module_offs = CORE_MOD,
2973                         .prcm_reg_id = 1,
2974                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2975                         .idlest_reg_id = 1,
2976                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2977                 },
2978         },
2979         .slaves         = omap34xx_mcspi1_slaves,
2980         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2981         .class          = &omap34xx_mcspi_class,
2982         .dev_attr       = &omap_mcspi1_dev_attr,
2983         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2984 };
2985
2986 /* mcspi2 */
2987 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
2988         { .name = "tx0", .dma_req = 43 },
2989         { .name = "rx0", .dma_req = 44 },
2990         { .name = "tx1", .dma_req = 45 },
2991         { .name = "rx1", .dma_req = 46 },
2992 };
2993
2994 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2995         &omap34xx_l4_core__mcspi2,
2996 };
2997
2998 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2999         .num_chipselect = 2,
3000 };
3001
3002 static struct omap_hwmod omap34xx_mcspi2 = {
3003         .name           = "mcspi2",
3004         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
3005         .sdma_reqs      = omap34xx_mcspi2_sdma_reqs,
3006         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
3007         .main_clk       = "mcspi2_fck",
3008         .prcm           = {
3009                 .omap2 = {
3010                         .module_offs = CORE_MOD,
3011                         .prcm_reg_id = 1,
3012                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
3013                         .idlest_reg_id = 1,
3014                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
3015                 },
3016         },
3017         .slaves         = omap34xx_mcspi2_slaves,
3018         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
3019         .class          = &omap34xx_mcspi_class,
3020         .dev_attr       = &omap_mcspi2_dev_attr,
3021         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3022 };
3023
3024 /* mcspi3 */
3025 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
3026         { .name = "irq", .irq = 91 }, /* 91 */
3027         { .irq = -1 }
3028 };
3029
3030 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
3031         { .name = "tx0", .dma_req = 15 },
3032         { .name = "rx0", .dma_req = 16 },
3033         { .name = "tx1", .dma_req = 23 },
3034         { .name = "rx1", .dma_req = 24 },
3035 };
3036
3037 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
3038         &omap34xx_l4_core__mcspi3,
3039 };
3040
3041 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
3042         .num_chipselect = 2,
3043 };
3044
3045 static struct omap_hwmod omap34xx_mcspi3 = {
3046         .name           = "mcspi3",
3047         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
3048         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
3049         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
3050         .main_clk       = "mcspi3_fck",
3051         .prcm           = {
3052                 .omap2 = {
3053                         .module_offs = CORE_MOD,
3054                         .prcm_reg_id = 1,
3055                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
3056                         .idlest_reg_id = 1,
3057                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
3058                 },
3059         },
3060         .slaves         = omap34xx_mcspi3_slaves,
3061         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3062         .class          = &omap34xx_mcspi_class,
3063         .dev_attr       = &omap_mcspi3_dev_attr,
3064         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3065 };
3066
3067 /* SPI4 */
3068 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3069         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3070         { .irq = -1 }
3071 };
3072
3073 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3074         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3075         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3076 };
3077
3078 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3079         &omap34xx_l4_core__mcspi4,
3080 };
3081
3082 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3083         .num_chipselect = 1,
3084 };
3085
3086 static struct omap_hwmod omap34xx_mcspi4 = {
3087         .name           = "mcspi4",
3088         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
3089         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
3090         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
3091         .main_clk       = "mcspi4_fck",
3092         .prcm           = {
3093                 .omap2 = {
3094                         .module_offs = CORE_MOD,
3095                         .prcm_reg_id = 1,
3096                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3097                         .idlest_reg_id = 1,
3098                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3099                 },
3100         },
3101         .slaves         = omap34xx_mcspi4_slaves,
3102         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3103         .class          = &omap34xx_mcspi_class,
3104         .dev_attr       = &omap_mcspi4_dev_attr,
3105         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3106 };
3107
3108 /*
3109  * usbhsotg
3110  */
3111 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3112         .rev_offs       = 0x0400,
3113         .sysc_offs      = 0x0404,
3114         .syss_offs      = 0x0408,
3115         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3116                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3117                           SYSC_HAS_AUTOIDLE),
3118         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3119                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3120         .sysc_fields    = &omap_hwmod_sysc_type1,
3121 };
3122
3123 static struct omap_hwmod_class usbotg_class = {
3124         .name = "usbotg",
3125         .sysc = &omap3xxx_usbhsotg_sysc,
3126 };
3127 /* usb_otg_hs */
3128 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3129
3130         { .name = "mc", .irq = 92 },
3131         { .name = "dma", .irq = 93 },
3132         { .irq = -1 }
3133 };
3134
3135 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3136         .name           = "usb_otg_hs",
3137         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
3138         .main_clk       = "hsotgusb_ick",
3139         .prcm           = {
3140                 .omap2 = {
3141                         .prcm_reg_id = 1,
3142                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3143                         .module_offs = CORE_MOD,
3144                         .idlest_reg_id = 1,
3145                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3146                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3147                 },
3148         },
3149         .masters        = omap3xxx_usbhsotg_masters,
3150         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3151         .slaves         = omap3xxx_usbhsotg_slaves,
3152         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3153         .class          = &usbotg_class,
3154
3155         /*
3156          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
3157          * broken when autoidle is enabled
3158          * workaround is to disable the autoidle bit at module level.
3159          */
3160         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3161                                 | HWMOD_SWSUP_MSTANDBY,
3162         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3163 };
3164
3165 /* usb_otg_hs */
3166 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3167
3168         { .name = "mc", .irq = 71 },
3169         { .irq = -1 }
3170 };
3171
3172 static struct omap_hwmod_class am35xx_usbotg_class = {
3173         .name = "am35xx_usbotg",
3174         .sysc = NULL,
3175 };
3176
3177 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3178         .name           = "am35x_otg_hs",
3179         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3180         .main_clk       = NULL,
3181         .prcm = {
3182                 .omap2 = {
3183                 },
3184         },
3185         .masters        = am35xx_usbhsotg_masters,
3186         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3187         .slaves         = am35xx_usbhsotg_slaves,
3188         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3189         .class          = &am35xx_usbotg_class,
3190         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3191 };
3192
3193 /* MMC/SD/SDIO common */
3194
3195 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3196         .rev_offs       = 0x1fc,
3197         .sysc_offs      = 0x10,
3198         .syss_offs      = 0x14,
3199         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3200                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3201                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3202         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3203         .sysc_fields    = &omap_hwmod_sysc_type1,
3204 };
3205
3206 static struct omap_hwmod_class omap34xx_mmc_class = {
3207         .name = "mmc",
3208         .sysc = &omap34xx_mmc_sysc,
3209 };
3210
3211 /* MMC/SD/SDIO1 */
3212
3213 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3214         { .irq = 83, },
3215         { .irq = -1 }
3216 };
3217
3218 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3219         { .name = "tx", .dma_req = 61, },
3220         { .name = "rx", .dma_req = 62, },
3221 };
3222
3223 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3224         { .role = "dbck", .clk = "omap_32k_fck", },
3225 };
3226
3227 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3228         &omap3xxx_l4_core__mmc1,
3229 };
3230
3231 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3232         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3233 };
3234
3235 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3236         .name           = "mmc1",
3237         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3238         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3239         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3240         .opt_clks       = omap34xx_mmc1_opt_clks,
3241         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3242         .main_clk       = "mmchs1_fck",
3243         .prcm           = {
3244                 .omap2 = {
3245                         .module_offs = CORE_MOD,
3246                         .prcm_reg_id = 1,
3247                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3248                         .idlest_reg_id = 1,
3249                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3250                 },
3251         },
3252         .dev_attr       = &mmc1_dev_attr,
3253         .slaves         = omap3xxx_mmc1_slaves,
3254         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3255         .class          = &omap34xx_mmc_class,
3256         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3257 };
3258
3259 /* MMC/SD/SDIO2 */
3260
3261 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3262         { .irq = INT_24XX_MMC2_IRQ, },
3263         { .irq = -1 }
3264 };
3265
3266 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3267         { .name = "tx", .dma_req = 47, },
3268         { .name = "rx", .dma_req = 48, },
3269 };
3270
3271 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3272         { .role = "dbck", .clk = "omap_32k_fck", },
3273 };
3274
3275 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3276         &omap3xxx_l4_core__mmc2,
3277 };
3278
3279 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3280         .name           = "mmc2",
3281         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3282         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3283         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3284         .opt_clks       = omap34xx_mmc2_opt_clks,
3285         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3286         .main_clk       = "mmchs2_fck",
3287         .prcm           = {
3288                 .omap2 = {
3289                         .module_offs = CORE_MOD,
3290                         .prcm_reg_id = 1,
3291                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3292                         .idlest_reg_id = 1,
3293                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3294                 },
3295         },
3296         .slaves         = omap3xxx_mmc2_slaves,
3297         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3298         .class          = &omap34xx_mmc_class,
3299         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3300 };
3301
3302 /* MMC/SD/SDIO3 */
3303
3304 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3305         { .irq = 94, },
3306         { .irq = -1 }
3307 };
3308
3309 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3310         { .name = "tx", .dma_req = 77, },
3311         { .name = "rx", .dma_req = 78, },
3312 };
3313
3314 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3315         { .role = "dbck", .clk = "omap_32k_fck", },
3316 };
3317
3318 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3319         &omap3xxx_l4_core__mmc3,
3320 };
3321
3322 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3323         .name           = "mmc3",
3324         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3325         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3326         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3327         .opt_clks       = omap34xx_mmc3_opt_clks,
3328         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3329         .main_clk       = "mmchs3_fck",
3330         .prcm           = {
3331                 .omap2 = {
3332                         .prcm_reg_id = 1,
3333                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3334                         .idlest_reg_id = 1,
3335                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3336                 },
3337         },
3338         .slaves         = omap3xxx_mmc3_slaves,
3339         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3340         .class          = &omap34xx_mmc_class,
3341         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3342 };
3343
3344 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3345         &omap3xxx_l3_main_hwmod,
3346         &omap3xxx_l4_core_hwmod,
3347         &omap3xxx_l4_per_hwmod,
3348         &omap3xxx_l4_wkup_hwmod,
3349         &omap3xxx_mmc1_hwmod,
3350         &omap3xxx_mmc2_hwmod,
3351         &omap3xxx_mmc3_hwmod,
3352         &omap3xxx_mpu_hwmod,
3353         &omap3xxx_iva_hwmod,
3354
3355         &omap3xxx_timer1_hwmod,
3356         &omap3xxx_timer2_hwmod,
3357         &omap3xxx_timer3_hwmod,
3358         &omap3xxx_timer4_hwmod,
3359         &omap3xxx_timer5_hwmod,
3360         &omap3xxx_timer6_hwmod,
3361         &omap3xxx_timer7_hwmod,
3362         &omap3xxx_timer8_hwmod,
3363         &omap3xxx_timer9_hwmod,
3364         &omap3xxx_timer10_hwmod,
3365         &omap3xxx_timer11_hwmod,
3366         &omap3xxx_timer12_hwmod,
3367
3368         &omap3xxx_wd_timer2_hwmod,
3369         &omap3xxx_uart1_hwmod,
3370         &omap3xxx_uart2_hwmod,
3371         &omap3xxx_uart3_hwmod,
3372         &omap3xxx_uart4_hwmod,
3373         /* dss class */
3374         &omap3430es1_dss_core_hwmod,
3375         &omap3xxx_dss_core_hwmod,
3376         &omap3xxx_dss_dispc_hwmod,
3377         &omap3xxx_dss_dsi1_hwmod,
3378         &omap3xxx_dss_rfbi_hwmod,
3379         &omap3xxx_dss_venc_hwmod,
3380
3381         /* i2c class */
3382         &omap3xxx_i2c1_hwmod,
3383         &omap3xxx_i2c2_hwmod,
3384         &omap3xxx_i2c3_hwmod,
3385         &omap34xx_sr1_hwmod,
3386         &omap34xx_sr2_hwmod,
3387         &omap36xx_sr1_hwmod,
3388         &omap36xx_sr2_hwmod,
3389
3390
3391         /* gpio class */
3392         &omap3xxx_gpio1_hwmod,
3393         &omap3xxx_gpio2_hwmod,
3394         &omap3xxx_gpio3_hwmod,
3395         &omap3xxx_gpio4_hwmod,
3396         &omap3xxx_gpio5_hwmod,
3397         &omap3xxx_gpio6_hwmod,
3398
3399         /* dma_system class*/
3400         &omap3xxx_dma_system_hwmod,
3401
3402         /* mcbsp class */
3403         &omap3xxx_mcbsp1_hwmod,
3404         &omap3xxx_mcbsp2_hwmod,
3405         &omap3xxx_mcbsp3_hwmod,
3406         &omap3xxx_mcbsp4_hwmod,
3407         &omap3xxx_mcbsp5_hwmod,
3408         &omap3xxx_mcbsp2_sidetone_hwmod,
3409         &omap3xxx_mcbsp3_sidetone_hwmod,
3410
3411         /* mailbox class */
3412         &omap3xxx_mailbox_hwmod,
3413
3414         /* mcspi class */
3415         &omap34xx_mcspi1,
3416         &omap34xx_mcspi2,
3417         &omap34xx_mcspi3,
3418         &omap34xx_mcspi4,
3419
3420         /* usbotg class */
3421         &omap3xxx_usbhsotg_hwmod,
3422
3423         /* usbotg for am35x */
3424         &am35xx_usbhsotg_hwmod,
3425
3426         NULL,
3427 };
3428
3429 int __init omap3xxx_hwmod_init(void)
3430 {
3431         return omap_hwmod_register(omap3xxx_hwmods);
3432 }