2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2010 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
14 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
24 #include <plat/gpio.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod_common_data.h"
32 #include "prm-regbits-34xx.h"
33 #include "cm-regbits-34xx.h"
35 #include <mach/am35xx.h>
38 * OMAP3xxx hardware module integration data
40 * ALl of the data in this section should be autogeneratable from the
41 * TI hardware database or other technical documentation. Data that
42 * is driver-specific or driver-kernel integration-specific belongs
46 static struct omap_hwmod omap3xxx_mpu_hwmod;
47 static struct omap_hwmod omap3xxx_iva_hwmod;
48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
67 static struct omap_hwmod omap34xx_sr1_hwmod;
68 static struct omap_hwmod omap34xx_sr2_hwmod;
69 static struct omap_hwmod omap34xx_mcspi1;
70 static struct omap_hwmod omap34xx_mcspi2;
71 static struct omap_hwmod omap34xx_mcspi3;
72 static struct omap_hwmod omap34xx_mcspi4;
73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
88 /* L3 -> L4_CORE interface */
89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
90 .master = &omap3xxx_l3_main_hwmod,
91 .slave = &omap3xxx_l4_core_hwmod,
92 .user = OCP_USER_MPU | OCP_USER_SDMA,
95 /* L3 -> L4_PER interface */
96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
97 .master = &omap3xxx_l3_main_hwmod,
98 .slave = &omap3xxx_l4_per_hwmod,
99 .user = OCP_USER_MPU | OCP_USER_SDMA,
102 /* L3 taret configuration and error log registers */
103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
104 { .irq = INT_34XX_L3_DBG_IRQ },
105 { .irq = INT_34XX_L3_APP_IRQ },
108 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
110 .pa_start = 0x68000000,
111 .pa_end = 0x6800ffff,
112 .flags = ADDR_TYPE_RT,
116 /* MPU -> L3 interface */
117 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
118 .master = &omap3xxx_mpu_hwmod,
119 .slave = &omap3xxx_l3_main_hwmod,
120 .addr = omap3xxx_l3_main_addrs,
121 .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
122 .user = OCP_USER_MPU,
125 /* Slave interfaces on the L3 interconnect */
126 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
127 &omap3xxx_mpu__l3_main,
131 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
132 .master = &omap3xxx_dss_core_hwmod,
133 .slave = &omap3xxx_l3_main_hwmod,
136 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
137 .flags = OMAP_FIREWALL_L3,
140 .user = OCP_USER_MPU | OCP_USER_SDMA,
143 /* Master interfaces on the L3 interconnect */
144 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
145 &omap3xxx_l3_main__l4_core,
146 &omap3xxx_l3_main__l4_per,
150 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
152 .class = &l3_hwmod_class,
153 .mpu_irqs = omap3xxx_l3_main_irqs,
154 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs),
155 .masters = omap3xxx_l3_main_masters,
156 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
157 .slaves = omap3xxx_l3_main_slaves,
158 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
159 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
160 .flags = HWMOD_NO_IDLEST,
163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
164 static struct omap_hwmod omap3xxx_uart1_hwmod;
165 static struct omap_hwmod omap3xxx_uart2_hwmod;
166 static struct omap_hwmod omap3xxx_uart3_hwmod;
167 static struct omap_hwmod omap3xxx_uart4_hwmod;
168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
170 /* l3_core -> usbhsotg interface */
171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
172 .master = &omap3xxx_usbhsotg_hwmod,
173 .slave = &omap3xxx_l3_main_hwmod,
174 .clk = "core_l3_ick",
175 .user = OCP_USER_MPU,
178 /* l3_core -> am35xx_usbhsotg interface */
179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
180 .master = &am35xx_usbhsotg_hwmod,
181 .slave = &omap3xxx_l3_main_hwmod,
182 .clk = "core_l3_ick",
183 .user = OCP_USER_MPU,
185 /* L4_CORE -> L4_WKUP interface */
186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
187 .master = &omap3xxx_l4_core_hwmod,
188 .slave = &omap3xxx_l4_wkup_hwmod,
189 .user = OCP_USER_MPU | OCP_USER_SDMA,
192 /* L4 CORE -> MMC1 interface */
193 static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
195 .pa_start = 0x4809c000,
196 .pa_end = 0x4809c1ff,
197 .flags = ADDR_TYPE_RT,
201 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
202 .master = &omap3xxx_l4_core_hwmod,
203 .slave = &omap3xxx_mmc1_hwmod,
205 .addr = omap3xxx_mmc1_addr_space,
206 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
207 .user = OCP_USER_MPU | OCP_USER_SDMA,
208 .flags = OMAP_FIREWALL_L4
211 /* L4 CORE -> MMC2 interface */
212 static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
214 .pa_start = 0x480b4000,
215 .pa_end = 0x480b41ff,
216 .flags = ADDR_TYPE_RT,
220 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
221 .master = &omap3xxx_l4_core_hwmod,
222 .slave = &omap3xxx_mmc2_hwmod,
224 .addr = omap3xxx_mmc2_addr_space,
225 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
226 .user = OCP_USER_MPU | OCP_USER_SDMA,
227 .flags = OMAP_FIREWALL_L4
230 /* L4 CORE -> MMC3 interface */
231 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
233 .pa_start = 0x480ad000,
234 .pa_end = 0x480ad1ff,
235 .flags = ADDR_TYPE_RT,
239 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
240 .master = &omap3xxx_l4_core_hwmod,
241 .slave = &omap3xxx_mmc3_hwmod,
243 .addr = omap3xxx_mmc3_addr_space,
244 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
245 .user = OCP_USER_MPU | OCP_USER_SDMA,
246 .flags = OMAP_FIREWALL_L4
249 /* L4 CORE -> UART1 interface */
250 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
252 .pa_start = OMAP3_UART1_BASE,
253 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
254 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
258 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
259 .master = &omap3xxx_l4_core_hwmod,
260 .slave = &omap3xxx_uart1_hwmod,
262 .addr = omap3xxx_uart1_addr_space,
263 .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
264 .user = OCP_USER_MPU | OCP_USER_SDMA,
267 /* L4 CORE -> UART2 interface */
268 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
270 .pa_start = OMAP3_UART2_BASE,
271 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
272 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
276 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
277 .master = &omap3xxx_l4_core_hwmod,
278 .slave = &omap3xxx_uart2_hwmod,
280 .addr = omap3xxx_uart2_addr_space,
281 .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
282 .user = OCP_USER_MPU | OCP_USER_SDMA,
285 /* L4 PER -> UART3 interface */
286 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
288 .pa_start = OMAP3_UART3_BASE,
289 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
290 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
294 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
295 .master = &omap3xxx_l4_per_hwmod,
296 .slave = &omap3xxx_uart3_hwmod,
298 .addr = omap3xxx_uart3_addr_space,
299 .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
300 .user = OCP_USER_MPU | OCP_USER_SDMA,
303 /* L4 PER -> UART4 interface */
304 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
306 .pa_start = OMAP3_UART4_BASE,
307 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
308 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
312 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
313 .master = &omap3xxx_l4_per_hwmod,
314 .slave = &omap3xxx_uart4_hwmod,
316 .addr = omap3xxx_uart4_addr_space,
317 .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
318 .user = OCP_USER_MPU | OCP_USER_SDMA,
321 /* I2C IP block address space length (in bytes) */
322 #define OMAP2_I2C_AS_LEN 128
324 /* L4 CORE -> I2C1 interface */
325 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
327 .pa_start = 0x48070000,
328 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
329 .flags = ADDR_TYPE_RT,
333 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
334 .master = &omap3xxx_l4_core_hwmod,
335 .slave = &omap3xxx_i2c1_hwmod,
337 .addr = omap3xxx_i2c1_addr_space,
338 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
341 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
343 .flags = OMAP_FIREWALL_L4,
346 .user = OCP_USER_MPU | OCP_USER_SDMA,
349 /* L4 CORE -> I2C2 interface */
350 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
352 .pa_start = 0x48072000,
353 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
354 .flags = ADDR_TYPE_RT,
358 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
359 .master = &omap3xxx_l4_core_hwmod,
360 .slave = &omap3xxx_i2c2_hwmod,
362 .addr = omap3xxx_i2c2_addr_space,
363 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
366 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
368 .flags = OMAP_FIREWALL_L4,
371 .user = OCP_USER_MPU | OCP_USER_SDMA,
374 /* L4 CORE -> I2C3 interface */
375 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
377 .pa_start = 0x48060000,
378 .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
379 .flags = ADDR_TYPE_RT,
383 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
384 .master = &omap3xxx_l4_core_hwmod,
385 .slave = &omap3xxx_i2c3_hwmod,
387 .addr = omap3xxx_i2c3_addr_space,
388 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
391 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
393 .flags = OMAP_FIREWALL_L4,
396 .user = OCP_USER_MPU | OCP_USER_SDMA,
399 /* L4 CORE -> SR1 interface */
400 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
402 .pa_start = OMAP34XX_SR1_BASE,
403 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
404 .flags = ADDR_TYPE_RT,
408 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
409 .master = &omap3xxx_l4_core_hwmod,
410 .slave = &omap34xx_sr1_hwmod,
412 .addr = omap3_sr1_addr_space,
413 .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
414 .user = OCP_USER_MPU,
417 /* L4 CORE -> SR1 interface */
418 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
420 .pa_start = OMAP34XX_SR2_BASE,
421 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
422 .flags = ADDR_TYPE_RT,
426 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
427 .master = &omap3xxx_l4_core_hwmod,
428 .slave = &omap34xx_sr2_hwmod,
430 .addr = omap3_sr2_addr_space,
431 .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
432 .user = OCP_USER_MPU,
436 * usbhsotg interface data
439 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
441 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
442 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
443 .flags = ADDR_TYPE_RT
447 /* l4_core -> usbhsotg */
448 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
449 .master = &omap3xxx_l4_core_hwmod,
450 .slave = &omap3xxx_usbhsotg_hwmod,
452 .addr = omap3xxx_usbhsotg_addrs,
453 .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
454 .user = OCP_USER_MPU,
457 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
458 &omap3xxx_usbhsotg__l3,
461 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
462 &omap3xxx_l4_core__usbhsotg,
465 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
467 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
468 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
469 .flags = ADDR_TYPE_RT
473 /* l4_core -> usbhsotg */
474 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
475 .master = &omap3xxx_l4_core_hwmod,
476 .slave = &am35xx_usbhsotg_hwmod,
478 .addr = am35xx_usbhsotg_addrs,
479 .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
480 .user = OCP_USER_MPU,
483 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
484 &am35xx_usbhsotg__l3,
487 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
488 &am35xx_l4_core__usbhsotg,
490 /* Slave interfaces on the L4_CORE interconnect */
491 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
492 &omap3xxx_l3_main__l4_core,
496 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
498 .class = &l4_hwmod_class,
499 .slaves = omap3xxx_l4_core_slaves,
500 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
501 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
502 .flags = HWMOD_NO_IDLEST,
505 /* Slave interfaces on the L4_PER interconnect */
506 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
507 &omap3xxx_l3_main__l4_per,
511 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
513 .class = &l4_hwmod_class,
514 .slaves = omap3xxx_l4_per_slaves,
515 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
516 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
517 .flags = HWMOD_NO_IDLEST,
520 /* Slave interfaces on the L4_WKUP interconnect */
521 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
522 &omap3xxx_l4_core__l4_wkup,
526 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
528 .class = &l4_hwmod_class,
529 .slaves = omap3xxx_l4_wkup_slaves,
530 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
531 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
532 .flags = HWMOD_NO_IDLEST,
535 /* Master interfaces on the MPU device */
536 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
537 &omap3xxx_mpu__l3_main,
541 static struct omap_hwmod omap3xxx_mpu_hwmod = {
543 .class = &mpu_hwmod_class,
544 .main_clk = "arm_fck",
545 .masters = omap3xxx_mpu_masters,
546 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
547 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
551 * IVA2_2 interface data
554 /* IVA2 <- L3 interface */
555 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
556 .master = &omap3xxx_l3_main_hwmod,
557 .slave = &omap3xxx_iva_hwmod,
559 .user = OCP_USER_MPU | OCP_USER_SDMA,
562 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
570 static struct omap_hwmod omap3xxx_iva_hwmod = {
572 .class = &iva_hwmod_class,
573 .masters = omap3xxx_iva_masters,
574 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
575 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
579 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
583 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
584 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
585 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
586 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
587 .sysc_fields = &omap_hwmod_sysc_type1,
590 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
592 .sysc = &omap3xxx_timer_1ms_sysc,
593 .rev = OMAP_TIMER_IP_VERSION_1,
596 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
600 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
601 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
602 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
603 .sysc_fields = &omap_hwmod_sysc_type1,
606 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
608 .sysc = &omap3xxx_timer_sysc,
609 .rev = OMAP_TIMER_IP_VERSION_1,
613 static struct omap_hwmod omap3xxx_timer1_hwmod;
614 static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
618 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
620 .pa_start = 0x48318000,
621 .pa_end = 0x48318000 + SZ_1K - 1,
622 .flags = ADDR_TYPE_RT
626 /* l4_wkup -> timer1 */
627 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
628 .master = &omap3xxx_l4_wkup_hwmod,
629 .slave = &omap3xxx_timer1_hwmod,
631 .addr = omap3xxx_timer1_addrs,
632 .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
633 .user = OCP_USER_MPU | OCP_USER_SDMA,
636 /* timer1 slave port */
637 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
638 &omap3xxx_l4_wkup__timer1,
642 static struct omap_hwmod omap3xxx_timer1_hwmod = {
644 .mpu_irqs = omap3xxx_timer1_mpu_irqs,
645 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
646 .main_clk = "gpt1_fck",
650 .module_bit = OMAP3430_EN_GPT1_SHIFT,
651 .module_offs = WKUP_MOD,
653 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
656 .slaves = omap3xxx_timer1_slaves,
657 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
658 .class = &omap3xxx_timer_1ms_hwmod_class,
659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
663 static struct omap_hwmod omap3xxx_timer2_hwmod;
664 static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
668 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
670 .pa_start = 0x49032000,
671 .pa_end = 0x49032000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT
676 /* l4_per -> timer2 */
677 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
678 .master = &omap3xxx_l4_per_hwmod,
679 .slave = &omap3xxx_timer2_hwmod,
681 .addr = omap3xxx_timer2_addrs,
682 .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
683 .user = OCP_USER_MPU | OCP_USER_SDMA,
686 /* timer2 slave port */
687 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
688 &omap3xxx_l4_per__timer2,
692 static struct omap_hwmod omap3xxx_timer2_hwmod = {
694 .mpu_irqs = omap3xxx_timer2_mpu_irqs,
695 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
696 .main_clk = "gpt2_fck",
700 .module_bit = OMAP3430_EN_GPT2_SHIFT,
701 .module_offs = OMAP3430_PER_MOD,
703 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
706 .slaves = omap3xxx_timer2_slaves,
707 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
708 .class = &omap3xxx_timer_1ms_hwmod_class,
709 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
713 static struct omap_hwmod omap3xxx_timer3_hwmod;
714 static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
718 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
720 .pa_start = 0x49034000,
721 .pa_end = 0x49034000 + SZ_1K - 1,
722 .flags = ADDR_TYPE_RT
726 /* l4_per -> timer3 */
727 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
728 .master = &omap3xxx_l4_per_hwmod,
729 .slave = &omap3xxx_timer3_hwmod,
731 .addr = omap3xxx_timer3_addrs,
732 .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
733 .user = OCP_USER_MPU | OCP_USER_SDMA,
736 /* timer3 slave port */
737 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
738 &omap3xxx_l4_per__timer3,
742 static struct omap_hwmod omap3xxx_timer3_hwmod = {
744 .mpu_irqs = omap3xxx_timer3_mpu_irqs,
745 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
746 .main_clk = "gpt3_fck",
750 .module_bit = OMAP3430_EN_GPT3_SHIFT,
751 .module_offs = OMAP3430_PER_MOD,
753 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
756 .slaves = omap3xxx_timer3_slaves,
757 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
758 .class = &omap3xxx_timer_hwmod_class,
759 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
763 static struct omap_hwmod omap3xxx_timer4_hwmod;
764 static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
768 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
770 .pa_start = 0x49036000,
771 .pa_end = 0x49036000 + SZ_1K - 1,
772 .flags = ADDR_TYPE_RT
776 /* l4_per -> timer4 */
777 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
778 .master = &omap3xxx_l4_per_hwmod,
779 .slave = &omap3xxx_timer4_hwmod,
781 .addr = omap3xxx_timer4_addrs,
782 .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
783 .user = OCP_USER_MPU | OCP_USER_SDMA,
786 /* timer4 slave port */
787 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
788 &omap3xxx_l4_per__timer4,
792 static struct omap_hwmod omap3xxx_timer4_hwmod = {
794 .mpu_irqs = omap3xxx_timer4_mpu_irqs,
795 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
796 .main_clk = "gpt4_fck",
800 .module_bit = OMAP3430_EN_GPT4_SHIFT,
801 .module_offs = OMAP3430_PER_MOD,
803 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
806 .slaves = omap3xxx_timer4_slaves,
807 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
808 .class = &omap3xxx_timer_hwmod_class,
809 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
813 static struct omap_hwmod omap3xxx_timer5_hwmod;
814 static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
818 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
820 .pa_start = 0x49038000,
821 .pa_end = 0x49038000 + SZ_1K - 1,
822 .flags = ADDR_TYPE_RT
826 /* l4_per -> timer5 */
827 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
828 .master = &omap3xxx_l4_per_hwmod,
829 .slave = &omap3xxx_timer5_hwmod,
831 .addr = omap3xxx_timer5_addrs,
832 .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
833 .user = OCP_USER_MPU | OCP_USER_SDMA,
836 /* timer5 slave port */
837 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
838 &omap3xxx_l4_per__timer5,
842 static struct omap_hwmod omap3xxx_timer5_hwmod = {
844 .mpu_irqs = omap3xxx_timer5_mpu_irqs,
845 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
846 .main_clk = "gpt5_fck",
850 .module_bit = OMAP3430_EN_GPT5_SHIFT,
851 .module_offs = OMAP3430_PER_MOD,
853 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
856 .slaves = omap3xxx_timer5_slaves,
857 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
858 .class = &omap3xxx_timer_hwmod_class,
859 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
863 static struct omap_hwmod omap3xxx_timer6_hwmod;
864 static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
868 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
870 .pa_start = 0x4903A000,
871 .pa_end = 0x4903A000 + SZ_1K - 1,
872 .flags = ADDR_TYPE_RT
876 /* l4_per -> timer6 */
877 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
878 .master = &omap3xxx_l4_per_hwmod,
879 .slave = &omap3xxx_timer6_hwmod,
881 .addr = omap3xxx_timer6_addrs,
882 .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
883 .user = OCP_USER_MPU | OCP_USER_SDMA,
886 /* timer6 slave port */
887 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
888 &omap3xxx_l4_per__timer6,
892 static struct omap_hwmod omap3xxx_timer6_hwmod = {
894 .mpu_irqs = omap3xxx_timer6_mpu_irqs,
895 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
896 .main_clk = "gpt6_fck",
900 .module_bit = OMAP3430_EN_GPT6_SHIFT,
901 .module_offs = OMAP3430_PER_MOD,
903 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
906 .slaves = omap3xxx_timer6_slaves,
907 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
908 .class = &omap3xxx_timer_hwmod_class,
909 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
913 static struct omap_hwmod omap3xxx_timer7_hwmod;
914 static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
918 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
920 .pa_start = 0x4903C000,
921 .pa_end = 0x4903C000 + SZ_1K - 1,
922 .flags = ADDR_TYPE_RT
926 /* l4_per -> timer7 */
927 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
928 .master = &omap3xxx_l4_per_hwmod,
929 .slave = &omap3xxx_timer7_hwmod,
931 .addr = omap3xxx_timer7_addrs,
932 .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
933 .user = OCP_USER_MPU | OCP_USER_SDMA,
936 /* timer7 slave port */
937 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
938 &omap3xxx_l4_per__timer7,
942 static struct omap_hwmod omap3xxx_timer7_hwmod = {
944 .mpu_irqs = omap3xxx_timer7_mpu_irqs,
945 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
946 .main_clk = "gpt7_fck",
950 .module_bit = OMAP3430_EN_GPT7_SHIFT,
951 .module_offs = OMAP3430_PER_MOD,
953 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
956 .slaves = omap3xxx_timer7_slaves,
957 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
958 .class = &omap3xxx_timer_hwmod_class,
959 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
963 static struct omap_hwmod omap3xxx_timer8_hwmod;
964 static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
968 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
970 .pa_start = 0x4903E000,
971 .pa_end = 0x4903E000 + SZ_1K - 1,
972 .flags = ADDR_TYPE_RT
976 /* l4_per -> timer8 */
977 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
978 .master = &omap3xxx_l4_per_hwmod,
979 .slave = &omap3xxx_timer8_hwmod,
981 .addr = omap3xxx_timer8_addrs,
982 .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
983 .user = OCP_USER_MPU | OCP_USER_SDMA,
986 /* timer8 slave port */
987 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
988 &omap3xxx_l4_per__timer8,
992 static struct omap_hwmod omap3xxx_timer8_hwmod = {
994 .mpu_irqs = omap3xxx_timer8_mpu_irqs,
995 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
996 .main_clk = "gpt8_fck",
1000 .module_bit = OMAP3430_EN_GPT8_SHIFT,
1001 .module_offs = OMAP3430_PER_MOD,
1003 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
1006 .slaves = omap3xxx_timer8_slaves,
1007 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
1008 .class = &omap3xxx_timer_hwmod_class,
1009 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1013 static struct omap_hwmod omap3xxx_timer9_hwmod;
1014 static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
1018 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
1020 .pa_start = 0x49040000,
1021 .pa_end = 0x49040000 + SZ_1K - 1,
1022 .flags = ADDR_TYPE_RT
1026 /* l4_per -> timer9 */
1027 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1028 .master = &omap3xxx_l4_per_hwmod,
1029 .slave = &omap3xxx_timer9_hwmod,
1031 .addr = omap3xxx_timer9_addrs,
1032 .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
1033 .user = OCP_USER_MPU | OCP_USER_SDMA,
1036 /* timer9 slave port */
1037 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1038 &omap3xxx_l4_per__timer9,
1042 static struct omap_hwmod omap3xxx_timer9_hwmod = {
1044 .mpu_irqs = omap3xxx_timer9_mpu_irqs,
1045 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
1046 .main_clk = "gpt9_fck",
1050 .module_bit = OMAP3430_EN_GPT9_SHIFT,
1051 .module_offs = OMAP3430_PER_MOD,
1053 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1056 .slaves = omap3xxx_timer9_slaves,
1057 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
1058 .class = &omap3xxx_timer_hwmod_class,
1059 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1063 static struct omap_hwmod omap3xxx_timer10_hwmod;
1064 static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1068 static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
1070 .pa_start = 0x48086000,
1071 .pa_end = 0x48086000 + SZ_1K - 1,
1072 .flags = ADDR_TYPE_RT
1076 /* l4_core -> timer10 */
1077 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1078 .master = &omap3xxx_l4_core_hwmod,
1079 .slave = &omap3xxx_timer10_hwmod,
1081 .addr = omap3xxx_timer10_addrs,
1082 .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
1083 .user = OCP_USER_MPU | OCP_USER_SDMA,
1086 /* timer10 slave port */
1087 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1088 &omap3xxx_l4_core__timer10,
1092 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1094 .mpu_irqs = omap3xxx_timer10_mpu_irqs,
1095 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
1096 .main_clk = "gpt10_fck",
1100 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1101 .module_offs = CORE_MOD,
1103 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1106 .slaves = omap3xxx_timer10_slaves,
1107 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1108 .class = &omap3xxx_timer_1ms_hwmod_class,
1109 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1113 static struct omap_hwmod omap3xxx_timer11_hwmod;
1114 static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1118 static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
1120 .pa_start = 0x48088000,
1121 .pa_end = 0x48088000 + SZ_1K - 1,
1122 .flags = ADDR_TYPE_RT
1126 /* l4_core -> timer11 */
1127 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1128 .master = &omap3xxx_l4_core_hwmod,
1129 .slave = &omap3xxx_timer11_hwmod,
1131 .addr = omap3xxx_timer11_addrs,
1132 .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
1133 .user = OCP_USER_MPU | OCP_USER_SDMA,
1136 /* timer11 slave port */
1137 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1138 &omap3xxx_l4_core__timer11,
1142 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1144 .mpu_irqs = omap3xxx_timer11_mpu_irqs,
1145 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
1146 .main_clk = "gpt11_fck",
1150 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1151 .module_offs = CORE_MOD,
1153 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1156 .slaves = omap3xxx_timer11_slaves,
1157 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1158 .class = &omap3xxx_timer_hwmod_class,
1159 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1163 static struct omap_hwmod omap3xxx_timer12_hwmod;
1164 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1168 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1170 .pa_start = 0x48304000,
1171 .pa_end = 0x48304000 + SZ_1K - 1,
1172 .flags = ADDR_TYPE_RT
1176 /* l4_core -> timer12 */
1177 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1178 .master = &omap3xxx_l4_core_hwmod,
1179 .slave = &omap3xxx_timer12_hwmod,
1181 .addr = omap3xxx_timer12_addrs,
1182 .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs),
1183 .user = OCP_USER_MPU | OCP_USER_SDMA,
1186 /* timer12 slave port */
1187 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1188 &omap3xxx_l4_core__timer12,
1192 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1194 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1195 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
1196 .main_clk = "gpt12_fck",
1200 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1201 .module_offs = WKUP_MOD,
1203 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1206 .slaves = omap3xxx_timer12_slaves,
1207 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1208 .class = &omap3xxx_timer_hwmod_class,
1209 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1212 /* l4_wkup -> wd_timer2 */
1213 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1215 .pa_start = 0x48314000,
1216 .pa_end = 0x4831407f,
1217 .flags = ADDR_TYPE_RT
1221 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1222 .master = &omap3xxx_l4_wkup_hwmod,
1223 .slave = &omap3xxx_wd_timer2_hwmod,
1225 .addr = omap3xxx_wd_timer2_addrs,
1226 .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
1227 .user = OCP_USER_MPU | OCP_USER_SDMA,
1232 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1233 * overflow condition
1236 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1238 .sysc_offs = 0x0010,
1239 .syss_offs = 0x0014,
1240 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1241 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1242 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1243 SYSS_HAS_RESET_STATUS),
1244 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1245 .sysc_fields = &omap_hwmod_sysc_type1,
1249 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1253 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1254 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1255 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1256 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1257 .sysc_fields = &omap_hwmod_sysc_type1,
1260 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1262 .sysc = &omap3xxx_wd_timer_sysc,
1263 .pre_shutdown = &omap2_wd_timer_disable
1267 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1268 &omap3xxx_l4_wkup__wd_timer2,
1271 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1272 .name = "wd_timer2",
1273 .class = &omap3xxx_wd_timer_hwmod_class,
1274 .main_clk = "wdt2_fck",
1278 .module_bit = OMAP3430_EN_WDT2_SHIFT,
1279 .module_offs = WKUP_MOD,
1281 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1284 .slaves = omap3xxx_wd_timer2_slaves,
1285 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1286 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1288 * XXX: Use software supervised mode, HW supervised smartidle seems to
1289 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1291 .flags = HWMOD_SWSUP_SIDLE,
1296 static struct omap_hwmod_class_sysconfig uart_sysc = {
1300 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1301 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1302 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1303 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1304 .sysc_fields = &omap_hwmod_sysc_type1,
1307 static struct omap_hwmod_class uart_class = {
1314 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1315 { .irq = INT_24XX_UART1_IRQ, },
1318 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1319 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1320 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1323 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1324 &omap3_l4_core__uart1,
1327 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1329 .mpu_irqs = uart1_mpu_irqs,
1330 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
1331 .sdma_reqs = uart1_sdma_reqs,
1332 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1333 .main_clk = "uart1_fck",
1336 .module_offs = CORE_MOD,
1338 .module_bit = OMAP3430_EN_UART1_SHIFT,
1340 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1343 .slaves = omap3xxx_uart1_slaves,
1344 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1345 .class = &uart_class,
1346 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1351 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1352 { .irq = INT_24XX_UART2_IRQ, },
1355 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1356 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1357 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1360 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1361 &omap3_l4_core__uart2,
1364 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1366 .mpu_irqs = uart2_mpu_irqs,
1367 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
1368 .sdma_reqs = uart2_sdma_reqs,
1369 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1370 .main_clk = "uart2_fck",
1373 .module_offs = CORE_MOD,
1375 .module_bit = OMAP3430_EN_UART2_SHIFT,
1377 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1380 .slaves = omap3xxx_uart2_slaves,
1381 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1382 .class = &uart_class,
1383 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1388 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1389 { .irq = INT_24XX_UART3_IRQ, },
1392 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1393 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1394 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1397 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1398 &omap3_l4_per__uart3,
1401 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1403 .mpu_irqs = uart3_mpu_irqs,
1404 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
1405 .sdma_reqs = uart3_sdma_reqs,
1406 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1407 .main_clk = "uart3_fck",
1410 .module_offs = OMAP3430_PER_MOD,
1412 .module_bit = OMAP3430_EN_UART3_SHIFT,
1414 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1417 .slaves = omap3xxx_uart3_slaves,
1418 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1419 .class = &uart_class,
1420 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1425 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1426 { .irq = INT_36XX_UART4_IRQ, },
1429 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1430 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1431 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1434 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1435 &omap3_l4_per__uart4,
1438 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1440 .mpu_irqs = uart4_mpu_irqs,
1441 .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
1442 .sdma_reqs = uart4_sdma_reqs,
1443 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
1444 .main_clk = "uart4_fck",
1447 .module_offs = OMAP3430_PER_MOD,
1449 .module_bit = OMAP3630_EN_UART4_SHIFT,
1451 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1454 .slaves = omap3xxx_uart4_slaves,
1455 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1456 .class = &uart_class,
1457 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1460 static struct omap_hwmod_class i2c_class = {
1467 * display sub-system
1470 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1472 .sysc_offs = 0x0010,
1473 .syss_offs = 0x0014,
1474 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1475 .sysc_fields = &omap_hwmod_sysc_type1,
1478 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1480 .sysc = &omap3xxx_dss_sysc,
1484 static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = {
1488 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1489 { .name = "dispc", .dma_req = 5 },
1490 { .name = "dsi1", .dma_req = 74 },
1494 /* dss master ports */
1495 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1499 static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
1501 .pa_start = 0x48050000,
1502 .pa_end = 0x480503FF,
1503 .flags = ADDR_TYPE_RT
1507 /* l4_core -> dss */
1508 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1509 .master = &omap3xxx_l4_core_hwmod,
1510 .slave = &omap3430es1_dss_core_hwmod,
1512 .addr = omap3xxx_dss_addrs,
1513 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1516 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1517 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1518 .flags = OMAP_FIREWALL_L4,
1521 .user = OCP_USER_MPU | OCP_USER_SDMA,
1524 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1525 .master = &omap3xxx_l4_core_hwmod,
1526 .slave = &omap3xxx_dss_core_hwmod,
1528 .addr = omap3xxx_dss_addrs,
1529 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1532 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1533 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1534 .flags = OMAP_FIREWALL_L4,
1537 .user = OCP_USER_MPU | OCP_USER_SDMA,
1540 /* dss slave ports */
1541 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1542 &omap3430es1_l4_core__dss,
1545 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1546 &omap3xxx_l4_core__dss,
1549 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1550 { .role = "tv_clk", .clk = "dss_tv_fck" },
1551 { .role = "dssclk", .clk = "dss_96m_fck" },
1552 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1555 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1557 .class = &omap3xxx_dss_hwmod_class,
1558 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1559 .mpu_irqs = omap3xxx_dss_irqs,
1560 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
1561 .sdma_reqs = omap3xxx_dss_sdma_chs,
1562 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1567 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1568 .module_offs = OMAP3430_DSS_MOD,
1570 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1573 .opt_clks = dss_opt_clks,
1574 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1575 .slaves = omap3430es1_dss_slaves,
1576 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1577 .masters = omap3xxx_dss_masters,
1578 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1579 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1580 .flags = HWMOD_NO_IDLEST,
1583 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1585 .class = &omap3xxx_dss_hwmod_class,
1586 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1587 .mpu_irqs = omap3xxx_dss_irqs,
1588 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
1589 .sdma_reqs = omap3xxx_dss_sdma_chs,
1590 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1595 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1596 .module_offs = OMAP3430_DSS_MOD,
1598 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1599 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1602 .opt_clks = dss_opt_clks,
1603 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1604 .slaves = omap3xxx_dss_slaves,
1605 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1606 .masters = omap3xxx_dss_masters,
1607 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1608 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1609 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1614 * display controller
1617 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1619 .sysc_offs = 0x0010,
1620 .syss_offs = 0x0014,
1621 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1622 SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1623 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1624 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1625 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1626 .sysc_fields = &omap_hwmod_sysc_type1,
1629 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1631 .sysc = &omap3xxx_dispc_sysc,
1634 static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
1636 .pa_start = 0x48050400,
1637 .pa_end = 0x480507FF,
1638 .flags = ADDR_TYPE_RT
1642 /* l4_core -> dss_dispc */
1643 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1644 .master = &omap3xxx_l4_core_hwmod,
1645 .slave = &omap3xxx_dss_dispc_hwmod,
1647 .addr = omap3xxx_dss_dispc_addrs,
1648 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
1651 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1652 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1653 .flags = OMAP_FIREWALL_L4,
1656 .user = OCP_USER_MPU | OCP_USER_SDMA,
1659 /* dss_dispc slave ports */
1660 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1661 &omap3xxx_l4_core__dss_dispc,
1664 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1665 .name = "dss_dispc",
1666 .class = &omap3xxx_dispc_hwmod_class,
1667 .main_clk = "dss1_alwon_fck",
1671 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1672 .module_offs = OMAP3430_DSS_MOD,
1675 .slaves = omap3xxx_dss_dispc_slaves,
1676 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1677 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1678 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1679 CHIP_GE_OMAP3630ES1_1),
1680 .flags = HWMOD_NO_IDLEST,
1685 * display serial interface controller
1688 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1693 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1695 .pa_start = 0x4804FC00,
1696 .pa_end = 0x4804FFFF,
1697 .flags = ADDR_TYPE_RT
1701 /* l4_core -> dss_dsi1 */
1702 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1703 .master = &omap3xxx_l4_core_hwmod,
1704 .slave = &omap3xxx_dss_dsi1_hwmod,
1705 .addr = omap3xxx_dss_dsi1_addrs,
1706 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
1709 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1710 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1711 .flags = OMAP_FIREWALL_L4,
1714 .user = OCP_USER_MPU | OCP_USER_SDMA,
1717 /* dss_dsi1 slave ports */
1718 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1719 &omap3xxx_l4_core__dss_dsi1,
1722 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1724 .class = &omap3xxx_dsi_hwmod_class,
1725 .main_clk = "dss1_alwon_fck",
1729 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1730 .module_offs = OMAP3430_DSS_MOD,
1733 .slaves = omap3xxx_dss_dsi1_slaves,
1734 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1735 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1736 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1737 CHIP_GE_OMAP3630ES1_1),
1738 .flags = HWMOD_NO_IDLEST,
1743 * remote frame buffer interface
1746 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1748 .sysc_offs = 0x0010,
1749 .syss_offs = 0x0014,
1750 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1752 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1753 .sysc_fields = &omap_hwmod_sysc_type1,
1756 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1758 .sysc = &omap3xxx_rfbi_sysc,
1761 static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1763 .pa_start = 0x48050800,
1764 .pa_end = 0x48050BFF,
1765 .flags = ADDR_TYPE_RT
1769 /* l4_core -> dss_rfbi */
1770 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1771 .master = &omap3xxx_l4_core_hwmod,
1772 .slave = &omap3xxx_dss_rfbi_hwmod,
1774 .addr = omap3xxx_dss_rfbi_addrs,
1775 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
1778 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1779 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1780 .flags = OMAP_FIREWALL_L4,
1783 .user = OCP_USER_MPU | OCP_USER_SDMA,
1786 /* dss_rfbi slave ports */
1787 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1788 &omap3xxx_l4_core__dss_rfbi,
1791 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1793 .class = &omap3xxx_rfbi_hwmod_class,
1794 .main_clk = "dss1_alwon_fck",
1798 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1799 .module_offs = OMAP3430_DSS_MOD,
1802 .slaves = omap3xxx_dss_rfbi_slaves,
1803 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1804 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1805 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1806 CHIP_GE_OMAP3630ES1_1),
1807 .flags = HWMOD_NO_IDLEST,
1815 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1820 static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1822 .pa_start = 0x48050C00,
1823 .pa_end = 0x48050FFF,
1824 .flags = ADDR_TYPE_RT
1828 /* l4_core -> dss_venc */
1829 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1830 .master = &omap3xxx_l4_core_hwmod,
1831 .slave = &omap3xxx_dss_venc_hwmod,
1832 .clk = "dss_tv_fck",
1833 .addr = omap3xxx_dss_venc_addrs,
1834 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
1837 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1838 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1839 .flags = OMAP_FIREWALL_L4,
1842 .flags = OCPIF_SWSUP_IDLE,
1843 .user = OCP_USER_MPU | OCP_USER_SDMA,
1846 /* dss_venc slave ports */
1847 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1848 &omap3xxx_l4_core__dss_venc,
1851 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1853 .class = &omap3xxx_venc_hwmod_class,
1854 .main_clk = "dss1_alwon_fck",
1858 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1859 .module_offs = OMAP3430_DSS_MOD,
1862 .slaves = omap3xxx_dss_venc_slaves,
1863 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1864 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1865 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1866 CHIP_GE_OMAP3630ES1_1),
1867 .flags = HWMOD_NO_IDLEST,
1872 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1873 .fifo_depth = 8, /* bytes */
1876 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1877 { .irq = INT_24XX_I2C1_IRQ, },
1880 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1881 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1882 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1885 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1886 &omap3_l4_core__i2c1,
1889 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1891 .mpu_irqs = i2c1_mpu_irqs,
1892 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
1893 .sdma_reqs = i2c1_sdma_reqs,
1894 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1895 .main_clk = "i2c1_fck",
1898 .module_offs = CORE_MOD,
1900 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1902 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1905 .slaves = omap3xxx_i2c1_slaves,
1906 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1907 .class = &i2c_class,
1908 .dev_attr = &i2c1_dev_attr,
1909 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1914 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1915 .fifo_depth = 8, /* bytes */
1918 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1919 { .irq = INT_24XX_I2C2_IRQ, },
1922 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1923 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1924 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1927 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1928 &omap3_l4_core__i2c2,
1931 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1933 .mpu_irqs = i2c2_mpu_irqs,
1934 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
1935 .sdma_reqs = i2c2_sdma_reqs,
1936 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1937 .main_clk = "i2c2_fck",
1940 .module_offs = CORE_MOD,
1942 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1944 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1947 .slaves = omap3xxx_i2c2_slaves,
1948 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1949 .class = &i2c_class,
1950 .dev_attr = &i2c2_dev_attr,
1951 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1956 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1957 .fifo_depth = 64, /* bytes */
1960 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1961 { .irq = INT_34XX_I2C3_IRQ, },
1964 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1965 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1966 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1969 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1970 &omap3_l4_core__i2c3,
1973 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1975 .mpu_irqs = i2c3_mpu_irqs,
1976 .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
1977 .sdma_reqs = i2c3_sdma_reqs,
1978 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
1979 .main_clk = "i2c3_fck",
1982 .module_offs = CORE_MOD,
1984 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1986 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1989 .slaves = omap3xxx_i2c3_slaves,
1990 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1991 .class = &i2c_class,
1992 .dev_attr = &i2c3_dev_attr,
1993 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1996 /* l4_wkup -> gpio1 */
1997 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1999 .pa_start = 0x48310000,
2000 .pa_end = 0x483101ff,
2001 .flags = ADDR_TYPE_RT
2005 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2006 .master = &omap3xxx_l4_wkup_hwmod,
2007 .slave = &omap3xxx_gpio1_hwmod,
2008 .addr = omap3xxx_gpio1_addrs,
2009 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
2010 .user = OCP_USER_MPU | OCP_USER_SDMA,
2013 /* l4_per -> gpio2 */
2014 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2016 .pa_start = 0x49050000,
2017 .pa_end = 0x490501ff,
2018 .flags = ADDR_TYPE_RT
2022 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2023 .master = &omap3xxx_l4_per_hwmod,
2024 .slave = &omap3xxx_gpio2_hwmod,
2025 .addr = omap3xxx_gpio2_addrs,
2026 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
2027 .user = OCP_USER_MPU | OCP_USER_SDMA,
2030 /* l4_per -> gpio3 */
2031 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2033 .pa_start = 0x49052000,
2034 .pa_end = 0x490521ff,
2035 .flags = ADDR_TYPE_RT
2039 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2040 .master = &omap3xxx_l4_per_hwmod,
2041 .slave = &omap3xxx_gpio3_hwmod,
2042 .addr = omap3xxx_gpio3_addrs,
2043 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
2044 .user = OCP_USER_MPU | OCP_USER_SDMA,
2047 /* l4_per -> gpio4 */
2048 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2050 .pa_start = 0x49054000,
2051 .pa_end = 0x490541ff,
2052 .flags = ADDR_TYPE_RT
2056 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2057 .master = &omap3xxx_l4_per_hwmod,
2058 .slave = &omap3xxx_gpio4_hwmod,
2059 .addr = omap3xxx_gpio4_addrs,
2060 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
2061 .user = OCP_USER_MPU | OCP_USER_SDMA,
2064 /* l4_per -> gpio5 */
2065 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2067 .pa_start = 0x49056000,
2068 .pa_end = 0x490561ff,
2069 .flags = ADDR_TYPE_RT
2073 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2074 .master = &omap3xxx_l4_per_hwmod,
2075 .slave = &omap3xxx_gpio5_hwmod,
2076 .addr = omap3xxx_gpio5_addrs,
2077 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
2078 .user = OCP_USER_MPU | OCP_USER_SDMA,
2081 /* l4_per -> gpio6 */
2082 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2084 .pa_start = 0x49058000,
2085 .pa_end = 0x490581ff,
2086 .flags = ADDR_TYPE_RT
2090 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2091 .master = &omap3xxx_l4_per_hwmod,
2092 .slave = &omap3xxx_gpio6_hwmod,
2093 .addr = omap3xxx_gpio6_addrs,
2094 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
2095 .user = OCP_USER_MPU | OCP_USER_SDMA,
2100 * general purpose io module
2103 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
2105 .sysc_offs = 0x0010,
2106 .syss_offs = 0x0014,
2107 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2108 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
2109 SYSS_HAS_RESET_STATUS),
2110 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2111 .sysc_fields = &omap_hwmod_sysc_type1,
2114 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
2116 .sysc = &omap3xxx_gpio_sysc,
2121 static struct omap_gpio_dev_attr gpio_dev_attr = {
2127 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
2128 { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
2131 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
2132 { .role = "dbclk", .clk = "gpio1_dbck", },
2135 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
2136 &omap3xxx_l4_wkup__gpio1,
2139 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2141 .mpu_irqs = omap3xxx_gpio1_irqs,
2142 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
2143 .main_clk = "gpio1_ick",
2144 .opt_clks = gpio1_opt_clks,
2145 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
2149 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
2150 .module_offs = WKUP_MOD,
2152 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
2155 .slaves = omap3xxx_gpio1_slaves,
2156 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
2157 .class = &omap3xxx_gpio_hwmod_class,
2158 .dev_attr = &gpio_dev_attr,
2159 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2163 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
2164 { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
2167 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
2168 { .role = "dbclk", .clk = "gpio2_dbck", },
2171 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
2172 &omap3xxx_l4_per__gpio2,
2175 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2177 .mpu_irqs = omap3xxx_gpio2_irqs,
2178 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
2179 .main_clk = "gpio2_ick",
2180 .opt_clks = gpio2_opt_clks,
2181 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
2185 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
2186 .module_offs = OMAP3430_PER_MOD,
2188 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2191 .slaves = omap3xxx_gpio2_slaves,
2192 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2193 .class = &omap3xxx_gpio_hwmod_class,
2194 .dev_attr = &gpio_dev_attr,
2195 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2199 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
2200 { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
2203 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2204 { .role = "dbclk", .clk = "gpio3_dbck", },
2207 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2208 &omap3xxx_l4_per__gpio3,
2211 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2213 .mpu_irqs = omap3xxx_gpio3_irqs,
2214 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
2215 .main_clk = "gpio3_ick",
2216 .opt_clks = gpio3_opt_clks,
2217 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
2221 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2222 .module_offs = OMAP3430_PER_MOD,
2224 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2227 .slaves = omap3xxx_gpio3_slaves,
2228 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2229 .class = &omap3xxx_gpio_hwmod_class,
2230 .dev_attr = &gpio_dev_attr,
2231 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2235 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
2236 { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
2239 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2240 { .role = "dbclk", .clk = "gpio4_dbck", },
2243 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2244 &omap3xxx_l4_per__gpio4,
2247 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2249 .mpu_irqs = omap3xxx_gpio4_irqs,
2250 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
2251 .main_clk = "gpio4_ick",
2252 .opt_clks = gpio4_opt_clks,
2253 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2257 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2258 .module_offs = OMAP3430_PER_MOD,
2260 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2263 .slaves = omap3xxx_gpio4_slaves,
2264 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2265 .class = &omap3xxx_gpio_hwmod_class,
2266 .dev_attr = &gpio_dev_attr,
2267 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2271 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2272 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2275 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2276 { .role = "dbclk", .clk = "gpio5_dbck", },
2279 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2280 &omap3xxx_l4_per__gpio5,
2283 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2285 .mpu_irqs = omap3xxx_gpio5_irqs,
2286 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
2287 .main_clk = "gpio5_ick",
2288 .opt_clks = gpio5_opt_clks,
2289 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2293 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2294 .module_offs = OMAP3430_PER_MOD,
2296 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2299 .slaves = omap3xxx_gpio5_slaves,
2300 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2301 .class = &omap3xxx_gpio_hwmod_class,
2302 .dev_attr = &gpio_dev_attr,
2303 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2307 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2308 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2311 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2312 { .role = "dbclk", .clk = "gpio6_dbck", },
2315 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2316 &omap3xxx_l4_per__gpio6,
2319 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2321 .mpu_irqs = omap3xxx_gpio6_irqs,
2322 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
2323 .main_clk = "gpio6_ick",
2324 .opt_clks = gpio6_opt_clks,
2325 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2329 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2330 .module_offs = OMAP3430_PER_MOD,
2332 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2335 .slaves = omap3xxx_gpio6_slaves,
2336 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2337 .class = &omap3xxx_gpio_hwmod_class,
2338 .dev_attr = &gpio_dev_attr,
2339 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2342 /* dma_system -> L3 */
2343 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2344 .master = &omap3xxx_dma_system_hwmod,
2345 .slave = &omap3xxx_l3_main_hwmod,
2346 .clk = "core_l3_ick",
2347 .user = OCP_USER_MPU | OCP_USER_SDMA,
2350 /* dma attributes */
2351 static struct omap_dma_dev_attr dma_dev_attr = {
2352 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2353 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2357 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2359 .sysc_offs = 0x002c,
2360 .syss_offs = 0x0028,
2361 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2362 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2363 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2364 SYSS_HAS_RESET_STATUS),
2365 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2366 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2367 .sysc_fields = &omap_hwmod_sysc_type1,
2370 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2372 .sysc = &omap3xxx_dma_sysc,
2376 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
2377 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
2378 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
2379 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
2380 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
2383 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2385 .pa_start = 0x48056000,
2386 .pa_end = 0x4a0560ff,
2387 .flags = ADDR_TYPE_RT
2391 /* dma_system master ports */
2392 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2393 &omap3xxx_dma_system__l3,
2396 /* l4_cfg -> dma_system */
2397 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2398 .master = &omap3xxx_l4_core_hwmod,
2399 .slave = &omap3xxx_dma_system_hwmod,
2400 .clk = "core_l4_ick",
2401 .addr = omap3xxx_dma_system_addrs,
2402 .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
2403 .user = OCP_USER_MPU | OCP_USER_SDMA,
2406 /* dma_system slave ports */
2407 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2408 &omap3xxx_l4_core__dma_system,
2411 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2413 .class = &omap3xxx_dma_hwmod_class,
2414 .mpu_irqs = omap3xxx_dma_system_irqs,
2415 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
2416 .main_clk = "core_l3_ick",
2419 .module_offs = CORE_MOD,
2421 .module_bit = OMAP3430_ST_SDMA_SHIFT,
2423 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2426 .slaves = omap3xxx_dma_system_slaves,
2427 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2428 .masters = omap3xxx_dma_system_masters,
2429 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2430 .dev_attr = &dma_dev_attr,
2431 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2432 .flags = HWMOD_NO_IDLEST,
2437 * multi channel buffered serial port controller
2440 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2441 .sysc_offs = 0x008c,
2442 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2443 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2444 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2445 .sysc_fields = &omap_hwmod_sysc_type1,
2449 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2451 .sysc = &omap3xxx_mcbsp_sysc,
2452 .rev = MCBSP_CONFIG_TYPE3,
2456 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2457 { .name = "irq", .irq = 16 },
2458 { .name = "tx", .irq = 59 },
2459 { .name = "rx", .irq = 60 },
2462 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2463 { .name = "rx", .dma_req = 32 },
2464 { .name = "tx", .dma_req = 31 },
2467 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2470 .pa_start = 0x48074000,
2471 .pa_end = 0x480740ff,
2472 .flags = ADDR_TYPE_RT
2476 /* l4_core -> mcbsp1 */
2477 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2478 .master = &omap3xxx_l4_core_hwmod,
2479 .slave = &omap3xxx_mcbsp1_hwmod,
2480 .clk = "mcbsp1_ick",
2481 .addr = omap3xxx_mcbsp1_addrs,
2482 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
2483 .user = OCP_USER_MPU | OCP_USER_SDMA,
2486 /* mcbsp1 slave ports */
2487 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2488 &omap3xxx_l4_core__mcbsp1,
2491 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2493 .class = &omap3xxx_mcbsp_hwmod_class,
2494 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2495 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
2496 .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
2497 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2498 .main_clk = "mcbsp1_fck",
2502 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2503 .module_offs = CORE_MOD,
2505 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2508 .slaves = omap3xxx_mcbsp1_slaves,
2509 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2510 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2514 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2515 { .name = "irq", .irq = 17 },
2516 { .name = "tx", .irq = 62 },
2517 { .name = "rx", .irq = 63 },
2520 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2521 { .name = "rx", .dma_req = 34 },
2522 { .name = "tx", .dma_req = 33 },
2525 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2528 .pa_start = 0x49022000,
2529 .pa_end = 0x490220ff,
2530 .flags = ADDR_TYPE_RT
2534 /* l4_per -> mcbsp2 */
2535 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2536 .master = &omap3xxx_l4_per_hwmod,
2537 .slave = &omap3xxx_mcbsp2_hwmod,
2538 .clk = "mcbsp2_ick",
2539 .addr = omap3xxx_mcbsp2_addrs,
2540 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
2541 .user = OCP_USER_MPU | OCP_USER_SDMA,
2544 /* mcbsp2 slave ports */
2545 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2546 &omap3xxx_l4_per__mcbsp2,
2549 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2550 .sidetone = "mcbsp2_sidetone",
2553 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2555 .class = &omap3xxx_mcbsp_hwmod_class,
2556 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2557 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
2558 .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
2559 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2560 .main_clk = "mcbsp2_fck",
2564 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2565 .module_offs = OMAP3430_PER_MOD,
2567 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2570 .slaves = omap3xxx_mcbsp2_slaves,
2571 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2572 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2573 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2577 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2578 { .name = "irq", .irq = 22 },
2579 { .name = "tx", .irq = 89 },
2580 { .name = "rx", .irq = 90 },
2583 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2584 { .name = "rx", .dma_req = 18 },
2585 { .name = "tx", .dma_req = 17 },
2588 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2591 .pa_start = 0x49024000,
2592 .pa_end = 0x490240ff,
2593 .flags = ADDR_TYPE_RT
2597 /* l4_per -> mcbsp3 */
2598 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2599 .master = &omap3xxx_l4_per_hwmod,
2600 .slave = &omap3xxx_mcbsp3_hwmod,
2601 .clk = "mcbsp3_ick",
2602 .addr = omap3xxx_mcbsp3_addrs,
2603 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
2604 .user = OCP_USER_MPU | OCP_USER_SDMA,
2607 /* mcbsp3 slave ports */
2608 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2609 &omap3xxx_l4_per__mcbsp3,
2612 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2613 .sidetone = "mcbsp3_sidetone",
2616 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2618 .class = &omap3xxx_mcbsp_hwmod_class,
2619 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2620 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
2621 .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
2622 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2623 .main_clk = "mcbsp3_fck",
2627 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2628 .module_offs = OMAP3430_PER_MOD,
2630 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2633 .slaves = omap3xxx_mcbsp3_slaves,
2634 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2635 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2636 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2640 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2641 { .name = "irq", .irq = 23 },
2642 { .name = "tx", .irq = 54 },
2643 { .name = "rx", .irq = 55 },
2646 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2647 { .name = "rx", .dma_req = 20 },
2648 { .name = "tx", .dma_req = 19 },
2651 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2654 .pa_start = 0x49026000,
2655 .pa_end = 0x490260ff,
2656 .flags = ADDR_TYPE_RT
2660 /* l4_per -> mcbsp4 */
2661 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2662 .master = &omap3xxx_l4_per_hwmod,
2663 .slave = &omap3xxx_mcbsp4_hwmod,
2664 .clk = "mcbsp4_ick",
2665 .addr = omap3xxx_mcbsp4_addrs,
2666 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
2667 .user = OCP_USER_MPU | OCP_USER_SDMA,
2670 /* mcbsp4 slave ports */
2671 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2672 &omap3xxx_l4_per__mcbsp4,
2675 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2677 .class = &omap3xxx_mcbsp_hwmod_class,
2678 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2679 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
2680 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2681 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2682 .main_clk = "mcbsp4_fck",
2686 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2687 .module_offs = OMAP3430_PER_MOD,
2689 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2692 .slaves = omap3xxx_mcbsp4_slaves,
2693 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2694 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2698 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2699 { .name = "irq", .irq = 27 },
2700 { .name = "tx", .irq = 81 },
2701 { .name = "rx", .irq = 82 },
2704 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2705 { .name = "rx", .dma_req = 22 },
2706 { .name = "tx", .dma_req = 21 },
2709 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2712 .pa_start = 0x48096000,
2713 .pa_end = 0x480960ff,
2714 .flags = ADDR_TYPE_RT
2718 /* l4_core -> mcbsp5 */
2719 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2720 .master = &omap3xxx_l4_core_hwmod,
2721 .slave = &omap3xxx_mcbsp5_hwmod,
2722 .clk = "mcbsp5_ick",
2723 .addr = omap3xxx_mcbsp5_addrs,
2724 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
2725 .user = OCP_USER_MPU | OCP_USER_SDMA,
2728 /* mcbsp5 slave ports */
2729 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2730 &omap3xxx_l4_core__mcbsp5,
2733 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2735 .class = &omap3xxx_mcbsp_hwmod_class,
2736 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2737 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
2738 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2739 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2740 .main_clk = "mcbsp5_fck",
2744 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2745 .module_offs = CORE_MOD,
2747 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2750 .slaves = omap3xxx_mcbsp5_slaves,
2751 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2752 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2754 /* 'mcbsp sidetone' class */
2756 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2757 .sysc_offs = 0x0010,
2758 .sysc_flags = SYSC_HAS_AUTOIDLE,
2759 .sysc_fields = &omap_hwmod_sysc_type1,
2762 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2763 .name = "mcbsp_sidetone",
2764 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2767 /* mcbsp2_sidetone */
2768 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2769 { .name = "irq", .irq = 4 },
2772 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2775 .pa_start = 0x49028000,
2776 .pa_end = 0x490280ff,
2777 .flags = ADDR_TYPE_RT
2781 /* l4_per -> mcbsp2_sidetone */
2782 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2783 .master = &omap3xxx_l4_per_hwmod,
2784 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2785 .clk = "mcbsp2_ick",
2786 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2787 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
2788 .user = OCP_USER_MPU,
2791 /* mcbsp2_sidetone slave ports */
2792 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2793 &omap3xxx_l4_per__mcbsp2_sidetone,
2796 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2797 .name = "mcbsp2_sidetone",
2798 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2799 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2800 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
2801 .main_clk = "mcbsp2_fck",
2805 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2806 .module_offs = OMAP3430_PER_MOD,
2808 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2811 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2812 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2813 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2816 /* mcbsp3_sidetone */
2817 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2818 { .name = "irq", .irq = 5 },
2821 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2824 .pa_start = 0x4902A000,
2825 .pa_end = 0x4902A0ff,
2826 .flags = ADDR_TYPE_RT
2830 /* l4_per -> mcbsp3_sidetone */
2831 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2832 .master = &omap3xxx_l4_per_hwmod,
2833 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2834 .clk = "mcbsp3_ick",
2835 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2836 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
2837 .user = OCP_USER_MPU,
2840 /* mcbsp3_sidetone slave ports */
2841 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2842 &omap3xxx_l4_per__mcbsp3_sidetone,
2845 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2846 .name = "mcbsp3_sidetone",
2847 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2848 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2849 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
2850 .main_clk = "mcbsp3_fck",
2854 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2855 .module_offs = OMAP3430_PER_MOD,
2857 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2860 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2861 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2862 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2867 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2871 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2873 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2874 .clockact = CLOCKACT_TEST_ICLK,
2875 .sysc_fields = &omap34xx_sr_sysc_fields,
2878 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2879 .name = "smartreflex",
2880 .sysc = &omap34xx_sr_sysc,
2884 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2889 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2891 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2892 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2894 .sysc_fields = &omap36xx_sr_sysc_fields,
2897 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2898 .name = "smartreflex",
2899 .sysc = &omap36xx_sr_sysc,
2904 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2905 &omap3_l4_core__sr1,
2908 static struct omap_hwmod omap34xx_sr1_hwmod = {
2909 .name = "sr1_hwmod",
2910 .class = &omap34xx_smartreflex_hwmod_class,
2911 .main_clk = "sr1_fck",
2916 .module_bit = OMAP3430_EN_SR1_SHIFT,
2917 .module_offs = WKUP_MOD,
2919 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2922 .slaves = omap3_sr1_slaves,
2923 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2924 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2925 CHIP_IS_OMAP3430ES3_0 |
2926 CHIP_IS_OMAP3430ES3_1),
2927 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2930 static struct omap_hwmod omap36xx_sr1_hwmod = {
2931 .name = "sr1_hwmod",
2932 .class = &omap36xx_smartreflex_hwmod_class,
2933 .main_clk = "sr1_fck",
2938 .module_bit = OMAP3430_EN_SR1_SHIFT,
2939 .module_offs = WKUP_MOD,
2941 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2944 .slaves = omap3_sr1_slaves,
2945 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2946 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2950 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2951 &omap3_l4_core__sr2,
2954 static struct omap_hwmod omap34xx_sr2_hwmod = {
2955 .name = "sr2_hwmod",
2956 .class = &omap34xx_smartreflex_hwmod_class,
2957 .main_clk = "sr2_fck",
2962 .module_bit = OMAP3430_EN_SR2_SHIFT,
2963 .module_offs = WKUP_MOD,
2965 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2968 .slaves = omap3_sr2_slaves,
2969 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2970 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2971 CHIP_IS_OMAP3430ES3_0 |
2972 CHIP_IS_OMAP3430ES3_1),
2973 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2976 static struct omap_hwmod omap36xx_sr2_hwmod = {
2977 .name = "sr2_hwmod",
2978 .class = &omap36xx_smartreflex_hwmod_class,
2979 .main_clk = "sr2_fck",
2984 .module_bit = OMAP3430_EN_SR2_SHIFT,
2985 .module_offs = WKUP_MOD,
2987 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2990 .slaves = omap3_sr2_slaves,
2991 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2992 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2997 * mailbox module allowing communication between the on-chip processors
2998 * using a queued mailbox-interrupt mechanism.
3001 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
3005 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3006 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
3007 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3008 .sysc_fields = &omap_hwmod_sysc_type1,
3011 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
3013 .sysc = &omap3xxx_mailbox_sysc,
3016 static struct omap_hwmod omap3xxx_mailbox_hwmod;
3017 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
3021 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3023 .pa_start = 0x48094000,
3024 .pa_end = 0x480941ff,
3025 .flags = ADDR_TYPE_RT,
3029 /* l4_core -> mailbox */
3030 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3031 .master = &omap3xxx_l4_core_hwmod,
3032 .slave = &omap3xxx_mailbox_hwmod,
3033 .addr = omap3xxx_mailbox_addrs,
3034 .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
3035 .user = OCP_USER_MPU | OCP_USER_SDMA,
3038 /* mailbox slave ports */
3039 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
3040 &omap3xxx_l4_core__mailbox,
3043 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
3045 .class = &omap3xxx_mailbox_hwmod_class,
3046 .mpu_irqs = omap3xxx_mailbox_irqs,
3047 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
3048 .main_clk = "mailboxes_ick",
3052 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
3053 .module_offs = CORE_MOD,
3055 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
3058 .slaves = omap3xxx_mailbox_slaves,
3059 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
3060 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3063 /* l4 core -> mcspi1 interface */
3064 static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
3066 .pa_start = 0x48098000,
3067 .pa_end = 0x480980ff,
3068 .flags = ADDR_TYPE_RT,
3072 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3073 .master = &omap3xxx_l4_core_hwmod,
3074 .slave = &omap34xx_mcspi1,
3075 .clk = "mcspi1_ick",
3076 .addr = omap34xx_mcspi1_addr_space,
3077 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
3078 .user = OCP_USER_MPU | OCP_USER_SDMA,
3081 /* l4 core -> mcspi2 interface */
3082 static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
3084 .pa_start = 0x4809a000,
3085 .pa_end = 0x4809a0ff,
3086 .flags = ADDR_TYPE_RT,
3090 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3091 .master = &omap3xxx_l4_core_hwmod,
3092 .slave = &omap34xx_mcspi2,
3093 .clk = "mcspi2_ick",
3094 .addr = omap34xx_mcspi2_addr_space,
3095 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
3096 .user = OCP_USER_MPU | OCP_USER_SDMA,
3099 /* l4 core -> mcspi3 interface */
3100 static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
3102 .pa_start = 0x480b8000,
3103 .pa_end = 0x480b80ff,
3104 .flags = ADDR_TYPE_RT,
3108 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3109 .master = &omap3xxx_l4_core_hwmod,
3110 .slave = &omap34xx_mcspi3,
3111 .clk = "mcspi3_ick",
3112 .addr = omap34xx_mcspi3_addr_space,
3113 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
3114 .user = OCP_USER_MPU | OCP_USER_SDMA,
3117 /* l4 core -> mcspi4 interface */
3118 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3120 .pa_start = 0x480ba000,
3121 .pa_end = 0x480ba0ff,
3122 .flags = ADDR_TYPE_RT,
3126 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3127 .master = &omap3xxx_l4_core_hwmod,
3128 .slave = &omap34xx_mcspi4,
3129 .clk = "mcspi4_ick",
3130 .addr = omap34xx_mcspi4_addr_space,
3131 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
3132 .user = OCP_USER_MPU | OCP_USER_SDMA,
3137 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3141 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
3143 .sysc_offs = 0x0010,
3144 .syss_offs = 0x0014,
3145 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3146 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3147 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3148 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3149 .sysc_fields = &omap_hwmod_sysc_type1,
3152 static struct omap_hwmod_class omap34xx_mcspi_class = {
3154 .sysc = &omap34xx_mcspi_sysc,
3155 .rev = OMAP3_MCSPI_REV,
3159 static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
3160 { .name = "irq", .irq = 65 },
3163 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
3164 { .name = "tx0", .dma_req = 35 },
3165 { .name = "rx0", .dma_req = 36 },
3166 { .name = "tx1", .dma_req = 37 },
3167 { .name = "rx1", .dma_req = 38 },
3168 { .name = "tx2", .dma_req = 39 },
3169 { .name = "rx2", .dma_req = 40 },
3170 { .name = "tx3", .dma_req = 41 },
3171 { .name = "rx3", .dma_req = 42 },
3174 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
3175 &omap34xx_l4_core__mcspi1,
3178 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
3179 .num_chipselect = 4,
3182 static struct omap_hwmod omap34xx_mcspi1 = {
3184 .mpu_irqs = omap34xx_mcspi1_mpu_irqs,
3185 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
3186 .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
3187 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
3188 .main_clk = "mcspi1_fck",
3191 .module_offs = CORE_MOD,
3193 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
3195 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
3198 .slaves = omap34xx_mcspi1_slaves,
3199 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
3200 .class = &omap34xx_mcspi_class,
3201 .dev_attr = &omap_mcspi1_dev_attr,
3202 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3206 static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
3207 { .name = "irq", .irq = 66 },
3210 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
3211 { .name = "tx0", .dma_req = 43 },
3212 { .name = "rx0", .dma_req = 44 },
3213 { .name = "tx1", .dma_req = 45 },
3214 { .name = "rx1", .dma_req = 46 },
3217 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
3218 &omap34xx_l4_core__mcspi2,
3221 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
3222 .num_chipselect = 2,
3225 static struct omap_hwmod omap34xx_mcspi2 = {
3227 .mpu_irqs = omap34xx_mcspi2_mpu_irqs,
3228 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
3229 .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
3230 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
3231 .main_clk = "mcspi2_fck",
3234 .module_offs = CORE_MOD,
3236 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
3238 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
3241 .slaves = omap34xx_mcspi2_slaves,
3242 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
3243 .class = &omap34xx_mcspi_class,
3244 .dev_attr = &omap_mcspi2_dev_attr,
3245 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3249 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
3250 { .name = "irq", .irq = 91 }, /* 91 */
3253 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
3254 { .name = "tx0", .dma_req = 15 },
3255 { .name = "rx0", .dma_req = 16 },
3256 { .name = "tx1", .dma_req = 23 },
3257 { .name = "rx1", .dma_req = 24 },
3260 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
3261 &omap34xx_l4_core__mcspi3,
3264 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
3265 .num_chipselect = 2,
3268 static struct omap_hwmod omap34xx_mcspi3 = {
3270 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
3271 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
3272 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
3273 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
3274 .main_clk = "mcspi3_fck",
3277 .module_offs = CORE_MOD,
3279 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
3281 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
3284 .slaves = omap34xx_mcspi3_slaves,
3285 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3286 .class = &omap34xx_mcspi_class,
3287 .dev_attr = &omap_mcspi3_dev_attr,
3288 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3292 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3293 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3296 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3297 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3298 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3301 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3302 &omap34xx_l4_core__mcspi4,
3305 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3306 .num_chipselect = 1,
3309 static struct omap_hwmod omap34xx_mcspi4 = {
3311 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
3312 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
3313 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
3314 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
3315 .main_clk = "mcspi4_fck",
3318 .module_offs = CORE_MOD,
3320 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3322 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3325 .slaves = omap34xx_mcspi4_slaves,
3326 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3327 .class = &omap34xx_mcspi_class,
3328 .dev_attr = &omap_mcspi4_dev_attr,
3329 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3335 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3337 .sysc_offs = 0x0404,
3338 .syss_offs = 0x0408,
3339 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3340 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3342 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3343 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3344 .sysc_fields = &omap_hwmod_sysc_type1,
3347 static struct omap_hwmod_class usbotg_class = {
3349 .sysc = &omap3xxx_usbhsotg_sysc,
3352 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3354 { .name = "mc", .irq = 92 },
3355 { .name = "dma", .irq = 93 },
3358 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3359 .name = "usb_otg_hs",
3360 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
3361 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
3362 .main_clk = "hsotgusb_ick",
3366 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3367 .module_offs = CORE_MOD,
3369 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3370 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3373 .masters = omap3xxx_usbhsotg_masters,
3374 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3375 .slaves = omap3xxx_usbhsotg_slaves,
3376 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3377 .class = &usbotg_class,
3380 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
3381 * broken when autoidle is enabled
3382 * workaround is to disable the autoidle bit at module level.
3384 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3385 | HWMOD_SWSUP_MSTANDBY,
3386 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3390 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3392 { .name = "mc", .irq = 71 },
3395 static struct omap_hwmod_class am35xx_usbotg_class = {
3396 .name = "am35xx_usbotg",
3400 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3401 .name = "am35x_otg_hs",
3402 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3403 .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
3409 .masters = am35xx_usbhsotg_masters,
3410 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3411 .slaves = am35xx_usbhsotg_slaves,
3412 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3413 .class = &am35xx_usbotg_class,
3414 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3417 /* MMC/SD/SDIO common */
3419 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3423 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3424 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3425 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3426 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3427 .sysc_fields = &omap_hwmod_sysc_type1,
3430 static struct omap_hwmod_class omap34xx_mmc_class = {
3432 .sysc = &omap34xx_mmc_sysc,
3437 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3441 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3442 { .name = "tx", .dma_req = 61, },
3443 { .name = "rx", .dma_req = 62, },
3446 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3447 { .role = "dbck", .clk = "omap_32k_fck", },
3450 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3451 &omap3xxx_l4_core__mmc1,
3454 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3455 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3458 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3460 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3461 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
3462 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3463 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3464 .opt_clks = omap34xx_mmc1_opt_clks,
3465 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3466 .main_clk = "mmchs1_fck",
3469 .module_offs = CORE_MOD,
3471 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3473 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3476 .dev_attr = &mmc1_dev_attr,
3477 .slaves = omap3xxx_mmc1_slaves,
3478 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3479 .class = &omap34xx_mmc_class,
3480 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3485 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3486 { .irq = INT_24XX_MMC2_IRQ, },
3489 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3490 { .name = "tx", .dma_req = 47, },
3491 { .name = "rx", .dma_req = 48, },
3494 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3495 { .role = "dbck", .clk = "omap_32k_fck", },
3498 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3499 &omap3xxx_l4_core__mmc2,
3502 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3504 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3505 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
3506 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3507 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3508 .opt_clks = omap34xx_mmc2_opt_clks,
3509 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3510 .main_clk = "mmchs2_fck",
3513 .module_offs = CORE_MOD,
3515 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3517 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3520 .slaves = omap3xxx_mmc2_slaves,
3521 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3522 .class = &omap34xx_mmc_class,
3523 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3528 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3532 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3533 { .name = "tx", .dma_req = 77, },
3534 { .name = "rx", .dma_req = 78, },
3537 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3538 { .role = "dbck", .clk = "omap_32k_fck", },
3541 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3542 &omap3xxx_l4_core__mmc3,
3545 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3547 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3548 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
3549 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3550 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3551 .opt_clks = omap34xx_mmc3_opt_clks,
3552 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3553 .main_clk = "mmchs3_fck",
3557 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3559 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3562 .slaves = omap3xxx_mmc3_slaves,
3563 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3564 .class = &omap34xx_mmc_class,
3565 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3568 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3569 &omap3xxx_l3_main_hwmod,
3570 &omap3xxx_l4_core_hwmod,
3571 &omap3xxx_l4_per_hwmod,
3572 &omap3xxx_l4_wkup_hwmod,
3573 &omap3xxx_mmc1_hwmod,
3574 &omap3xxx_mmc2_hwmod,
3575 &omap3xxx_mmc3_hwmod,
3576 &omap3xxx_mpu_hwmod,
3577 &omap3xxx_iva_hwmod,
3579 &omap3xxx_timer1_hwmod,
3580 &omap3xxx_timer2_hwmod,
3581 &omap3xxx_timer3_hwmod,
3582 &omap3xxx_timer4_hwmod,
3583 &omap3xxx_timer5_hwmod,
3584 &omap3xxx_timer6_hwmod,
3585 &omap3xxx_timer7_hwmod,
3586 &omap3xxx_timer8_hwmod,
3587 &omap3xxx_timer9_hwmod,
3588 &omap3xxx_timer10_hwmod,
3589 &omap3xxx_timer11_hwmod,
3590 &omap3xxx_timer12_hwmod,
3592 &omap3xxx_wd_timer2_hwmod,
3593 &omap3xxx_uart1_hwmod,
3594 &omap3xxx_uart2_hwmod,
3595 &omap3xxx_uart3_hwmod,
3596 &omap3xxx_uart4_hwmod,
3598 &omap3430es1_dss_core_hwmod,
3599 &omap3xxx_dss_core_hwmod,
3600 &omap3xxx_dss_dispc_hwmod,
3601 &omap3xxx_dss_dsi1_hwmod,
3602 &omap3xxx_dss_rfbi_hwmod,
3603 &omap3xxx_dss_venc_hwmod,
3606 &omap3xxx_i2c1_hwmod,
3607 &omap3xxx_i2c2_hwmod,
3608 &omap3xxx_i2c3_hwmod,
3609 &omap34xx_sr1_hwmod,
3610 &omap34xx_sr2_hwmod,
3611 &omap36xx_sr1_hwmod,
3612 &omap36xx_sr2_hwmod,
3616 &omap3xxx_gpio1_hwmod,
3617 &omap3xxx_gpio2_hwmod,
3618 &omap3xxx_gpio3_hwmod,
3619 &omap3xxx_gpio4_hwmod,
3620 &omap3xxx_gpio5_hwmod,
3621 &omap3xxx_gpio6_hwmod,
3623 /* dma_system class*/
3624 &omap3xxx_dma_system_hwmod,
3627 &omap3xxx_mcbsp1_hwmod,
3628 &omap3xxx_mcbsp2_hwmod,
3629 &omap3xxx_mcbsp3_hwmod,
3630 &omap3xxx_mcbsp4_hwmod,
3631 &omap3xxx_mcbsp5_hwmod,
3632 &omap3xxx_mcbsp2_sidetone_hwmod,
3633 &omap3xxx_mcbsp3_sidetone_hwmod,
3636 &omap3xxx_mailbox_hwmod,
3645 &omap3xxx_usbhsotg_hwmod,
3647 /* usbotg for am35x */
3648 &am35xx_usbhsotg_hwmod,
3653 int __init omap3xxx_hwmod_init(void)
3655 return omap_hwmod_register(omap3xxx_hwmods);