2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2011 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
14 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
24 #include <plat/gpio.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod_common_data.h"
32 #include "prm-regbits-34xx.h"
33 #include "cm-regbits-34xx.h"
35 #include <mach/am35xx.h>
38 * OMAP3xxx hardware module integration data
40 * ALl of the data in this section should be autogeneratable from the
41 * TI hardware database or other technical documentation. Data that
42 * is driver-specific or driver-kernel integration-specific belongs
46 static struct omap_hwmod omap3xxx_mpu_hwmod;
47 static struct omap_hwmod omap3xxx_iva_hwmod;
48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
67 static struct omap_hwmod omap34xx_sr1_hwmod;
68 static struct omap_hwmod omap34xx_sr2_hwmod;
69 static struct omap_hwmod omap34xx_mcspi1;
70 static struct omap_hwmod omap34xx_mcspi2;
71 static struct omap_hwmod omap34xx_mcspi3;
72 static struct omap_hwmod omap34xx_mcspi4;
73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
88 /* L3 -> L4_CORE interface */
89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
90 .master = &omap3xxx_l3_main_hwmod,
91 .slave = &omap3xxx_l4_core_hwmod,
92 .user = OCP_USER_MPU | OCP_USER_SDMA,
95 /* L3 -> L4_PER interface */
96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
97 .master = &omap3xxx_l3_main_hwmod,
98 .slave = &omap3xxx_l4_per_hwmod,
99 .user = OCP_USER_MPU | OCP_USER_SDMA,
102 /* L3 taret configuration and error log registers */
103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
104 { .irq = INT_34XX_L3_DBG_IRQ },
105 { .irq = INT_34XX_L3_APP_IRQ },
109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
111 .pa_start = 0x68000000,
112 .pa_end = 0x6800ffff,
113 .flags = ADDR_TYPE_RT,
118 /* MPU -> L3 interface */
119 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
120 .master = &omap3xxx_mpu_hwmod,
121 .slave = &omap3xxx_l3_main_hwmod,
122 .addr = omap3xxx_l3_main_addrs,
123 .user = OCP_USER_MPU,
126 /* Slave interfaces on the L3 interconnect */
127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
128 &omap3xxx_mpu__l3_main,
132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
133 .master = &omap3xxx_dss_core_hwmod,
134 .slave = &omap3xxx_l3_main_hwmod,
137 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
138 .flags = OMAP_FIREWALL_L3,
141 .user = OCP_USER_MPU | OCP_USER_SDMA,
144 /* Master interfaces on the L3 interconnect */
145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
146 &omap3xxx_l3_main__l4_core,
147 &omap3xxx_l3_main__l4_per,
151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
153 .class = &l3_hwmod_class,
154 .mpu_irqs = omap3xxx_l3_main_irqs,
155 .masters = omap3xxx_l3_main_masters,
156 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
157 .slaves = omap3xxx_l3_main_slaves,
158 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
159 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
160 .flags = HWMOD_NO_IDLEST,
163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
164 static struct omap_hwmod omap3xxx_uart1_hwmod;
165 static struct omap_hwmod omap3xxx_uart2_hwmod;
166 static struct omap_hwmod omap3xxx_uart3_hwmod;
167 static struct omap_hwmod omap3xxx_uart4_hwmod;
168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
170 /* l3_core -> usbhsotg interface */
171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
172 .master = &omap3xxx_usbhsotg_hwmod,
173 .slave = &omap3xxx_l3_main_hwmod,
174 .clk = "core_l3_ick",
175 .user = OCP_USER_MPU,
178 /* l3_core -> am35xx_usbhsotg interface */
179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
180 .master = &am35xx_usbhsotg_hwmod,
181 .slave = &omap3xxx_l3_main_hwmod,
182 .clk = "core_l3_ick",
183 .user = OCP_USER_MPU,
185 /* L4_CORE -> L4_WKUP interface */
186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
187 .master = &omap3xxx_l4_core_hwmod,
188 .slave = &omap3xxx_l4_wkup_hwmod,
189 .user = OCP_USER_MPU | OCP_USER_SDMA,
192 /* L4 CORE -> MMC1 interface */
193 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
194 .master = &omap3xxx_l4_core_hwmod,
195 .slave = &omap3xxx_mmc1_hwmod,
197 .addr = omap2430_mmc1_addr_space,
198 .user = OCP_USER_MPU | OCP_USER_SDMA,
199 .flags = OMAP_FIREWALL_L4
202 /* L4 CORE -> MMC2 interface */
203 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
204 .master = &omap3xxx_l4_core_hwmod,
205 .slave = &omap3xxx_mmc2_hwmod,
207 .addr = omap2430_mmc2_addr_space,
208 .user = OCP_USER_MPU | OCP_USER_SDMA,
209 .flags = OMAP_FIREWALL_L4
212 /* L4 CORE -> MMC3 interface */
213 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
215 .pa_start = 0x480ad000,
216 .pa_end = 0x480ad1ff,
217 .flags = ADDR_TYPE_RT,
222 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
223 .master = &omap3xxx_l4_core_hwmod,
224 .slave = &omap3xxx_mmc3_hwmod,
226 .addr = omap3xxx_mmc3_addr_space,
227 .user = OCP_USER_MPU | OCP_USER_SDMA,
228 .flags = OMAP_FIREWALL_L4
231 /* L4 CORE -> UART1 interface */
232 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
234 .pa_start = OMAP3_UART1_BASE,
235 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
236 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
241 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
242 .master = &omap3xxx_l4_core_hwmod,
243 .slave = &omap3xxx_uart1_hwmod,
245 .addr = omap3xxx_uart1_addr_space,
246 .user = OCP_USER_MPU | OCP_USER_SDMA,
249 /* L4 CORE -> UART2 interface */
250 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
252 .pa_start = OMAP3_UART2_BASE,
253 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
254 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
259 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
260 .master = &omap3xxx_l4_core_hwmod,
261 .slave = &omap3xxx_uart2_hwmod,
263 .addr = omap3xxx_uart2_addr_space,
264 .user = OCP_USER_MPU | OCP_USER_SDMA,
267 /* L4 PER -> UART3 interface */
268 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
270 .pa_start = OMAP3_UART3_BASE,
271 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
272 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
277 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
278 .master = &omap3xxx_l4_per_hwmod,
279 .slave = &omap3xxx_uart3_hwmod,
281 .addr = omap3xxx_uart3_addr_space,
282 .user = OCP_USER_MPU | OCP_USER_SDMA,
285 /* L4 PER -> UART4 interface */
286 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
288 .pa_start = OMAP3_UART4_BASE,
289 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
290 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
295 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
296 .master = &omap3xxx_l4_per_hwmod,
297 .slave = &omap3xxx_uart4_hwmod,
299 .addr = omap3xxx_uart4_addr_space,
300 .user = OCP_USER_MPU | OCP_USER_SDMA,
303 /* L4 CORE -> I2C1 interface */
304 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
305 .master = &omap3xxx_l4_core_hwmod,
306 .slave = &omap3xxx_i2c1_hwmod,
308 .addr = omap2_i2c1_addr_space,
311 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
313 .flags = OMAP_FIREWALL_L4,
316 .user = OCP_USER_MPU | OCP_USER_SDMA,
319 /* L4 CORE -> I2C2 interface */
320 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
321 .master = &omap3xxx_l4_core_hwmod,
322 .slave = &omap3xxx_i2c2_hwmod,
324 .addr = omap2_i2c2_addr_space,
327 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
329 .flags = OMAP_FIREWALL_L4,
332 .user = OCP_USER_MPU | OCP_USER_SDMA,
335 /* L4 CORE -> I2C3 interface */
336 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
338 .pa_start = 0x48060000,
339 .pa_end = 0x48060000 + SZ_128 - 1,
340 .flags = ADDR_TYPE_RT,
345 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
346 .master = &omap3xxx_l4_core_hwmod,
347 .slave = &omap3xxx_i2c3_hwmod,
349 .addr = omap3xxx_i2c3_addr_space,
352 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
354 .flags = OMAP_FIREWALL_L4,
357 .user = OCP_USER_MPU | OCP_USER_SDMA,
360 /* L4 CORE -> SR1 interface */
361 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
363 .pa_start = OMAP34XX_SR1_BASE,
364 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
365 .flags = ADDR_TYPE_RT,
370 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
371 .master = &omap3xxx_l4_core_hwmod,
372 .slave = &omap34xx_sr1_hwmod,
374 .addr = omap3_sr1_addr_space,
375 .user = OCP_USER_MPU,
378 /* L4 CORE -> SR1 interface */
379 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
381 .pa_start = OMAP34XX_SR2_BASE,
382 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
383 .flags = ADDR_TYPE_RT,
388 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
389 .master = &omap3xxx_l4_core_hwmod,
390 .slave = &omap34xx_sr2_hwmod,
392 .addr = omap3_sr2_addr_space,
393 .user = OCP_USER_MPU,
397 * usbhsotg interface data
400 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
402 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
403 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
404 .flags = ADDR_TYPE_RT
409 /* l4_core -> usbhsotg */
410 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
411 .master = &omap3xxx_l4_core_hwmod,
412 .slave = &omap3xxx_usbhsotg_hwmod,
414 .addr = omap3xxx_usbhsotg_addrs,
415 .user = OCP_USER_MPU,
418 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
419 &omap3xxx_usbhsotg__l3,
422 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
423 &omap3xxx_l4_core__usbhsotg,
426 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
428 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
429 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
430 .flags = ADDR_TYPE_RT
435 /* l4_core -> usbhsotg */
436 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
437 .master = &omap3xxx_l4_core_hwmod,
438 .slave = &am35xx_usbhsotg_hwmod,
440 .addr = am35xx_usbhsotg_addrs,
441 .user = OCP_USER_MPU,
444 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
445 &am35xx_usbhsotg__l3,
448 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
449 &am35xx_l4_core__usbhsotg,
451 /* Slave interfaces on the L4_CORE interconnect */
452 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
453 &omap3xxx_l3_main__l4_core,
457 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
459 .class = &l4_hwmod_class,
460 .slaves = omap3xxx_l4_core_slaves,
461 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
462 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
463 .flags = HWMOD_NO_IDLEST,
466 /* Slave interfaces on the L4_PER interconnect */
467 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
468 &omap3xxx_l3_main__l4_per,
472 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
474 .class = &l4_hwmod_class,
475 .slaves = omap3xxx_l4_per_slaves,
476 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
477 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
478 .flags = HWMOD_NO_IDLEST,
481 /* Slave interfaces on the L4_WKUP interconnect */
482 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
483 &omap3xxx_l4_core__l4_wkup,
487 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
489 .class = &l4_hwmod_class,
490 .slaves = omap3xxx_l4_wkup_slaves,
491 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
492 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
493 .flags = HWMOD_NO_IDLEST,
496 /* Master interfaces on the MPU device */
497 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
498 &omap3xxx_mpu__l3_main,
502 static struct omap_hwmod omap3xxx_mpu_hwmod = {
504 .class = &mpu_hwmod_class,
505 .main_clk = "arm_fck",
506 .masters = omap3xxx_mpu_masters,
507 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
508 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
512 * IVA2_2 interface data
515 /* IVA2 <- L3 interface */
516 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
517 .master = &omap3xxx_l3_main_hwmod,
518 .slave = &omap3xxx_iva_hwmod,
520 .user = OCP_USER_MPU | OCP_USER_SDMA,
523 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
531 static struct omap_hwmod omap3xxx_iva_hwmod = {
533 .class = &iva_hwmod_class,
534 .masters = omap3xxx_iva_masters,
535 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
536 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
540 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
544 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
545 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
546 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
547 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
548 .sysc_fields = &omap_hwmod_sysc_type1,
551 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
553 .sysc = &omap3xxx_timer_1ms_sysc,
554 .rev = OMAP_TIMER_IP_VERSION_1,
557 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
561 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
562 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
563 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
564 .sysc_fields = &omap_hwmod_sysc_type1,
567 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
569 .sysc = &omap3xxx_timer_sysc,
570 .rev = OMAP_TIMER_IP_VERSION_1,
574 static struct omap_hwmod omap3xxx_timer1_hwmod;
575 static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
580 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
582 .pa_start = 0x48318000,
583 .pa_end = 0x48318000 + SZ_1K - 1,
584 .flags = ADDR_TYPE_RT
589 /* l4_wkup -> timer1 */
590 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
591 .master = &omap3xxx_l4_wkup_hwmod,
592 .slave = &omap3xxx_timer1_hwmod,
594 .addr = omap3xxx_timer1_addrs,
595 .user = OCP_USER_MPU | OCP_USER_SDMA,
598 /* timer1 slave port */
599 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
600 &omap3xxx_l4_wkup__timer1,
604 static struct omap_hwmod omap3xxx_timer1_hwmod = {
606 .mpu_irqs = omap3xxx_timer1_mpu_irqs,
607 .main_clk = "gpt1_fck",
611 .module_bit = OMAP3430_EN_GPT1_SHIFT,
612 .module_offs = WKUP_MOD,
614 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
617 .slaves = omap3xxx_timer1_slaves,
618 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
619 .class = &omap3xxx_timer_1ms_hwmod_class,
620 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
624 static struct omap_hwmod omap3xxx_timer2_hwmod;
625 static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
630 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
632 .pa_start = 0x49032000,
633 .pa_end = 0x49032000 + SZ_1K - 1,
634 .flags = ADDR_TYPE_RT
639 /* l4_per -> timer2 */
640 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
641 .master = &omap3xxx_l4_per_hwmod,
642 .slave = &omap3xxx_timer2_hwmod,
644 .addr = omap3xxx_timer2_addrs,
645 .user = OCP_USER_MPU | OCP_USER_SDMA,
648 /* timer2 slave port */
649 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
650 &omap3xxx_l4_per__timer2,
654 static struct omap_hwmod omap3xxx_timer2_hwmod = {
656 .mpu_irqs = omap3xxx_timer2_mpu_irqs,
657 .main_clk = "gpt2_fck",
661 .module_bit = OMAP3430_EN_GPT2_SHIFT,
662 .module_offs = OMAP3430_PER_MOD,
664 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
667 .slaves = omap3xxx_timer2_slaves,
668 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
669 .class = &omap3xxx_timer_1ms_hwmod_class,
670 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
674 static struct omap_hwmod omap3xxx_timer3_hwmod;
675 static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
680 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
682 .pa_start = 0x49034000,
683 .pa_end = 0x49034000 + SZ_1K - 1,
684 .flags = ADDR_TYPE_RT
689 /* l4_per -> timer3 */
690 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
691 .master = &omap3xxx_l4_per_hwmod,
692 .slave = &omap3xxx_timer3_hwmod,
694 .addr = omap3xxx_timer3_addrs,
695 .user = OCP_USER_MPU | OCP_USER_SDMA,
698 /* timer3 slave port */
699 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
700 &omap3xxx_l4_per__timer3,
704 static struct omap_hwmod omap3xxx_timer3_hwmod = {
706 .mpu_irqs = omap3xxx_timer3_mpu_irqs,
707 .main_clk = "gpt3_fck",
711 .module_bit = OMAP3430_EN_GPT3_SHIFT,
712 .module_offs = OMAP3430_PER_MOD,
714 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
717 .slaves = omap3xxx_timer3_slaves,
718 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
719 .class = &omap3xxx_timer_hwmod_class,
720 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
724 static struct omap_hwmod omap3xxx_timer4_hwmod;
725 static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
730 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
732 .pa_start = 0x49036000,
733 .pa_end = 0x49036000 + SZ_1K - 1,
734 .flags = ADDR_TYPE_RT
739 /* l4_per -> timer4 */
740 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
741 .master = &omap3xxx_l4_per_hwmod,
742 .slave = &omap3xxx_timer4_hwmod,
744 .addr = omap3xxx_timer4_addrs,
745 .user = OCP_USER_MPU | OCP_USER_SDMA,
748 /* timer4 slave port */
749 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
750 &omap3xxx_l4_per__timer4,
754 static struct omap_hwmod omap3xxx_timer4_hwmod = {
756 .mpu_irqs = omap3xxx_timer4_mpu_irqs,
757 .main_clk = "gpt4_fck",
761 .module_bit = OMAP3430_EN_GPT4_SHIFT,
762 .module_offs = OMAP3430_PER_MOD,
764 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
767 .slaves = omap3xxx_timer4_slaves,
768 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
769 .class = &omap3xxx_timer_hwmod_class,
770 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
774 static struct omap_hwmod omap3xxx_timer5_hwmod;
775 static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
780 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
782 .pa_start = 0x49038000,
783 .pa_end = 0x49038000 + SZ_1K - 1,
784 .flags = ADDR_TYPE_RT
789 /* l4_per -> timer5 */
790 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
791 .master = &omap3xxx_l4_per_hwmod,
792 .slave = &omap3xxx_timer5_hwmod,
794 .addr = omap3xxx_timer5_addrs,
795 .user = OCP_USER_MPU | OCP_USER_SDMA,
798 /* timer5 slave port */
799 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
800 &omap3xxx_l4_per__timer5,
804 static struct omap_hwmod omap3xxx_timer5_hwmod = {
806 .mpu_irqs = omap3xxx_timer5_mpu_irqs,
807 .main_clk = "gpt5_fck",
811 .module_bit = OMAP3430_EN_GPT5_SHIFT,
812 .module_offs = OMAP3430_PER_MOD,
814 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
817 .slaves = omap3xxx_timer5_slaves,
818 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
819 .class = &omap3xxx_timer_hwmod_class,
820 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
824 static struct omap_hwmod omap3xxx_timer6_hwmod;
825 static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
830 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
832 .pa_start = 0x4903A000,
833 .pa_end = 0x4903A000 + SZ_1K - 1,
834 .flags = ADDR_TYPE_RT
839 /* l4_per -> timer6 */
840 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
841 .master = &omap3xxx_l4_per_hwmod,
842 .slave = &omap3xxx_timer6_hwmod,
844 .addr = omap3xxx_timer6_addrs,
845 .user = OCP_USER_MPU | OCP_USER_SDMA,
848 /* timer6 slave port */
849 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
850 &omap3xxx_l4_per__timer6,
854 static struct omap_hwmod omap3xxx_timer6_hwmod = {
856 .mpu_irqs = omap3xxx_timer6_mpu_irqs,
857 .main_clk = "gpt6_fck",
861 .module_bit = OMAP3430_EN_GPT6_SHIFT,
862 .module_offs = OMAP3430_PER_MOD,
864 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
867 .slaves = omap3xxx_timer6_slaves,
868 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
869 .class = &omap3xxx_timer_hwmod_class,
870 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
874 static struct omap_hwmod omap3xxx_timer7_hwmod;
875 static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
880 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
882 .pa_start = 0x4903C000,
883 .pa_end = 0x4903C000 + SZ_1K - 1,
884 .flags = ADDR_TYPE_RT
889 /* l4_per -> timer7 */
890 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
891 .master = &omap3xxx_l4_per_hwmod,
892 .slave = &omap3xxx_timer7_hwmod,
894 .addr = omap3xxx_timer7_addrs,
895 .user = OCP_USER_MPU | OCP_USER_SDMA,
898 /* timer7 slave port */
899 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
900 &omap3xxx_l4_per__timer7,
904 static struct omap_hwmod omap3xxx_timer7_hwmod = {
906 .mpu_irqs = omap3xxx_timer7_mpu_irqs,
907 .main_clk = "gpt7_fck",
911 .module_bit = OMAP3430_EN_GPT7_SHIFT,
912 .module_offs = OMAP3430_PER_MOD,
914 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
917 .slaves = omap3xxx_timer7_slaves,
918 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
919 .class = &omap3xxx_timer_hwmod_class,
920 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
924 static struct omap_hwmod omap3xxx_timer8_hwmod;
925 static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
930 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
932 .pa_start = 0x4903E000,
933 .pa_end = 0x4903E000 + SZ_1K - 1,
934 .flags = ADDR_TYPE_RT
939 /* l4_per -> timer8 */
940 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
941 .master = &omap3xxx_l4_per_hwmod,
942 .slave = &omap3xxx_timer8_hwmod,
944 .addr = omap3xxx_timer8_addrs,
945 .user = OCP_USER_MPU | OCP_USER_SDMA,
948 /* timer8 slave port */
949 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
950 &omap3xxx_l4_per__timer8,
954 static struct omap_hwmod omap3xxx_timer8_hwmod = {
956 .mpu_irqs = omap3xxx_timer8_mpu_irqs,
957 .main_clk = "gpt8_fck",
961 .module_bit = OMAP3430_EN_GPT8_SHIFT,
962 .module_offs = OMAP3430_PER_MOD,
964 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
967 .slaves = omap3xxx_timer8_slaves,
968 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
969 .class = &omap3xxx_timer_hwmod_class,
970 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
974 static struct omap_hwmod omap3xxx_timer9_hwmod;
975 static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
980 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
982 .pa_start = 0x49040000,
983 .pa_end = 0x49040000 + SZ_1K - 1,
984 .flags = ADDR_TYPE_RT
989 /* l4_per -> timer9 */
990 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
991 .master = &omap3xxx_l4_per_hwmod,
992 .slave = &omap3xxx_timer9_hwmod,
994 .addr = omap3xxx_timer9_addrs,
995 .user = OCP_USER_MPU | OCP_USER_SDMA,
998 /* timer9 slave port */
999 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1000 &omap3xxx_l4_per__timer9,
1004 static struct omap_hwmod omap3xxx_timer9_hwmod = {
1006 .mpu_irqs = omap3xxx_timer9_mpu_irqs,
1007 .main_clk = "gpt9_fck",
1011 .module_bit = OMAP3430_EN_GPT9_SHIFT,
1012 .module_offs = OMAP3430_PER_MOD,
1014 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1017 .slaves = omap3xxx_timer9_slaves,
1018 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
1019 .class = &omap3xxx_timer_hwmod_class,
1020 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1024 static struct omap_hwmod omap3xxx_timer10_hwmod;
1025 static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1030 /* l4_core -> timer10 */
1031 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1032 .master = &omap3xxx_l4_core_hwmod,
1033 .slave = &omap3xxx_timer10_hwmod,
1035 .addr = omap2_timer10_addrs,
1036 .user = OCP_USER_MPU | OCP_USER_SDMA,
1039 /* timer10 slave port */
1040 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1041 &omap3xxx_l4_core__timer10,
1045 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1047 .mpu_irqs = omap3xxx_timer10_mpu_irqs,
1048 .main_clk = "gpt10_fck",
1052 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1053 .module_offs = CORE_MOD,
1055 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1058 .slaves = omap3xxx_timer10_slaves,
1059 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1060 .class = &omap3xxx_timer_1ms_hwmod_class,
1061 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1065 static struct omap_hwmod omap3xxx_timer11_hwmod;
1066 static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1071 /* l4_core -> timer11 */
1072 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1073 .master = &omap3xxx_l4_core_hwmod,
1074 .slave = &omap3xxx_timer11_hwmod,
1076 .addr = omap2_timer11_addrs,
1077 .user = OCP_USER_MPU | OCP_USER_SDMA,
1080 /* timer11 slave port */
1081 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1082 &omap3xxx_l4_core__timer11,
1086 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1088 .mpu_irqs = omap3xxx_timer11_mpu_irqs,
1089 .main_clk = "gpt11_fck",
1093 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1094 .module_offs = CORE_MOD,
1096 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1099 .slaves = omap3xxx_timer11_slaves,
1100 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1101 .class = &omap3xxx_timer_hwmod_class,
1102 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1106 static struct omap_hwmod omap3xxx_timer12_hwmod;
1107 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1112 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1114 .pa_start = 0x48304000,
1115 .pa_end = 0x48304000 + SZ_1K - 1,
1116 .flags = ADDR_TYPE_RT
1121 /* l4_core -> timer12 */
1122 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1123 .master = &omap3xxx_l4_core_hwmod,
1124 .slave = &omap3xxx_timer12_hwmod,
1126 .addr = omap3xxx_timer12_addrs,
1127 .user = OCP_USER_MPU | OCP_USER_SDMA,
1130 /* timer12 slave port */
1131 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1132 &omap3xxx_l4_core__timer12,
1136 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1138 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1139 .main_clk = "gpt12_fck",
1143 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1144 .module_offs = WKUP_MOD,
1146 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1149 .slaves = omap3xxx_timer12_slaves,
1150 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1151 .class = &omap3xxx_timer_hwmod_class,
1152 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1155 /* l4_wkup -> wd_timer2 */
1156 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1158 .pa_start = 0x48314000,
1159 .pa_end = 0x4831407f,
1160 .flags = ADDR_TYPE_RT
1165 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1166 .master = &omap3xxx_l4_wkup_hwmod,
1167 .slave = &omap3xxx_wd_timer2_hwmod,
1169 .addr = omap3xxx_wd_timer2_addrs,
1170 .user = OCP_USER_MPU | OCP_USER_SDMA,
1175 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1176 * overflow condition
1179 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1181 .sysc_offs = 0x0010,
1182 .syss_offs = 0x0014,
1183 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1184 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1185 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1186 SYSS_HAS_RESET_STATUS),
1187 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1188 .sysc_fields = &omap_hwmod_sysc_type1,
1192 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1196 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1197 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1198 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1199 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1200 .sysc_fields = &omap_hwmod_sysc_type1,
1203 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1205 .sysc = &omap3xxx_wd_timer_sysc,
1206 .pre_shutdown = &omap2_wd_timer_disable
1210 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1211 &omap3xxx_l4_wkup__wd_timer2,
1214 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1215 .name = "wd_timer2",
1216 .class = &omap3xxx_wd_timer_hwmod_class,
1217 .main_clk = "wdt2_fck",
1221 .module_bit = OMAP3430_EN_WDT2_SHIFT,
1222 .module_offs = WKUP_MOD,
1224 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1227 .slaves = omap3xxx_wd_timer2_slaves,
1228 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1229 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1231 * XXX: Use software supervised mode, HW supervised smartidle seems to
1232 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1234 .flags = HWMOD_SWSUP_SIDLE,
1239 static struct omap_hwmod_class_sysconfig uart_sysc = {
1243 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1244 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1245 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1246 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1247 .sysc_fields = &omap_hwmod_sysc_type1,
1250 static struct omap_hwmod_class uart_class = {
1257 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1258 { .irq = INT_24XX_UART1_IRQ, },
1262 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1263 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1264 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1267 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1268 &omap3_l4_core__uart1,
1271 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1273 .mpu_irqs = uart1_mpu_irqs,
1274 .sdma_reqs = uart1_sdma_reqs,
1275 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1276 .main_clk = "uart1_fck",
1279 .module_offs = CORE_MOD,
1281 .module_bit = OMAP3430_EN_UART1_SHIFT,
1283 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1286 .slaves = omap3xxx_uart1_slaves,
1287 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1288 .class = &uart_class,
1289 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1294 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1295 { .irq = INT_24XX_UART2_IRQ, },
1299 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1300 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1301 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1304 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1305 &omap3_l4_core__uart2,
1308 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1310 .mpu_irqs = uart2_mpu_irqs,
1311 .sdma_reqs = uart2_sdma_reqs,
1312 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1313 .main_clk = "uart2_fck",
1316 .module_offs = CORE_MOD,
1318 .module_bit = OMAP3430_EN_UART2_SHIFT,
1320 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1323 .slaves = omap3xxx_uart2_slaves,
1324 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1325 .class = &uart_class,
1326 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1331 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1332 { .irq = INT_24XX_UART3_IRQ, },
1336 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1337 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1338 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1341 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1342 &omap3_l4_per__uart3,
1345 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1347 .mpu_irqs = uart3_mpu_irqs,
1348 .sdma_reqs = uart3_sdma_reqs,
1349 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1350 .main_clk = "uart3_fck",
1353 .module_offs = OMAP3430_PER_MOD,
1355 .module_bit = OMAP3430_EN_UART3_SHIFT,
1357 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1360 .slaves = omap3xxx_uart3_slaves,
1361 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1362 .class = &uart_class,
1363 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1368 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1369 { .irq = INT_36XX_UART4_IRQ, },
1373 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1374 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1375 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1378 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1379 &omap3_l4_per__uart4,
1382 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1384 .mpu_irqs = uart4_mpu_irqs,
1385 .sdma_reqs = uart4_sdma_reqs,
1386 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
1387 .main_clk = "uart4_fck",
1390 .module_offs = OMAP3430_PER_MOD,
1392 .module_bit = OMAP3630_EN_UART4_SHIFT,
1394 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1397 .slaves = omap3xxx_uart4_slaves,
1398 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1399 .class = &uart_class,
1400 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1403 static struct omap_hwmod_class i2c_class = {
1410 * display sub-system
1413 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1415 .sysc_offs = 0x0010,
1416 .syss_offs = 0x0014,
1417 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1418 .sysc_fields = &omap_hwmod_sysc_type1,
1421 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1423 .sysc = &omap3xxx_dss_sysc,
1426 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1427 { .name = "dispc", .dma_req = 5 },
1428 { .name = "dsi1", .dma_req = 74 },
1432 /* dss master ports */
1433 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1437 /* l4_core -> dss */
1438 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1439 .master = &omap3xxx_l4_core_hwmod,
1440 .slave = &omap3430es1_dss_core_hwmod,
1442 .addr = omap2_dss_addrs,
1445 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1446 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1447 .flags = OMAP_FIREWALL_L4,
1450 .user = OCP_USER_MPU | OCP_USER_SDMA,
1453 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1454 .master = &omap3xxx_l4_core_hwmod,
1455 .slave = &omap3xxx_dss_core_hwmod,
1457 .addr = omap2_dss_addrs,
1460 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1461 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1462 .flags = OMAP_FIREWALL_L4,
1465 .user = OCP_USER_MPU | OCP_USER_SDMA,
1468 /* dss slave ports */
1469 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1470 &omap3430es1_l4_core__dss,
1473 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1474 &omap3xxx_l4_core__dss,
1477 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1478 { .role = "tv_clk", .clk = "dss_tv_fck" },
1479 { .role = "video_clk", .clk = "dss_96m_fck" },
1480 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1483 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1485 .class = &omap3xxx_dss_hwmod_class,
1486 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1487 .sdma_reqs = omap3xxx_dss_sdma_chs,
1488 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1493 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1494 .module_offs = OMAP3430_DSS_MOD,
1496 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1499 .opt_clks = dss_opt_clks,
1500 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1501 .slaves = omap3430es1_dss_slaves,
1502 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1503 .masters = omap3xxx_dss_masters,
1504 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1505 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1506 .flags = HWMOD_NO_IDLEST,
1509 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1511 .class = &omap3xxx_dss_hwmod_class,
1512 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1513 .sdma_reqs = omap3xxx_dss_sdma_chs,
1514 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1519 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1520 .module_offs = OMAP3430_DSS_MOD,
1522 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1523 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1526 .opt_clks = dss_opt_clks,
1527 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1528 .slaves = omap3xxx_dss_slaves,
1529 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1530 .masters = omap3xxx_dss_masters,
1531 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1532 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1533 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1538 * display controller
1541 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1543 .sysc_offs = 0x0010,
1544 .syss_offs = 0x0014,
1545 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1546 SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1547 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1548 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1549 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1550 .sysc_fields = &omap_hwmod_sysc_type1,
1553 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1555 .sysc = &omap3xxx_dispc_sysc,
1558 static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
1563 /* l4_core -> dss_dispc */
1564 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1565 .master = &omap3xxx_l4_core_hwmod,
1566 .slave = &omap3xxx_dss_dispc_hwmod,
1568 .addr = omap2_dss_dispc_addrs,
1571 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1572 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1573 .flags = OMAP_FIREWALL_L4,
1576 .user = OCP_USER_MPU | OCP_USER_SDMA,
1579 /* dss_dispc slave ports */
1580 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1581 &omap3xxx_l4_core__dss_dispc,
1584 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1585 .name = "dss_dispc",
1586 .class = &omap3xxx_dispc_hwmod_class,
1587 .mpu_irqs = omap3xxx_dispc_irqs,
1588 .main_clk = "dss1_alwon_fck",
1592 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1593 .module_offs = OMAP3430_DSS_MOD,
1596 .slaves = omap3xxx_dss_dispc_slaves,
1597 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1598 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1599 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1600 CHIP_GE_OMAP3630ES1_1),
1601 .flags = HWMOD_NO_IDLEST,
1606 * display serial interface controller
1609 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1613 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1619 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1621 .pa_start = 0x4804FC00,
1622 .pa_end = 0x4804FFFF,
1623 .flags = ADDR_TYPE_RT
1628 /* l4_core -> dss_dsi1 */
1629 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1630 .master = &omap3xxx_l4_core_hwmod,
1631 .slave = &omap3xxx_dss_dsi1_hwmod,
1632 .addr = omap3xxx_dss_dsi1_addrs,
1635 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1636 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1637 .flags = OMAP_FIREWALL_L4,
1640 .user = OCP_USER_MPU | OCP_USER_SDMA,
1643 /* dss_dsi1 slave ports */
1644 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1645 &omap3xxx_l4_core__dss_dsi1,
1648 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1650 .class = &omap3xxx_dsi_hwmod_class,
1651 .mpu_irqs = omap3xxx_dsi1_irqs,
1652 .main_clk = "dss1_alwon_fck",
1656 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1657 .module_offs = OMAP3430_DSS_MOD,
1660 .slaves = omap3xxx_dss_dsi1_slaves,
1661 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1662 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1663 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1664 CHIP_GE_OMAP3630ES1_1),
1665 .flags = HWMOD_NO_IDLEST,
1670 * remote frame buffer interface
1673 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1675 .sysc_offs = 0x0010,
1676 .syss_offs = 0x0014,
1677 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1679 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1680 .sysc_fields = &omap_hwmod_sysc_type1,
1683 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1685 .sysc = &omap3xxx_rfbi_sysc,
1688 /* l4_core -> dss_rfbi */
1689 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1690 .master = &omap3xxx_l4_core_hwmod,
1691 .slave = &omap3xxx_dss_rfbi_hwmod,
1693 .addr = omap2_dss_rfbi_addrs,
1696 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1697 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1698 .flags = OMAP_FIREWALL_L4,
1701 .user = OCP_USER_MPU | OCP_USER_SDMA,
1704 /* dss_rfbi slave ports */
1705 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1706 &omap3xxx_l4_core__dss_rfbi,
1709 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1711 .class = &omap3xxx_rfbi_hwmod_class,
1712 .main_clk = "dss1_alwon_fck",
1716 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1717 .module_offs = OMAP3430_DSS_MOD,
1720 .slaves = omap3xxx_dss_rfbi_slaves,
1721 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1722 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1723 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1724 CHIP_GE_OMAP3630ES1_1),
1725 .flags = HWMOD_NO_IDLEST,
1733 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1737 /* l4_core -> dss_venc */
1738 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1739 .master = &omap3xxx_l4_core_hwmod,
1740 .slave = &omap3xxx_dss_venc_hwmod,
1741 .clk = "dss_tv_fck",
1742 .addr = omap2_dss_venc_addrs,
1745 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1746 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1747 .flags = OMAP_FIREWALL_L4,
1750 .flags = OCPIF_SWSUP_IDLE,
1751 .user = OCP_USER_MPU | OCP_USER_SDMA,
1754 /* dss_venc slave ports */
1755 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1756 &omap3xxx_l4_core__dss_venc,
1759 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1761 .class = &omap3xxx_venc_hwmod_class,
1762 .main_clk = "dss1_alwon_fck",
1766 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1767 .module_offs = OMAP3430_DSS_MOD,
1770 .slaves = omap3xxx_dss_venc_slaves,
1771 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1772 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1773 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1774 CHIP_GE_OMAP3630ES1_1),
1775 .flags = HWMOD_NO_IDLEST,
1780 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1781 .fifo_depth = 8, /* bytes */
1784 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1785 { .irq = INT_24XX_I2C1_IRQ, },
1789 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1790 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1791 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1794 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1795 &omap3_l4_core__i2c1,
1798 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1800 .mpu_irqs = i2c1_mpu_irqs,
1801 .sdma_reqs = i2c1_sdma_reqs,
1802 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1803 .main_clk = "i2c1_fck",
1806 .module_offs = CORE_MOD,
1808 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1810 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1813 .slaves = omap3xxx_i2c1_slaves,
1814 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1815 .class = &i2c_class,
1816 .dev_attr = &i2c1_dev_attr,
1817 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1822 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1823 .fifo_depth = 8, /* bytes */
1826 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1827 { .irq = INT_24XX_I2C2_IRQ, },
1831 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1832 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1833 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1836 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1837 &omap3_l4_core__i2c2,
1840 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1842 .mpu_irqs = i2c2_mpu_irqs,
1843 .sdma_reqs = i2c2_sdma_reqs,
1844 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1845 .main_clk = "i2c2_fck",
1848 .module_offs = CORE_MOD,
1850 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1852 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1855 .slaves = omap3xxx_i2c2_slaves,
1856 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1857 .class = &i2c_class,
1858 .dev_attr = &i2c2_dev_attr,
1859 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1864 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1865 .fifo_depth = 64, /* bytes */
1868 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1869 { .irq = INT_34XX_I2C3_IRQ, },
1873 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1874 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1875 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1878 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1879 &omap3_l4_core__i2c3,
1882 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1884 .mpu_irqs = i2c3_mpu_irqs,
1885 .sdma_reqs = i2c3_sdma_reqs,
1886 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
1887 .main_clk = "i2c3_fck",
1890 .module_offs = CORE_MOD,
1892 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1894 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1897 .slaves = omap3xxx_i2c3_slaves,
1898 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1899 .class = &i2c_class,
1900 .dev_attr = &i2c3_dev_attr,
1901 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1904 /* l4_wkup -> gpio1 */
1905 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1907 .pa_start = 0x48310000,
1908 .pa_end = 0x483101ff,
1909 .flags = ADDR_TYPE_RT
1914 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1915 .master = &omap3xxx_l4_wkup_hwmod,
1916 .slave = &omap3xxx_gpio1_hwmod,
1917 .addr = omap3xxx_gpio1_addrs,
1918 .user = OCP_USER_MPU | OCP_USER_SDMA,
1921 /* l4_per -> gpio2 */
1922 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1924 .pa_start = 0x49050000,
1925 .pa_end = 0x490501ff,
1926 .flags = ADDR_TYPE_RT
1931 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1932 .master = &omap3xxx_l4_per_hwmod,
1933 .slave = &omap3xxx_gpio2_hwmod,
1934 .addr = omap3xxx_gpio2_addrs,
1935 .user = OCP_USER_MPU | OCP_USER_SDMA,
1938 /* l4_per -> gpio3 */
1939 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1941 .pa_start = 0x49052000,
1942 .pa_end = 0x490521ff,
1943 .flags = ADDR_TYPE_RT
1948 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1949 .master = &omap3xxx_l4_per_hwmod,
1950 .slave = &omap3xxx_gpio3_hwmod,
1951 .addr = omap3xxx_gpio3_addrs,
1952 .user = OCP_USER_MPU | OCP_USER_SDMA,
1955 /* l4_per -> gpio4 */
1956 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1958 .pa_start = 0x49054000,
1959 .pa_end = 0x490541ff,
1960 .flags = ADDR_TYPE_RT
1965 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1966 .master = &omap3xxx_l4_per_hwmod,
1967 .slave = &omap3xxx_gpio4_hwmod,
1968 .addr = omap3xxx_gpio4_addrs,
1969 .user = OCP_USER_MPU | OCP_USER_SDMA,
1972 /* l4_per -> gpio5 */
1973 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1975 .pa_start = 0x49056000,
1976 .pa_end = 0x490561ff,
1977 .flags = ADDR_TYPE_RT
1982 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1983 .master = &omap3xxx_l4_per_hwmod,
1984 .slave = &omap3xxx_gpio5_hwmod,
1985 .addr = omap3xxx_gpio5_addrs,
1986 .user = OCP_USER_MPU | OCP_USER_SDMA,
1989 /* l4_per -> gpio6 */
1990 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1992 .pa_start = 0x49058000,
1993 .pa_end = 0x490581ff,
1994 .flags = ADDR_TYPE_RT
1999 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2000 .master = &omap3xxx_l4_per_hwmod,
2001 .slave = &omap3xxx_gpio6_hwmod,
2002 .addr = omap3xxx_gpio6_addrs,
2003 .user = OCP_USER_MPU | OCP_USER_SDMA,
2008 * general purpose io module
2011 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
2013 .sysc_offs = 0x0010,
2014 .syss_offs = 0x0014,
2015 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2016 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
2017 SYSS_HAS_RESET_STATUS),
2018 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2019 .sysc_fields = &omap_hwmod_sysc_type1,
2022 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
2024 .sysc = &omap3xxx_gpio_sysc,
2029 static struct omap_gpio_dev_attr gpio_dev_attr = {
2035 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
2036 { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
2040 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
2041 { .role = "dbclk", .clk = "gpio1_dbck", },
2044 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
2045 &omap3xxx_l4_wkup__gpio1,
2048 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2050 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2051 .mpu_irqs = omap3xxx_gpio1_irqs,
2052 .main_clk = "gpio1_ick",
2053 .opt_clks = gpio1_opt_clks,
2054 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
2058 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
2059 .module_offs = WKUP_MOD,
2061 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
2064 .slaves = omap3xxx_gpio1_slaves,
2065 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
2066 .class = &omap3xxx_gpio_hwmod_class,
2067 .dev_attr = &gpio_dev_attr,
2068 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2072 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
2073 { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
2077 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
2078 { .role = "dbclk", .clk = "gpio2_dbck", },
2081 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
2082 &omap3xxx_l4_per__gpio2,
2085 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2087 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2088 .mpu_irqs = omap3xxx_gpio2_irqs,
2089 .main_clk = "gpio2_ick",
2090 .opt_clks = gpio2_opt_clks,
2091 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
2095 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
2096 .module_offs = OMAP3430_PER_MOD,
2098 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2101 .slaves = omap3xxx_gpio2_slaves,
2102 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2103 .class = &omap3xxx_gpio_hwmod_class,
2104 .dev_attr = &gpio_dev_attr,
2105 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2109 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
2110 { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
2114 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2115 { .role = "dbclk", .clk = "gpio3_dbck", },
2118 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2119 &omap3xxx_l4_per__gpio3,
2122 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2124 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2125 .mpu_irqs = omap3xxx_gpio3_irqs,
2126 .main_clk = "gpio3_ick",
2127 .opt_clks = gpio3_opt_clks,
2128 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
2132 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2133 .module_offs = OMAP3430_PER_MOD,
2135 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2138 .slaves = omap3xxx_gpio3_slaves,
2139 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2140 .class = &omap3xxx_gpio_hwmod_class,
2141 .dev_attr = &gpio_dev_attr,
2142 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2146 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
2147 { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
2151 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2152 { .role = "dbclk", .clk = "gpio4_dbck", },
2155 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2156 &omap3xxx_l4_per__gpio4,
2159 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2161 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2162 .mpu_irqs = omap3xxx_gpio4_irqs,
2163 .main_clk = "gpio4_ick",
2164 .opt_clks = gpio4_opt_clks,
2165 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2169 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2170 .module_offs = OMAP3430_PER_MOD,
2172 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2175 .slaves = omap3xxx_gpio4_slaves,
2176 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2177 .class = &omap3xxx_gpio_hwmod_class,
2178 .dev_attr = &gpio_dev_attr,
2179 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2183 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2184 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2188 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2189 { .role = "dbclk", .clk = "gpio5_dbck", },
2192 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2193 &omap3xxx_l4_per__gpio5,
2196 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2198 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2199 .mpu_irqs = omap3xxx_gpio5_irqs,
2200 .main_clk = "gpio5_ick",
2201 .opt_clks = gpio5_opt_clks,
2202 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2206 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2207 .module_offs = OMAP3430_PER_MOD,
2209 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2212 .slaves = omap3xxx_gpio5_slaves,
2213 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2214 .class = &omap3xxx_gpio_hwmod_class,
2215 .dev_attr = &gpio_dev_attr,
2216 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2220 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2221 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2225 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2226 { .role = "dbclk", .clk = "gpio6_dbck", },
2229 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2230 &omap3xxx_l4_per__gpio6,
2233 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2235 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2236 .mpu_irqs = omap3xxx_gpio6_irqs,
2237 .main_clk = "gpio6_ick",
2238 .opt_clks = gpio6_opt_clks,
2239 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2243 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2244 .module_offs = OMAP3430_PER_MOD,
2246 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2249 .slaves = omap3xxx_gpio6_slaves,
2250 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2251 .class = &omap3xxx_gpio_hwmod_class,
2252 .dev_attr = &gpio_dev_attr,
2253 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2256 /* dma_system -> L3 */
2257 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2258 .master = &omap3xxx_dma_system_hwmod,
2259 .slave = &omap3xxx_l3_main_hwmod,
2260 .clk = "core_l3_ick",
2261 .user = OCP_USER_MPU | OCP_USER_SDMA,
2264 /* dma attributes */
2265 static struct omap_dma_dev_attr dma_dev_attr = {
2266 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2267 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2271 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2273 .sysc_offs = 0x002c,
2274 .syss_offs = 0x0028,
2275 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2276 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2277 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2278 SYSS_HAS_RESET_STATUS),
2279 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2280 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2281 .sysc_fields = &omap_hwmod_sysc_type1,
2284 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2286 .sysc = &omap3xxx_dma_sysc,
2290 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
2291 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
2292 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
2293 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
2294 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
2298 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2300 .pa_start = 0x48056000,
2301 .pa_end = 0x48056fff,
2302 .flags = ADDR_TYPE_RT
2307 /* dma_system master ports */
2308 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2309 &omap3xxx_dma_system__l3,
2312 /* l4_cfg -> dma_system */
2313 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2314 .master = &omap3xxx_l4_core_hwmod,
2315 .slave = &omap3xxx_dma_system_hwmod,
2316 .clk = "core_l4_ick",
2317 .addr = omap3xxx_dma_system_addrs,
2318 .user = OCP_USER_MPU | OCP_USER_SDMA,
2321 /* dma_system slave ports */
2322 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2323 &omap3xxx_l4_core__dma_system,
2326 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2328 .class = &omap3xxx_dma_hwmod_class,
2329 .mpu_irqs = omap3xxx_dma_system_irqs,
2330 .main_clk = "core_l3_ick",
2333 .module_offs = CORE_MOD,
2335 .module_bit = OMAP3430_ST_SDMA_SHIFT,
2337 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2340 .slaves = omap3xxx_dma_system_slaves,
2341 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2342 .masters = omap3xxx_dma_system_masters,
2343 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2344 .dev_attr = &dma_dev_attr,
2345 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2346 .flags = HWMOD_NO_IDLEST,
2351 * multi channel buffered serial port controller
2354 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2355 .sysc_offs = 0x008c,
2356 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2357 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2358 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2359 .sysc_fields = &omap_hwmod_sysc_type1,
2363 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2365 .sysc = &omap3xxx_mcbsp_sysc,
2366 .rev = MCBSP_CONFIG_TYPE3,
2370 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2371 { .name = "irq", .irq = 16 },
2372 { .name = "tx", .irq = 59 },
2373 { .name = "rx", .irq = 60 },
2377 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2378 { .name = "rx", .dma_req = 32 },
2379 { .name = "tx", .dma_req = 31 },
2382 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2385 .pa_start = 0x48074000,
2386 .pa_end = 0x480740ff,
2387 .flags = ADDR_TYPE_RT
2392 /* l4_core -> mcbsp1 */
2393 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2394 .master = &omap3xxx_l4_core_hwmod,
2395 .slave = &omap3xxx_mcbsp1_hwmod,
2396 .clk = "mcbsp1_ick",
2397 .addr = omap3xxx_mcbsp1_addrs,
2398 .user = OCP_USER_MPU | OCP_USER_SDMA,
2401 /* mcbsp1 slave ports */
2402 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2403 &omap3xxx_l4_core__mcbsp1,
2406 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2408 .class = &omap3xxx_mcbsp_hwmod_class,
2409 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2410 .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
2411 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2412 .main_clk = "mcbsp1_fck",
2416 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2417 .module_offs = CORE_MOD,
2419 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2422 .slaves = omap3xxx_mcbsp1_slaves,
2423 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2424 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2428 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2429 { .name = "irq", .irq = 17 },
2430 { .name = "tx", .irq = 62 },
2431 { .name = "rx", .irq = 63 },
2435 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2436 { .name = "rx", .dma_req = 34 },
2437 { .name = "tx", .dma_req = 33 },
2440 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2443 .pa_start = 0x49022000,
2444 .pa_end = 0x490220ff,
2445 .flags = ADDR_TYPE_RT
2450 /* l4_per -> mcbsp2 */
2451 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2452 .master = &omap3xxx_l4_per_hwmod,
2453 .slave = &omap3xxx_mcbsp2_hwmod,
2454 .clk = "mcbsp2_ick",
2455 .addr = omap3xxx_mcbsp2_addrs,
2457 .user = OCP_USER_MPU | OCP_USER_SDMA,
2460 /* mcbsp2 slave ports */
2461 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2462 &omap3xxx_l4_per__mcbsp2,
2465 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2466 .sidetone = "mcbsp2_sidetone",
2469 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2471 .class = &omap3xxx_mcbsp_hwmod_class,
2472 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2473 .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
2474 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2475 .main_clk = "mcbsp2_fck",
2479 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2480 .module_offs = OMAP3430_PER_MOD,
2482 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2485 .slaves = omap3xxx_mcbsp2_slaves,
2486 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2487 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2488 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2492 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2493 { .name = "irq", .irq = 22 },
2494 { .name = "tx", .irq = 89 },
2495 { .name = "rx", .irq = 90 },
2499 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2500 { .name = "rx", .dma_req = 18 },
2501 { .name = "tx", .dma_req = 17 },
2504 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2507 .pa_start = 0x49024000,
2508 .pa_end = 0x490240ff,
2509 .flags = ADDR_TYPE_RT
2514 /* l4_per -> mcbsp3 */
2515 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2516 .master = &omap3xxx_l4_per_hwmod,
2517 .slave = &omap3xxx_mcbsp3_hwmod,
2518 .clk = "mcbsp3_ick",
2519 .addr = omap3xxx_mcbsp3_addrs,
2520 .user = OCP_USER_MPU | OCP_USER_SDMA,
2523 /* mcbsp3 slave ports */
2524 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2525 &omap3xxx_l4_per__mcbsp3,
2528 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2529 .sidetone = "mcbsp3_sidetone",
2532 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2534 .class = &omap3xxx_mcbsp_hwmod_class,
2535 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2536 .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
2537 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2538 .main_clk = "mcbsp3_fck",
2542 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2543 .module_offs = OMAP3430_PER_MOD,
2545 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2548 .slaves = omap3xxx_mcbsp3_slaves,
2549 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2550 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2551 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2555 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2556 { .name = "irq", .irq = 23 },
2557 { .name = "tx", .irq = 54 },
2558 { .name = "rx", .irq = 55 },
2562 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2563 { .name = "rx", .dma_req = 20 },
2564 { .name = "tx", .dma_req = 19 },
2567 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2570 .pa_start = 0x49026000,
2571 .pa_end = 0x490260ff,
2572 .flags = ADDR_TYPE_RT
2577 /* l4_per -> mcbsp4 */
2578 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2579 .master = &omap3xxx_l4_per_hwmod,
2580 .slave = &omap3xxx_mcbsp4_hwmod,
2581 .clk = "mcbsp4_ick",
2582 .addr = omap3xxx_mcbsp4_addrs,
2583 .user = OCP_USER_MPU | OCP_USER_SDMA,
2586 /* mcbsp4 slave ports */
2587 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2588 &omap3xxx_l4_per__mcbsp4,
2591 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2593 .class = &omap3xxx_mcbsp_hwmod_class,
2594 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2595 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2596 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2597 .main_clk = "mcbsp4_fck",
2601 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2602 .module_offs = OMAP3430_PER_MOD,
2604 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2607 .slaves = omap3xxx_mcbsp4_slaves,
2608 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2609 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2613 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2614 { .name = "irq", .irq = 27 },
2615 { .name = "tx", .irq = 81 },
2616 { .name = "rx", .irq = 82 },
2620 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2621 { .name = "rx", .dma_req = 22 },
2622 { .name = "tx", .dma_req = 21 },
2625 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2628 .pa_start = 0x48096000,
2629 .pa_end = 0x480960ff,
2630 .flags = ADDR_TYPE_RT
2635 /* l4_core -> mcbsp5 */
2636 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2637 .master = &omap3xxx_l4_core_hwmod,
2638 .slave = &omap3xxx_mcbsp5_hwmod,
2639 .clk = "mcbsp5_ick",
2640 .addr = omap3xxx_mcbsp5_addrs,
2641 .user = OCP_USER_MPU | OCP_USER_SDMA,
2644 /* mcbsp5 slave ports */
2645 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2646 &omap3xxx_l4_core__mcbsp5,
2649 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2651 .class = &omap3xxx_mcbsp_hwmod_class,
2652 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2653 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2654 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2655 .main_clk = "mcbsp5_fck",
2659 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2660 .module_offs = CORE_MOD,
2662 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2665 .slaves = omap3xxx_mcbsp5_slaves,
2666 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2667 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2669 /* 'mcbsp sidetone' class */
2671 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2672 .sysc_offs = 0x0010,
2673 .sysc_flags = SYSC_HAS_AUTOIDLE,
2674 .sysc_fields = &omap_hwmod_sysc_type1,
2677 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2678 .name = "mcbsp_sidetone",
2679 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2682 /* mcbsp2_sidetone */
2683 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2684 { .name = "irq", .irq = 4 },
2688 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2691 .pa_start = 0x49028000,
2692 .pa_end = 0x490280ff,
2693 .flags = ADDR_TYPE_RT
2698 /* l4_per -> mcbsp2_sidetone */
2699 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2700 .master = &omap3xxx_l4_per_hwmod,
2701 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2702 .clk = "mcbsp2_ick",
2703 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2704 .user = OCP_USER_MPU,
2707 /* mcbsp2_sidetone slave ports */
2708 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2709 &omap3xxx_l4_per__mcbsp2_sidetone,
2712 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2713 .name = "mcbsp2_sidetone",
2714 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2715 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2716 .main_clk = "mcbsp2_fck",
2720 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2721 .module_offs = OMAP3430_PER_MOD,
2723 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2726 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2727 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2728 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2731 /* mcbsp3_sidetone */
2732 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2733 { .name = "irq", .irq = 5 },
2737 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2740 .pa_start = 0x4902A000,
2741 .pa_end = 0x4902A0ff,
2742 .flags = ADDR_TYPE_RT
2747 /* l4_per -> mcbsp3_sidetone */
2748 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2749 .master = &omap3xxx_l4_per_hwmod,
2750 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2751 .clk = "mcbsp3_ick",
2752 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2753 .user = OCP_USER_MPU,
2756 /* mcbsp3_sidetone slave ports */
2757 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2758 &omap3xxx_l4_per__mcbsp3_sidetone,
2761 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2762 .name = "mcbsp3_sidetone",
2763 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2764 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2765 .main_clk = "mcbsp3_fck",
2769 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2770 .module_offs = OMAP3430_PER_MOD,
2772 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2775 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2776 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2777 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2782 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2786 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2788 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2789 .clockact = CLOCKACT_TEST_ICLK,
2790 .sysc_fields = &omap34xx_sr_sysc_fields,
2793 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2794 .name = "smartreflex",
2795 .sysc = &omap34xx_sr_sysc,
2799 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2804 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2806 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2807 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2809 .sysc_fields = &omap36xx_sr_sysc_fields,
2812 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2813 .name = "smartreflex",
2814 .sysc = &omap36xx_sr_sysc,
2819 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2820 &omap3_l4_core__sr1,
2823 static struct omap_hwmod omap34xx_sr1_hwmod = {
2824 .name = "sr1_hwmod",
2825 .class = &omap34xx_smartreflex_hwmod_class,
2826 .main_clk = "sr1_fck",
2831 .module_bit = OMAP3430_EN_SR1_SHIFT,
2832 .module_offs = WKUP_MOD,
2834 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2837 .slaves = omap3_sr1_slaves,
2838 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2839 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2840 CHIP_IS_OMAP3430ES3_0 |
2841 CHIP_IS_OMAP3430ES3_1),
2842 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2845 static struct omap_hwmod omap36xx_sr1_hwmod = {
2846 .name = "sr1_hwmod",
2847 .class = &omap36xx_smartreflex_hwmod_class,
2848 .main_clk = "sr1_fck",
2853 .module_bit = OMAP3430_EN_SR1_SHIFT,
2854 .module_offs = WKUP_MOD,
2856 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2859 .slaves = omap3_sr1_slaves,
2860 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2861 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2865 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2866 &omap3_l4_core__sr2,
2869 static struct omap_hwmod omap34xx_sr2_hwmod = {
2870 .name = "sr2_hwmod",
2871 .class = &omap34xx_smartreflex_hwmod_class,
2872 .main_clk = "sr2_fck",
2877 .module_bit = OMAP3430_EN_SR2_SHIFT,
2878 .module_offs = WKUP_MOD,
2880 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2883 .slaves = omap3_sr2_slaves,
2884 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2885 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2886 CHIP_IS_OMAP3430ES3_0 |
2887 CHIP_IS_OMAP3430ES3_1),
2888 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2891 static struct omap_hwmod omap36xx_sr2_hwmod = {
2892 .name = "sr2_hwmod",
2893 .class = &omap36xx_smartreflex_hwmod_class,
2894 .main_clk = "sr2_fck",
2899 .module_bit = OMAP3430_EN_SR2_SHIFT,
2900 .module_offs = WKUP_MOD,
2902 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2905 .slaves = omap3_sr2_slaves,
2906 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2907 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2912 * mailbox module allowing communication between the on-chip processors
2913 * using a queued mailbox-interrupt mechanism.
2916 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2920 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2921 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2922 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2923 .sysc_fields = &omap_hwmod_sysc_type1,
2926 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2928 .sysc = &omap3xxx_mailbox_sysc,
2931 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2932 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2937 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2939 .pa_start = 0x48094000,
2940 .pa_end = 0x480941ff,
2941 .flags = ADDR_TYPE_RT,
2946 /* l4_core -> mailbox */
2947 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2948 .master = &omap3xxx_l4_core_hwmod,
2949 .slave = &omap3xxx_mailbox_hwmod,
2950 .addr = omap3xxx_mailbox_addrs,
2951 .user = OCP_USER_MPU | OCP_USER_SDMA,
2954 /* mailbox slave ports */
2955 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2956 &omap3xxx_l4_core__mailbox,
2959 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2961 .class = &omap3xxx_mailbox_hwmod_class,
2962 .mpu_irqs = omap3xxx_mailbox_irqs,
2963 .main_clk = "mailboxes_ick",
2967 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2968 .module_offs = CORE_MOD,
2970 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2973 .slaves = omap3xxx_mailbox_slaves,
2974 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2975 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2978 /* l4 core -> mcspi1 interface */
2979 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2980 .master = &omap3xxx_l4_core_hwmod,
2981 .slave = &omap34xx_mcspi1,
2982 .clk = "mcspi1_ick",
2983 .addr = omap2_mcspi1_addr_space,
2984 .user = OCP_USER_MPU | OCP_USER_SDMA,
2987 /* l4 core -> mcspi2 interface */
2988 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2989 .master = &omap3xxx_l4_core_hwmod,
2990 .slave = &omap34xx_mcspi2,
2991 .clk = "mcspi2_ick",
2992 .addr = omap2_mcspi2_addr_space,
2993 .user = OCP_USER_MPU | OCP_USER_SDMA,
2996 /* l4 core -> mcspi3 interface */
2997 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2998 .master = &omap3xxx_l4_core_hwmod,
2999 .slave = &omap34xx_mcspi3,
3000 .clk = "mcspi3_ick",
3001 .addr = omap2430_mcspi3_addr_space,
3002 .user = OCP_USER_MPU | OCP_USER_SDMA,
3005 /* l4 core -> mcspi4 interface */
3006 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3008 .pa_start = 0x480ba000,
3009 .pa_end = 0x480ba0ff,
3010 .flags = ADDR_TYPE_RT,
3015 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3016 .master = &omap3xxx_l4_core_hwmod,
3017 .slave = &omap34xx_mcspi4,
3018 .clk = "mcspi4_ick",
3019 .addr = omap34xx_mcspi4_addr_space,
3020 .user = OCP_USER_MPU | OCP_USER_SDMA,
3025 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3029 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
3031 .sysc_offs = 0x0010,
3032 .syss_offs = 0x0014,
3033 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3034 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3035 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3036 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3037 .sysc_fields = &omap_hwmod_sysc_type1,
3040 static struct omap_hwmod_class omap34xx_mcspi_class = {
3042 .sysc = &omap34xx_mcspi_sysc,
3043 .rev = OMAP3_MCSPI_REV,
3047 static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
3048 { .name = "irq", .irq = 65 },
3052 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
3053 { .name = "tx0", .dma_req = 35 },
3054 { .name = "rx0", .dma_req = 36 },
3055 { .name = "tx1", .dma_req = 37 },
3056 { .name = "rx1", .dma_req = 38 },
3057 { .name = "tx2", .dma_req = 39 },
3058 { .name = "rx2", .dma_req = 40 },
3059 { .name = "tx3", .dma_req = 41 },
3060 { .name = "rx3", .dma_req = 42 },
3063 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
3064 &omap34xx_l4_core__mcspi1,
3067 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
3068 .num_chipselect = 4,
3071 static struct omap_hwmod omap34xx_mcspi1 = {
3073 .mpu_irqs = omap34xx_mcspi1_mpu_irqs,
3074 .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
3075 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
3076 .main_clk = "mcspi1_fck",
3079 .module_offs = CORE_MOD,
3081 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
3083 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
3086 .slaves = omap34xx_mcspi1_slaves,
3087 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
3088 .class = &omap34xx_mcspi_class,
3089 .dev_attr = &omap_mcspi1_dev_attr,
3090 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3094 static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
3095 { .name = "irq", .irq = 66 },
3099 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
3100 { .name = "tx0", .dma_req = 43 },
3101 { .name = "rx0", .dma_req = 44 },
3102 { .name = "tx1", .dma_req = 45 },
3103 { .name = "rx1", .dma_req = 46 },
3106 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
3107 &omap34xx_l4_core__mcspi2,
3110 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
3111 .num_chipselect = 2,
3114 static struct omap_hwmod omap34xx_mcspi2 = {
3116 .mpu_irqs = omap34xx_mcspi2_mpu_irqs,
3117 .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
3118 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
3119 .main_clk = "mcspi2_fck",
3122 .module_offs = CORE_MOD,
3124 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
3126 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
3129 .slaves = omap34xx_mcspi2_slaves,
3130 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
3131 .class = &omap34xx_mcspi_class,
3132 .dev_attr = &omap_mcspi2_dev_attr,
3133 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3137 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
3138 { .name = "irq", .irq = 91 }, /* 91 */
3142 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
3143 { .name = "tx0", .dma_req = 15 },
3144 { .name = "rx0", .dma_req = 16 },
3145 { .name = "tx1", .dma_req = 23 },
3146 { .name = "rx1", .dma_req = 24 },
3149 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
3150 &omap34xx_l4_core__mcspi3,
3153 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
3154 .num_chipselect = 2,
3157 static struct omap_hwmod omap34xx_mcspi3 = {
3159 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
3160 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
3161 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
3162 .main_clk = "mcspi3_fck",
3165 .module_offs = CORE_MOD,
3167 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
3169 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
3172 .slaves = omap34xx_mcspi3_slaves,
3173 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3174 .class = &omap34xx_mcspi_class,
3175 .dev_attr = &omap_mcspi3_dev_attr,
3176 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3180 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3181 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3185 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3186 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3187 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3190 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3191 &omap34xx_l4_core__mcspi4,
3194 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3195 .num_chipselect = 1,
3198 static struct omap_hwmod omap34xx_mcspi4 = {
3200 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
3201 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
3202 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
3203 .main_clk = "mcspi4_fck",
3206 .module_offs = CORE_MOD,
3208 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3210 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3213 .slaves = omap34xx_mcspi4_slaves,
3214 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3215 .class = &omap34xx_mcspi_class,
3216 .dev_attr = &omap_mcspi4_dev_attr,
3217 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3223 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3225 .sysc_offs = 0x0404,
3226 .syss_offs = 0x0408,
3227 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3228 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3230 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3231 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3232 .sysc_fields = &omap_hwmod_sysc_type1,
3235 static struct omap_hwmod_class usbotg_class = {
3237 .sysc = &omap3xxx_usbhsotg_sysc,
3240 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3242 { .name = "mc", .irq = 92 },
3243 { .name = "dma", .irq = 93 },
3247 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3248 .name = "usb_otg_hs",
3249 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
3250 .main_clk = "hsotgusb_ick",
3254 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3255 .module_offs = CORE_MOD,
3257 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3258 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3261 .masters = omap3xxx_usbhsotg_masters,
3262 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3263 .slaves = omap3xxx_usbhsotg_slaves,
3264 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3265 .class = &usbotg_class,
3268 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
3269 * broken when autoidle is enabled
3270 * workaround is to disable the autoidle bit at module level.
3272 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3273 | HWMOD_SWSUP_MSTANDBY,
3274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3278 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3280 { .name = "mc", .irq = 71 },
3284 static struct omap_hwmod_class am35xx_usbotg_class = {
3285 .name = "am35xx_usbotg",
3289 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3290 .name = "am35x_otg_hs",
3291 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3297 .masters = am35xx_usbhsotg_masters,
3298 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3299 .slaves = am35xx_usbhsotg_slaves,
3300 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3301 .class = &am35xx_usbotg_class,
3302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3305 /* MMC/SD/SDIO common */
3307 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3311 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3312 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3313 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3314 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3315 .sysc_fields = &omap_hwmod_sysc_type1,
3318 static struct omap_hwmod_class omap34xx_mmc_class = {
3320 .sysc = &omap34xx_mmc_sysc,
3325 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3330 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3331 { .name = "tx", .dma_req = 61, },
3332 { .name = "rx", .dma_req = 62, },
3335 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3336 { .role = "dbck", .clk = "omap_32k_fck", },
3339 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3340 &omap3xxx_l4_core__mmc1,
3343 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3344 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3347 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3349 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3350 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3351 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3352 .opt_clks = omap34xx_mmc1_opt_clks,
3353 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3354 .main_clk = "mmchs1_fck",
3357 .module_offs = CORE_MOD,
3359 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3361 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3364 .dev_attr = &mmc1_dev_attr,
3365 .slaves = omap3xxx_mmc1_slaves,
3366 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3367 .class = &omap34xx_mmc_class,
3368 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3373 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3374 { .irq = INT_24XX_MMC2_IRQ, },
3378 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3379 { .name = "tx", .dma_req = 47, },
3380 { .name = "rx", .dma_req = 48, },
3383 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3384 { .role = "dbck", .clk = "omap_32k_fck", },
3387 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3388 &omap3xxx_l4_core__mmc2,
3391 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3393 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3394 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3395 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3396 .opt_clks = omap34xx_mmc2_opt_clks,
3397 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3398 .main_clk = "mmchs2_fck",
3401 .module_offs = CORE_MOD,
3403 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3405 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3408 .slaves = omap3xxx_mmc2_slaves,
3409 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3410 .class = &omap34xx_mmc_class,
3411 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3416 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3421 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3422 { .name = "tx", .dma_req = 77, },
3423 { .name = "rx", .dma_req = 78, },
3426 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3427 { .role = "dbck", .clk = "omap_32k_fck", },
3430 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3431 &omap3xxx_l4_core__mmc3,
3434 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3436 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3437 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3438 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3439 .opt_clks = omap34xx_mmc3_opt_clks,
3440 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3441 .main_clk = "mmchs3_fck",
3445 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3447 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3450 .slaves = omap3xxx_mmc3_slaves,
3451 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3452 .class = &omap34xx_mmc_class,
3453 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3456 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3457 &omap3xxx_l3_main_hwmod,
3458 &omap3xxx_l4_core_hwmod,
3459 &omap3xxx_l4_per_hwmod,
3460 &omap3xxx_l4_wkup_hwmod,
3461 &omap3xxx_mmc1_hwmod,
3462 &omap3xxx_mmc2_hwmod,
3463 &omap3xxx_mmc3_hwmod,
3464 &omap3xxx_mpu_hwmod,
3465 &omap3xxx_iva_hwmod,
3467 &omap3xxx_timer1_hwmod,
3468 &omap3xxx_timer2_hwmod,
3469 &omap3xxx_timer3_hwmod,
3470 &omap3xxx_timer4_hwmod,
3471 &omap3xxx_timer5_hwmod,
3472 &omap3xxx_timer6_hwmod,
3473 &omap3xxx_timer7_hwmod,
3474 &omap3xxx_timer8_hwmod,
3475 &omap3xxx_timer9_hwmod,
3476 &omap3xxx_timer10_hwmod,
3477 &omap3xxx_timer11_hwmod,
3478 &omap3xxx_timer12_hwmod,
3480 &omap3xxx_wd_timer2_hwmod,
3481 &omap3xxx_uart1_hwmod,
3482 &omap3xxx_uart2_hwmod,
3483 &omap3xxx_uart3_hwmod,
3484 &omap3xxx_uart4_hwmod,
3486 &omap3430es1_dss_core_hwmod,
3487 &omap3xxx_dss_core_hwmod,
3488 &omap3xxx_dss_dispc_hwmod,
3489 &omap3xxx_dss_dsi1_hwmod,
3490 &omap3xxx_dss_rfbi_hwmod,
3491 &omap3xxx_dss_venc_hwmod,
3494 &omap3xxx_i2c1_hwmod,
3495 &omap3xxx_i2c2_hwmod,
3496 &omap3xxx_i2c3_hwmod,
3497 &omap34xx_sr1_hwmod,
3498 &omap34xx_sr2_hwmod,
3499 &omap36xx_sr1_hwmod,
3500 &omap36xx_sr2_hwmod,
3504 &omap3xxx_gpio1_hwmod,
3505 &omap3xxx_gpio2_hwmod,
3506 &omap3xxx_gpio3_hwmod,
3507 &omap3xxx_gpio4_hwmod,
3508 &omap3xxx_gpio5_hwmod,
3509 &omap3xxx_gpio6_hwmod,
3511 /* dma_system class*/
3512 &omap3xxx_dma_system_hwmod,
3515 &omap3xxx_mcbsp1_hwmod,
3516 &omap3xxx_mcbsp2_hwmod,
3517 &omap3xxx_mcbsp3_hwmod,
3518 &omap3xxx_mcbsp4_hwmod,
3519 &omap3xxx_mcbsp5_hwmod,
3520 &omap3xxx_mcbsp2_sidetone_hwmod,
3521 &omap3xxx_mcbsp3_sidetone_hwmod,
3524 &omap3xxx_mailbox_hwmod,
3533 &omap3xxx_usbhsotg_hwmod,
3535 /* usbotg for am35x */
3536 &am35xx_usbhsotg_hwmod,
3541 int __init omap3xxx_hwmod_init(void)
3543 return omap_hwmod_register(omap3xxx_hwmods);