arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "smartreflex.h"
  33 #include "prm-regbits-34xx.h"
  34 #include "cm-regbits-34xx.h"
  35 #include "wd_timer.h"
  36 #include <mach/am35xx.h>
  37
  38 /*
  39  * OMAP3xxx hardware module integration data
  40  *
  41  * ALl of the data in this section should be autogeneratable from the
  42  * TI hardware database or other technical documentation.  Data that
  43  * is driver-specific or driver-kernel integration-specific belongs
  44  * elsewhere.
  45  */
  46
  47 static struct omap_hwmod omap3xxx_mpu_hwmod;
  48 static struct omap_hwmod omap3xxx_iva_hwmod;
  49 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  51 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  52 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  53 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  58 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  61 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  67 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  68 static struct omap_hwmod omap34xx_sr1_hwmod;
  69 static struct omap_hwmod omap36xx_sr1_hwmod;
  70 static struct omap_hwmod omap34xx_sr2_hwmod;
  71 static struct omap_hwmod omap36xx_sr2_hwmod;
  72 static struct omap_hwmod omap34xx_mcspi1;
  73 static struct omap_hwmod omap34xx_mcspi2;
  74 static struct omap_hwmod omap34xx_mcspi3;
  75 static struct omap_hwmod omap34xx_mcspi4;
  76 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  77 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  78 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  79 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  80
  81 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  82
  83 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  87 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  88 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  89 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  90
  91 /* L3 -> L4_CORE interface */
  92 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  93         .master = &omap3xxx_l3_main_hwmod,
  94         .slave  = &omap3xxx_l4_core_hwmod,
  95         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  96 };
  97
  98 /* L3 -> L4_PER interface */
  99 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
 100         .master = &omap3xxx_l3_main_hwmod,
 101         .slave  = &omap3xxx_l4_per_hwmod,
 102         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 103 };
 104
 105 /* L3 taret configuration and error log registers */
 106 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 107         { .irq = INT_34XX_L3_DBG_IRQ },
 108         { .irq = INT_34XX_L3_APP_IRQ },
 109         { .irq = -1 }
 110 };
 111
 112 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 113         {
 114                 .pa_start       = 0x68000000,
 115                 .pa_end         = 0x6800ffff,
 116                 .flags          = ADDR_TYPE_RT,
 117         },
 118         { }
 119 };
 120
 121 /* MPU -> L3 interface */
 122 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 123         .master   = &omap3xxx_mpu_hwmod,
 124         .slave    = &omap3xxx_l3_main_hwmod,
 125         .addr     = omap3xxx_l3_main_addrs,
 126         .user   = OCP_USER_MPU,
 127 };
 128
 129 /* Slave interfaces on the L3 interconnect */
 130 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 131         &omap3xxx_mpu__l3_main,
 132 };
 133
 134 /* DSS -> l3 */
 135 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 136         .master         = &omap3xxx_dss_core_hwmod,
 137         .slave          = &omap3xxx_l3_main_hwmod,
 138         .fw = {
 139                 .omap2 = {
 140                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 141                         .flags  = OMAP_FIREWALL_L3,
 142                 }
 143         },
 144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 145 };
 146
 147 /* Master interfaces on the L3 interconnect */
 148 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 149         &omap3xxx_l3_main__l4_core,
 150         &omap3xxx_l3_main__l4_per,
 151 };
 152
 153 /* L3 */
 154 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 155         .name           = "l3_main",
 156         .class          = &l3_hwmod_class,
 157         .mpu_irqs       = omap3xxx_l3_main_irqs,
 158         .masters        = omap3xxx_l3_main_masters,
 159         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 160         .slaves         = omap3xxx_l3_main_slaves,
 161         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 162         .flags          = HWMOD_NO_IDLEST,
 163 };
 164
 165 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 166 static struct omap_hwmod omap3xxx_uart1_hwmod;
 167 static struct omap_hwmod omap3xxx_uart2_hwmod;
 168 static struct omap_hwmod omap3xxx_uart3_hwmod;
 169 static struct omap_hwmod omap36xx_uart4_hwmod;
 170 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 171
 172 /* l3_core -> usbhsotg interface */
 173 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 174         .master         = &omap3xxx_usbhsotg_hwmod,
 175         .slave          = &omap3xxx_l3_main_hwmod,
 176         .clk            = "core_l3_ick",
 177         .user           = OCP_USER_MPU,
 178 };
 179
 180 /* l3_core -> am35xx_usbhsotg interface */
 181 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 182         .master         = &am35xx_usbhsotg_hwmod,
 183         .slave          = &omap3xxx_l3_main_hwmod,
 184         .clk            = "core_l3_ick",
 185         .user           = OCP_USER_MPU,
 186 };
 187 /* L4_CORE -> L4_WKUP interface */
 188 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 189         .master = &omap3xxx_l4_core_hwmod,
 190         .slave  = &omap3xxx_l4_wkup_hwmod,
 191         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 192 };
 193
 194 /* L4 CORE -> MMC1 interface */
 195 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 196         .master         = &omap3xxx_l4_core_hwmod,
 197         .slave          = &omap3xxx_mmc1_hwmod,
 198         .clk            = "mmchs1_ick",
 199         .addr           = omap2430_mmc1_addr_space,
 200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 201         .flags          = OMAP_FIREWALL_L4
 202 };
 203
 204 /* L4 CORE -> MMC2 interface */
 205 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 206         .master         = &omap3xxx_l4_core_hwmod,
 207         .slave          = &omap3xxx_mmc2_hwmod,
 208         .clk            = "mmchs2_ick",
 209         .addr           = omap2430_mmc2_addr_space,
 210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 211         .flags          = OMAP_FIREWALL_L4
 212 };
 213
 214 /* L4 CORE -> MMC3 interface */
 215 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 216         {
 217                 .pa_start       = 0x480ad000,
 218                 .pa_end         = 0x480ad1ff,
 219                 .flags          = ADDR_TYPE_RT,
 220         },
 221         { }
 222 };
 223
 224 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 225         .master         = &omap3xxx_l4_core_hwmod,
 226         .slave          = &omap3xxx_mmc3_hwmod,
 227         .clk            = "mmchs3_ick",
 228         .addr           = omap3xxx_mmc3_addr_space,
 229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 230         .flags          = OMAP_FIREWALL_L4
 231 };
 232
 233 /* L4 CORE -> UART1 interface */
 234 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 235         {
 236                 .pa_start       = OMAP3_UART1_BASE,
 237                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 238                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 239         },
 240         { }
 241 };
 242
 243 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 244         .master         = &omap3xxx_l4_core_hwmod,
 245         .slave          = &omap3xxx_uart1_hwmod,
 246         .clk            = "uart1_ick",
 247         .addr           = omap3xxx_uart1_addr_space,
 248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 249 };
 250
 251 /* L4 CORE -> UART2 interface */
 252 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 253         {
 254                 .pa_start       = OMAP3_UART2_BASE,
 255                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 256                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 257         },
 258         { }
 259 };
 260
 261 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 262         .master         = &omap3xxx_l4_core_hwmod,
 263         .slave          = &omap3xxx_uart2_hwmod,
 264         .clk            = "uart2_ick",
 265         .addr           = omap3xxx_uart2_addr_space,
 266         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 267 };
 268
 269 /* L4 PER -> UART3 interface */
 270 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 271         {
 272                 .pa_start       = OMAP3_UART3_BASE,
 273                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 274                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 275         },
 276         { }
 277 };
 278
 279 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 280         .master         = &omap3xxx_l4_per_hwmod,
 281         .slave          = &omap3xxx_uart3_hwmod,
 282         .clk            = "uart3_ick",
 283         .addr           = omap3xxx_uart3_addr_space,
 284         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 285 };
 286
 287 /* L4 PER -> UART4 interface */
 288 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
 289         {
 290                 .pa_start       = OMAP3_UART4_BASE,
 291                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 292                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 293         },
 294         { }
 295 };
 296
 297 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
 298         .master         = &omap3xxx_l4_per_hwmod,
 299         .slave          = &omap36xx_uart4_hwmod,
 300         .clk            = "uart4_ick",
 301         .addr           = omap36xx_uart4_addr_space,
 302         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 303 };
 304
 305 /* L4 CORE -> I2C1 interface */
 306 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 307         .master         = &omap3xxx_l4_core_hwmod,
 308         .slave          = &omap3xxx_i2c1_hwmod,
 309         .clk            = "i2c1_ick",
 310         .addr           = omap2_i2c1_addr_space,
 311         .fw = {
 312                 .omap2 = {
 313                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 314                         .l4_prot_group = 7,
 315                         .flags  = OMAP_FIREWALL_L4,
 316                 }
 317         },
 318         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 319 };
 320
 321 /* L4 CORE -> I2C2 interface */
 322 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 323         .master         = &omap3xxx_l4_core_hwmod,
 324         .slave          = &omap3xxx_i2c2_hwmod,
 325         .clk            = "i2c2_ick",
 326         .addr           = omap2_i2c2_addr_space,
 327         .fw = {
 328                 .omap2 = {
 329                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 330                         .l4_prot_group = 7,
 331                         .flags = OMAP_FIREWALL_L4,
 332                 }
 333         },
 334         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 335 };
 336
 337 /* L4 CORE -> I2C3 interface */
 338 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 339         {
 340                 .pa_start       = 0x48060000,
 341                 .pa_end         = 0x48060000 + SZ_128 - 1,
 342                 .flags          = ADDR_TYPE_RT,
 343         },
 344         { }
 345 };
 346
 347 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 348         .master         = &omap3xxx_l4_core_hwmod,
 349         .slave          = &omap3xxx_i2c3_hwmod,
 350         .clk            = "i2c3_ick",
 351         .addr           = omap3xxx_i2c3_addr_space,
 352         .fw = {
 353                 .omap2 = {
 354                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 355                         .l4_prot_group = 7,
 356                         .flags = OMAP_FIREWALL_L4,
 357                 }
 358         },
 359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 360 };
 361
 362 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
 363         { .irq = 18},
 364         { .irq = -1 }
 365 };
 366
 367 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
 368         { .irq = 19},
 369         { .irq = -1 }
 370 };
 371
 372 /* L4 CORE -> SR1 interface */
 373 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 374         {
 375                 .pa_start       = OMAP34XX_SR1_BASE,
 376                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 377                 .flags          = ADDR_TYPE_RT,
 378         },
 379         { }
 380 };
 381
 382 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
 383         .master         = &omap3xxx_l4_core_hwmod,
 384         .slave          = &omap34xx_sr1_hwmod,
 385         .clk            = "sr_l4_ick",
 386         .addr           = omap3_sr1_addr_space,
 387         .user           = OCP_USER_MPU,
 388 };
 389
 390 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
 391         .master         = &omap3xxx_l4_core_hwmod,
 392         .slave          = &omap36xx_sr1_hwmod,
 393         .clk            = "sr_l4_ick",
 394         .addr           = omap3_sr1_addr_space,
 395         .user           = OCP_USER_MPU,
 396 };
 397
 398 /* L4 CORE -> SR1 interface */
 399 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 400         {
 401                 .pa_start       = OMAP34XX_SR2_BASE,
 402                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 403                 .flags          = ADDR_TYPE_RT,
 404         },
 405         { }
 406 };
 407
 408 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
 409         .master         = &omap3xxx_l4_core_hwmod,
 410         .slave          = &omap34xx_sr2_hwmod,
 411         .clk            = "sr_l4_ick",
 412         .addr           = omap3_sr2_addr_space,
 413         .user           = OCP_USER_MPU,
 414 };
 415
 416 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
 417         .master         = &omap3xxx_l4_core_hwmod,
 418         .slave          = &omap36xx_sr2_hwmod,
 419         .clk            = "sr_l4_ick",
 420         .addr           = omap3_sr2_addr_space,
 421         .user           = OCP_USER_MPU,
 422 };
 423
 424 /*
 425 * usbhsotg interface data
 426 */
 427
 428 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 429         {
 430                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 431                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 432                 .flags          = ADDR_TYPE_RT
 433         },
 434         { }
 435 };
 436
 437 /* l4_core -> usbhsotg  */
 438 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 439         .master         = &omap3xxx_l4_core_hwmod,
 440         .slave          = &omap3xxx_usbhsotg_hwmod,
 441         .clk            = "l4_ick",
 442         .addr           = omap3xxx_usbhsotg_addrs,
 443         .user           = OCP_USER_MPU,
 444 };
 445
 446 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 447         &omap3xxx_usbhsotg__l3,
 448 };
 449
 450 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 451         &omap3xxx_l4_core__usbhsotg,
 452 };
 453
 454 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 455         {
 456                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 457                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 458                 .flags          = ADDR_TYPE_RT
 459         },
 460         { }
 461 };
 462
 463 /* l4_core -> usbhsotg  */
 464 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 465         .master         = &omap3xxx_l4_core_hwmod,
 466         .slave          = &am35xx_usbhsotg_hwmod,
 467         .clk            = "l4_ick",
 468         .addr           = am35xx_usbhsotg_addrs,
 469         .user           = OCP_USER_MPU,
 470 };
 471
 472 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 473         &am35xx_usbhsotg__l3,
 474 };
 475
 476 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 477         &am35xx_l4_core__usbhsotg,
 478 };
 479 /* Slave interfaces on the L4_CORE interconnect */
 480 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 481         &omap3xxx_l3_main__l4_core,
 482 };
 483
 484 /* L4 CORE */
 485 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 486         .name           = "l4_core",
 487         .class          = &l4_hwmod_class,
 488         .slaves         = omap3xxx_l4_core_slaves,
 489         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 490         .flags          = HWMOD_NO_IDLEST,
 491 };
 492
 493 /* Slave interfaces on the L4_PER interconnect */
 494 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 495         &omap3xxx_l3_main__l4_per,
 496 };
 497
 498 /* L4 PER */
 499 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 500         .name           = "l4_per",
 501         .class          = &l4_hwmod_class,
 502         .slaves         = omap3xxx_l4_per_slaves,
 503         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 504         .flags          = HWMOD_NO_IDLEST,
 505 };
 506
 507 /* Slave interfaces on the L4_WKUP interconnect */
 508 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 509         &omap3xxx_l4_core__l4_wkup,
 510 };
 511
 512 /* L4 WKUP */
 513 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 514         .name           = "l4_wkup",
 515         .class          = &l4_hwmod_class,
 516         .slaves         = omap3xxx_l4_wkup_slaves,
 517         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 518         .flags          = HWMOD_NO_IDLEST,
 519 };
 520
 521 /* Master interfaces on the MPU device */
 522 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 523         &omap3xxx_mpu__l3_main,
 524 };
 525
 526 /* MPU */
 527 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 528         .name           = "mpu",
 529         .class          = &mpu_hwmod_class,
 530         .main_clk       = "arm_fck",
 531         .masters        = omap3xxx_mpu_masters,
 532         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 533 };
 534
 535 /*
 536  * IVA2_2 interface data
 537  */
 538
 539 /* IVA2 <- L3 interface */
 540 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 541         .master         = &omap3xxx_l3_main_hwmod,
 542         .slave          = &omap3xxx_iva_hwmod,
 543         .clk            = "iva2_ck",
 544         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 545 };
 546
 547 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 548         &omap3xxx_l3__iva,
 549 };
 550
 551 /*
 552  * IVA2 (IVA2)
 553  */
 554
 555 static struct omap_hwmod omap3xxx_iva_hwmod = {
 556         .name           = "iva",
 557         .class          = &iva_hwmod_class,
 558         .masters        = omap3xxx_iva_masters,
 559         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 560 };
 561
 562 /* timer class */
 563 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 564         .rev_offs       = 0x0000,
 565         .sysc_offs      = 0x0010,
 566         .syss_offs      = 0x0014,
 567         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 568                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 569                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 570         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 571         .sysc_fields    = &omap_hwmod_sysc_type1,
 572 };
 573
 574 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 575         .name = "timer",
 576         .sysc = &omap3xxx_timer_1ms_sysc,
 577         .rev = OMAP_TIMER_IP_VERSION_1,
 578 };
 579
 580 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 581         .rev_offs       = 0x0000,
 582         .sysc_offs      = 0x0010,
 583         .syss_offs      = 0x0014,
 584         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 585                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 586         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 587         .sysc_fields    = &omap_hwmod_sysc_type1,
 588 };
 589
 590 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 591         .name = "timer",
 592         .sysc = &omap3xxx_timer_sysc,
 593         .rev =  OMAP_TIMER_IP_VERSION_1,
 594 };
 595
 596 /* secure timers dev attribute */
 597 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 598         .timer_capability       = OMAP_TIMER_SECURE,
 599 };
 600
 601 /* always-on timers dev attribute */
 602 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 603         .timer_capability       = OMAP_TIMER_ALWON,
 604 };
 605
 606 /* pwm timers dev attribute */
 607 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 608         .timer_capability       = OMAP_TIMER_HAS_PWM,
 609 };
 610
 611 /* timer1 */
 612 static struct omap_hwmod omap3xxx_timer1_hwmod;
 613
 614 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 615         {
 616                 .pa_start       = 0x48318000,
 617                 .pa_end         = 0x48318000 + SZ_1K - 1,
 618                 .flags          = ADDR_TYPE_RT
 619         },
 620         { }
 621 };
 622
 623 /* l4_wkup -> timer1 */
 624 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 625         .master         = &omap3xxx_l4_wkup_hwmod,
 626         .slave          = &omap3xxx_timer1_hwmod,
 627         .clk            = "gpt1_ick",
 628         .addr           = omap3xxx_timer1_addrs,
 629         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 630 };
 631
 632 /* timer1 slave port */
 633 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 634         &omap3xxx_l4_wkup__timer1,
 635 };
 636
 637 /* timer1 hwmod */
 638 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 639         .name           = "timer1",
 640         .mpu_irqs       = omap2_timer1_mpu_irqs,
 641         .main_clk       = "gpt1_fck",
 642         .prcm           = {
 643                 .omap2 = {
 644                         .prcm_reg_id = 1,
 645                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 646                         .module_offs = WKUP_MOD,
 647                         .idlest_reg_id = 1,
 648                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 649                 },
 650         },
 651         .dev_attr       = &capability_alwon_dev_attr,
 652         .slaves         = omap3xxx_timer1_slaves,
 653         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 654         .class          = &omap3xxx_timer_1ms_hwmod_class,
 655 };
 656
 657 /* timer2 */
 658 static struct omap_hwmod omap3xxx_timer2_hwmod;
 659
 660 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 661         {
 662                 .pa_start       = 0x49032000,
 663                 .pa_end         = 0x49032000 + SZ_1K - 1,
 664                 .flags          = ADDR_TYPE_RT
 665         },
 666         { }
 667 };
 668
 669 /* l4_per -> timer2 */
 670 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 671         .master         = &omap3xxx_l4_per_hwmod,
 672         .slave          = &omap3xxx_timer2_hwmod,
 673         .clk            = "gpt2_ick",
 674         .addr           = omap3xxx_timer2_addrs,
 675         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 676 };
 677
 678 /* timer2 slave port */
 679 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 680         &omap3xxx_l4_per__timer2,
 681 };
 682
 683 /* timer2 hwmod */
 684 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 685         .name           = "timer2",
 686         .mpu_irqs       = omap2_timer2_mpu_irqs,
 687         .main_clk       = "gpt2_fck",
 688         .prcm           = {
 689                 .omap2 = {
 690                         .prcm_reg_id = 1,
 691                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 692                         .module_offs = OMAP3430_PER_MOD,
 693                         .idlest_reg_id = 1,
 694                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 695                 },
 696         },
 697         .dev_attr       = &capability_alwon_dev_attr,
 698         .slaves         = omap3xxx_timer2_slaves,
 699         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 700         .class          = &omap3xxx_timer_1ms_hwmod_class,
 701 };
 702
 703 /* timer3 */
 704 static struct omap_hwmod omap3xxx_timer3_hwmod;
 705
 706 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 707         {
 708                 .pa_start       = 0x49034000,
 709                 .pa_end         = 0x49034000 + SZ_1K - 1,
 710                 .flags          = ADDR_TYPE_RT
 711         },
 712         { }
 713 };
 714
 715 /* l4_per -> timer3 */
 716 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 717         .master         = &omap3xxx_l4_per_hwmod,
 718         .slave          = &omap3xxx_timer3_hwmod,
 719         .clk            = "gpt3_ick",
 720         .addr           = omap3xxx_timer3_addrs,
 721         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 722 };
 723
 724 /* timer3 slave port */
 725 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 726         &omap3xxx_l4_per__timer3,
 727 };
 728
 729 /* timer3 hwmod */
 730 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 731         .name           = "timer3",
 732         .mpu_irqs       = omap2_timer3_mpu_irqs,
 733         .main_clk       = "gpt3_fck",
 734         .prcm           = {
 735                 .omap2 = {
 736                         .prcm_reg_id = 1,
 737                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 738                         .module_offs = OMAP3430_PER_MOD,
 739                         .idlest_reg_id = 1,
 740                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 741                 },
 742         },
 743         .dev_attr       = &capability_alwon_dev_attr,
 744         .slaves         = omap3xxx_timer3_slaves,
 745         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 746         .class          = &omap3xxx_timer_hwmod_class,
 747 };
 748
 749 /* timer4 */
 750 static struct omap_hwmod omap3xxx_timer4_hwmod;
 751
 752 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 753         {
 754                 .pa_start       = 0x49036000,
 755                 .pa_end         = 0x49036000 + SZ_1K - 1,
 756                 .flags          = ADDR_TYPE_RT
 757         },
 758         { }
 759 };
 760
 761 /* l4_per -> timer4 */
 762 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 763         .master         = &omap3xxx_l4_per_hwmod,
 764         .slave          = &omap3xxx_timer4_hwmod,
 765         .clk            = "gpt4_ick",
 766         .addr           = omap3xxx_timer4_addrs,
 767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 768 };
 769
 770 /* timer4 slave port */
 771 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 772         &omap3xxx_l4_per__timer4,
 773 };
 774
 775 /* timer4 hwmod */
 776 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 777         .name           = "timer4",
 778         .mpu_irqs       = omap2_timer4_mpu_irqs,
 779         .main_clk       = "gpt4_fck",
 780         .prcm           = {
 781                 .omap2 = {
 782                         .prcm_reg_id = 1,
 783                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 784                         .module_offs = OMAP3430_PER_MOD,
 785                         .idlest_reg_id = 1,
 786                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 787                 },
 788         },
 789         .dev_attr       = &capability_alwon_dev_attr,
 790         .slaves         = omap3xxx_timer4_slaves,
 791         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 792         .class          = &omap3xxx_timer_hwmod_class,
 793 };
 794
 795 /* timer5 */
 796 static struct omap_hwmod omap3xxx_timer5_hwmod;
 797
 798 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 799         {
 800                 .pa_start       = 0x49038000,
 801                 .pa_end         = 0x49038000 + SZ_1K - 1,
 802                 .flags          = ADDR_TYPE_RT
 803         },
 804         { }
 805 };
 806
 807 /* l4_per -> timer5 */
 808 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 809         .master         = &omap3xxx_l4_per_hwmod,
 810         .slave          = &omap3xxx_timer5_hwmod,
 811         .clk            = "gpt5_ick",
 812         .addr           = omap3xxx_timer5_addrs,
 813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 814 };
 815
 816 /* timer5 slave port */
 817 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 818         &omap3xxx_l4_per__timer5,
 819 };
 820
 821 /* timer5 hwmod */
 822 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 823         .name           = "timer5",
 824         .mpu_irqs       = omap2_timer5_mpu_irqs,
 825         .main_clk       = "gpt5_fck",
 826         .prcm           = {
 827                 .omap2 = {
 828                         .prcm_reg_id = 1,
 829                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 830                         .module_offs = OMAP3430_PER_MOD,
 831                         .idlest_reg_id = 1,
 832                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 833                 },
 834         },
 835         .dev_attr       = &capability_alwon_dev_attr,
 836         .slaves         = omap3xxx_timer5_slaves,
 837         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 838         .class          = &omap3xxx_timer_hwmod_class,
 839 };
 840
 841 /* timer6 */
 842 static struct omap_hwmod omap3xxx_timer6_hwmod;
 843
 844 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 845         {
 846                 .pa_start       = 0x4903A000,
 847                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 848                 .flags          = ADDR_TYPE_RT
 849         },
 850         { }
 851 };
 852
 853 /* l4_per -> timer6 */
 854 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 855         .master         = &omap3xxx_l4_per_hwmod,
 856         .slave          = &omap3xxx_timer6_hwmod,
 857         .clk            = "gpt6_ick",
 858         .addr           = omap3xxx_timer6_addrs,
 859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 860 };
 861
 862 /* timer6 slave port */
 863 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 864         &omap3xxx_l4_per__timer6,
 865 };
 866
 867 /* timer6 hwmod */
 868 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 869         .name           = "timer6",
 870         .mpu_irqs       = omap2_timer6_mpu_irqs,
 871         .main_clk       = "gpt6_fck",
 872         .prcm           = {
 873                 .omap2 = {
 874                         .prcm_reg_id = 1,
 875                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 876                         .module_offs = OMAP3430_PER_MOD,
 877                         .idlest_reg_id = 1,
 878                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 879                 },
 880         },
 881         .dev_attr       = &capability_alwon_dev_attr,
 882         .slaves         = omap3xxx_timer6_slaves,
 883         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 884         .class          = &omap3xxx_timer_hwmod_class,
 885 };
 886
 887 /* timer7 */
 888 static struct omap_hwmod omap3xxx_timer7_hwmod;
 889
 890 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 891         {
 892                 .pa_start       = 0x4903C000,
 893                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 894                 .flags          = ADDR_TYPE_RT
 895         },
 896         { }
 897 };
 898
 899 /* l4_per -> timer7 */
 900 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 901         .master         = &omap3xxx_l4_per_hwmod,
 902         .slave          = &omap3xxx_timer7_hwmod,
 903         .clk            = "gpt7_ick",
 904         .addr           = omap3xxx_timer7_addrs,
 905         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 906 };
 907
 908 /* timer7 slave port */
 909 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 910         &omap3xxx_l4_per__timer7,
 911 };
 912
 913 /* timer7 hwmod */
 914 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 915         .name           = "timer7",
 916         .mpu_irqs       = omap2_timer7_mpu_irqs,
 917         .main_clk       = "gpt7_fck",
 918         .prcm           = {
 919                 .omap2 = {
 920                         .prcm_reg_id = 1,
 921                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 922                         .module_offs = OMAP3430_PER_MOD,
 923                         .idlest_reg_id = 1,
 924                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 925                 },
 926         },
 927         .dev_attr       = &capability_alwon_dev_attr,
 928         .slaves         = omap3xxx_timer7_slaves,
 929         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 930         .class          = &omap3xxx_timer_hwmod_class,
 931 };
 932
 933 /* timer8 */
 934 static struct omap_hwmod omap3xxx_timer8_hwmod;
 935
 936 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 937         {
 938                 .pa_start       = 0x4903E000,
 939                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 940                 .flags          = ADDR_TYPE_RT
 941         },
 942         { }
 943 };
 944
 945 /* l4_per -> timer8 */
 946 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 947         .master         = &omap3xxx_l4_per_hwmod,
 948         .slave          = &omap3xxx_timer8_hwmod,
 949         .clk            = "gpt8_ick",
 950         .addr           = omap3xxx_timer8_addrs,
 951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 952 };
 953
 954 /* timer8 slave port */
 955 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 956         &omap3xxx_l4_per__timer8,
 957 };
 958
 959 /* timer8 hwmod */
 960 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 961         .name           = "timer8",
 962         .mpu_irqs       = omap2_timer8_mpu_irqs,
 963         .main_clk       = "gpt8_fck",
 964         .prcm           = {
 965                 .omap2 = {
 966                         .prcm_reg_id = 1,
 967                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 968                         .module_offs = OMAP3430_PER_MOD,
 969                         .idlest_reg_id = 1,
 970                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 971                 },
 972         },
 973         .dev_attr       = &capability_pwm_dev_attr,
 974         .slaves         = omap3xxx_timer8_slaves,
 975         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
 976         .class          = &omap3xxx_timer_hwmod_class,
 977 };
 978
 979 /* timer9 */
 980 static struct omap_hwmod omap3xxx_timer9_hwmod;
 981
 982 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
 983         {
 984                 .pa_start       = 0x49040000,
 985                 .pa_end         = 0x49040000 + SZ_1K - 1,
 986                 .flags          = ADDR_TYPE_RT
 987         },
 988         { }
 989 };
 990
 991 /* l4_per -> timer9 */
 992 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
 993         .master         = &omap3xxx_l4_per_hwmod,
 994         .slave          = &omap3xxx_timer9_hwmod,
 995         .clk            = "gpt9_ick",
 996         .addr           = omap3xxx_timer9_addrs,
 997         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 998 };
 999
1000 /* timer9 slave port */
1001 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1002         &omap3xxx_l4_per__timer9,
1003 };
1004
1005 /* timer9 hwmod */
1006 static struct omap_hwmod omap3xxx_timer9_hwmod = {
1007         .name           = "timer9",
1008         .mpu_irqs       = omap2_timer9_mpu_irqs,
1009         .main_clk       = "gpt9_fck",
1010         .prcm           = {
1011                 .omap2 = {
1012                         .prcm_reg_id = 1,
1013                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
1014                         .module_offs = OMAP3430_PER_MOD,
1015                         .idlest_reg_id = 1,
1016                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1017                 },
1018         },
1019         .dev_attr       = &capability_pwm_dev_attr,
1020         .slaves         = omap3xxx_timer9_slaves,
1021         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
1022         .class          = &omap3xxx_timer_hwmod_class,
1023 };
1024
1025 /* timer10 */
1026 static struct omap_hwmod omap3xxx_timer10_hwmod;
1027
1028 /* l4_core -> timer10 */
1029 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1030         .master         = &omap3xxx_l4_core_hwmod,
1031         .slave          = &omap3xxx_timer10_hwmod,
1032         .clk            = "gpt10_ick",
1033         .addr           = omap2_timer10_addrs,
1034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1035 };
1036
1037 /* timer10 slave port */
1038 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1039         &omap3xxx_l4_core__timer10,
1040 };
1041
1042 /* timer10 hwmod */
1043 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1044         .name           = "timer10",
1045         .mpu_irqs       = omap2_timer10_mpu_irqs,
1046         .main_clk       = "gpt10_fck",
1047         .prcm           = {
1048                 .omap2 = {
1049                         .prcm_reg_id = 1,
1050                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1051                         .module_offs = CORE_MOD,
1052                         .idlest_reg_id = 1,
1053                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1054                 },
1055         },
1056         .dev_attr       = &capability_pwm_dev_attr,
1057         .slaves         = omap3xxx_timer10_slaves,
1058         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1059         .class          = &omap3xxx_timer_1ms_hwmod_class,
1060 };
1061
1062 /* timer11 */
1063 static struct omap_hwmod omap3xxx_timer11_hwmod;
1064
1065 /* l4_core -> timer11 */
1066 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1067         .master         = &omap3xxx_l4_core_hwmod,
1068         .slave          = &omap3xxx_timer11_hwmod,
1069         .clk            = "gpt11_ick",
1070         .addr           = omap2_timer11_addrs,
1071         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1072 };
1073
1074 /* timer11 slave port */
1075 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1076         &omap3xxx_l4_core__timer11,
1077 };
1078
1079 /* timer11 hwmod */
1080 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1081         .name           = "timer11",
1082         .mpu_irqs       = omap2_timer11_mpu_irqs,
1083         .main_clk       = "gpt11_fck",
1084         .prcm           = {
1085                 .omap2 = {
1086                         .prcm_reg_id = 1,
1087                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1088                         .module_offs = CORE_MOD,
1089                         .idlest_reg_id = 1,
1090                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1091                 },
1092         },
1093         .dev_attr       = &capability_pwm_dev_attr,
1094         .slaves         = omap3xxx_timer11_slaves,
1095         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1096         .class          = &omap3xxx_timer_hwmod_class,
1097 };
1098
1099 /* timer12 */
1100 static struct omap_hwmod omap3xxx_timer12_hwmod;
1101 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1102         { .irq = 95, },
1103         { .irq = -1 }
1104 };
1105
1106 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1107         {
1108                 .pa_start       = 0x48304000,
1109                 .pa_end         = 0x48304000 + SZ_1K - 1,
1110                 .flags          = ADDR_TYPE_RT
1111         },
1112         { }
1113 };
1114
1115 /* l4_core -> timer12 */
1116 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1117         .master         = &omap3xxx_l4_core_hwmod,
1118         .slave          = &omap3xxx_timer12_hwmod,
1119         .clk            = "gpt12_ick",
1120         .addr           = omap3xxx_timer12_addrs,
1121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1122 };
1123
1124 /* timer12 slave port */
1125 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1126         &omap3xxx_l4_core__timer12,
1127 };
1128
1129 /* timer12 hwmod */
1130 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1131         .name           = "timer12",
1132         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1133         .main_clk       = "gpt12_fck",
1134         .prcm           = {
1135                 .omap2 = {
1136                         .prcm_reg_id = 1,
1137                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1138                         .module_offs = WKUP_MOD,
1139                         .idlest_reg_id = 1,
1140                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1141                 },
1142         },
1143         .dev_attr       = &capability_secure_dev_attr,
1144         .slaves         = omap3xxx_timer12_slaves,
1145         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1146         .class          = &omap3xxx_timer_hwmod_class,
1147 };
1148
1149 /* l4_wkup -> wd_timer2 */
1150 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1151         {
1152                 .pa_start       = 0x48314000,
1153                 .pa_end         = 0x4831407f,
1154                 .flags          = ADDR_TYPE_RT
1155         },
1156         { }
1157 };
1158
1159 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1160         .master         = &omap3xxx_l4_wkup_hwmod,
1161         .slave          = &omap3xxx_wd_timer2_hwmod,
1162         .clk            = "wdt2_ick",
1163         .addr           = omap3xxx_wd_timer2_addrs,
1164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1165 };
1166
1167 /*
1168  * 'wd_timer' class
1169  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1170  * overflow condition
1171  */
1172
1173 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1174         .rev_offs       = 0x0000,
1175         .sysc_offs      = 0x0010,
1176         .syss_offs      = 0x0014,
1177         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1178                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1179                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1180                            SYSS_HAS_RESET_STATUS),
1181         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1182         .sysc_fields    = &omap_hwmod_sysc_type1,
1183 };
1184
1185 /* I2C common */
1186 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1187         .rev_offs       = 0x00,
1188         .sysc_offs      = 0x20,
1189         .syss_offs      = 0x10,
1190         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1191                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1192                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1193         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1194         .sysc_fields    = &omap_hwmod_sysc_type1,
1195 };
1196
1197 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1198         .name           = "wd_timer",
1199         .sysc           = &omap3xxx_wd_timer_sysc,
1200         .pre_shutdown   = &omap2_wd_timer_disable
1201 };
1202
1203 /* wd_timer2 */
1204 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1205         &omap3xxx_l4_wkup__wd_timer2,
1206 };
1207
1208 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1209         .name           = "wd_timer2",
1210         .class          = &omap3xxx_wd_timer_hwmod_class,
1211         .main_clk       = "wdt2_fck",
1212         .prcm           = {
1213                 .omap2 = {
1214                         .prcm_reg_id = 1,
1215                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1216                         .module_offs = WKUP_MOD,
1217                         .idlest_reg_id = 1,
1218                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1219                 },
1220         },
1221         .slaves         = omap3xxx_wd_timer2_slaves,
1222         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1223         /*
1224          * XXX: Use software supervised mode, HW supervised smartidle seems to
1225          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1226          */
1227         .flags          = HWMOD_SWSUP_SIDLE,
1228 };
1229
1230 /* UART1 */
1231
1232 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1233         &omap3_l4_core__uart1,
1234 };
1235
1236 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1237         .name           = "uart1",
1238         .mpu_irqs       = omap2_uart1_mpu_irqs,
1239         .sdma_reqs      = omap2_uart1_sdma_reqs,
1240         .main_clk       = "uart1_fck",
1241         .prcm           = {
1242                 .omap2 = {
1243                         .module_offs = CORE_MOD,
1244                         .prcm_reg_id = 1,
1245                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1246                         .idlest_reg_id = 1,
1247                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1248                 },
1249         },
1250         .slaves         = omap3xxx_uart1_slaves,
1251         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1252         .class          = &omap2_uart_class,
1253 };
1254
1255 /* UART2 */
1256
1257 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1258         &omap3_l4_core__uart2,
1259 };
1260
1261 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1262         .name           = "uart2",
1263         .mpu_irqs       = omap2_uart2_mpu_irqs,
1264         .sdma_reqs      = omap2_uart2_sdma_reqs,
1265         .main_clk       = "uart2_fck",
1266         .prcm           = {
1267                 .omap2 = {
1268                         .module_offs = CORE_MOD,
1269                         .prcm_reg_id = 1,
1270                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1271                         .idlest_reg_id = 1,
1272                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1273                 },
1274         },
1275         .slaves         = omap3xxx_uart2_slaves,
1276         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1277         .class          = &omap2_uart_class,
1278 };
1279
1280 /* UART3 */
1281
1282 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1283         &omap3_l4_per__uart3,
1284 };
1285
1286 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1287         .name           = "uart3",
1288         .mpu_irqs       = omap2_uart3_mpu_irqs,
1289         .sdma_reqs      = omap2_uart3_sdma_reqs,
1290         .main_clk       = "uart3_fck",
1291         .prcm           = {
1292                 .omap2 = {
1293                         .module_offs = OMAP3430_PER_MOD,
1294                         .prcm_reg_id = 1,
1295                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1296                         .idlest_reg_id = 1,
1297                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1298                 },
1299         },
1300         .slaves         = omap3xxx_uart3_slaves,
1301         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1302         .class          = &omap2_uart_class,
1303 };
1304
1305 /* UART4 */
1306
1307 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1308         { .irq = INT_36XX_UART4_IRQ, },
1309         { .irq = -1 }
1310 };
1311
1312 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1313         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1314         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1315         { .dma_req = -1 }
1316 };
1317
1318 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1319         &omap36xx_l4_per__uart4,
1320 };
1321
1322 static struct omap_hwmod omap36xx_uart4_hwmod = {
1323         .name           = "uart4",
1324         .mpu_irqs       = uart4_mpu_irqs,
1325         .sdma_reqs      = uart4_sdma_reqs,
1326         .main_clk       = "uart4_fck",
1327         .flags          = HWMOD_SWSUP_SIDLE,
1328         .prcm           = {
1329                 .omap2 = {
1330                         .module_offs = OMAP3430_PER_MOD,
1331                         .prcm_reg_id = 1,
1332                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1333                         .idlest_reg_id = 1,
1334                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1335                 },
1336         },
1337         .slaves         = omap3xxx_uart4_slaves,
1338         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1339         .class          = &omap2_uart_class,
1340 };
1341
1342 static struct omap_hwmod_class i2c_class = {
1343         .name   = "i2c",
1344         .sysc   = &i2c_sysc,
1345         .rev    = OMAP_I2C_IP_VERSION_1,
1346         .reset  = &omap_i2c_reset,
1347 };
1348
1349 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1350         { .name = "dispc", .dma_req = 5 },
1351         { .name = "dsi1", .dma_req = 74 },
1352         { .dma_req = -1 }
1353 };
1354
1355 /* dss */
1356 /* dss master ports */
1357 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1358         &omap3xxx_dss__l3,
1359 };
1360
1361 /* l4_core -> dss */
1362 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1363         .master         = &omap3xxx_l4_core_hwmod,
1364         .slave          = &omap3430es1_dss_core_hwmod,
1365         .clk            = "dss_ick",
1366         .addr           = omap2_dss_addrs,
1367         .fw = {
1368                 .omap2 = {
1369                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1370                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1371                         .flags  = OMAP_FIREWALL_L4,
1372                 }
1373         },
1374         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1375 };
1376
1377 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1378         .master         = &omap3xxx_l4_core_hwmod,
1379         .slave          = &omap3xxx_dss_core_hwmod,
1380         .clk            = "dss_ick",
1381         .addr           = omap2_dss_addrs,
1382         .fw = {
1383                 .omap2 = {
1384                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1385                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1386                         .flags  = OMAP_FIREWALL_L4,
1387                 }
1388         },
1389         .flags          = OCPIF_SWSUP_IDLE,
1390         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1391 };
1392
1393 /* dss slave ports */
1394 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1395         &omap3430es1_l4_core__dss,
1396 };
1397
1398 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1399         &omap3xxx_l4_core__dss,
1400 };
1401
1402 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1403         /*
1404          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1405          * driver does not use these clocks.
1406          */
1407         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1408         { .role = "tv_clk", .clk = "dss_tv_fck" },
1409         /* required only on OMAP3430 */
1410         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1411 };
1412
1413 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1414         .name           = "dss_core",
1415         .class          = &omap2_dss_hwmod_class,
1416         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1417         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1418         .prcm           = {
1419                 .omap2 = {
1420                         .prcm_reg_id = 1,
1421                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1422                         .module_offs = OMAP3430_DSS_MOD,
1423                         .idlest_reg_id = 1,
1424                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1425                 },
1426         },
1427         .opt_clks       = dss_opt_clks,
1428         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1429         .slaves         = omap3430es1_dss_slaves,
1430         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1431         .masters        = omap3xxx_dss_masters,
1432         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1433         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1434 };
1435
1436 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1437         .name           = "dss_core",
1438         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1439         .class          = &omap2_dss_hwmod_class,
1440         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1441         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1442         .prcm           = {
1443                 .omap2 = {
1444                         .prcm_reg_id = 1,
1445                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1446                         .module_offs = OMAP3430_DSS_MOD,
1447                         .idlest_reg_id = 1,
1448                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1449                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1450                 },
1451         },
1452         .opt_clks       = dss_opt_clks,
1453         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1454         .slaves         = omap3xxx_dss_slaves,
1455         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1456         .masters        = omap3xxx_dss_masters,
1457         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1458 };
1459
1460 /*
1461  * 'dispc' class
1462  * display controller
1463  */
1464
1465 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
1466         .rev_offs       = 0x0000,
1467         .sysc_offs      = 0x0010,
1468         .syss_offs      = 0x0014,
1469         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1470                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1471                            SYSC_HAS_ENAWAKEUP),
1472         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1473                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1474         .sysc_fields    = &omap_hwmod_sysc_type1,
1475 };
1476
1477 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1478         .name   = "dispc",
1479         .sysc   = &omap3_dispc_sysc,
1480 };
1481
1482 /* l4_core -> dss_dispc */
1483 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1484         .master         = &omap3xxx_l4_core_hwmod,
1485         .slave          = &omap3xxx_dss_dispc_hwmod,
1486         .clk            = "dss_ick",
1487         .addr           = omap2_dss_dispc_addrs,
1488         .fw = {
1489                 .omap2 = {
1490                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1491                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1492                         .flags  = OMAP_FIREWALL_L4,
1493                 }
1494         },
1495         .flags          = OCPIF_SWSUP_IDLE,
1496         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1497 };
1498
1499 /* dss_dispc slave ports */
1500 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1501         &omap3xxx_l4_core__dss_dispc,
1502 };
1503
1504 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1505         .name           = "dss_dispc",
1506         .class          = &omap3_dispc_hwmod_class,
1507         .mpu_irqs       = omap2_dispc_irqs,
1508         .main_clk       = "dss1_alwon_fck",
1509         .prcm           = {
1510                 .omap2 = {
1511                         .prcm_reg_id = 1,
1512                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1513                         .module_offs = OMAP3430_DSS_MOD,
1514                 },
1515         },
1516         .slaves         = omap3xxx_dss_dispc_slaves,
1517         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1518         .flags          = HWMOD_NO_IDLEST,
1519         .dev_attr       = &omap2_3_dss_dispc_dev_attr
1520 };
1521
1522 /*
1523  * 'dsi' class
1524  * display serial interface controller
1525  */
1526
1527 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
1528         .rev_offs       = 0x0000,
1529         .sysc_offs      = 0x0010,
1530         .syss_offs      = 0x0014,
1531         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1532                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1533                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1534         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1535         .sysc_fields    = &omap_hwmod_sysc_type1,
1536 };
1537
1538 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1539         .name = "dsi",
1540         .sysc   = &omap3xxx_dsi_sysc,
1541 };
1542
1543 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1544         { .irq = 25 },
1545         { .irq = -1 }
1546 };
1547
1548 /* dss_dsi1 */
1549 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1550         {
1551                 .pa_start       = 0x4804FC00,
1552                 .pa_end         = 0x4804FFFF,
1553                 .flags          = ADDR_TYPE_RT
1554         },
1555         { }
1556 };
1557
1558 /* l4_core -> dss_dsi1 */
1559 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1560         .master         = &omap3xxx_l4_core_hwmod,
1561         .slave          = &omap3xxx_dss_dsi1_hwmod,
1562         .clk            = "dss_ick",
1563         .addr           = omap3xxx_dss_dsi1_addrs,
1564         .fw = {
1565                 .omap2 = {
1566                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1567                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1568                         .flags  = OMAP_FIREWALL_L4,
1569                 }
1570         },
1571         .flags          = OCPIF_SWSUP_IDLE,
1572         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1573 };
1574
1575 /* dss_dsi1 slave ports */
1576 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1577         &omap3xxx_l4_core__dss_dsi1,
1578 };
1579
1580 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1581         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1582 };
1583
1584 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1585         .name           = "dss_dsi1",
1586         .class          = &omap3xxx_dsi_hwmod_class,
1587         .mpu_irqs       = omap3xxx_dsi1_irqs,
1588         .main_clk       = "dss1_alwon_fck",
1589         .prcm           = {
1590                 .omap2 = {
1591                         .prcm_reg_id = 1,
1592                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1593                         .module_offs = OMAP3430_DSS_MOD,
1594                 },
1595         },
1596         .opt_clks       = dss_dsi1_opt_clks,
1597         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1598         .slaves         = omap3xxx_dss_dsi1_slaves,
1599         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1600         .flags          = HWMOD_NO_IDLEST,
1601 };
1602
1603 /* l4_core -> dss_rfbi */
1604 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1605         .master         = &omap3xxx_l4_core_hwmod,
1606         .slave          = &omap3xxx_dss_rfbi_hwmod,
1607         .clk            = "dss_ick",
1608         .addr           = omap2_dss_rfbi_addrs,
1609         .fw = {
1610                 .omap2 = {
1611                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1612                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1613                         .flags  = OMAP_FIREWALL_L4,
1614                 }
1615         },
1616         .flags          = OCPIF_SWSUP_IDLE,
1617         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1618 };
1619
1620 /* dss_rfbi slave ports */
1621 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1622         &omap3xxx_l4_core__dss_rfbi,
1623 };
1624
1625 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1626         { .role = "ick", .clk = "dss_ick" },
1627 };
1628
1629 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1630         .name           = "dss_rfbi",
1631         .class          = &omap2_rfbi_hwmod_class,
1632         .main_clk       = "dss1_alwon_fck",
1633         .prcm           = {
1634                 .omap2 = {
1635                         .prcm_reg_id = 1,
1636                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1637                         .module_offs = OMAP3430_DSS_MOD,
1638                 },
1639         },
1640         .opt_clks       = dss_rfbi_opt_clks,
1641         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1642         .slaves         = omap3xxx_dss_rfbi_slaves,
1643         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1644         .flags          = HWMOD_NO_IDLEST,
1645 };
1646
1647 /* l4_core -> dss_venc */
1648 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1649         .master         = &omap3xxx_l4_core_hwmod,
1650         .slave          = &omap3xxx_dss_venc_hwmod,
1651         .clk            = "dss_ick",
1652         .addr           = omap2_dss_venc_addrs,
1653         .fw = {
1654                 .omap2 = {
1655                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1656                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1657                         .flags  = OMAP_FIREWALL_L4,
1658                 }
1659         },
1660         .flags          = OCPIF_SWSUP_IDLE,
1661         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1662 };
1663
1664 /* dss_venc slave ports */
1665 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1666         &omap3xxx_l4_core__dss_venc,
1667 };
1668
1669 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1670         /* required only on OMAP3430 */
1671         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1672 };
1673
1674 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1675         .name           = "dss_venc",
1676         .class          = &omap2_venc_hwmod_class,
1677         .main_clk       = "dss_tv_fck",
1678         .prcm           = {
1679                 .omap2 = {
1680                         .prcm_reg_id = 1,
1681                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1682                         .module_offs = OMAP3430_DSS_MOD,
1683                 },
1684         },
1685         .opt_clks       = dss_venc_opt_clks,
1686         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
1687         .slaves         = omap3xxx_dss_venc_slaves,
1688         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1689         .flags          = HWMOD_NO_IDLEST,
1690 };
1691
1692 /* I2C1 */
1693
1694 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1695         .fifo_depth     = 8, /* bytes */
1696         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1697                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1698                           OMAP_I2C_FLAG_BUS_SHIFT_2,
1699 };
1700
1701 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1702         &omap3_l4_core__i2c1,
1703 };
1704
1705 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1706         .name           = "i2c1",
1707         .flags          = HWMOD_16BIT_REG,
1708         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1709         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1710         .main_clk       = "i2c1_fck",
1711         .prcm           = {
1712                 .omap2 = {
1713                         .module_offs = CORE_MOD,
1714                         .prcm_reg_id = 1,
1715                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1716                         .idlest_reg_id = 1,
1717                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1718                 },
1719         },
1720         .slaves         = omap3xxx_i2c1_slaves,
1721         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1722         .class          = &i2c_class,
1723         .dev_attr       = &i2c1_dev_attr,
1724 };
1725
1726 /* I2C2 */
1727
1728 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1729         .fifo_depth     = 8, /* bytes */
1730         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1731                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1732                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1733 };
1734
1735 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1736         &omap3_l4_core__i2c2,
1737 };
1738
1739 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1740         .name           = "i2c2",
1741         .flags          = HWMOD_16BIT_REG,
1742         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1743         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1744         .main_clk       = "i2c2_fck",
1745         .prcm           = {
1746                 .omap2 = {
1747                         .module_offs = CORE_MOD,
1748                         .prcm_reg_id = 1,
1749                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1750                         .idlest_reg_id = 1,
1751                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1752                 },
1753         },
1754         .slaves         = omap3xxx_i2c2_slaves,
1755         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1756         .class          = &i2c_class,
1757         .dev_attr       = &i2c2_dev_attr,
1758 };
1759
1760 /* I2C3 */
1761
1762 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1763         .fifo_depth     = 64, /* bytes */
1764         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1765                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1766                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1767 };
1768
1769 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1770         { .irq = INT_34XX_I2C3_IRQ, },
1771         { .irq = -1 }
1772 };
1773
1774 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1775         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1776         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1777         { .dma_req = -1 }
1778 };
1779
1780 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1781         &omap3_l4_core__i2c3,
1782 };
1783
1784 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1785         .name           = "i2c3",
1786         .flags          = HWMOD_16BIT_REG,
1787         .mpu_irqs       = i2c3_mpu_irqs,
1788         .sdma_reqs      = i2c3_sdma_reqs,
1789         .main_clk       = "i2c3_fck",
1790         .prcm           = {
1791                 .omap2 = {
1792                         .module_offs = CORE_MOD,
1793                         .prcm_reg_id = 1,
1794                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1795                         .idlest_reg_id = 1,
1796                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1797                 },
1798         },
1799         .slaves         = omap3xxx_i2c3_slaves,
1800         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1801         .class          = &i2c_class,
1802         .dev_attr       = &i2c3_dev_attr,
1803 };
1804
1805 /* l4_wkup -> gpio1 */
1806 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1807         {
1808                 .pa_start       = 0x48310000,
1809                 .pa_end         = 0x483101ff,
1810                 .flags          = ADDR_TYPE_RT
1811         },
1812         { }
1813 };
1814
1815 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1816         .master         = &omap3xxx_l4_wkup_hwmod,
1817         .slave          = &omap3xxx_gpio1_hwmod,
1818         .addr           = omap3xxx_gpio1_addrs,
1819         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1820 };
1821
1822 /* l4_per -> gpio2 */
1823 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1824         {
1825                 .pa_start       = 0x49050000,
1826                 .pa_end         = 0x490501ff,
1827                 .flags          = ADDR_TYPE_RT
1828         },
1829         { }
1830 };
1831
1832 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1833         .master         = &omap3xxx_l4_per_hwmod,
1834         .slave          = &omap3xxx_gpio2_hwmod,
1835         .addr           = omap3xxx_gpio2_addrs,
1836         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1837 };
1838
1839 /* l4_per -> gpio3 */
1840 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1841         {
1842                 .pa_start       = 0x49052000,
1843                 .pa_end         = 0x490521ff,
1844                 .flags          = ADDR_TYPE_RT
1845         },
1846         { }
1847 };
1848
1849 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1850         .master         = &omap3xxx_l4_per_hwmod,
1851         .slave          = &omap3xxx_gpio3_hwmod,
1852         .addr           = omap3xxx_gpio3_addrs,
1853         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1854 };
1855
1856 /* l4_per -> gpio4 */
1857 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1858         {
1859                 .pa_start       = 0x49054000,
1860                 .pa_end         = 0x490541ff,
1861                 .flags          = ADDR_TYPE_RT
1862         },
1863         { }
1864 };
1865
1866 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1867         .master         = &omap3xxx_l4_per_hwmod,
1868         .slave          = &omap3xxx_gpio4_hwmod,
1869         .addr           = omap3xxx_gpio4_addrs,
1870         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1871 };
1872
1873 /* l4_per -> gpio5 */
1874 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1875         {
1876                 .pa_start       = 0x49056000,
1877                 .pa_end         = 0x490561ff,
1878                 .flags          = ADDR_TYPE_RT
1879         },
1880         { }
1881 };
1882
1883 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1884         .master         = &omap3xxx_l4_per_hwmod,
1885         .slave          = &omap3xxx_gpio5_hwmod,
1886         .addr           = omap3xxx_gpio5_addrs,
1887         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1888 };
1889
1890 /* l4_per -> gpio6 */
1891 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1892         {
1893                 .pa_start       = 0x49058000,
1894                 .pa_end         = 0x490581ff,
1895                 .flags          = ADDR_TYPE_RT
1896         },
1897         { }
1898 };
1899
1900 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1901         .master         = &omap3xxx_l4_per_hwmod,
1902         .slave          = &omap3xxx_gpio6_hwmod,
1903         .addr           = omap3xxx_gpio6_addrs,
1904         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1905 };
1906
1907 /*
1908  * 'gpio' class
1909  * general purpose io module
1910  */
1911
1912 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1913         .rev_offs       = 0x0000,
1914         .sysc_offs      = 0x0010,
1915         .syss_offs      = 0x0014,
1916         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1917                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1918                            SYSS_HAS_RESET_STATUS),
1919         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1920         .sysc_fields    = &omap_hwmod_sysc_type1,
1921 };
1922
1923 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1924         .name = "gpio",
1925         .sysc = &omap3xxx_gpio_sysc,
1926         .rev = 1,
1927 };
1928
1929 /* gpio_dev_attr*/
1930 static struct omap_gpio_dev_attr gpio_dev_attr = {
1931         .bank_width = 32,
1932         .dbck_flag = true,
1933 };
1934
1935 /* gpio1 */
1936 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1937         { .role = "dbclk", .clk = "gpio1_dbck", },
1938 };
1939
1940 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1941         &omap3xxx_l4_wkup__gpio1,
1942 };
1943
1944 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1945         .name           = "gpio1",
1946         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1947         .mpu_irqs       = omap2_gpio1_irqs,
1948         .main_clk       = "gpio1_ick",
1949         .opt_clks       = gpio1_opt_clks,
1950         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1951         .prcm           = {
1952                 .omap2 = {
1953                         .prcm_reg_id = 1,
1954                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1955                         .module_offs = WKUP_MOD,
1956                         .idlest_reg_id = 1,
1957                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1958                 },
1959         },
1960         .slaves         = omap3xxx_gpio1_slaves,
1961         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1962         .class          = &omap3xxx_gpio_hwmod_class,
1963         .dev_attr       = &gpio_dev_attr,
1964 };
1965
1966 /* gpio2 */
1967 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1968         { .role = "dbclk", .clk = "gpio2_dbck", },
1969 };
1970
1971 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1972         &omap3xxx_l4_per__gpio2,
1973 };
1974
1975 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1976         .name           = "gpio2",
1977         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1978         .mpu_irqs       = omap2_gpio2_irqs,
1979         .main_clk       = "gpio2_ick",
1980         .opt_clks       = gpio2_opt_clks,
1981         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1982         .prcm           = {
1983                 .omap2 = {
1984                         .prcm_reg_id = 1,
1985                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1986                         .module_offs = OMAP3430_PER_MOD,
1987                         .idlest_reg_id = 1,
1988                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1989                 },
1990         },
1991         .slaves         = omap3xxx_gpio2_slaves,
1992         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1993         .class          = &omap3xxx_gpio_hwmod_class,
1994         .dev_attr       = &gpio_dev_attr,
1995 };
1996
1997 /* gpio3 */
1998 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1999         { .role = "dbclk", .clk = "gpio3_dbck", },
2000 };
2001
2002 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2003         &omap3xxx_l4_per__gpio3,
2004 };
2005
2006 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2007         .name           = "gpio3",
2008         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2009         .mpu_irqs       = omap2_gpio3_irqs,
2010         .main_clk       = "gpio3_ick",
2011         .opt_clks       = gpio3_opt_clks,
2012         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
2013         .prcm           = {
2014                 .omap2 = {
2015                         .prcm_reg_id = 1,
2016                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2017                         .module_offs = OMAP3430_PER_MOD,
2018                         .idlest_reg_id = 1,
2019                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2020                 },
2021         },
2022         .slaves         = omap3xxx_gpio3_slaves,
2023         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2024         .class          = &omap3xxx_gpio_hwmod_class,
2025         .dev_attr       = &gpio_dev_attr,
2026 };
2027
2028 /* gpio4 */
2029 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2030         { .role = "dbclk", .clk = "gpio4_dbck", },
2031 };
2032
2033 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2034         &omap3xxx_l4_per__gpio4,
2035 };
2036
2037 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2038         .name           = "gpio4",
2039         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2040         .mpu_irqs       = omap2_gpio4_irqs,
2041         .main_clk       = "gpio4_ick",
2042         .opt_clks       = gpio4_opt_clks,
2043         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2044         .prcm           = {
2045                 .omap2 = {
2046                         .prcm_reg_id = 1,
2047                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2048                         .module_offs = OMAP3430_PER_MOD,
2049                         .idlest_reg_id = 1,
2050                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2051                 },
2052         },
2053         .slaves         = omap3xxx_gpio4_slaves,
2054         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2055         .class          = &omap3xxx_gpio_hwmod_class,
2056         .dev_attr       = &gpio_dev_attr,
2057 };
2058
2059 /* gpio5 */
2060 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2061         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2062         { .irq = -1 }
2063 };
2064
2065 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2066         { .role = "dbclk", .clk = "gpio5_dbck", },
2067 };
2068
2069 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2070         &omap3xxx_l4_per__gpio5,
2071 };
2072
2073 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2074         .name           = "gpio5",
2075         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2076         .mpu_irqs       = omap3xxx_gpio5_irqs,
2077         .main_clk       = "gpio5_ick",
2078         .opt_clks       = gpio5_opt_clks,
2079         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2080         .prcm           = {
2081                 .omap2 = {
2082                         .prcm_reg_id = 1,
2083                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2084                         .module_offs = OMAP3430_PER_MOD,
2085                         .idlest_reg_id = 1,
2086                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2087                 },
2088         },
2089         .slaves         = omap3xxx_gpio5_slaves,
2090         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2091         .class          = &omap3xxx_gpio_hwmod_class,
2092         .dev_attr       = &gpio_dev_attr,
2093 };
2094
2095 /* gpio6 */
2096 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2097         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2098         { .irq = -1 }
2099 };
2100
2101 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2102         { .role = "dbclk", .clk = "gpio6_dbck", },
2103 };
2104
2105 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2106         &omap3xxx_l4_per__gpio6,
2107 };
2108
2109 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2110         .name           = "gpio6",
2111         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2112         .mpu_irqs       = omap3xxx_gpio6_irqs,
2113         .main_clk       = "gpio6_ick",
2114         .opt_clks       = gpio6_opt_clks,
2115         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2116         .prcm           = {
2117                 .omap2 = {
2118                         .prcm_reg_id = 1,
2119                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2120                         .module_offs = OMAP3430_PER_MOD,
2121                         .idlest_reg_id = 1,
2122                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2123                 },
2124         },
2125         .slaves         = omap3xxx_gpio6_slaves,
2126         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2127         .class          = &omap3xxx_gpio_hwmod_class,
2128         .dev_attr       = &gpio_dev_attr,
2129 };
2130
2131 /* dma_system -> L3 */
2132 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2133         .master         = &omap3xxx_dma_system_hwmod,
2134         .slave          = &omap3xxx_l3_main_hwmod,
2135         .clk            = "core_l3_ick",
2136         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2137 };
2138
2139 /* dma attributes */
2140 static struct omap_dma_dev_attr dma_dev_attr = {
2141         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2142                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2143         .lch_count = 32,
2144 };
2145
2146 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2147         .rev_offs       = 0x0000,
2148         .sysc_offs      = 0x002c,
2149         .syss_offs      = 0x0028,
2150         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2151                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2152                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2153                            SYSS_HAS_RESET_STATUS),
2154         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2155                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2156         .sysc_fields    = &omap_hwmod_sysc_type1,
2157 };
2158
2159 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2160         .name = "dma",
2161         .sysc = &omap3xxx_dma_sysc,
2162 };
2163
2164 /* dma_system */
2165 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2166         {
2167                 .pa_start       = 0x48056000,
2168                 .pa_end         = 0x48056fff,
2169                 .flags          = ADDR_TYPE_RT
2170         },
2171         { }
2172 };
2173
2174 /* dma_system master ports */
2175 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2176         &omap3xxx_dma_system__l3,
2177 };
2178
2179 /* l4_cfg -> dma_system */
2180 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2181         .master         = &omap3xxx_l4_core_hwmod,
2182         .slave          = &omap3xxx_dma_system_hwmod,
2183         .clk            = "core_l4_ick",
2184         .addr           = omap3xxx_dma_system_addrs,
2185         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2186 };
2187
2188 /* dma_system slave ports */
2189 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2190         &omap3xxx_l4_core__dma_system,
2191 };
2192
2193 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2194         .name           = "dma",
2195         .class          = &omap3xxx_dma_hwmod_class,
2196         .mpu_irqs       = omap2_dma_system_irqs,
2197         .main_clk       = "core_l3_ick",
2198         .prcm = {
2199                 .omap2 = {
2200                         .module_offs            = CORE_MOD,
2201                         .prcm_reg_id            = 1,
2202                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2203                         .idlest_reg_id          = 1,
2204                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2205                 },
2206         },
2207         .slaves         = omap3xxx_dma_system_slaves,
2208         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2209         .masters        = omap3xxx_dma_system_masters,
2210         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2211         .dev_attr       = &dma_dev_attr,
2212         .flags          = HWMOD_NO_IDLEST,
2213 };
2214
2215 /*
2216  * 'mcbsp' class
2217  * multi channel buffered serial port controller
2218  */
2219
2220 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2221         .sysc_offs      = 0x008c,
2222         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2223                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2224         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2225         .sysc_fields    = &omap_hwmod_sysc_type1,
2226         .clockact       = 0x2,
2227 };
2228
2229 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2230         .name = "mcbsp",
2231         .sysc = &omap3xxx_mcbsp_sysc,
2232         .rev  = MCBSP_CONFIG_TYPE3,
2233 };
2234
2235 /* mcbsp1 */
2236 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2237         { .name = "irq", .irq = 16 },
2238         { .name = "tx", .irq = 59 },
2239         { .name = "rx", .irq = 60 },
2240         { .irq = -1 }
2241 };
2242
2243 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2244         {
2245                 .name           = "mpu",
2246                 .pa_start       = 0x48074000,
2247                 .pa_end         = 0x480740ff,
2248                 .flags          = ADDR_TYPE_RT
2249         },
2250         { }
2251 };
2252
2253 /* l4_core -> mcbsp1 */
2254 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2255         .master         = &omap3xxx_l4_core_hwmod,
2256         .slave          = &omap3xxx_mcbsp1_hwmod,
2257         .clk            = "mcbsp1_ick",
2258         .addr           = omap3xxx_mcbsp1_addrs,
2259         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2260 };
2261
2262 /* mcbsp1 slave ports */
2263 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2264         &omap3xxx_l4_core__mcbsp1,
2265 };
2266
2267 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2268         .name           = "mcbsp1",
2269         .class          = &omap3xxx_mcbsp_hwmod_class,
2270         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2271         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
2272         .main_clk       = "mcbsp1_fck",
2273         .prcm           = {
2274                 .omap2 = {
2275                         .prcm_reg_id = 1,
2276                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2277                         .module_offs = CORE_MOD,
2278                         .idlest_reg_id = 1,
2279                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2280                 },
2281         },
2282         .slaves         = omap3xxx_mcbsp1_slaves,
2283         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2284 };
2285
2286 /* mcbsp2 */
2287 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2288         { .name = "irq", .irq = 17 },
2289         { .name = "tx", .irq = 62 },
2290         { .name = "rx", .irq = 63 },
2291         { .irq = -1 }
2292 };
2293
2294 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2295         {
2296                 .name           = "mpu",
2297                 .pa_start       = 0x49022000,
2298                 .pa_end         = 0x490220ff,
2299                 .flags          = ADDR_TYPE_RT
2300         },
2301         { }
2302 };
2303
2304 /* l4_per -> mcbsp2 */
2305 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2306         .master         = &omap3xxx_l4_per_hwmod,
2307         .slave          = &omap3xxx_mcbsp2_hwmod,
2308         .clk            = "mcbsp2_ick",
2309         .addr           = omap3xxx_mcbsp2_addrs,
2310         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2311 };
2312
2313 /* mcbsp2 slave ports */
2314 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2315         &omap3xxx_l4_per__mcbsp2,
2316 };
2317
2318 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2319         .sidetone       = "mcbsp2_sidetone",
2320 };
2321
2322 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2323         .name           = "mcbsp2",
2324         .class          = &omap3xxx_mcbsp_hwmod_class,
2325         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2326         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
2327         .main_clk       = "mcbsp2_fck",
2328         .prcm           = {
2329                 .omap2 = {
2330                         .prcm_reg_id = 1,
2331                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2332                         .module_offs = OMAP3430_PER_MOD,
2333                         .idlest_reg_id = 1,
2334                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2335                 },
2336         },
2337         .slaves         = omap3xxx_mcbsp2_slaves,
2338         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2339         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2340 };
2341
2342 /* mcbsp3 */
2343 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2344         { .name = "irq", .irq = 22 },
2345         { .name = "tx", .irq = 89 },
2346         { .name = "rx", .irq = 90 },
2347         { .irq = -1 }
2348 };
2349
2350 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2351         {
2352                 .name           = "mpu",
2353                 .pa_start       = 0x49024000,
2354                 .pa_end         = 0x490240ff,
2355                 .flags          = ADDR_TYPE_RT
2356         },
2357         { }
2358 };
2359
2360 /* l4_per -> mcbsp3 */
2361 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2362         .master         = &omap3xxx_l4_per_hwmod,
2363         .slave          = &omap3xxx_mcbsp3_hwmod,
2364         .clk            = "mcbsp3_ick",
2365         .addr           = omap3xxx_mcbsp3_addrs,
2366         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2367 };
2368
2369 /* mcbsp3 slave ports */
2370 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2371         &omap3xxx_l4_per__mcbsp3,
2372 };
2373
2374 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2375         .sidetone       = "mcbsp3_sidetone",
2376 };
2377
2378 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2379         .name           = "mcbsp3",
2380         .class          = &omap3xxx_mcbsp_hwmod_class,
2381         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2382         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
2383         .main_clk       = "mcbsp3_fck",
2384         .prcm           = {
2385                 .omap2 = {
2386                         .prcm_reg_id = 1,
2387                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2388                         .module_offs = OMAP3430_PER_MOD,
2389                         .idlest_reg_id = 1,
2390                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2391                 },
2392         },
2393         .slaves         = omap3xxx_mcbsp3_slaves,
2394         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2395         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2396 };
2397
2398 /* mcbsp4 */
2399 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2400         { .name = "irq", .irq = 23 },
2401         { .name = "tx", .irq = 54 },
2402         { .name = "rx", .irq = 55 },
2403         { .irq = -1 }
2404 };
2405
2406 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2407         { .name = "rx", .dma_req = 20 },
2408         { .name = "tx", .dma_req = 19 },
2409         { .dma_req = -1 }
2410 };
2411
2412 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2413         {
2414                 .name           = "mpu",
2415                 .pa_start       = 0x49026000,
2416                 .pa_end         = 0x490260ff,
2417                 .flags          = ADDR_TYPE_RT
2418         },
2419         { }
2420 };
2421
2422 /* l4_per -> mcbsp4 */
2423 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2424         .master         = &omap3xxx_l4_per_hwmod,
2425         .slave          = &omap3xxx_mcbsp4_hwmod,
2426         .clk            = "mcbsp4_ick",
2427         .addr           = omap3xxx_mcbsp4_addrs,
2428         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2429 };
2430
2431 /* mcbsp4 slave ports */
2432 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2433         &omap3xxx_l4_per__mcbsp4,
2434 };
2435
2436 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2437         .name           = "mcbsp4",
2438         .class          = &omap3xxx_mcbsp_hwmod_class,
2439         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2440         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2441         .main_clk       = "mcbsp4_fck",
2442         .prcm           = {
2443                 .omap2 = {
2444                         .prcm_reg_id = 1,
2445                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2446                         .module_offs = OMAP3430_PER_MOD,
2447                         .idlest_reg_id = 1,
2448                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2449                 },
2450         },
2451         .slaves         = omap3xxx_mcbsp4_slaves,
2452         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2453 };
2454
2455 /* mcbsp5 */
2456 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2457         { .name = "irq", .irq = 27 },
2458         { .name = "tx", .irq = 81 },
2459         { .name = "rx", .irq = 82 },
2460         { .irq = -1 }
2461 };
2462
2463 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2464         { .name = "rx", .dma_req = 22 },
2465         { .name = "tx", .dma_req = 21 },
2466         { .dma_req = -1 }
2467 };
2468
2469 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2470         {
2471                 .name           = "mpu",
2472                 .pa_start       = 0x48096000,
2473                 .pa_end         = 0x480960ff,
2474                 .flags          = ADDR_TYPE_RT
2475         },
2476         { }
2477 };
2478
2479 /* l4_core -> mcbsp5 */
2480 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2481         .master         = &omap3xxx_l4_core_hwmod,
2482         .slave          = &omap3xxx_mcbsp5_hwmod,
2483         .clk            = "mcbsp5_ick",
2484         .addr           = omap3xxx_mcbsp5_addrs,
2485         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2486 };
2487
2488 /* mcbsp5 slave ports */
2489 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2490         &omap3xxx_l4_core__mcbsp5,
2491 };
2492
2493 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2494         .name           = "mcbsp5",
2495         .class          = &omap3xxx_mcbsp_hwmod_class,
2496         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2497         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2498         .main_clk       = "mcbsp5_fck",
2499         .prcm           = {
2500                 .omap2 = {
2501                         .prcm_reg_id = 1,
2502                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2503                         .module_offs = CORE_MOD,
2504                         .idlest_reg_id = 1,
2505                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2506                 },
2507         },
2508         .slaves         = omap3xxx_mcbsp5_slaves,
2509         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2510 };
2511 /* 'mcbsp sidetone' class */
2512
2513 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2514         .sysc_offs      = 0x0010,
2515         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2516         .sysc_fields    = &omap_hwmod_sysc_type1,
2517 };
2518
2519 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2520         .name = "mcbsp_sidetone",
2521         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2522 };
2523
2524 /* mcbsp2_sidetone */
2525 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2526         { .name = "irq", .irq = 4 },
2527         { .irq = -1 }
2528 };
2529
2530 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2531         {
2532                 .name           = "sidetone",
2533                 .pa_start       = 0x49028000,
2534                 .pa_end         = 0x490280ff,
2535                 .flags          = ADDR_TYPE_RT
2536         },
2537         { }
2538 };
2539
2540 /* l4_per -> mcbsp2_sidetone */
2541 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2542         .master         = &omap3xxx_l4_per_hwmod,
2543         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2544         .clk            = "mcbsp2_ick",
2545         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2546         .user           = OCP_USER_MPU,
2547 };
2548
2549 /* mcbsp2_sidetone slave ports */
2550 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2551         &omap3xxx_l4_per__mcbsp2_sidetone,
2552 };
2553
2554 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2555         .name           = "mcbsp2_sidetone",
2556         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2557         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2558         .main_clk       = "mcbsp2_fck",
2559         .prcm           = {
2560                 .omap2 = {
2561                         .prcm_reg_id = 1,
2562                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2563                         .module_offs = OMAP3430_PER_MOD,
2564                         .idlest_reg_id = 1,
2565                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2566                 },
2567         },
2568         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2569         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2570 };
2571
2572 /* mcbsp3_sidetone */
2573 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2574         { .name = "irq", .irq = 5 },
2575         { .irq = -1 }
2576 };
2577
2578 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2579         {
2580                 .name           = "sidetone",
2581                 .pa_start       = 0x4902A000,
2582                 .pa_end         = 0x4902A0ff,
2583                 .flags          = ADDR_TYPE_RT
2584         },
2585         { }
2586 };
2587
2588 /* l4_per -> mcbsp3_sidetone */
2589 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2590         .master         = &omap3xxx_l4_per_hwmod,
2591         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2592         .clk            = "mcbsp3_ick",
2593         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2594         .user           = OCP_USER_MPU,
2595 };
2596
2597 /* mcbsp3_sidetone slave ports */
2598 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2599         &omap3xxx_l4_per__mcbsp3_sidetone,
2600 };
2601
2602 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2603         .name           = "mcbsp3_sidetone",
2604         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2605         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2606         .main_clk       = "mcbsp3_fck",
2607         .prcm           = {
2608                 .omap2 = {
2609                         .prcm_reg_id = 1,
2610                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2611                         .module_offs = OMAP3430_PER_MOD,
2612                         .idlest_reg_id = 1,
2613                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2614                 },
2615         },
2616         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2617         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2618 };
2619
2620
2621 /* SR common */
2622 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2623         .clkact_shift   = 20,
2624 };
2625
2626 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2627         .sysc_offs      = 0x24,
2628         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2629         .clockact       = CLOCKACT_TEST_ICLK,
2630         .sysc_fields    = &omap34xx_sr_sysc_fields,
2631 };
2632
2633 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2634         .name = "smartreflex",
2635         .sysc = &omap34xx_sr_sysc,
2636         .rev  = 1,
2637 };
2638
2639 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2640         .sidle_shift    = 24,
2641         .enwkup_shift   = 26
2642 };
2643
2644 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2645         .sysc_offs      = 0x38,
2646         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2647         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2648                         SYSC_NO_CACHE),
2649         .sysc_fields    = &omap36xx_sr_sysc_fields,
2650 };
2651
2652 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2653         .name = "smartreflex",
2654         .sysc = &omap36xx_sr_sysc,
2655         .rev  = 2,
2656 };
2657
2658 /* SR1 */
2659 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
2660         .sensor_voltdm_name   = "mpu_iva",
2661 };
2662
2663 static struct omap_hwmod_ocp_if *omap34xx_sr1_slaves[] = {
2664         &omap34xx_l4_core__sr1,
2665 };
2666
2667 static struct omap_hwmod omap34xx_sr1_hwmod = {
2668         .name           = "sr1",
2669         .class          = &omap34xx_smartreflex_hwmod_class,
2670         .main_clk       = "sr1_fck",
2671         .prcm           = {
2672                 .omap2 = {
2673                         .prcm_reg_id = 1,
2674                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2675                         .module_offs = WKUP_MOD,
2676                         .idlest_reg_id = 1,
2677                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2678                 },
2679         },
2680         .slaves         = omap34xx_sr1_slaves,
2681         .slaves_cnt     = ARRAY_SIZE(omap34xx_sr1_slaves),
2682         .dev_attr       = &sr1_dev_attr,
2683         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
2684         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2685 };
2686
2687 static struct omap_hwmod_ocp_if *omap36xx_sr1_slaves[] = {
2688         &omap36xx_l4_core__sr1,
2689 };
2690
2691 static struct omap_hwmod omap36xx_sr1_hwmod = {
2692         .name           = "sr1",
2693         .class          = &omap36xx_smartreflex_hwmod_class,
2694         .main_clk       = "sr1_fck",
2695         .prcm           = {
2696                 .omap2 = {
2697                         .prcm_reg_id = 1,
2698                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2699                         .module_offs = WKUP_MOD,
2700                         .idlest_reg_id = 1,
2701                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2702                 },
2703         },
2704         .slaves         = omap36xx_sr1_slaves,
2705         .slaves_cnt     = ARRAY_SIZE(omap36xx_sr1_slaves),
2706         .dev_attr       = &sr1_dev_attr,
2707         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
2708 };
2709
2710 /* SR2 */
2711 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
2712         .sensor_voltdm_name     = "core",
2713 };
2714
2715 static struct omap_hwmod_ocp_if *omap34xx_sr2_slaves[] = {
2716         &omap34xx_l4_core__sr2,
2717 };
2718
2719 static struct omap_hwmod omap34xx_sr2_hwmod = {
2720         .name           = "sr2",
2721         .class          = &omap34xx_smartreflex_hwmod_class,
2722         .main_clk       = "sr2_fck",
2723         .prcm           = {
2724                 .omap2 = {
2725                         .prcm_reg_id = 1,
2726                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2727                         .module_offs = WKUP_MOD,
2728                         .idlest_reg_id = 1,
2729                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2730                 },
2731         },
2732         .slaves         = omap34xx_sr2_slaves,
2733         .slaves_cnt     = ARRAY_SIZE(omap34xx_sr2_slaves),
2734         .dev_attr       = &sr2_dev_attr,
2735         .mpu_irqs       = omap3_smartreflex_core_irqs,
2736         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2737 };
2738
2739 static struct omap_hwmod_ocp_if *omap36xx_sr2_slaves[] = {
2740         &omap36xx_l4_core__sr2,
2741 };
2742
2743 static struct omap_hwmod omap36xx_sr2_hwmod = {
2744         .name           = "sr2",
2745         .class          = &omap36xx_smartreflex_hwmod_class,
2746         .main_clk       = "sr2_fck",
2747         .prcm           = {
2748                 .omap2 = {
2749                         .prcm_reg_id = 1,
2750                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2751                         .module_offs = WKUP_MOD,
2752                         .idlest_reg_id = 1,
2753                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2754                 },
2755         },
2756         .slaves         = omap36xx_sr2_slaves,
2757         .slaves_cnt     = ARRAY_SIZE(omap36xx_sr2_slaves),
2758         .dev_attr       = &sr2_dev_attr,
2759         .mpu_irqs       = omap3_smartreflex_core_irqs,
2760 };
2761
2762 /*
2763  * 'mailbox' class
2764  * mailbox module allowing communication between the on-chip processors
2765  * using a queued mailbox-interrupt mechanism.
2766  */
2767
2768 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2769         .rev_offs       = 0x000,
2770         .sysc_offs      = 0x010,
2771         .syss_offs      = 0x014,
2772         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2773                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2774         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2775         .sysc_fields    = &omap_hwmod_sysc_type1,
2776 };
2777
2778 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2779         .name = "mailbox",
2780         .sysc = &omap3xxx_mailbox_sysc,
2781 };
2782
2783 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2784 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2785         { .irq = 26 },
2786         { .irq = -1 }
2787 };
2788
2789 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2790         {
2791                 .pa_start       = 0x48094000,
2792                 .pa_end         = 0x480941ff,
2793                 .flags          = ADDR_TYPE_RT,
2794         },
2795         { }
2796 };
2797
2798 /* l4_core -> mailbox */
2799 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2800         .master         = &omap3xxx_l4_core_hwmod,
2801         .slave          = &omap3xxx_mailbox_hwmod,
2802         .addr           = omap3xxx_mailbox_addrs,
2803         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2804 };
2805
2806 /* mailbox slave ports */
2807 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2808         &omap3xxx_l4_core__mailbox,
2809 };
2810
2811 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2812         .name           = "mailbox",
2813         .class          = &omap3xxx_mailbox_hwmod_class,
2814         .mpu_irqs       = omap3xxx_mailbox_irqs,
2815         .main_clk       = "mailboxes_ick",
2816         .prcm           = {
2817                 .omap2 = {
2818                         .prcm_reg_id = 1,
2819                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2820                         .module_offs = CORE_MOD,
2821                         .idlest_reg_id = 1,
2822                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2823                 },
2824         },
2825         .slaves         = omap3xxx_mailbox_slaves,
2826         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2827 };
2828
2829 /* l4 core -> mcspi1 interface */
2830 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2831         .master         = &omap3xxx_l4_core_hwmod,
2832         .slave          = &omap34xx_mcspi1,
2833         .clk            = "mcspi1_ick",
2834         .addr           = omap2_mcspi1_addr_space,
2835         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2836 };
2837
2838 /* l4 core -> mcspi2 interface */
2839 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2840         .master         = &omap3xxx_l4_core_hwmod,
2841         .slave          = &omap34xx_mcspi2,
2842         .clk            = "mcspi2_ick",
2843         .addr           = omap2_mcspi2_addr_space,
2844         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2845 };
2846
2847 /* l4 core -> mcspi3 interface */
2848 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2849         .master         = &omap3xxx_l4_core_hwmod,
2850         .slave          = &omap34xx_mcspi3,
2851         .clk            = "mcspi3_ick",
2852         .addr           = omap2430_mcspi3_addr_space,
2853         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2854 };
2855
2856 /* l4 core -> mcspi4 interface */
2857 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2858         {
2859                 .pa_start       = 0x480ba000,
2860                 .pa_end         = 0x480ba0ff,
2861                 .flags          = ADDR_TYPE_RT,
2862         },
2863         { }
2864 };
2865
2866 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2867         .master         = &omap3xxx_l4_core_hwmod,
2868         .slave          = &omap34xx_mcspi4,
2869         .clk            = "mcspi4_ick",
2870         .addr           = omap34xx_mcspi4_addr_space,
2871         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2872 };
2873
2874 /*
2875  * 'mcspi' class
2876  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2877  * bus
2878  */
2879
2880 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2881         .rev_offs       = 0x0000,
2882         .sysc_offs      = 0x0010,
2883         .syss_offs      = 0x0014,
2884         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2885                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2886                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2887         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2888         .sysc_fields    = &omap_hwmod_sysc_type1,
2889 };
2890
2891 static struct omap_hwmod_class omap34xx_mcspi_class = {
2892         .name = "mcspi",
2893         .sysc = &omap34xx_mcspi_sysc,
2894         .rev = OMAP3_MCSPI_REV,
2895 };
2896
2897 /* mcspi1 */
2898 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2899         &omap34xx_l4_core__mcspi1,
2900 };
2901
2902 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2903         .num_chipselect = 4,
2904 };
2905
2906 static struct omap_hwmod omap34xx_mcspi1 = {
2907         .name           = "mcspi1",
2908         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
2909         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
2910         .main_clk       = "mcspi1_fck",
2911         .prcm           = {
2912                 .omap2 = {
2913                         .module_offs = CORE_MOD,
2914                         .prcm_reg_id = 1,
2915                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2916                         .idlest_reg_id = 1,
2917                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2918                 },
2919         },
2920         .slaves         = omap34xx_mcspi1_slaves,
2921         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2922         .class          = &omap34xx_mcspi_class,
2923         .dev_attr       = &omap_mcspi1_dev_attr,
2924 };
2925
2926 /* mcspi2 */
2927 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2928         &omap34xx_l4_core__mcspi2,
2929 };
2930
2931 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2932         .num_chipselect = 2,
2933 };
2934
2935 static struct omap_hwmod omap34xx_mcspi2 = {
2936         .name           = "mcspi2",
2937         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
2938         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
2939         .main_clk       = "mcspi2_fck",
2940         .prcm           = {
2941                 .omap2 = {
2942                         .module_offs = CORE_MOD,
2943                         .prcm_reg_id = 1,
2944                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2945                         .idlest_reg_id = 1,
2946                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2947                 },
2948         },
2949         .slaves         = omap34xx_mcspi2_slaves,
2950         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2951         .class          = &omap34xx_mcspi_class,
2952         .dev_attr       = &omap_mcspi2_dev_attr,
2953 };
2954
2955 /* mcspi3 */
2956 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2957         { .name = "irq", .irq = 91 }, /* 91 */
2958         { .irq = -1 }
2959 };
2960
2961 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2962         { .name = "tx0", .dma_req = 15 },
2963         { .name = "rx0", .dma_req = 16 },
2964         { .name = "tx1", .dma_req = 23 },
2965         { .name = "rx1", .dma_req = 24 },
2966         { .dma_req = -1 }
2967 };
2968
2969 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2970         &omap34xx_l4_core__mcspi3,
2971 };
2972
2973 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2974         .num_chipselect = 2,
2975 };
2976
2977 static struct omap_hwmod omap34xx_mcspi3 = {
2978         .name           = "mcspi3",
2979         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
2980         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
2981         .main_clk       = "mcspi3_fck",
2982         .prcm           = {
2983                 .omap2 = {
2984                         .module_offs = CORE_MOD,
2985                         .prcm_reg_id = 1,
2986                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2987                         .idlest_reg_id = 1,
2988                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2989                 },
2990         },
2991         .slaves         = omap34xx_mcspi3_slaves,
2992         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2993         .class          = &omap34xx_mcspi_class,
2994         .dev_attr       = &omap_mcspi3_dev_attr,
2995 };
2996
2997 /* SPI4 */
2998 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2999         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3000         { .irq = -1 }
3001 };
3002
3003 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3004         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3005         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3006         { .dma_req = -1 }
3007 };
3008
3009 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3010         &omap34xx_l4_core__mcspi4,
3011 };
3012
3013 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3014         .num_chipselect = 1,
3015 };
3016
3017 static struct omap_hwmod omap34xx_mcspi4 = {
3018         .name           = "mcspi4",
3019         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
3020         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
3021         .main_clk       = "mcspi4_fck",
3022         .prcm           = {
3023                 .omap2 = {
3024                         .module_offs = CORE_MOD,
3025                         .prcm_reg_id = 1,
3026                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3027                         .idlest_reg_id = 1,
3028                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3029                 },
3030         },
3031         .slaves         = omap34xx_mcspi4_slaves,
3032         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3033         .class          = &omap34xx_mcspi_class,
3034         .dev_attr       = &omap_mcspi4_dev_attr,
3035 };
3036
3037 /* temp. sensor */
3038 struct omap_hwmod_class omap34xx_bandgap_ts_class = {
3039         .name   = "bandgap_ts",
3040 };
3041
3042 static struct omap_hwmod_addr_space omap3xxx_bandgap_ts_addrs[] = {
3043         {
3044                 .name           = "mpu",
3045                 .pa_start       = 0x48002524,
3046                 .pa_end         = 0x48002524 + 4,
3047                 .flags          = ADDR_TYPE_RT
3048         },
3049         { }
3050 };
3051
3052 static struct omap_hwmod omap34xx_bandgap_ts;
3053
3054 /* l4_core -> bandgap */
3055 static struct omap_hwmod_ocp_if omap3xxx_l4_core__bandgap_ts = {
3056         .master         = &omap3xxx_l4_core_hwmod,
3057         .slave          = &omap34xx_bandgap_ts,
3058         .addr           = omap3xxx_bandgap_ts_addrs,
3059         .user           = OCP_USER_MPU,
3060 };
3061
3062 static struct omap_hwmod_ocp_if *omap3xxx_bandgap_ts_slaves[] = {
3063         &omap3xxx_l4_core__bandgap_ts,
3064 };
3065
3066 static struct omap_hwmod omap34xx_bandgap_ts = {
3067         .name           = "bandgap_ts",
3068         .main_clk       = "ts_fck",
3069         .slaves         = omap3xxx_bandgap_ts_slaves,
3070         .slaves_cnt     = ARRAY_SIZE(omap3xxx_bandgap_ts_slaves),
3071         .class          = &omap34xx_bandgap_ts_class,
3072         .flags          = HWMOD_NO_IDLEST,
3073 };
3074
3075 /*
3076  * usbhsotg
3077  */
3078 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3079         .rev_offs       = 0x0400,
3080         .sysc_offs      = 0x0404,
3081         .syss_offs      = 0x0408,
3082         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3083                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3084                           SYSC_HAS_AUTOIDLE),
3085         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3086                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3087         .sysc_fields    = &omap_hwmod_sysc_type1,
3088 };
3089
3090 static struct omap_hwmod_class usbotg_class = {
3091         .name = "usbotg",
3092         .sysc = &omap3xxx_usbhsotg_sysc,
3093 };
3094 /* usb_otg_hs */
3095 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3096
3097         { .name = "mc", .irq = 92 },
3098         { .name = "dma", .irq = 93 },
3099         { .irq = -1 }
3100 };
3101
3102 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3103         .name           = "usb_otg_hs",
3104         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
3105         .main_clk       = "hsotgusb_ick",
3106         .prcm           = {
3107                 .omap2 = {
3108                         .prcm_reg_id = 1,
3109                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3110                         .module_offs = CORE_MOD,
3111                         .idlest_reg_id = 1,
3112                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3113                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3114                 },
3115         },
3116         .masters        = omap3xxx_usbhsotg_masters,
3117         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3118         .slaves         = omap3xxx_usbhsotg_slaves,
3119         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3120         .class          = &usbotg_class,
3121
3122         /*
3123          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
3124          * broken when autoidle is enabled
3125          * workaround is to disable the autoidle bit at module level.
3126          *
3127          * Enabling the device in any other MIDLEMODE setting but force-idle
3128          * causes core_pwrdm not enter idle states at least on OMAP3630.
3129          * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
3130          * signal when MIDLEMODE is set to force-idle.
3131          */
3132         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3133                                 | HWMOD_FORCE_MSTANDBY,
3134 };
3135
3136 /* usb_otg_hs */
3137 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3138
3139         { .name = "mc", .irq = 71 },
3140         { .irq = -1 }
3141 };
3142
3143 static struct omap_hwmod_class am35xx_usbotg_class = {
3144         .name = "am35xx_usbotg",
3145         .sysc = NULL,
3146 };
3147
3148 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3149         .name           = "am35x_otg_hs",
3150         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3151         .main_clk       = NULL,
3152         .prcm = {
3153                 .omap2 = {
3154                 },
3155         },
3156         .masters        = am35xx_usbhsotg_masters,
3157         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3158         .slaves         = am35xx_usbhsotg_slaves,
3159         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3160         .class          = &am35xx_usbotg_class,
3161 };
3162
3163 /* MMC/SD/SDIO common */
3164
3165 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3166         .rev_offs       = 0x1fc,
3167         .sysc_offs      = 0x10,
3168         .syss_offs      = 0x14,
3169         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3170                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3171                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3172         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3173         .sysc_fields    = &omap_hwmod_sysc_type1,
3174 };
3175
3176 static struct omap_hwmod_class omap34xx_mmc_class = {
3177         .name = "mmc",
3178         .sysc = &omap34xx_mmc_sysc,
3179 };
3180
3181 /* MMC/SD/SDIO1 */
3182
3183 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3184         { .irq = 83, },
3185         { .irq = -1 }
3186 };
3187
3188 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3189         { .name = "tx", .dma_req = 61, },
3190         { .name = "rx", .dma_req = 62, },
3191         { .dma_req = -1 }
3192 };
3193
3194 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3195         { .role = "dbck", .clk = "omap_32k_fck", },
3196 };
3197
3198 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3199         &omap3xxx_l4_core__mmc1,
3200 };
3201
3202 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3203         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3204 };
3205
3206 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3207 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
3208         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
3209                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
3210 };
3211
3212 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
3213         .name           = "mmc1",
3214         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3215         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3216         .opt_clks       = omap34xx_mmc1_opt_clks,
3217         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3218         .main_clk       = "mmchs1_fck",
3219         .prcm           = {
3220                 .omap2 = {
3221                         .module_offs = CORE_MOD,
3222                         .prcm_reg_id = 1,
3223                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3224                         .idlest_reg_id = 1,
3225                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3226                 },
3227         },
3228         .dev_attr       = &mmc1_pre_es3_dev_attr,
3229         .slaves         = omap3xxx_mmc1_slaves,
3230         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3231         .class          = &omap34xx_mmc_class,
3232 };
3233
3234 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
3235         .name           = "mmc1",
3236         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3237         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3238         .opt_clks       = omap34xx_mmc1_opt_clks,
3239         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3240         .main_clk       = "mmchs1_fck",
3241         .prcm           = {
3242                 .omap2 = {
3243                         .module_offs = CORE_MOD,
3244                         .prcm_reg_id = 1,
3245                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3246                         .idlest_reg_id = 1,
3247                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3248                 },
3249         },
3250         .dev_attr       = &mmc1_dev_attr,
3251         .slaves         = omap3xxx_mmc1_slaves,
3252         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3253         .class          = &omap34xx_mmc_class,
3254 };
3255
3256 /* MMC/SD/SDIO2 */
3257
3258 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3259         { .irq = INT_24XX_MMC2_IRQ, },
3260         { .irq = -1 }
3261 };
3262
3263 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3264         { .name = "tx", .dma_req = 47, },
3265         { .name = "rx", .dma_req = 48, },
3266         { .dma_req = -1 }
3267 };
3268
3269 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3270         { .role = "dbck", .clk = "omap_32k_fck", },
3271 };
3272
3273 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3274         &omap3xxx_l4_core__mmc2,
3275 };
3276
3277 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3278 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
3279         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
3280 };
3281
3282 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
3283         .name           = "mmc2",
3284         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3285         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3286         .opt_clks       = omap34xx_mmc2_opt_clks,
3287         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3288         .main_clk       = "mmchs2_fck",
3289         .prcm           = {
3290                 .omap2 = {
3291                         .module_offs = CORE_MOD,
3292                         .prcm_reg_id = 1,
3293                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3294                         .idlest_reg_id = 1,
3295                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3296                 },
3297         },
3298         .dev_attr       = &mmc2_pre_es3_dev_attr,
3299         .slaves         = omap3xxx_mmc2_slaves,
3300         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3301         .class          = &omap34xx_mmc_class,
3302 };
3303
3304 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
3305         .name           = "mmc2",
3306         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3307         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3308         .opt_clks       = omap34xx_mmc2_opt_clks,
3309         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3310         .main_clk       = "mmchs2_fck",
3311         .prcm           = {
3312                 .omap2 = {
3313                         .module_offs = CORE_MOD,
3314                         .prcm_reg_id = 1,
3315                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3316                         .idlest_reg_id = 1,
3317                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3318                 },
3319         },
3320         .slaves         = omap3xxx_mmc2_slaves,
3321         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3322         .class          = &omap34xx_mmc_class,
3323 };
3324
3325 /* MMC/SD/SDIO3 */
3326
3327 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3328         { .irq = 94, },
3329         { .irq = -1 }
3330 };
3331
3332 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3333         { .name = "tx", .dma_req = 77, },
3334         { .name = "rx", .dma_req = 78, },
3335         { .dma_req = -1 }
3336 };
3337
3338 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3339         { .role = "dbck", .clk = "omap_32k_fck", },
3340 };
3341
3342 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3343         &omap3xxx_l4_core__mmc3,
3344 };
3345
3346 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3347         .name           = "mmc3",
3348         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3349         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3350         .opt_clks       = omap34xx_mmc3_opt_clks,
3351         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3352         .main_clk       = "mmchs3_fck",
3353         .prcm           = {
3354                 .omap2 = {
3355                         .prcm_reg_id = 1,
3356                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3357                         .idlest_reg_id = 1,
3358                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3359                 },
3360         },
3361         .slaves         = omap3xxx_mmc3_slaves,
3362         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3363         .class          = &omap34xx_mmc_class,
3364 };
3365
3366 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3367         &omap3xxx_l3_main_hwmod,
3368         &omap3xxx_l4_core_hwmod,
3369         &omap3xxx_l4_per_hwmod,
3370         &omap3xxx_l4_wkup_hwmod,
3371         &omap3xxx_mmc3_hwmod,
3372         &omap3xxx_mpu_hwmod,
3373
3374         &omap3xxx_timer1_hwmod,
3375         &omap3xxx_timer2_hwmod,
3376         &omap3xxx_timer3_hwmod,
3377         &omap3xxx_timer4_hwmod,
3378         &omap3xxx_timer5_hwmod,
3379         &omap3xxx_timer6_hwmod,
3380         &omap3xxx_timer7_hwmod,
3381         &omap3xxx_timer8_hwmod,
3382         &omap3xxx_timer9_hwmod,
3383         &omap3xxx_timer10_hwmod,
3384         &omap3xxx_timer11_hwmod,
3385
3386         &omap3xxx_wd_timer2_hwmod,
3387         &omap3xxx_uart1_hwmod,
3388         &omap3xxx_uart2_hwmod,
3389         &omap3xxx_uart3_hwmod,
3390
3391         /* i2c class */
3392         &omap3xxx_i2c1_hwmod,
3393         &omap3xxx_i2c2_hwmod,
3394         &omap3xxx_i2c3_hwmod,
3395
3396         /* gpio class */
3397         &omap3xxx_gpio1_hwmod,
3398         &omap3xxx_gpio2_hwmod,
3399         &omap3xxx_gpio3_hwmod,
3400         &omap3xxx_gpio4_hwmod,
3401         &omap3xxx_gpio5_hwmod,
3402         &omap3xxx_gpio6_hwmod,
3403
3404         /* dma_system class*/
3405         &omap3xxx_dma_system_hwmod,
3406
3407         /* mcbsp class */
3408         &omap3xxx_mcbsp1_hwmod,
3409         &omap3xxx_mcbsp2_hwmod,
3410         &omap3xxx_mcbsp3_hwmod,
3411         &omap3xxx_mcbsp4_hwmod,
3412         &omap3xxx_mcbsp5_hwmod,
3413         &omap3xxx_mcbsp2_sidetone_hwmod,
3414         &omap3xxx_mcbsp3_sidetone_hwmod,
3415
3416
3417         /* mcspi class */
3418         &omap34xx_mcspi1,
3419         &omap34xx_mcspi2,
3420         &omap34xx_mcspi3,
3421         &omap34xx_mcspi4,
3422
3423         &omap34xx_bandgap_ts,
3424
3425         NULL,
3426 };
3427
3428 /* GP-only hwmods */
3429 static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
3430         &omap3xxx_timer12_hwmod,
3431         NULL
3432 };
3433
3434 /* 3430ES1-only hwmods */
3435 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
3436         &omap3430es1_dss_core_hwmod,
3437         NULL
3438 };
3439
3440 /* 3430ES2+-only hwmods */
3441 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
3442         &omap3xxx_dss_core_hwmod,
3443         &omap3xxx_usbhsotg_hwmod,
3444         NULL
3445 };
3446
3447 /* <= 3430ES3-only hwmods */
3448 static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
3449         &omap3xxx_pre_es3_mmc1_hwmod,
3450         &omap3xxx_pre_es3_mmc2_hwmod,
3451         NULL
3452 };
3453
3454 /* 3430ES3+-only hwmods */
3455 static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
3456         &omap3xxx_es3plus_mmc1_hwmod,
3457         &omap3xxx_es3plus_mmc2_hwmod,
3458         NULL
3459 };
3460
3461 /* 34xx-only hwmods (all ES revisions) */
3462 static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
3463         &omap3xxx_iva_hwmod,
3464         &omap34xx_sr1_hwmod,
3465         &omap34xx_sr2_hwmod,
3466         &omap3xxx_mailbox_hwmod,
3467         NULL
3468 };
3469
3470 /* 36xx-only hwmods (all ES revisions) */
3471 static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
3472         &omap3xxx_iva_hwmod,
3473         &omap36xx_uart4_hwmod,
3474         &omap3xxx_dss_core_hwmod,
3475         &omap36xx_sr1_hwmod,
3476         &omap36xx_sr2_hwmod,
3477         &omap3xxx_usbhsotg_hwmod,
3478         &omap3xxx_mailbox_hwmod,
3479         &omap3xxx_es3plus_mmc1_hwmod,
3480         &omap3xxx_es3plus_mmc2_hwmod,
3481         NULL
3482 };
3483
3484 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3485         &omap3xxx_dss_core_hwmod, /* XXX ??? */
3486         &am35xx_usbhsotg_hwmod,
3487         &omap3xxx_es3plus_mmc1_hwmod,
3488         &omap3xxx_es3plus_mmc2_hwmod,
3489         NULL
3490 };
3491
3492 static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
3493         /* dss class */
3494         &omap3xxx_dss_dispc_hwmod,
3495         &omap3xxx_dss_dsi1_hwmod,
3496         &omap3xxx_dss_rfbi_hwmod,
3497         &omap3xxx_dss_venc_hwmod,
3498         NULL
3499 };
3500
3501 int __init omap3xxx_hwmod_init(void)
3502 {
3503         int r;
3504         struct omap_hwmod **h = NULL;
3505         unsigned int rev;
3506
3507         /* Register hwmods common to all OMAP3 */
3508         r = omap_hwmod_register(omap3xxx_hwmods);
3509         if (r < 0)
3510                 return r;
3511
3512         /* Register GP-only hwmods. */
3513         if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3514                 r = omap_hwmod_register(omap3xxx_gp_hwmods);
3515                 if (r < 0)
3516                         return r;
3517         }
3518
3519         rev = omap_rev();
3520
3521         /*
3522          * Register hwmods common to individual OMAP3 families, all
3523          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3524          * All possible revisions should be included in this conditional.
3525          */
3526         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3527             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3528             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3529                 h = omap34xx_hwmods;
3530         } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3531                 h = am35xx_hwmods;
3532         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3533                    rev == OMAP3630_REV_ES1_2) {
3534                 h = omap36xx_hwmods;
3535         } else {
3536                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3537                 return -EINVAL;
3538         };
3539
3540         r = omap_hwmod_register(h);
3541         if (r < 0)
3542                 return r;
3543
3544         /*
3545          * Register hwmods specific to certain ES levels of a
3546          * particular family of silicon (e.g., 34xx ES1.0)
3547          */
3548         h = NULL;
3549         if (rev == OMAP3430_REV_ES1_0) {
3550                 h = omap3430es1_hwmods;
3551         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3552                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3553                    rev == OMAP3430_REV_ES3_1_2) {
3554                 h = omap3430es2plus_hwmods;
3555         };
3556
3557         if (h) {
3558                 r = omap_hwmod_register(h);
3559                 if (r < 0)
3560                         return r;
3561         }
3562
3563         h = NULL;
3564         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3565             rev == OMAP3430_REV_ES2_1) {
3566                 h = omap3430_pre_es3_hwmods;
3567         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3568                    rev == OMAP3430_REV_ES3_1_2) {
3569                 h = omap3430_es3plus_hwmods;
3570         };
3571
3572         if (h)
3573                 r = omap_hwmod_register(h);
3574         if (r < 0)
3575                 return r;
3576
3577         /*
3578          * DSS code presumes that dss_core hwmod is handled first,
3579          * _before_ any other DSS related hwmods so register common
3580          * DSS hwmods last to ensure that dss_core is already registered.
3581          * Otherwise some change things may happen, for ex. if dispc
3582          * is handled before dss_core and DSS is enabled in bootloader
3583          * DIPSC will be reset with outputs enabled which sometimes leads
3584          * to unrecoverable L3 error.
3585          */
3586         r = omap_hwmod_register(omap3xxx_dss_hwmods);
3587
3588         return r;
3589 }