ARM: OMAP3: hwmod data: some mainline backports
[pandora-kernel.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
1 /*
2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3  *
4  * Copyright (C) 2009-2011 Nokia Corporation
5  * Paul Walmsley
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  * The data in this file should be completely autogeneratable from
12  * the TI hardware database or other technical documentation.
13  *
14  * XXX these should be marked initdata for multi-OMAP kernels
15  */
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
18 #include <plat/cpu.h>
19 #include <plat/dma.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
23 #include <plat/i2c.h>
24 #include <plat/gpio.h>
25 #include <plat/mmc.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
28 #include <plat/dmtimer.h>
29
30 #include "omap_hwmod_common_data.h"
31
32 #include "smartreflex.h"
33 #include "prm-regbits-34xx.h"
34 #include "cm-regbits-34xx.h"
35 #include "wd_timer.h"
36 #include <mach/am35xx.h>
37
38 /*
39  * OMAP3xxx hardware module integration data
40  *
41  * ALl of the data in this section should be autogeneratable from the
42  * TI hardware database or other technical documentation.  Data that
43  * is driver-specific or driver-kernel integration-specific belongs
44  * elsewhere.
45  */
46
47 static struct omap_hwmod omap3xxx_mpu_hwmod;
48 static struct omap_hwmod omap3xxx_iva_hwmod;
49 static struct omap_hwmod omap3xxx_l3_main_hwmod;
50 static struct omap_hwmod omap3xxx_l4_core_hwmod;
51 static struct omap_hwmod omap3xxx_l4_per_hwmod;
52 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
53 static struct omap_hwmod omap3430es1_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_core_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
56 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
57 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
58 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
59 static struct omap_hwmod omap3xxx_i2c1_hwmod;
60 static struct omap_hwmod omap3xxx_i2c2_hwmod;
61 static struct omap_hwmod omap3xxx_i2c3_hwmod;
62 static struct omap_hwmod omap3xxx_gpio1_hwmod;
63 static struct omap_hwmod omap3xxx_gpio2_hwmod;
64 static struct omap_hwmod omap3xxx_gpio3_hwmod;
65 static struct omap_hwmod omap3xxx_gpio4_hwmod;
66 static struct omap_hwmod omap3xxx_gpio5_hwmod;
67 static struct omap_hwmod omap3xxx_gpio6_hwmod;
68 static struct omap_hwmod omap34xx_sr1_hwmod;
69 static struct omap_hwmod omap36xx_sr1_hwmod;
70 static struct omap_hwmod omap34xx_sr2_hwmod;
71 static struct omap_hwmod omap36xx_sr2_hwmod;
72 static struct omap_hwmod omap34xx_mcspi1;
73 static struct omap_hwmod omap34xx_mcspi2;
74 static struct omap_hwmod omap34xx_mcspi3;
75 static struct omap_hwmod omap34xx_mcspi4;
76 static struct omap_hwmod omap3xxx_mmc1_hwmod;
77 static struct omap_hwmod omap3xxx_mmc2_hwmod;
78 static struct omap_hwmod omap3xxx_mmc3_hwmod;
79 static struct omap_hwmod am35xx_usbhsotg_hwmod;
80
81 static struct omap_hwmod omap3xxx_dma_system_hwmod;
82
83 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
87 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
88 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
89 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
90
91 /* L3 -> L4_CORE interface */
92 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
93         .master = &omap3xxx_l3_main_hwmod,
94         .slave  = &omap3xxx_l4_core_hwmod,
95         .user   = OCP_USER_MPU | OCP_USER_SDMA,
96 };
97
98 /* L3 -> L4_PER interface */
99 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
100         .master = &omap3xxx_l3_main_hwmod,
101         .slave  = &omap3xxx_l4_per_hwmod,
102         .user   = OCP_USER_MPU | OCP_USER_SDMA,
103 };
104
105 /* L3 taret configuration and error log registers */
106 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
107         { .irq = INT_34XX_L3_DBG_IRQ },
108         { .irq = INT_34XX_L3_APP_IRQ },
109         { .irq = -1 }
110 };
111
112 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
113         {
114                 .pa_start       = 0x68000000,
115                 .pa_end         = 0x6800ffff,
116                 .flags          = ADDR_TYPE_RT,
117         },
118         { }
119 };
120
121 /* MPU -> L3 interface */
122 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
123         .master   = &omap3xxx_mpu_hwmod,
124         .slave    = &omap3xxx_l3_main_hwmod,
125         .addr     = omap3xxx_l3_main_addrs,
126         .user   = OCP_USER_MPU,
127 };
128
129 /* Slave interfaces on the L3 interconnect */
130 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
131         &omap3xxx_mpu__l3_main,
132 };
133
134 /* DSS -> l3 */
135 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
136         .master         = &omap3xxx_dss_core_hwmod,
137         .slave          = &omap3xxx_l3_main_hwmod,
138         .fw = {
139                 .omap2 = {
140                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
141                         .flags  = OMAP_FIREWALL_L3,
142                 }
143         },
144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
145 };
146
147 /* Master interfaces on the L3 interconnect */
148 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
149         &omap3xxx_l3_main__l4_core,
150         &omap3xxx_l3_main__l4_per,
151 };
152
153 /* L3 */
154 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
155         .name           = "l3_main",
156         .class          = &l3_hwmod_class,
157         .mpu_irqs       = omap3xxx_l3_main_irqs,
158         .masters        = omap3xxx_l3_main_masters,
159         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
160         .slaves         = omap3xxx_l3_main_slaves,
161         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
162         .flags          = HWMOD_NO_IDLEST,
163 };
164
165 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
166 static struct omap_hwmod omap3xxx_uart1_hwmod;
167 static struct omap_hwmod omap3xxx_uart2_hwmod;
168 static struct omap_hwmod omap3xxx_uart3_hwmod;
169 static struct omap_hwmod omap36xx_uart4_hwmod;
170 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
171
172 /* l3_core -> usbhsotg interface */
173 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
174         .master         = &omap3xxx_usbhsotg_hwmod,
175         .slave          = &omap3xxx_l3_main_hwmod,
176         .clk            = "core_l3_ick",
177         .user           = OCP_USER_MPU,
178 };
179
180 /* l3_core -> am35xx_usbhsotg interface */
181 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
182         .master         = &am35xx_usbhsotg_hwmod,
183         .slave          = &omap3xxx_l3_main_hwmod,
184         .clk            = "core_l3_ick",
185         .user           = OCP_USER_MPU,
186 };
187 /* L4_CORE -> L4_WKUP interface */
188 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
189         .master = &omap3xxx_l4_core_hwmod,
190         .slave  = &omap3xxx_l4_wkup_hwmod,
191         .user   = OCP_USER_MPU | OCP_USER_SDMA,
192 };
193
194 /* L4 CORE -> MMC1 interface */
195 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
196         .master         = &omap3xxx_l4_core_hwmod,
197         .slave          = &omap3xxx_mmc1_hwmod,
198         .clk            = "mmchs1_ick",
199         .addr           = omap2430_mmc1_addr_space,
200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
201         .flags          = OMAP_FIREWALL_L4
202 };
203
204 /* L4 CORE -> MMC2 interface */
205 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
206         .master         = &omap3xxx_l4_core_hwmod,
207         .slave          = &omap3xxx_mmc2_hwmod,
208         .clk            = "mmchs2_ick",
209         .addr           = omap2430_mmc2_addr_space,
210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
211         .flags          = OMAP_FIREWALL_L4
212 };
213
214 /* L4 CORE -> MMC3 interface */
215 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
216         {
217                 .pa_start       = 0x480ad000,
218                 .pa_end         = 0x480ad1ff,
219                 .flags          = ADDR_TYPE_RT,
220         },
221         { }
222 };
223
224 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
225         .master         = &omap3xxx_l4_core_hwmod,
226         .slave          = &omap3xxx_mmc3_hwmod,
227         .clk            = "mmchs3_ick",
228         .addr           = omap3xxx_mmc3_addr_space,
229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
230         .flags          = OMAP_FIREWALL_L4
231 };
232
233 /* L4 CORE -> UART1 interface */
234 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
235         {
236                 .pa_start       = OMAP3_UART1_BASE,
237                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
238                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
239         },
240         { }
241 };
242
243 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
244         .master         = &omap3xxx_l4_core_hwmod,
245         .slave          = &omap3xxx_uart1_hwmod,
246         .clk            = "uart1_ick",
247         .addr           = omap3xxx_uart1_addr_space,
248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
249 };
250
251 /* L4 CORE -> UART2 interface */
252 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
253         {
254                 .pa_start       = OMAP3_UART2_BASE,
255                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
256                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
257         },
258         { }
259 };
260
261 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
262         .master         = &omap3xxx_l4_core_hwmod,
263         .slave          = &omap3xxx_uart2_hwmod,
264         .clk            = "uart2_ick",
265         .addr           = omap3xxx_uart2_addr_space,
266         .user           = OCP_USER_MPU | OCP_USER_SDMA,
267 };
268
269 /* L4 PER -> UART3 interface */
270 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
271         {
272                 .pa_start       = OMAP3_UART3_BASE,
273                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
274                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
275         },
276         { }
277 };
278
279 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
280         .master         = &omap3xxx_l4_per_hwmod,
281         .slave          = &omap3xxx_uart3_hwmod,
282         .clk            = "uart3_ick",
283         .addr           = omap3xxx_uart3_addr_space,
284         .user           = OCP_USER_MPU | OCP_USER_SDMA,
285 };
286
287 /* L4 PER -> UART4 interface */
288 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
289         {
290                 .pa_start       = OMAP3_UART4_BASE,
291                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
292                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
293         },
294         { }
295 };
296
297 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
298         .master         = &omap3xxx_l4_per_hwmod,
299         .slave          = &omap36xx_uart4_hwmod,
300         .clk            = "uart4_ick",
301         .addr           = omap36xx_uart4_addr_space,
302         .user           = OCP_USER_MPU | OCP_USER_SDMA,
303 };
304
305 /* L4 CORE -> I2C1 interface */
306 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
307         .master         = &omap3xxx_l4_core_hwmod,
308         .slave          = &omap3xxx_i2c1_hwmod,
309         .clk            = "i2c1_ick",
310         .addr           = omap2_i2c1_addr_space,
311         .fw = {
312                 .omap2 = {
313                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
314                         .l4_prot_group = 7,
315                         .flags  = OMAP_FIREWALL_L4,
316                 }
317         },
318         .user           = OCP_USER_MPU | OCP_USER_SDMA,
319 };
320
321 /* L4 CORE -> I2C2 interface */
322 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
323         .master         = &omap3xxx_l4_core_hwmod,
324         .slave          = &omap3xxx_i2c2_hwmod,
325         .clk            = "i2c2_ick",
326         .addr           = omap2_i2c2_addr_space,
327         .fw = {
328                 .omap2 = {
329                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
330                         .l4_prot_group = 7,
331                         .flags = OMAP_FIREWALL_L4,
332                 }
333         },
334         .user           = OCP_USER_MPU | OCP_USER_SDMA,
335 };
336
337 /* L4 CORE -> I2C3 interface */
338 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
339         {
340                 .pa_start       = 0x48060000,
341                 .pa_end         = 0x48060000 + SZ_128 - 1,
342                 .flags          = ADDR_TYPE_RT,
343         },
344         { }
345 };
346
347 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
348         .master         = &omap3xxx_l4_core_hwmod,
349         .slave          = &omap3xxx_i2c3_hwmod,
350         .clk            = "i2c3_ick",
351         .addr           = omap3xxx_i2c3_addr_space,
352         .fw = {
353                 .omap2 = {
354                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
355                         .l4_prot_group = 7,
356                         .flags = OMAP_FIREWALL_L4,
357                 }
358         },
359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
360 };
361
362 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
363         { .irq = 18},
364         { .irq = -1 }
365 };
366
367 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
368         { .irq = 19},
369         { .irq = -1 }
370 };
371
372 /* L4 CORE -> SR1 interface */
373 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
374         {
375                 .pa_start       = OMAP34XX_SR1_BASE,
376                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
377                 .flags          = ADDR_TYPE_RT,
378         },
379         { }
380 };
381
382 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
383         .master         = &omap3xxx_l4_core_hwmod,
384         .slave          = &omap34xx_sr1_hwmod,
385         .clk            = "sr_l4_ick",
386         .addr           = omap3_sr1_addr_space,
387         .user           = OCP_USER_MPU,
388 };
389
390 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
391         .master         = &omap3xxx_l4_core_hwmod,
392         .slave          = &omap36xx_sr1_hwmod,
393         .clk            = "sr_l4_ick",
394         .addr           = omap3_sr1_addr_space,
395         .user           = OCP_USER_MPU,
396 };
397
398 /* L4 CORE -> SR1 interface */
399 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
400         {
401                 .pa_start       = OMAP34XX_SR2_BASE,
402                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
403                 .flags          = ADDR_TYPE_RT,
404         },
405         { }
406 };
407
408 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
409         .master         = &omap3xxx_l4_core_hwmod,
410         .slave          = &omap34xx_sr2_hwmod,
411         .clk            = "sr_l4_ick",
412         .addr           = omap3_sr2_addr_space,
413         .user           = OCP_USER_MPU,
414 };
415
416 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
417         .master         = &omap3xxx_l4_core_hwmod,
418         .slave          = &omap36xx_sr2_hwmod,
419         .clk            = "sr_l4_ick",
420         .addr           = omap3_sr2_addr_space,
421         .user           = OCP_USER_MPU,
422 };
423
424 /*
425 * usbhsotg interface data
426 */
427
428 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
429         {
430                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
431                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
432                 .flags          = ADDR_TYPE_RT
433         },
434         { }
435 };
436
437 /* l4_core -> usbhsotg  */
438 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
439         .master         = &omap3xxx_l4_core_hwmod,
440         .slave          = &omap3xxx_usbhsotg_hwmod,
441         .clk            = "l4_ick",
442         .addr           = omap3xxx_usbhsotg_addrs,
443         .user           = OCP_USER_MPU,
444 };
445
446 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
447         &omap3xxx_usbhsotg__l3,
448 };
449
450 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
451         &omap3xxx_l4_core__usbhsotg,
452 };
453
454 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
455         {
456                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
457                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
458                 .flags          = ADDR_TYPE_RT
459         },
460         { }
461 };
462
463 /* l4_core -> usbhsotg  */
464 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
465         .master         = &omap3xxx_l4_core_hwmod,
466         .slave          = &am35xx_usbhsotg_hwmod,
467         .clk            = "l4_ick",
468         .addr           = am35xx_usbhsotg_addrs,
469         .user           = OCP_USER_MPU,
470 };
471
472 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
473         &am35xx_usbhsotg__l3,
474 };
475
476 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
477         &am35xx_l4_core__usbhsotg,
478 };
479 /* Slave interfaces on the L4_CORE interconnect */
480 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
481         &omap3xxx_l3_main__l4_core,
482 };
483
484 /* L4 CORE */
485 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
486         .name           = "l4_core",
487         .class          = &l4_hwmod_class,
488         .slaves         = omap3xxx_l4_core_slaves,
489         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
490         .flags          = HWMOD_NO_IDLEST,
491 };
492
493 /* Slave interfaces on the L4_PER interconnect */
494 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
495         &omap3xxx_l3_main__l4_per,
496 };
497
498 /* L4 PER */
499 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
500         .name           = "l4_per",
501         .class          = &l4_hwmod_class,
502         .slaves         = omap3xxx_l4_per_slaves,
503         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
504         .flags          = HWMOD_NO_IDLEST,
505 };
506
507 /* Slave interfaces on the L4_WKUP interconnect */
508 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
509         &omap3xxx_l4_core__l4_wkup,
510 };
511
512 /* L4 WKUP */
513 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
514         .name           = "l4_wkup",
515         .class          = &l4_hwmod_class,
516         .slaves         = omap3xxx_l4_wkup_slaves,
517         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
518         .flags          = HWMOD_NO_IDLEST,
519 };
520
521 /* Master interfaces on the MPU device */
522 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
523         &omap3xxx_mpu__l3_main,
524 };
525
526 /* MPU */
527 static struct omap_hwmod omap3xxx_mpu_hwmod = {
528         .name           = "mpu",
529         .class          = &mpu_hwmod_class,
530         .main_clk       = "arm_fck",
531         .masters        = omap3xxx_mpu_masters,
532         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
533 };
534
535 /*
536  * IVA2_2 interface data
537  */
538
539 /* IVA2 <- L3 interface */
540 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
541         .master         = &omap3xxx_l3_main_hwmod,
542         .slave          = &omap3xxx_iva_hwmod,
543         .clk            = "iva2_ck",
544         .user           = OCP_USER_MPU | OCP_USER_SDMA,
545 };
546
547 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
548         &omap3xxx_l3__iva,
549 };
550
551 /*
552  * IVA2 (IVA2)
553  */
554
555 static struct omap_hwmod omap3xxx_iva_hwmod = {
556         .name           = "iva",
557         .class          = &iva_hwmod_class,
558         .masters        = omap3xxx_iva_masters,
559         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
560 };
561
562 /* timer class */
563 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
564         .rev_offs       = 0x0000,
565         .sysc_offs      = 0x0010,
566         .syss_offs      = 0x0014,
567         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
568                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
569                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
570         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
571         .sysc_fields    = &omap_hwmod_sysc_type1,
572 };
573
574 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
575         .name = "timer",
576         .sysc = &omap3xxx_timer_1ms_sysc,
577         .rev = OMAP_TIMER_IP_VERSION_1,
578 };
579
580 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
581         .rev_offs       = 0x0000,
582         .sysc_offs      = 0x0010,
583         .syss_offs      = 0x0014,
584         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
585                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
586         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
587         .sysc_fields    = &omap_hwmod_sysc_type1,
588 };
589
590 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
591         .name = "timer",
592         .sysc = &omap3xxx_timer_sysc,
593         .rev =  OMAP_TIMER_IP_VERSION_1,
594 };
595
596 /* secure timers dev attribute */
597 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
598         .timer_capability       = OMAP_TIMER_SECURE,
599 };
600
601 /* always-on timers dev attribute */
602 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
603         .timer_capability       = OMAP_TIMER_ALWON,
604 };
605
606 /* pwm timers dev attribute */
607 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
608         .timer_capability       = OMAP_TIMER_HAS_PWM,
609 };
610
611 /* timer1 */
612 static struct omap_hwmod omap3xxx_timer1_hwmod;
613
614 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
615         {
616                 .pa_start       = 0x48318000,
617                 .pa_end         = 0x48318000 + SZ_1K - 1,
618                 .flags          = ADDR_TYPE_RT
619         },
620         { }
621 };
622
623 /* l4_wkup -> timer1 */
624 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
625         .master         = &omap3xxx_l4_wkup_hwmod,
626         .slave          = &omap3xxx_timer1_hwmod,
627         .clk            = "gpt1_ick",
628         .addr           = omap3xxx_timer1_addrs,
629         .user           = OCP_USER_MPU | OCP_USER_SDMA,
630 };
631
632 /* timer1 slave port */
633 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
634         &omap3xxx_l4_wkup__timer1,
635 };
636
637 /* timer1 hwmod */
638 static struct omap_hwmod omap3xxx_timer1_hwmod = {
639         .name           = "timer1",
640         .mpu_irqs       = omap2_timer1_mpu_irqs,
641         .main_clk       = "gpt1_fck",
642         .prcm           = {
643                 .omap2 = {
644                         .prcm_reg_id = 1,
645                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
646                         .module_offs = WKUP_MOD,
647                         .idlest_reg_id = 1,
648                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
649                 },
650         },
651         .dev_attr       = &capability_alwon_dev_attr,
652         .slaves         = omap3xxx_timer1_slaves,
653         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
654         .class          = &omap3xxx_timer_1ms_hwmod_class,
655 };
656
657 /* timer2 */
658 static struct omap_hwmod omap3xxx_timer2_hwmod;
659
660 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
661         {
662                 .pa_start       = 0x49032000,
663                 .pa_end         = 0x49032000 + SZ_1K - 1,
664                 .flags          = ADDR_TYPE_RT
665         },
666         { }
667 };
668
669 /* l4_per -> timer2 */
670 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
671         .master         = &omap3xxx_l4_per_hwmod,
672         .slave          = &omap3xxx_timer2_hwmod,
673         .clk            = "gpt2_ick",
674         .addr           = omap3xxx_timer2_addrs,
675         .user           = OCP_USER_MPU | OCP_USER_SDMA,
676 };
677
678 /* timer2 slave port */
679 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
680         &omap3xxx_l4_per__timer2,
681 };
682
683 /* timer2 hwmod */
684 static struct omap_hwmod omap3xxx_timer2_hwmod = {
685         .name           = "timer2",
686         .mpu_irqs       = omap2_timer2_mpu_irqs,
687         .main_clk       = "gpt2_fck",
688         .prcm           = {
689                 .omap2 = {
690                         .prcm_reg_id = 1,
691                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
692                         .module_offs = OMAP3430_PER_MOD,
693                         .idlest_reg_id = 1,
694                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
695                 },
696         },
697         .dev_attr       = &capability_alwon_dev_attr,
698         .slaves         = omap3xxx_timer2_slaves,
699         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
700         .class          = &omap3xxx_timer_1ms_hwmod_class,
701 };
702
703 /* timer3 */
704 static struct omap_hwmod omap3xxx_timer3_hwmod;
705
706 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
707         {
708                 .pa_start       = 0x49034000,
709                 .pa_end         = 0x49034000 + SZ_1K - 1,
710                 .flags          = ADDR_TYPE_RT
711         },
712         { }
713 };
714
715 /* l4_per -> timer3 */
716 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
717         .master         = &omap3xxx_l4_per_hwmod,
718         .slave          = &omap3xxx_timer3_hwmod,
719         .clk            = "gpt3_ick",
720         .addr           = omap3xxx_timer3_addrs,
721         .user           = OCP_USER_MPU | OCP_USER_SDMA,
722 };
723
724 /* timer3 slave port */
725 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
726         &omap3xxx_l4_per__timer3,
727 };
728
729 /* timer3 hwmod */
730 static struct omap_hwmod omap3xxx_timer3_hwmod = {
731         .name           = "timer3",
732         .mpu_irqs       = omap2_timer3_mpu_irqs,
733         .main_clk       = "gpt3_fck",
734         .prcm           = {
735                 .omap2 = {
736                         .prcm_reg_id = 1,
737                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
738                         .module_offs = OMAP3430_PER_MOD,
739                         .idlest_reg_id = 1,
740                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
741                 },
742         },
743         .dev_attr       = &capability_alwon_dev_attr,
744         .slaves         = omap3xxx_timer3_slaves,
745         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
746         .class          = &omap3xxx_timer_hwmod_class,
747 };
748
749 /* timer4 */
750 static struct omap_hwmod omap3xxx_timer4_hwmod;
751
752 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
753         {
754                 .pa_start       = 0x49036000,
755                 .pa_end         = 0x49036000 + SZ_1K - 1,
756                 .flags          = ADDR_TYPE_RT
757         },
758         { }
759 };
760
761 /* l4_per -> timer4 */
762 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
763         .master         = &omap3xxx_l4_per_hwmod,
764         .slave          = &omap3xxx_timer4_hwmod,
765         .clk            = "gpt4_ick",
766         .addr           = omap3xxx_timer4_addrs,
767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
768 };
769
770 /* timer4 slave port */
771 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
772         &omap3xxx_l4_per__timer4,
773 };
774
775 /* timer4 hwmod */
776 static struct omap_hwmod omap3xxx_timer4_hwmod = {
777         .name           = "timer4",
778         .mpu_irqs       = omap2_timer4_mpu_irqs,
779         .main_clk       = "gpt4_fck",
780         .prcm           = {
781                 .omap2 = {
782                         .prcm_reg_id = 1,
783                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
784                         .module_offs = OMAP3430_PER_MOD,
785                         .idlest_reg_id = 1,
786                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
787                 },
788         },
789         .dev_attr       = &capability_alwon_dev_attr,
790         .slaves         = omap3xxx_timer4_slaves,
791         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
792         .class          = &omap3xxx_timer_hwmod_class,
793 };
794
795 /* timer5 */
796 static struct omap_hwmod omap3xxx_timer5_hwmod;
797
798 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
799         {
800                 .pa_start       = 0x49038000,
801                 .pa_end         = 0x49038000 + SZ_1K - 1,
802                 .flags          = ADDR_TYPE_RT
803         },
804         { }
805 };
806
807 /* l4_per -> timer5 */
808 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
809         .master         = &omap3xxx_l4_per_hwmod,
810         .slave          = &omap3xxx_timer5_hwmod,
811         .clk            = "gpt5_ick",
812         .addr           = omap3xxx_timer5_addrs,
813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
814 };
815
816 /* timer5 slave port */
817 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
818         &omap3xxx_l4_per__timer5,
819 };
820
821 /* timer5 hwmod */
822 static struct omap_hwmod omap3xxx_timer5_hwmod = {
823         .name           = "timer5",
824         .mpu_irqs       = omap2_timer5_mpu_irqs,
825         .main_clk       = "gpt5_fck",
826         .prcm           = {
827                 .omap2 = {
828                         .prcm_reg_id = 1,
829                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
830                         .module_offs = OMAP3430_PER_MOD,
831                         .idlest_reg_id = 1,
832                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
833                 },
834         },
835         .dev_attr       = &capability_alwon_dev_attr,
836         .slaves         = omap3xxx_timer5_slaves,
837         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
838         .class          = &omap3xxx_timer_hwmod_class,
839 };
840
841 /* timer6 */
842 static struct omap_hwmod omap3xxx_timer6_hwmod;
843
844 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
845         {
846                 .pa_start       = 0x4903A000,
847                 .pa_end         = 0x4903A000 + SZ_1K - 1,
848                 .flags          = ADDR_TYPE_RT
849         },
850         { }
851 };
852
853 /* l4_per -> timer6 */
854 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
855         .master         = &omap3xxx_l4_per_hwmod,
856         .slave          = &omap3xxx_timer6_hwmod,
857         .clk            = "gpt6_ick",
858         .addr           = omap3xxx_timer6_addrs,
859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
860 };
861
862 /* timer6 slave port */
863 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
864         &omap3xxx_l4_per__timer6,
865 };
866
867 /* timer6 hwmod */
868 static struct omap_hwmod omap3xxx_timer6_hwmod = {
869         .name           = "timer6",
870         .mpu_irqs       = omap2_timer6_mpu_irqs,
871         .main_clk       = "gpt6_fck",
872         .prcm           = {
873                 .omap2 = {
874                         .prcm_reg_id = 1,
875                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
876                         .module_offs = OMAP3430_PER_MOD,
877                         .idlest_reg_id = 1,
878                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
879                 },
880         },
881         .dev_attr       = &capability_alwon_dev_attr,
882         .slaves         = omap3xxx_timer6_slaves,
883         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
884         .class          = &omap3xxx_timer_hwmod_class,
885 };
886
887 /* timer7 */
888 static struct omap_hwmod omap3xxx_timer7_hwmod;
889
890 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
891         {
892                 .pa_start       = 0x4903C000,
893                 .pa_end         = 0x4903C000 + SZ_1K - 1,
894                 .flags          = ADDR_TYPE_RT
895         },
896         { }
897 };
898
899 /* l4_per -> timer7 */
900 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
901         .master         = &omap3xxx_l4_per_hwmod,
902         .slave          = &omap3xxx_timer7_hwmod,
903         .clk            = "gpt7_ick",
904         .addr           = omap3xxx_timer7_addrs,
905         .user           = OCP_USER_MPU | OCP_USER_SDMA,
906 };
907
908 /* timer7 slave port */
909 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
910         &omap3xxx_l4_per__timer7,
911 };
912
913 /* timer7 hwmod */
914 static struct omap_hwmod omap3xxx_timer7_hwmod = {
915         .name           = "timer7",
916         .mpu_irqs       = omap2_timer7_mpu_irqs,
917         .main_clk       = "gpt7_fck",
918         .prcm           = {
919                 .omap2 = {
920                         .prcm_reg_id = 1,
921                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
922                         .module_offs = OMAP3430_PER_MOD,
923                         .idlest_reg_id = 1,
924                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
925                 },
926         },
927         .dev_attr       = &capability_alwon_dev_attr,
928         .slaves         = omap3xxx_timer7_slaves,
929         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
930         .class          = &omap3xxx_timer_hwmod_class,
931 };
932
933 /* timer8 */
934 static struct omap_hwmod omap3xxx_timer8_hwmod;
935
936 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
937         {
938                 .pa_start       = 0x4903E000,
939                 .pa_end         = 0x4903E000 + SZ_1K - 1,
940                 .flags          = ADDR_TYPE_RT
941         },
942         { }
943 };
944
945 /* l4_per -> timer8 */
946 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
947         .master         = &omap3xxx_l4_per_hwmod,
948         .slave          = &omap3xxx_timer8_hwmod,
949         .clk            = "gpt8_ick",
950         .addr           = omap3xxx_timer8_addrs,
951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
952 };
953
954 /* timer8 slave port */
955 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
956         &omap3xxx_l4_per__timer8,
957 };
958
959 /* timer8 hwmod */
960 static struct omap_hwmod omap3xxx_timer8_hwmod = {
961         .name           = "timer8",
962         .mpu_irqs       = omap2_timer8_mpu_irqs,
963         .main_clk       = "gpt8_fck",
964         .prcm           = {
965                 .omap2 = {
966                         .prcm_reg_id = 1,
967                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
968                         .module_offs = OMAP3430_PER_MOD,
969                         .idlest_reg_id = 1,
970                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
971                 },
972         },
973         .dev_attr       = &capability_pwm_dev_attr,
974         .slaves         = omap3xxx_timer8_slaves,
975         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
976         .class          = &omap3xxx_timer_hwmod_class,
977 };
978
979 /* timer9 */
980 static struct omap_hwmod omap3xxx_timer9_hwmod;
981
982 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
983         {
984                 .pa_start       = 0x49040000,
985                 .pa_end         = 0x49040000 + SZ_1K - 1,
986                 .flags          = ADDR_TYPE_RT
987         },
988         { }
989 };
990
991 /* l4_per -> timer9 */
992 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
993         .master         = &omap3xxx_l4_per_hwmod,
994         .slave          = &omap3xxx_timer9_hwmod,
995         .clk            = "gpt9_ick",
996         .addr           = omap3xxx_timer9_addrs,
997         .user           = OCP_USER_MPU | OCP_USER_SDMA,
998 };
999
1000 /* timer9 slave port */
1001 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1002         &omap3xxx_l4_per__timer9,
1003 };
1004
1005 /* timer9 hwmod */
1006 static struct omap_hwmod omap3xxx_timer9_hwmod = {
1007         .name           = "timer9",
1008         .mpu_irqs       = omap2_timer9_mpu_irqs,
1009         .main_clk       = "gpt9_fck",
1010         .prcm           = {
1011                 .omap2 = {
1012                         .prcm_reg_id = 1,
1013                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
1014                         .module_offs = OMAP3430_PER_MOD,
1015                         .idlest_reg_id = 1,
1016                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1017                 },
1018         },
1019         .dev_attr       = &capability_pwm_dev_attr,
1020         .slaves         = omap3xxx_timer9_slaves,
1021         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
1022         .class          = &omap3xxx_timer_hwmod_class,
1023 };
1024
1025 /* timer10 */
1026 static struct omap_hwmod omap3xxx_timer10_hwmod;
1027
1028 /* l4_core -> timer10 */
1029 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1030         .master         = &omap3xxx_l4_core_hwmod,
1031         .slave          = &omap3xxx_timer10_hwmod,
1032         .clk            = "gpt10_ick",
1033         .addr           = omap2_timer10_addrs,
1034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1035 };
1036
1037 /* timer10 slave port */
1038 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1039         &omap3xxx_l4_core__timer10,
1040 };
1041
1042 /* timer10 hwmod */
1043 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1044         .name           = "timer10",
1045         .mpu_irqs       = omap2_timer10_mpu_irqs,
1046         .main_clk       = "gpt10_fck",
1047         .prcm           = {
1048                 .omap2 = {
1049                         .prcm_reg_id = 1,
1050                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1051                         .module_offs = CORE_MOD,
1052                         .idlest_reg_id = 1,
1053                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1054                 },
1055         },
1056         .dev_attr       = &capability_pwm_dev_attr,
1057         .slaves         = omap3xxx_timer10_slaves,
1058         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1059         .class          = &omap3xxx_timer_1ms_hwmod_class,
1060 };
1061
1062 /* timer11 */
1063 static struct omap_hwmod omap3xxx_timer11_hwmod;
1064
1065 /* l4_core -> timer11 */
1066 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1067         .master         = &omap3xxx_l4_core_hwmod,
1068         .slave          = &omap3xxx_timer11_hwmod,
1069         .clk            = "gpt11_ick",
1070         .addr           = omap2_timer11_addrs,
1071         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1072 };
1073
1074 /* timer11 slave port */
1075 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1076         &omap3xxx_l4_core__timer11,
1077 };
1078
1079 /* timer11 hwmod */
1080 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1081         .name           = "timer11",
1082         .mpu_irqs       = omap2_timer11_mpu_irqs,
1083         .main_clk       = "gpt11_fck",
1084         .prcm           = {
1085                 .omap2 = {
1086                         .prcm_reg_id = 1,
1087                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1088                         .module_offs = CORE_MOD,
1089                         .idlest_reg_id = 1,
1090                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1091                 },
1092         },
1093         .dev_attr       = &capability_pwm_dev_attr,
1094         .slaves         = omap3xxx_timer11_slaves,
1095         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1096         .class          = &omap3xxx_timer_hwmod_class,
1097 };
1098
1099 /* timer12 */
1100 static struct omap_hwmod omap3xxx_timer12_hwmod;
1101 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1102         { .irq = 95, },
1103         { .irq = -1 }
1104 };
1105
1106 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1107         {
1108                 .pa_start       = 0x48304000,
1109                 .pa_end         = 0x48304000 + SZ_1K - 1,
1110                 .flags          = ADDR_TYPE_RT
1111         },
1112         { }
1113 };
1114
1115 /* l4_core -> timer12 */
1116 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1117         .master         = &omap3xxx_l4_core_hwmod,
1118         .slave          = &omap3xxx_timer12_hwmod,
1119         .clk            = "gpt12_ick",
1120         .addr           = omap3xxx_timer12_addrs,
1121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1122 };
1123
1124 /* timer12 slave port */
1125 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1126         &omap3xxx_l4_core__timer12,
1127 };
1128
1129 /* timer12 hwmod */
1130 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1131         .name           = "timer12",
1132         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1133         .main_clk       = "gpt12_fck",
1134         .prcm           = {
1135                 .omap2 = {
1136                         .prcm_reg_id = 1,
1137                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1138                         .module_offs = WKUP_MOD,
1139                         .idlest_reg_id = 1,
1140                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1141                 },
1142         },
1143         .dev_attr       = &capability_secure_dev_attr,
1144         .slaves         = omap3xxx_timer12_slaves,
1145         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1146         .class          = &omap3xxx_timer_hwmod_class,
1147 };
1148
1149 /* l4_wkup -> wd_timer2 */
1150 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1151         {
1152                 .pa_start       = 0x48314000,
1153                 .pa_end         = 0x4831407f,
1154                 .flags          = ADDR_TYPE_RT
1155         },
1156         { }
1157 };
1158
1159 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1160         .master         = &omap3xxx_l4_wkup_hwmod,
1161         .slave          = &omap3xxx_wd_timer2_hwmod,
1162         .clk            = "wdt2_ick",
1163         .addr           = omap3xxx_wd_timer2_addrs,
1164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1165 };
1166
1167 /*
1168  * 'wd_timer' class
1169  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1170  * overflow condition
1171  */
1172
1173 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1174         .rev_offs       = 0x0000,
1175         .sysc_offs      = 0x0010,
1176         .syss_offs      = 0x0014,
1177         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1178                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1179                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1180                            SYSS_HAS_RESET_STATUS),
1181         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1182         .sysc_fields    = &omap_hwmod_sysc_type1,
1183 };
1184
1185 /* I2C common */
1186 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1187         .rev_offs       = 0x00,
1188         .sysc_offs      = 0x20,
1189         .syss_offs      = 0x10,
1190         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1191                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1192                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1193         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1194         .sysc_fields    = &omap_hwmod_sysc_type1,
1195 };
1196
1197 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1198         .name           = "wd_timer",
1199         .sysc           = &omap3xxx_wd_timer_sysc,
1200         .pre_shutdown   = &omap2_wd_timer_disable
1201 };
1202
1203 /* wd_timer2 */
1204 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1205         &omap3xxx_l4_wkup__wd_timer2,
1206 };
1207
1208 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1209         .name           = "wd_timer2",
1210         .class          = &omap3xxx_wd_timer_hwmod_class,
1211         .main_clk       = "wdt2_fck",
1212         .prcm           = {
1213                 .omap2 = {
1214                         .prcm_reg_id = 1,
1215                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1216                         .module_offs = WKUP_MOD,
1217                         .idlest_reg_id = 1,
1218                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1219                 },
1220         },
1221         .slaves         = omap3xxx_wd_timer2_slaves,
1222         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1223         /*
1224          * XXX: Use software supervised mode, HW supervised smartidle seems to
1225          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1226          */
1227         .flags          = HWMOD_SWSUP_SIDLE,
1228 };
1229
1230 /* UART1 */
1231
1232 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1233         &omap3_l4_core__uart1,
1234 };
1235
1236 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1237         .name           = "uart1",
1238         .mpu_irqs       = omap2_uart1_mpu_irqs,
1239         .sdma_reqs      = omap2_uart1_sdma_reqs,
1240         .main_clk       = "uart1_fck",
1241         .prcm           = {
1242                 .omap2 = {
1243                         .module_offs = CORE_MOD,
1244                         .prcm_reg_id = 1,
1245                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1246                         .idlest_reg_id = 1,
1247                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1248                 },
1249         },
1250         .slaves         = omap3xxx_uart1_slaves,
1251         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1252         .class          = &omap2_uart_class,
1253 };
1254
1255 /* UART2 */
1256
1257 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1258         &omap3_l4_core__uart2,
1259 };
1260
1261 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1262         .name           = "uart2",
1263         .mpu_irqs       = omap2_uart2_mpu_irqs,
1264         .sdma_reqs      = omap2_uart2_sdma_reqs,
1265         .main_clk       = "uart2_fck",
1266         .prcm           = {
1267                 .omap2 = {
1268                         .module_offs = CORE_MOD,
1269                         .prcm_reg_id = 1,
1270                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1271                         .idlest_reg_id = 1,
1272                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1273                 },
1274         },
1275         .slaves         = omap3xxx_uart2_slaves,
1276         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1277         .class          = &omap2_uart_class,
1278 };
1279
1280 /* UART3 */
1281
1282 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1283         &omap3_l4_per__uart3,
1284 };
1285
1286 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1287         .name           = "uart3",
1288         .mpu_irqs       = omap2_uart3_mpu_irqs,
1289         .sdma_reqs      = omap2_uart3_sdma_reqs,
1290         .main_clk       = "uart3_fck",
1291         .prcm           = {
1292                 .omap2 = {
1293                         .module_offs = OMAP3430_PER_MOD,
1294                         .prcm_reg_id = 1,
1295                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1296                         .idlest_reg_id = 1,
1297                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1298                 },
1299         },
1300         .slaves         = omap3xxx_uart3_slaves,
1301         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1302         .class          = &omap2_uart_class,
1303 };
1304
1305 /* UART4 */
1306
1307 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1308         { .irq = INT_36XX_UART4_IRQ, },
1309         { .irq = -1 }
1310 };
1311
1312 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1313         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1314         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1315         { .dma_req = -1 }
1316 };
1317
1318 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1319         &omap36xx_l4_per__uart4,
1320 };
1321
1322 static struct omap_hwmod omap36xx_uart4_hwmod = {
1323         .name           = "uart4",
1324         .mpu_irqs       = uart4_mpu_irqs,
1325         .sdma_reqs      = uart4_sdma_reqs,
1326         .main_clk       = "uart4_fck",
1327         .flags          = HWMOD_SWSUP_SIDLE,
1328         .prcm           = {
1329                 .omap2 = {
1330                         .module_offs = OMAP3430_PER_MOD,
1331                         .prcm_reg_id = 1,
1332                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1333                         .idlest_reg_id = 1,
1334                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1335                 },
1336         },
1337         .slaves         = omap3xxx_uart4_slaves,
1338         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1339         .class          = &omap2_uart_class,
1340 };
1341
1342 static struct omap_hwmod_class i2c_class = {
1343         .name   = "i2c",
1344         .sysc   = &i2c_sysc,
1345         .rev    = OMAP_I2C_IP_VERSION_1,
1346         .reset  = &omap_i2c_reset,
1347 };
1348
1349 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1350         { .name = "dispc", .dma_req = 5 },
1351         { .name = "dsi1", .dma_req = 74 },
1352         { .dma_req = -1 }
1353 };
1354
1355 /* dss */
1356 /* dss master ports */
1357 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1358         &omap3xxx_dss__l3,
1359 };
1360
1361 /* l4_core -> dss */
1362 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1363         .master         = &omap3xxx_l4_core_hwmod,
1364         .slave          = &omap3430es1_dss_core_hwmod,
1365         .clk            = "dss_ick",
1366         .addr           = omap2_dss_addrs,
1367         .fw = {
1368                 .omap2 = {
1369                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1370                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1371                         .flags  = OMAP_FIREWALL_L4,
1372                 }
1373         },
1374         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1375 };
1376
1377 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1378         .master         = &omap3xxx_l4_core_hwmod,
1379         .slave          = &omap3xxx_dss_core_hwmod,
1380         .clk            = "dss_ick",
1381         .addr           = omap2_dss_addrs,
1382         .fw = {
1383                 .omap2 = {
1384                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1385                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1386                         .flags  = OMAP_FIREWALL_L4,
1387                 }
1388         },
1389         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1390 };
1391
1392 /* dss slave ports */
1393 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1394         &omap3430es1_l4_core__dss,
1395 };
1396
1397 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1398         &omap3xxx_l4_core__dss,
1399 };
1400
1401 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1402         /*
1403          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1404          * driver does not use these clocks.
1405          */
1406         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1407         { .role = "tv_clk", .clk = "dss_tv_fck" },
1408         /* required only on OMAP3430 */
1409         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1410 };
1411
1412 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1413         .name           = "dss_core",
1414         .class          = &omap2_dss_hwmod_class,
1415         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1416         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1417         .prcm           = {
1418                 .omap2 = {
1419                         .prcm_reg_id = 1,
1420                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1421                         .module_offs = OMAP3430_DSS_MOD,
1422                         .idlest_reg_id = 1,
1423                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1424                 },
1425         },
1426         .opt_clks       = dss_opt_clks,
1427         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1428         .slaves         = omap3430es1_dss_slaves,
1429         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1430         .masters        = omap3xxx_dss_masters,
1431         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1432         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1433 };
1434
1435 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1436         .name           = "dss_core",
1437         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1438         .class          = &omap2_dss_hwmod_class,
1439         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1440         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1441         .prcm           = {
1442                 .omap2 = {
1443                         .prcm_reg_id = 1,
1444                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1445                         .module_offs = OMAP3430_DSS_MOD,
1446                         .idlest_reg_id = 1,
1447                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1448                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1449                 },
1450         },
1451         .opt_clks       = dss_opt_clks,
1452         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1453         .slaves         = omap3xxx_dss_slaves,
1454         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1455         .masters        = omap3xxx_dss_masters,
1456         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1457 };
1458
1459 /*
1460  * 'dispc' class
1461  * display controller
1462  */
1463
1464 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
1465         .rev_offs       = 0x0000,
1466         .sysc_offs      = 0x0010,
1467         .syss_offs      = 0x0014,
1468         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1469                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1470                            SYSC_HAS_ENAWAKEUP),
1471         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1472                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1473         .sysc_fields    = &omap_hwmod_sysc_type1,
1474 };
1475
1476 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1477         .name   = "dispc",
1478         .sysc   = &omap3_dispc_sysc,
1479 };
1480
1481 /* l4_core -> dss_dispc */
1482 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1483         .master         = &omap3xxx_l4_core_hwmod,
1484         .slave          = &omap3xxx_dss_dispc_hwmod,
1485         .clk            = "dss_ick",
1486         .addr           = omap2_dss_dispc_addrs,
1487         .fw = {
1488                 .omap2 = {
1489                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1490                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1491                         .flags  = OMAP_FIREWALL_L4,
1492                 }
1493         },
1494         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1495 };
1496
1497 /* dss_dispc slave ports */
1498 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1499         &omap3xxx_l4_core__dss_dispc,
1500 };
1501
1502 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1503         .name           = "dss_dispc",
1504         .class          = &omap3_dispc_hwmod_class,
1505         .mpu_irqs       = omap2_dispc_irqs,
1506         .main_clk       = "dss1_alwon_fck",
1507         .prcm           = {
1508                 .omap2 = {
1509                         .prcm_reg_id = 1,
1510                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1511                         .module_offs = OMAP3430_DSS_MOD,
1512                 },
1513         },
1514         .slaves         = omap3xxx_dss_dispc_slaves,
1515         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1516         .flags          = HWMOD_NO_IDLEST,
1517         .dev_attr       = &omap2_3_dss_dispc_dev_attr
1518 };
1519
1520 /*
1521  * 'dsi' class
1522  * display serial interface controller
1523  */
1524
1525 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1526         .name = "dsi",
1527 };
1528
1529 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1530         { .irq = 25 },
1531         { .irq = -1 }
1532 };
1533
1534 /* dss_dsi1 */
1535 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1536         {
1537                 .pa_start       = 0x4804FC00,
1538                 .pa_end         = 0x4804FFFF,
1539                 .flags          = ADDR_TYPE_RT
1540         },
1541         { }
1542 };
1543
1544 /* l4_core -> dss_dsi1 */
1545 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1546         .master         = &omap3xxx_l4_core_hwmod,
1547         .slave          = &omap3xxx_dss_dsi1_hwmod,
1548         .clk            = "dss_ick",
1549         .addr           = omap3xxx_dss_dsi1_addrs,
1550         .fw = {
1551                 .omap2 = {
1552                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1553                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1554                         .flags  = OMAP_FIREWALL_L4,
1555                 }
1556         },
1557         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1558 };
1559
1560 /* dss_dsi1 slave ports */
1561 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1562         &omap3xxx_l4_core__dss_dsi1,
1563 };
1564
1565 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1566         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1567 };
1568
1569 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1570         .name           = "dss_dsi1",
1571         .class          = &omap3xxx_dsi_hwmod_class,
1572         .mpu_irqs       = omap3xxx_dsi1_irqs,
1573         .main_clk       = "dss1_alwon_fck",
1574         .prcm           = {
1575                 .omap2 = {
1576                         .prcm_reg_id = 1,
1577                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1578                         .module_offs = OMAP3430_DSS_MOD,
1579                 },
1580         },
1581         .opt_clks       = dss_dsi1_opt_clks,
1582         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1583         .slaves         = omap3xxx_dss_dsi1_slaves,
1584         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1585         .flags          = HWMOD_NO_IDLEST,
1586 };
1587
1588 /* l4_core -> dss_rfbi */
1589 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1590         .master         = &omap3xxx_l4_core_hwmod,
1591         .slave          = &omap3xxx_dss_rfbi_hwmod,
1592         .clk            = "dss_ick",
1593         .addr           = omap2_dss_rfbi_addrs,
1594         .fw = {
1595                 .omap2 = {
1596                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1597                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1598                         .flags  = OMAP_FIREWALL_L4,
1599                 }
1600         },
1601         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1602 };
1603
1604 /* dss_rfbi slave ports */
1605 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1606         &omap3xxx_l4_core__dss_rfbi,
1607 };
1608
1609 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1610         { .role = "ick", .clk = "dss_ick" },
1611 };
1612
1613 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1614         .name           = "dss_rfbi",
1615         .class          = &omap2_rfbi_hwmod_class,
1616         .main_clk       = "dss1_alwon_fck",
1617         .prcm           = {
1618                 .omap2 = {
1619                         .prcm_reg_id = 1,
1620                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1621                         .module_offs = OMAP3430_DSS_MOD,
1622                 },
1623         },
1624         .opt_clks       = dss_rfbi_opt_clks,
1625         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1626         .slaves         = omap3xxx_dss_rfbi_slaves,
1627         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1628         .flags          = HWMOD_NO_IDLEST,
1629 };
1630
1631 /* l4_core -> dss_venc */
1632 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1633         .master         = &omap3xxx_l4_core_hwmod,
1634         .slave          = &omap3xxx_dss_venc_hwmod,
1635         .clk            = "dss_ick",
1636         .addr           = omap2_dss_venc_addrs,
1637         .fw = {
1638                 .omap2 = {
1639                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1640                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1641                         .flags  = OMAP_FIREWALL_L4,
1642                 }
1643         },
1644         .flags          = OCPIF_SWSUP_IDLE,
1645         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1646 };
1647
1648 /* dss_venc slave ports */
1649 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1650         &omap3xxx_l4_core__dss_venc,
1651 };
1652
1653 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1654         /* required only on OMAP3430 */
1655         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1656 };
1657
1658 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1659         .name           = "dss_venc",
1660         .class          = &omap2_venc_hwmod_class,
1661         .main_clk       = "dss_tv_fck",
1662         .prcm           = {
1663                 .omap2 = {
1664                         .prcm_reg_id = 1,
1665                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1666                         .module_offs = OMAP3430_DSS_MOD,
1667                 },
1668         },
1669         .opt_clks       = dss_venc_opt_clks,
1670         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
1671         .slaves         = omap3xxx_dss_venc_slaves,
1672         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1673         .flags          = HWMOD_NO_IDLEST,
1674 };
1675
1676 /* I2C1 */
1677
1678 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1679         .fifo_depth     = 8, /* bytes */
1680         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1681                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1682                           OMAP_I2C_FLAG_BUS_SHIFT_2,
1683 };
1684
1685 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1686         &omap3_l4_core__i2c1,
1687 };
1688
1689 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1690         .name           = "i2c1",
1691         .flags          = HWMOD_16BIT_REG,
1692         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1693         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1694         .main_clk       = "i2c1_fck",
1695         .prcm           = {
1696                 .omap2 = {
1697                         .module_offs = CORE_MOD,
1698                         .prcm_reg_id = 1,
1699                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1700                         .idlest_reg_id = 1,
1701                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1702                 },
1703         },
1704         .slaves         = omap3xxx_i2c1_slaves,
1705         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1706         .class          = &i2c_class,
1707         .dev_attr       = &i2c1_dev_attr,
1708 };
1709
1710 /* I2C2 */
1711
1712 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1713         .fifo_depth     = 8, /* bytes */
1714         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1715                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1716                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1717 };
1718
1719 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1720         &omap3_l4_core__i2c2,
1721 };
1722
1723 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1724         .name           = "i2c2",
1725         .flags          = HWMOD_16BIT_REG,
1726         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1727         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1728         .main_clk       = "i2c2_fck",
1729         .prcm           = {
1730                 .omap2 = {
1731                         .module_offs = CORE_MOD,
1732                         .prcm_reg_id = 1,
1733                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1734                         .idlest_reg_id = 1,
1735                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1736                 },
1737         },
1738         .slaves         = omap3xxx_i2c2_slaves,
1739         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1740         .class          = &i2c_class,
1741         .dev_attr       = &i2c2_dev_attr,
1742 };
1743
1744 /* I2C3 */
1745
1746 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1747         .fifo_depth     = 64, /* bytes */
1748         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1749                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1750                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1751 };
1752
1753 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1754         { .irq = INT_34XX_I2C3_IRQ, },
1755         { .irq = -1 }
1756 };
1757
1758 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1759         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1760         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1761         { .dma_req = -1 }
1762 };
1763
1764 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1765         &omap3_l4_core__i2c3,
1766 };
1767
1768 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1769         .name           = "i2c3",
1770         .flags          = HWMOD_16BIT_REG,
1771         .mpu_irqs       = i2c3_mpu_irqs,
1772         .sdma_reqs      = i2c3_sdma_reqs,
1773         .main_clk       = "i2c3_fck",
1774         .prcm           = {
1775                 .omap2 = {
1776                         .module_offs = CORE_MOD,
1777                         .prcm_reg_id = 1,
1778                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1779                         .idlest_reg_id = 1,
1780                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1781                 },
1782         },
1783         .slaves         = omap3xxx_i2c3_slaves,
1784         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1785         .class          = &i2c_class,
1786         .dev_attr       = &i2c3_dev_attr,
1787 };
1788
1789 /* l4_wkup -> gpio1 */
1790 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1791         {
1792                 .pa_start       = 0x48310000,
1793                 .pa_end         = 0x483101ff,
1794                 .flags          = ADDR_TYPE_RT
1795         },
1796         { }
1797 };
1798
1799 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1800         .master         = &omap3xxx_l4_wkup_hwmod,
1801         .slave          = &omap3xxx_gpio1_hwmod,
1802         .addr           = omap3xxx_gpio1_addrs,
1803         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1804 };
1805
1806 /* l4_per -> gpio2 */
1807 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1808         {
1809                 .pa_start       = 0x49050000,
1810                 .pa_end         = 0x490501ff,
1811                 .flags          = ADDR_TYPE_RT
1812         },
1813         { }
1814 };
1815
1816 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1817         .master         = &omap3xxx_l4_per_hwmod,
1818         .slave          = &omap3xxx_gpio2_hwmod,
1819         .addr           = omap3xxx_gpio2_addrs,
1820         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1821 };
1822
1823 /* l4_per -> gpio3 */
1824 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1825         {
1826                 .pa_start       = 0x49052000,
1827                 .pa_end         = 0x490521ff,
1828                 .flags          = ADDR_TYPE_RT
1829         },
1830         { }
1831 };
1832
1833 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1834         .master         = &omap3xxx_l4_per_hwmod,
1835         .slave          = &omap3xxx_gpio3_hwmod,
1836         .addr           = omap3xxx_gpio3_addrs,
1837         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1838 };
1839
1840 /* l4_per -> gpio4 */
1841 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1842         {
1843                 .pa_start       = 0x49054000,
1844                 .pa_end         = 0x490541ff,
1845                 .flags          = ADDR_TYPE_RT
1846         },
1847         { }
1848 };
1849
1850 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1851         .master         = &omap3xxx_l4_per_hwmod,
1852         .slave          = &omap3xxx_gpio4_hwmod,
1853         .addr           = omap3xxx_gpio4_addrs,
1854         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1855 };
1856
1857 /* l4_per -> gpio5 */
1858 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1859         {
1860                 .pa_start       = 0x49056000,
1861                 .pa_end         = 0x490561ff,
1862                 .flags          = ADDR_TYPE_RT
1863         },
1864         { }
1865 };
1866
1867 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1868         .master         = &omap3xxx_l4_per_hwmod,
1869         .slave          = &omap3xxx_gpio5_hwmod,
1870         .addr           = omap3xxx_gpio5_addrs,
1871         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1872 };
1873
1874 /* l4_per -> gpio6 */
1875 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1876         {
1877                 .pa_start       = 0x49058000,
1878                 .pa_end         = 0x490581ff,
1879                 .flags          = ADDR_TYPE_RT
1880         },
1881         { }
1882 };
1883
1884 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1885         .master         = &omap3xxx_l4_per_hwmod,
1886         .slave          = &omap3xxx_gpio6_hwmod,
1887         .addr           = omap3xxx_gpio6_addrs,
1888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1889 };
1890
1891 /*
1892  * 'gpio' class
1893  * general purpose io module
1894  */
1895
1896 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1897         .rev_offs       = 0x0000,
1898         .sysc_offs      = 0x0010,
1899         .syss_offs      = 0x0014,
1900         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1901                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1902                            SYSS_HAS_RESET_STATUS),
1903         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1904         .sysc_fields    = &omap_hwmod_sysc_type1,
1905 };
1906
1907 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1908         .name = "gpio",
1909         .sysc = &omap3xxx_gpio_sysc,
1910         .rev = 1,
1911 };
1912
1913 /* gpio_dev_attr*/
1914 static struct omap_gpio_dev_attr gpio_dev_attr = {
1915         .bank_width = 32,
1916         .dbck_flag = true,
1917 };
1918
1919 /* gpio1 */
1920 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1921         { .role = "dbclk", .clk = "gpio1_dbck", },
1922 };
1923
1924 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1925         &omap3xxx_l4_wkup__gpio1,
1926 };
1927
1928 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1929         .name           = "gpio1",
1930         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1931         .mpu_irqs       = omap2_gpio1_irqs,
1932         .main_clk       = "gpio1_ick",
1933         .opt_clks       = gpio1_opt_clks,
1934         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1935         .prcm           = {
1936                 .omap2 = {
1937                         .prcm_reg_id = 1,
1938                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1939                         .module_offs = WKUP_MOD,
1940                         .idlest_reg_id = 1,
1941                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1942                 },
1943         },
1944         .slaves         = omap3xxx_gpio1_slaves,
1945         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1946         .class          = &omap3xxx_gpio_hwmod_class,
1947         .dev_attr       = &gpio_dev_attr,
1948 };
1949
1950 /* gpio2 */
1951 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1952         { .role = "dbclk", .clk = "gpio2_dbck", },
1953 };
1954
1955 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1956         &omap3xxx_l4_per__gpio2,
1957 };
1958
1959 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1960         .name           = "gpio2",
1961         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1962         .mpu_irqs       = omap2_gpio2_irqs,
1963         .main_clk       = "gpio2_ick",
1964         .opt_clks       = gpio2_opt_clks,
1965         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1966         .prcm           = {
1967                 .omap2 = {
1968                         .prcm_reg_id = 1,
1969                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1970                         .module_offs = OMAP3430_PER_MOD,
1971                         .idlest_reg_id = 1,
1972                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1973                 },
1974         },
1975         .slaves         = omap3xxx_gpio2_slaves,
1976         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1977         .class          = &omap3xxx_gpio_hwmod_class,
1978         .dev_attr       = &gpio_dev_attr,
1979 };
1980
1981 /* gpio3 */
1982 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1983         { .role = "dbclk", .clk = "gpio3_dbck", },
1984 };
1985
1986 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1987         &omap3xxx_l4_per__gpio3,
1988 };
1989
1990 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1991         .name           = "gpio3",
1992         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1993         .mpu_irqs       = omap2_gpio3_irqs,
1994         .main_clk       = "gpio3_ick",
1995         .opt_clks       = gpio3_opt_clks,
1996         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1997         .prcm           = {
1998                 .omap2 = {
1999                         .prcm_reg_id = 1,
2000                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2001                         .module_offs = OMAP3430_PER_MOD,
2002                         .idlest_reg_id = 1,
2003                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2004                 },
2005         },
2006         .slaves         = omap3xxx_gpio3_slaves,
2007         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2008         .class          = &omap3xxx_gpio_hwmod_class,
2009         .dev_attr       = &gpio_dev_attr,
2010 };
2011
2012 /* gpio4 */
2013 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2014         { .role = "dbclk", .clk = "gpio4_dbck", },
2015 };
2016
2017 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2018         &omap3xxx_l4_per__gpio4,
2019 };
2020
2021 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2022         .name           = "gpio4",
2023         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2024         .mpu_irqs       = omap2_gpio4_irqs,
2025         .main_clk       = "gpio4_ick",
2026         .opt_clks       = gpio4_opt_clks,
2027         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2028         .prcm           = {
2029                 .omap2 = {
2030                         .prcm_reg_id = 1,
2031                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2032                         .module_offs = OMAP3430_PER_MOD,
2033                         .idlest_reg_id = 1,
2034                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2035                 },
2036         },
2037         .slaves         = omap3xxx_gpio4_slaves,
2038         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2039         .class          = &omap3xxx_gpio_hwmod_class,
2040         .dev_attr       = &gpio_dev_attr,
2041 };
2042
2043 /* gpio5 */
2044 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2045         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2046         { .irq = -1 }
2047 };
2048
2049 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2050         { .role = "dbclk", .clk = "gpio5_dbck", },
2051 };
2052
2053 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2054         &omap3xxx_l4_per__gpio5,
2055 };
2056
2057 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2058         .name           = "gpio5",
2059         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2060         .mpu_irqs       = omap3xxx_gpio5_irqs,
2061         .main_clk       = "gpio5_ick",
2062         .opt_clks       = gpio5_opt_clks,
2063         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2064         .prcm           = {
2065                 .omap2 = {
2066                         .prcm_reg_id = 1,
2067                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2068                         .module_offs = OMAP3430_PER_MOD,
2069                         .idlest_reg_id = 1,
2070                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2071                 },
2072         },
2073         .slaves         = omap3xxx_gpio5_slaves,
2074         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2075         .class          = &omap3xxx_gpio_hwmod_class,
2076         .dev_attr       = &gpio_dev_attr,
2077 };
2078
2079 /* gpio6 */
2080 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2081         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2082         { .irq = -1 }
2083 };
2084
2085 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2086         { .role = "dbclk", .clk = "gpio6_dbck", },
2087 };
2088
2089 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2090         &omap3xxx_l4_per__gpio6,
2091 };
2092
2093 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2094         .name           = "gpio6",
2095         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2096         .mpu_irqs       = omap3xxx_gpio6_irqs,
2097         .main_clk       = "gpio6_ick",
2098         .opt_clks       = gpio6_opt_clks,
2099         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2100         .prcm           = {
2101                 .omap2 = {
2102                         .prcm_reg_id = 1,
2103                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2104                         .module_offs = OMAP3430_PER_MOD,
2105                         .idlest_reg_id = 1,
2106                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2107                 },
2108         },
2109         .slaves         = omap3xxx_gpio6_slaves,
2110         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2111         .class          = &omap3xxx_gpio_hwmod_class,
2112         .dev_attr       = &gpio_dev_attr,
2113 };
2114
2115 /* dma_system -> L3 */
2116 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2117         .master         = &omap3xxx_dma_system_hwmod,
2118         .slave          = &omap3xxx_l3_main_hwmod,
2119         .clk            = "core_l3_ick",
2120         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2121 };
2122
2123 /* dma attributes */
2124 static struct omap_dma_dev_attr dma_dev_attr = {
2125         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2126                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2127         .lch_count = 32,
2128 };
2129
2130 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2131         .rev_offs       = 0x0000,
2132         .sysc_offs      = 0x002c,
2133         .syss_offs      = 0x0028,
2134         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2135                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2136                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2137                            SYSS_HAS_RESET_STATUS),
2138         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2139                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2140         .sysc_fields    = &omap_hwmod_sysc_type1,
2141 };
2142
2143 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2144         .name = "dma",
2145         .sysc = &omap3xxx_dma_sysc,
2146 };
2147
2148 /* dma_system */
2149 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2150         {
2151                 .pa_start       = 0x48056000,
2152                 .pa_end         = 0x48056fff,
2153                 .flags          = ADDR_TYPE_RT
2154         },
2155         { }
2156 };
2157
2158 /* dma_system master ports */
2159 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2160         &omap3xxx_dma_system__l3,
2161 };
2162
2163 /* l4_cfg -> dma_system */
2164 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2165         .master         = &omap3xxx_l4_core_hwmod,
2166         .slave          = &omap3xxx_dma_system_hwmod,
2167         .clk            = "core_l4_ick",
2168         .addr           = omap3xxx_dma_system_addrs,
2169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2170 };
2171
2172 /* dma_system slave ports */
2173 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2174         &omap3xxx_l4_core__dma_system,
2175 };
2176
2177 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2178         .name           = "dma",
2179         .class          = &omap3xxx_dma_hwmod_class,
2180         .mpu_irqs       = omap2_dma_system_irqs,
2181         .main_clk       = "core_l3_ick",
2182         .prcm = {
2183                 .omap2 = {
2184                         .module_offs            = CORE_MOD,
2185                         .prcm_reg_id            = 1,
2186                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2187                         .idlest_reg_id          = 1,
2188                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2189                 },
2190         },
2191         .slaves         = omap3xxx_dma_system_slaves,
2192         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2193         .masters        = omap3xxx_dma_system_masters,
2194         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2195         .dev_attr       = &dma_dev_attr,
2196         .flags          = HWMOD_NO_IDLEST,
2197 };
2198
2199 /*
2200  * 'mcbsp' class
2201  * multi channel buffered serial port controller
2202  */
2203
2204 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2205         .sysc_offs      = 0x008c,
2206         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2207                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2208         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2209         .sysc_fields    = &omap_hwmod_sysc_type1,
2210         .clockact       = 0x2,
2211 };
2212
2213 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2214         .name = "mcbsp",
2215         .sysc = &omap3xxx_mcbsp_sysc,
2216         .rev  = MCBSP_CONFIG_TYPE3,
2217 };
2218
2219 /* mcbsp1 */
2220 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2221         { .name = "irq", .irq = 16 },
2222         { .name = "tx", .irq = 59 },
2223         { .name = "rx", .irq = 60 },
2224         { .irq = -1 }
2225 };
2226
2227 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2228         {
2229                 .name           = "mpu",
2230                 .pa_start       = 0x48074000,
2231                 .pa_end         = 0x480740ff,
2232                 .flags          = ADDR_TYPE_RT
2233         },
2234         { }
2235 };
2236
2237 /* l4_core -> mcbsp1 */
2238 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2239         .master         = &omap3xxx_l4_core_hwmod,
2240         .slave          = &omap3xxx_mcbsp1_hwmod,
2241         .clk            = "mcbsp1_ick",
2242         .addr           = omap3xxx_mcbsp1_addrs,
2243         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2244 };
2245
2246 /* mcbsp1 slave ports */
2247 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2248         &omap3xxx_l4_core__mcbsp1,
2249 };
2250
2251 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2252         .name           = "mcbsp1",
2253         .class          = &omap3xxx_mcbsp_hwmod_class,
2254         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2255         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
2256         .main_clk       = "mcbsp1_fck",
2257         .prcm           = {
2258                 .omap2 = {
2259                         .prcm_reg_id = 1,
2260                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2261                         .module_offs = CORE_MOD,
2262                         .idlest_reg_id = 1,
2263                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2264                 },
2265         },
2266         .slaves         = omap3xxx_mcbsp1_slaves,
2267         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2268 };
2269
2270 /* mcbsp2 */
2271 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2272         { .name = "irq", .irq = 17 },
2273         { .name = "tx", .irq = 62 },
2274         { .name = "rx", .irq = 63 },
2275         { .irq = -1 }
2276 };
2277
2278 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2279         {
2280                 .name           = "mpu",
2281                 .pa_start       = 0x49022000,
2282                 .pa_end         = 0x490220ff,
2283                 .flags          = ADDR_TYPE_RT
2284         },
2285         { }
2286 };
2287
2288 /* l4_per -> mcbsp2 */
2289 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2290         .master         = &omap3xxx_l4_per_hwmod,
2291         .slave          = &omap3xxx_mcbsp2_hwmod,
2292         .clk            = "mcbsp2_ick",
2293         .addr           = omap3xxx_mcbsp2_addrs,
2294         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2295 };
2296
2297 /* mcbsp2 slave ports */
2298 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2299         &omap3xxx_l4_per__mcbsp2,
2300 };
2301
2302 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2303         .sidetone       = "mcbsp2_sidetone",
2304 };
2305
2306 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2307         .name           = "mcbsp2",
2308         .class          = &omap3xxx_mcbsp_hwmod_class,
2309         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2310         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
2311         .main_clk       = "mcbsp2_fck",
2312         .prcm           = {
2313                 .omap2 = {
2314                         .prcm_reg_id = 1,
2315                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2316                         .module_offs = OMAP3430_PER_MOD,
2317                         .idlest_reg_id = 1,
2318                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2319                 },
2320         },
2321         .slaves         = omap3xxx_mcbsp2_slaves,
2322         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2323         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2324 };
2325
2326 /* mcbsp3 */
2327 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2328         { .name = "irq", .irq = 22 },
2329         { .name = "tx", .irq = 89 },
2330         { .name = "rx", .irq = 90 },
2331         { .irq = -1 }
2332 };
2333
2334 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2335         {
2336                 .name           = "mpu",
2337                 .pa_start       = 0x49024000,
2338                 .pa_end         = 0x490240ff,
2339                 .flags          = ADDR_TYPE_RT
2340         },
2341         { }
2342 };
2343
2344 /* l4_per -> mcbsp3 */
2345 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2346         .master         = &omap3xxx_l4_per_hwmod,
2347         .slave          = &omap3xxx_mcbsp3_hwmod,
2348         .clk            = "mcbsp3_ick",
2349         .addr           = omap3xxx_mcbsp3_addrs,
2350         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2351 };
2352
2353 /* mcbsp3 slave ports */
2354 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2355         &omap3xxx_l4_per__mcbsp3,
2356 };
2357
2358 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2359         .sidetone       = "mcbsp3_sidetone",
2360 };
2361
2362 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2363         .name           = "mcbsp3",
2364         .class          = &omap3xxx_mcbsp_hwmod_class,
2365         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2366         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
2367         .main_clk       = "mcbsp3_fck",
2368         .prcm           = {
2369                 .omap2 = {
2370                         .prcm_reg_id = 1,
2371                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2372                         .module_offs = OMAP3430_PER_MOD,
2373                         .idlest_reg_id = 1,
2374                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2375                 },
2376         },
2377         .slaves         = omap3xxx_mcbsp3_slaves,
2378         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2379         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2380 };
2381
2382 /* mcbsp4 */
2383 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2384         { .name = "irq", .irq = 23 },
2385         { .name = "tx", .irq = 54 },
2386         { .name = "rx", .irq = 55 },
2387         { .irq = -1 }
2388 };
2389
2390 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2391         { .name = "rx", .dma_req = 20 },
2392         { .name = "tx", .dma_req = 19 },
2393         { .dma_req = -1 }
2394 };
2395
2396 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2397         {
2398                 .name           = "mpu",
2399                 .pa_start       = 0x49026000,
2400                 .pa_end         = 0x490260ff,
2401                 .flags          = ADDR_TYPE_RT
2402         },
2403         { }
2404 };
2405
2406 /* l4_per -> mcbsp4 */
2407 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2408         .master         = &omap3xxx_l4_per_hwmod,
2409         .slave          = &omap3xxx_mcbsp4_hwmod,
2410         .clk            = "mcbsp4_ick",
2411         .addr           = omap3xxx_mcbsp4_addrs,
2412         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2413 };
2414
2415 /* mcbsp4 slave ports */
2416 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2417         &omap3xxx_l4_per__mcbsp4,
2418 };
2419
2420 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2421         .name           = "mcbsp4",
2422         .class          = &omap3xxx_mcbsp_hwmod_class,
2423         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2424         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2425         .main_clk       = "mcbsp4_fck",
2426         .prcm           = {
2427                 .omap2 = {
2428                         .prcm_reg_id = 1,
2429                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2430                         .module_offs = OMAP3430_PER_MOD,
2431                         .idlest_reg_id = 1,
2432                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2433                 },
2434         },
2435         .slaves         = omap3xxx_mcbsp4_slaves,
2436         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2437 };
2438
2439 /* mcbsp5 */
2440 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2441         { .name = "irq", .irq = 27 },
2442         { .name = "tx", .irq = 81 },
2443         { .name = "rx", .irq = 82 },
2444         { .irq = -1 }
2445 };
2446
2447 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2448         { .name = "rx", .dma_req = 22 },
2449         { .name = "tx", .dma_req = 21 },
2450         { .dma_req = -1 }
2451 };
2452
2453 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2454         {
2455                 .name           = "mpu",
2456                 .pa_start       = 0x48096000,
2457                 .pa_end         = 0x480960ff,
2458                 .flags          = ADDR_TYPE_RT
2459         },
2460         { }
2461 };
2462
2463 /* l4_core -> mcbsp5 */
2464 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2465         .master         = &omap3xxx_l4_core_hwmod,
2466         .slave          = &omap3xxx_mcbsp5_hwmod,
2467         .clk            = "mcbsp5_ick",
2468         .addr           = omap3xxx_mcbsp5_addrs,
2469         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2470 };
2471
2472 /* mcbsp5 slave ports */
2473 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2474         &omap3xxx_l4_core__mcbsp5,
2475 };
2476
2477 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2478         .name           = "mcbsp5",
2479         .class          = &omap3xxx_mcbsp_hwmod_class,
2480         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2481         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2482         .main_clk       = "mcbsp5_fck",
2483         .prcm           = {
2484                 .omap2 = {
2485                         .prcm_reg_id = 1,
2486                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2487                         .module_offs = CORE_MOD,
2488                         .idlest_reg_id = 1,
2489                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2490                 },
2491         },
2492         .slaves         = omap3xxx_mcbsp5_slaves,
2493         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2494 };
2495 /* 'mcbsp sidetone' class */
2496
2497 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2498         .sysc_offs      = 0x0010,
2499         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2500         .sysc_fields    = &omap_hwmod_sysc_type1,
2501 };
2502
2503 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2504         .name = "mcbsp_sidetone",
2505         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2506 };
2507
2508 /* mcbsp2_sidetone */
2509 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2510         { .name = "irq", .irq = 4 },
2511         { .irq = -1 }
2512 };
2513
2514 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2515         {
2516                 .name           = "sidetone",
2517                 .pa_start       = 0x49028000,
2518                 .pa_end         = 0x490280ff,
2519                 .flags          = ADDR_TYPE_RT
2520         },
2521         { }
2522 };
2523
2524 /* l4_per -> mcbsp2_sidetone */
2525 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2526         .master         = &omap3xxx_l4_per_hwmod,
2527         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2528         .clk            = "mcbsp2_ick",
2529         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2530         .user           = OCP_USER_MPU,
2531 };
2532
2533 /* mcbsp2_sidetone slave ports */
2534 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2535         &omap3xxx_l4_per__mcbsp2_sidetone,
2536 };
2537
2538 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2539         .name           = "mcbsp2_sidetone",
2540         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2541         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2542         .main_clk       = "mcbsp2_fck",
2543         .prcm           = {
2544                 .omap2 = {
2545                         .prcm_reg_id = 1,
2546                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2547                         .module_offs = OMAP3430_PER_MOD,
2548                         .idlest_reg_id = 1,
2549                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2550                 },
2551         },
2552         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2553         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2554 };
2555
2556 /* mcbsp3_sidetone */
2557 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2558         { .name = "irq", .irq = 5 },
2559         { .irq = -1 }
2560 };
2561
2562 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2563         {
2564                 .name           = "sidetone",
2565                 .pa_start       = 0x4902A000,
2566                 .pa_end         = 0x4902A0ff,
2567                 .flags          = ADDR_TYPE_RT
2568         },
2569         { }
2570 };
2571
2572 /* l4_per -> mcbsp3_sidetone */
2573 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2574         .master         = &omap3xxx_l4_per_hwmod,
2575         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2576         .clk            = "mcbsp3_ick",
2577         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2578         .user           = OCP_USER_MPU,
2579 };
2580
2581 /* mcbsp3_sidetone slave ports */
2582 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2583         &omap3xxx_l4_per__mcbsp3_sidetone,
2584 };
2585
2586 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2587         .name           = "mcbsp3_sidetone",
2588         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2589         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2590         .main_clk       = "mcbsp3_fck",
2591         .prcm           = {
2592                 .omap2 = {
2593                         .prcm_reg_id = 1,
2594                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2595                         .module_offs = OMAP3430_PER_MOD,
2596                         .idlest_reg_id = 1,
2597                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2598                 },
2599         },
2600         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2601         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2602 };
2603
2604
2605 /* SR common */
2606 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2607         .clkact_shift   = 20,
2608 };
2609
2610 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2611         .sysc_offs      = 0x24,
2612         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2613         .clockact       = CLOCKACT_TEST_ICLK,
2614         .sysc_fields    = &omap34xx_sr_sysc_fields,
2615 };
2616
2617 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2618         .name = "smartreflex",
2619         .sysc = &omap34xx_sr_sysc,
2620         .rev  = 1,
2621 };
2622
2623 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2624         .sidle_shift    = 24,
2625         .enwkup_shift   = 26
2626 };
2627
2628 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2629         .sysc_offs      = 0x38,
2630         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2631         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2632                         SYSC_NO_CACHE),
2633         .sysc_fields    = &omap36xx_sr_sysc_fields,
2634 };
2635
2636 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2637         .name = "smartreflex",
2638         .sysc = &omap36xx_sr_sysc,
2639         .rev  = 2,
2640 };
2641
2642 /* SR1 */
2643 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
2644         .sensor_voltdm_name   = "mpu_iva",
2645 };
2646
2647 static struct omap_hwmod_ocp_if *omap34xx_sr1_slaves[] = {
2648         &omap34xx_l4_core__sr1,
2649 };
2650
2651 static struct omap_hwmod omap34xx_sr1_hwmod = {
2652         .name           = "sr1",
2653         .class          = &omap34xx_smartreflex_hwmod_class,
2654         .main_clk       = "sr1_fck",
2655         .prcm           = {
2656                 .omap2 = {
2657                         .prcm_reg_id = 1,
2658                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2659                         .module_offs = WKUP_MOD,
2660                         .idlest_reg_id = 1,
2661                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2662                 },
2663         },
2664         .slaves         = omap34xx_sr1_slaves,
2665         .slaves_cnt     = ARRAY_SIZE(omap34xx_sr1_slaves),
2666         .dev_attr       = &sr1_dev_attr,
2667         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
2668         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2669 };
2670
2671 static struct omap_hwmod_ocp_if *omap36xx_sr1_slaves[] = {
2672         &omap36xx_l4_core__sr1,
2673 };
2674
2675 static struct omap_hwmod omap36xx_sr1_hwmod = {
2676         .name           = "sr1",
2677         .class          = &omap36xx_smartreflex_hwmod_class,
2678         .main_clk       = "sr1_fck",
2679         .prcm           = {
2680                 .omap2 = {
2681                         .prcm_reg_id = 1,
2682                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2683                         .module_offs = WKUP_MOD,
2684                         .idlest_reg_id = 1,
2685                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2686                 },
2687         },
2688         .slaves         = omap36xx_sr1_slaves,
2689         .slaves_cnt     = ARRAY_SIZE(omap36xx_sr1_slaves),
2690         .dev_attr       = &sr1_dev_attr,
2691         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
2692 };
2693
2694 /* SR2 */
2695 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
2696         .sensor_voltdm_name     = "core",
2697 };
2698
2699 static struct omap_hwmod_ocp_if *omap34xx_sr2_slaves[] = {
2700         &omap34xx_l4_core__sr2,
2701 };
2702
2703 static struct omap_hwmod omap34xx_sr2_hwmod = {
2704         .name           = "sr2",
2705         .class          = &omap34xx_smartreflex_hwmod_class,
2706         .main_clk       = "sr2_fck",
2707         .prcm           = {
2708                 .omap2 = {
2709                         .prcm_reg_id = 1,
2710                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2711                         .module_offs = WKUP_MOD,
2712                         .idlest_reg_id = 1,
2713                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2714                 },
2715         },
2716         .slaves         = omap34xx_sr2_slaves,
2717         .slaves_cnt     = ARRAY_SIZE(omap34xx_sr2_slaves),
2718         .dev_attr       = &sr2_dev_attr,
2719         .mpu_irqs       = omap3_smartreflex_core_irqs,
2720         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2721 };
2722
2723 static struct omap_hwmod_ocp_if *omap36xx_sr2_slaves[] = {
2724         &omap36xx_l4_core__sr2,
2725 };
2726
2727 static struct omap_hwmod omap36xx_sr2_hwmod = {
2728         .name           = "sr2",
2729         .class          = &omap36xx_smartreflex_hwmod_class,
2730         .main_clk       = "sr2_fck",
2731         .prcm           = {
2732                 .omap2 = {
2733                         .prcm_reg_id = 1,
2734                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2735                         .module_offs = WKUP_MOD,
2736                         .idlest_reg_id = 1,
2737                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2738                 },
2739         },
2740         .slaves         = omap36xx_sr2_slaves,
2741         .slaves_cnt     = ARRAY_SIZE(omap36xx_sr2_slaves),
2742         .dev_attr       = &sr2_dev_attr,
2743         .mpu_irqs       = omap3_smartreflex_core_irqs,
2744 };
2745
2746 /*
2747  * 'mailbox' class
2748  * mailbox module allowing communication between the on-chip processors
2749  * using a queued mailbox-interrupt mechanism.
2750  */
2751
2752 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2753         .rev_offs       = 0x000,
2754         .sysc_offs      = 0x010,
2755         .syss_offs      = 0x014,
2756         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2757                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2758         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2759         .sysc_fields    = &omap_hwmod_sysc_type1,
2760 };
2761
2762 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2763         .name = "mailbox",
2764         .sysc = &omap3xxx_mailbox_sysc,
2765 };
2766
2767 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2768 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2769         { .irq = 26 },
2770         { .irq = -1 }
2771 };
2772
2773 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2774         {
2775                 .pa_start       = 0x48094000,
2776                 .pa_end         = 0x480941ff,
2777                 .flags          = ADDR_TYPE_RT,
2778         },
2779         { }
2780 };
2781
2782 /* l4_core -> mailbox */
2783 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2784         .master         = &omap3xxx_l4_core_hwmod,
2785         .slave          = &omap3xxx_mailbox_hwmod,
2786         .addr           = omap3xxx_mailbox_addrs,
2787         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2788 };
2789
2790 /* mailbox slave ports */
2791 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2792         &omap3xxx_l4_core__mailbox,
2793 };
2794
2795 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2796         .name           = "mailbox",
2797         .class          = &omap3xxx_mailbox_hwmod_class,
2798         .mpu_irqs       = omap3xxx_mailbox_irqs,
2799         .main_clk       = "mailboxes_ick",
2800         .prcm           = {
2801                 .omap2 = {
2802                         .prcm_reg_id = 1,
2803                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2804                         .module_offs = CORE_MOD,
2805                         .idlest_reg_id = 1,
2806                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2807                 },
2808         },
2809         .slaves         = omap3xxx_mailbox_slaves,
2810         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2811 };
2812
2813 /* l4 core -> mcspi1 interface */
2814 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2815         .master         = &omap3xxx_l4_core_hwmod,
2816         .slave          = &omap34xx_mcspi1,
2817         .clk            = "mcspi1_ick",
2818         .addr           = omap2_mcspi1_addr_space,
2819         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2820 };
2821
2822 /* l4 core -> mcspi2 interface */
2823 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2824         .master         = &omap3xxx_l4_core_hwmod,
2825         .slave          = &omap34xx_mcspi2,
2826         .clk            = "mcspi2_ick",
2827         .addr           = omap2_mcspi2_addr_space,
2828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2829 };
2830
2831 /* l4 core -> mcspi3 interface */
2832 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2833         .master         = &omap3xxx_l4_core_hwmod,
2834         .slave          = &omap34xx_mcspi3,
2835         .clk            = "mcspi3_ick",
2836         .addr           = omap2430_mcspi3_addr_space,
2837         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2838 };
2839
2840 /* l4 core -> mcspi4 interface */
2841 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2842         {
2843                 .pa_start       = 0x480ba000,
2844                 .pa_end         = 0x480ba0ff,
2845                 .flags          = ADDR_TYPE_RT,
2846         },
2847         { }
2848 };
2849
2850 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2851         .master         = &omap3xxx_l4_core_hwmod,
2852         .slave          = &omap34xx_mcspi4,
2853         .clk            = "mcspi4_ick",
2854         .addr           = omap34xx_mcspi4_addr_space,
2855         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2856 };
2857
2858 /*
2859  * 'mcspi' class
2860  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2861  * bus
2862  */
2863
2864 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2865         .rev_offs       = 0x0000,
2866         .sysc_offs      = 0x0010,
2867         .syss_offs      = 0x0014,
2868         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2869                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2870                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2871         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2872         .sysc_fields    = &omap_hwmod_sysc_type1,
2873 };
2874
2875 static struct omap_hwmod_class omap34xx_mcspi_class = {
2876         .name = "mcspi",
2877         .sysc = &omap34xx_mcspi_sysc,
2878         .rev = OMAP3_MCSPI_REV,
2879 };
2880
2881 /* mcspi1 */
2882 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2883         &omap34xx_l4_core__mcspi1,
2884 };
2885
2886 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2887         .num_chipselect = 4,
2888 };
2889
2890 static struct omap_hwmod omap34xx_mcspi1 = {
2891         .name           = "mcspi1",
2892         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
2893         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
2894         .main_clk       = "mcspi1_fck",
2895         .prcm           = {
2896                 .omap2 = {
2897                         .module_offs = CORE_MOD,
2898                         .prcm_reg_id = 1,
2899                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2900                         .idlest_reg_id = 1,
2901                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2902                 },
2903         },
2904         .slaves         = omap34xx_mcspi1_slaves,
2905         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2906         .class          = &omap34xx_mcspi_class,
2907         .dev_attr       = &omap_mcspi1_dev_attr,
2908 };
2909
2910 /* mcspi2 */
2911 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2912         &omap34xx_l4_core__mcspi2,
2913 };
2914
2915 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2916         .num_chipselect = 2,
2917 };
2918
2919 static struct omap_hwmod omap34xx_mcspi2 = {
2920         .name           = "mcspi2",
2921         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
2922         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
2923         .main_clk       = "mcspi2_fck",
2924         .prcm           = {
2925                 .omap2 = {
2926                         .module_offs = CORE_MOD,
2927                         .prcm_reg_id = 1,
2928                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2929                         .idlest_reg_id = 1,
2930                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2931                 },
2932         },
2933         .slaves         = omap34xx_mcspi2_slaves,
2934         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2935         .class          = &omap34xx_mcspi_class,
2936         .dev_attr       = &omap_mcspi2_dev_attr,
2937 };
2938
2939 /* mcspi3 */
2940 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2941         { .name = "irq", .irq = 91 }, /* 91 */
2942         { .irq = -1 }
2943 };
2944
2945 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2946         { .name = "tx0", .dma_req = 15 },
2947         { .name = "rx0", .dma_req = 16 },
2948         { .name = "tx1", .dma_req = 23 },
2949         { .name = "rx1", .dma_req = 24 },
2950         { .dma_req = -1 }
2951 };
2952
2953 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2954         &omap34xx_l4_core__mcspi3,
2955 };
2956
2957 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2958         .num_chipselect = 2,
2959 };
2960
2961 static struct omap_hwmod omap34xx_mcspi3 = {
2962         .name           = "mcspi3",
2963         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
2964         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
2965         .main_clk       = "mcspi3_fck",
2966         .prcm           = {
2967                 .omap2 = {
2968                         .module_offs = CORE_MOD,
2969                         .prcm_reg_id = 1,
2970                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2971                         .idlest_reg_id = 1,
2972                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2973                 },
2974         },
2975         .slaves         = omap34xx_mcspi3_slaves,
2976         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2977         .class          = &omap34xx_mcspi_class,
2978         .dev_attr       = &omap_mcspi3_dev_attr,
2979 };
2980
2981 /* SPI4 */
2982 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2983         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2984         { .irq = -1 }
2985 };
2986
2987 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2988         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2989         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2990         { .dma_req = -1 }
2991 };
2992
2993 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2994         &omap34xx_l4_core__mcspi4,
2995 };
2996
2997 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2998         .num_chipselect = 1,
2999 };
3000
3001 static struct omap_hwmod omap34xx_mcspi4 = {
3002         .name           = "mcspi4",
3003         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
3004         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
3005         .main_clk       = "mcspi4_fck",
3006         .prcm           = {
3007                 .omap2 = {
3008                         .module_offs = CORE_MOD,
3009                         .prcm_reg_id = 1,
3010                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3011                         .idlest_reg_id = 1,
3012                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3013                 },