2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2011 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
14 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
24 #include <plat/gpio.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod_common_data.h"
32 #include "smartreflex.h"
33 #include "prm-regbits-34xx.h"
34 #include "cm-regbits-34xx.h"
36 #include <mach/am35xx.h>
39 * OMAP3xxx hardware module integration data
41 * ALl of the data in this section should be autogeneratable from the
42 * TI hardware database or other technical documentation. Data that
43 * is driver-specific or driver-kernel integration-specific belongs
47 static struct omap_hwmod omap3xxx_mpu_hwmod;
48 static struct omap_hwmod omap3xxx_iva_hwmod;
49 static struct omap_hwmod omap3xxx_l3_main_hwmod;
50 static struct omap_hwmod omap3xxx_l4_core_hwmod;
51 static struct omap_hwmod omap3xxx_l4_per_hwmod;
52 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
53 static struct omap_hwmod omap3430es1_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_core_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
56 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
57 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
58 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
59 static struct omap_hwmod omap3xxx_i2c1_hwmod;
60 static struct omap_hwmod omap3xxx_i2c2_hwmod;
61 static struct omap_hwmod omap3xxx_i2c3_hwmod;
62 static struct omap_hwmod omap3xxx_gpio1_hwmod;
63 static struct omap_hwmod omap3xxx_gpio2_hwmod;
64 static struct omap_hwmod omap3xxx_gpio3_hwmod;
65 static struct omap_hwmod omap3xxx_gpio4_hwmod;
66 static struct omap_hwmod omap3xxx_gpio5_hwmod;
67 static struct omap_hwmod omap3xxx_gpio6_hwmod;
68 static struct omap_hwmod omap34xx_sr1_hwmod;
69 static struct omap_hwmod omap36xx_sr1_hwmod;
70 static struct omap_hwmod omap34xx_sr2_hwmod;
71 static struct omap_hwmod omap36xx_sr2_hwmod;
72 static struct omap_hwmod omap34xx_mcspi1;
73 static struct omap_hwmod omap34xx_mcspi2;
74 static struct omap_hwmod omap34xx_mcspi3;
75 static struct omap_hwmod omap34xx_mcspi4;
76 static struct omap_hwmod omap3xxx_mmc1_hwmod;
77 static struct omap_hwmod omap3xxx_mmc2_hwmod;
78 static struct omap_hwmod omap3xxx_mmc3_hwmod;
79 static struct omap_hwmod am35xx_usbhsotg_hwmod;
81 static struct omap_hwmod omap3xxx_dma_system_hwmod;
83 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
87 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
88 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
89 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
91 /* L3 -> L4_CORE interface */
92 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
93 .master = &omap3xxx_l3_main_hwmod,
94 .slave = &omap3xxx_l4_core_hwmod,
95 .user = OCP_USER_MPU | OCP_USER_SDMA,
98 /* L3 -> L4_PER interface */
99 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
100 .master = &omap3xxx_l3_main_hwmod,
101 .slave = &omap3xxx_l4_per_hwmod,
102 .user = OCP_USER_MPU | OCP_USER_SDMA,
105 /* L3 taret configuration and error log registers */
106 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
107 { .irq = INT_34XX_L3_DBG_IRQ },
108 { .irq = INT_34XX_L3_APP_IRQ },
112 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
114 .pa_start = 0x68000000,
115 .pa_end = 0x6800ffff,
116 .flags = ADDR_TYPE_RT,
121 /* MPU -> L3 interface */
122 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
123 .master = &omap3xxx_mpu_hwmod,
124 .slave = &omap3xxx_l3_main_hwmod,
125 .addr = omap3xxx_l3_main_addrs,
126 .user = OCP_USER_MPU,
129 /* Slave interfaces on the L3 interconnect */
130 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
131 &omap3xxx_mpu__l3_main,
135 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
136 .master = &omap3xxx_dss_core_hwmod,
137 .slave = &omap3xxx_l3_main_hwmod,
140 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
141 .flags = OMAP_FIREWALL_L3,
144 .user = OCP_USER_MPU | OCP_USER_SDMA,
147 /* Master interfaces on the L3 interconnect */
148 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
149 &omap3xxx_l3_main__l4_core,
150 &omap3xxx_l3_main__l4_per,
154 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
156 .class = &l3_hwmod_class,
157 .mpu_irqs = omap3xxx_l3_main_irqs,
158 .masters = omap3xxx_l3_main_masters,
159 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
160 .slaves = omap3xxx_l3_main_slaves,
161 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
162 .flags = HWMOD_NO_IDLEST,
165 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
166 static struct omap_hwmod omap3xxx_uart1_hwmod;
167 static struct omap_hwmod omap3xxx_uart2_hwmod;
168 static struct omap_hwmod omap3xxx_uart3_hwmod;
169 static struct omap_hwmod omap36xx_uart4_hwmod;
170 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
172 /* l3_core -> usbhsotg interface */
173 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
174 .master = &omap3xxx_usbhsotg_hwmod,
175 .slave = &omap3xxx_l3_main_hwmod,
176 .clk = "core_l3_ick",
177 .user = OCP_USER_MPU,
180 /* l3_core -> am35xx_usbhsotg interface */
181 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
182 .master = &am35xx_usbhsotg_hwmod,
183 .slave = &omap3xxx_l3_main_hwmod,
184 .clk = "core_l3_ick",
185 .user = OCP_USER_MPU,
187 /* L4_CORE -> L4_WKUP interface */
188 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
189 .master = &omap3xxx_l4_core_hwmod,
190 .slave = &omap3xxx_l4_wkup_hwmod,
191 .user = OCP_USER_MPU | OCP_USER_SDMA,
194 /* L4 CORE -> MMC1 interface */
195 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
196 .master = &omap3xxx_l4_core_hwmod,
197 .slave = &omap3xxx_mmc1_hwmod,
199 .addr = omap2430_mmc1_addr_space,
200 .user = OCP_USER_MPU | OCP_USER_SDMA,
201 .flags = OMAP_FIREWALL_L4
204 /* L4 CORE -> MMC2 interface */
205 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
206 .master = &omap3xxx_l4_core_hwmod,
207 .slave = &omap3xxx_mmc2_hwmod,
209 .addr = omap2430_mmc2_addr_space,
210 .user = OCP_USER_MPU | OCP_USER_SDMA,
211 .flags = OMAP_FIREWALL_L4
214 /* L4 CORE -> MMC3 interface */
215 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
217 .pa_start = 0x480ad000,
218 .pa_end = 0x480ad1ff,
219 .flags = ADDR_TYPE_RT,
224 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
225 .master = &omap3xxx_l4_core_hwmod,
226 .slave = &omap3xxx_mmc3_hwmod,
228 .addr = omap3xxx_mmc3_addr_space,
229 .user = OCP_USER_MPU | OCP_USER_SDMA,
230 .flags = OMAP_FIREWALL_L4
233 /* L4 CORE -> UART1 interface */
234 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
236 .pa_start = OMAP3_UART1_BASE,
237 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
238 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
243 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
244 .master = &omap3xxx_l4_core_hwmod,
245 .slave = &omap3xxx_uart1_hwmod,
247 .addr = omap3xxx_uart1_addr_space,
248 .user = OCP_USER_MPU | OCP_USER_SDMA,
251 /* L4 CORE -> UART2 interface */
252 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
254 .pa_start = OMAP3_UART2_BASE,
255 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
256 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
261 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
262 .master = &omap3xxx_l4_core_hwmod,
263 .slave = &omap3xxx_uart2_hwmod,
265 .addr = omap3xxx_uart2_addr_space,
266 .user = OCP_USER_MPU | OCP_USER_SDMA,
269 /* L4 PER -> UART3 interface */
270 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
272 .pa_start = OMAP3_UART3_BASE,
273 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
274 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
279 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
280 .master = &omap3xxx_l4_per_hwmod,
281 .slave = &omap3xxx_uart3_hwmod,
283 .addr = omap3xxx_uart3_addr_space,
284 .user = OCP_USER_MPU | OCP_USER_SDMA,
287 /* L4 PER -> UART4 interface */
288 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
290 .pa_start = OMAP3_UART4_BASE,
291 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
292 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
297 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
298 .master = &omap3xxx_l4_per_hwmod,
299 .slave = &omap36xx_uart4_hwmod,
301 .addr = omap36xx_uart4_addr_space,
302 .user = OCP_USER_MPU | OCP_USER_SDMA,
305 /* L4 CORE -> I2C1 interface */
306 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
307 .master = &omap3xxx_l4_core_hwmod,
308 .slave = &omap3xxx_i2c1_hwmod,
310 .addr = omap2_i2c1_addr_space,
313 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
315 .flags = OMAP_FIREWALL_L4,
318 .user = OCP_USER_MPU | OCP_USER_SDMA,
321 /* L4 CORE -> I2C2 interface */
322 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
323 .master = &omap3xxx_l4_core_hwmod,
324 .slave = &omap3xxx_i2c2_hwmod,
326 .addr = omap2_i2c2_addr_space,
329 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
331 .flags = OMAP_FIREWALL_L4,
334 .user = OCP_USER_MPU | OCP_USER_SDMA,
337 /* L4 CORE -> I2C3 interface */
338 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
340 .pa_start = 0x48060000,
341 .pa_end = 0x48060000 + SZ_128 - 1,
342 .flags = ADDR_TYPE_RT,
347 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
348 .master = &omap3xxx_l4_core_hwmod,
349 .slave = &omap3xxx_i2c3_hwmod,
351 .addr = omap3xxx_i2c3_addr_space,
354 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
356 .flags = OMAP_FIREWALL_L4,
359 .user = OCP_USER_MPU | OCP_USER_SDMA,
362 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
367 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
372 /* L4 CORE -> SR1 interface */
373 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
375 .pa_start = OMAP34XX_SR1_BASE,
376 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
377 .flags = ADDR_TYPE_RT,
382 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
383 .master = &omap3xxx_l4_core_hwmod,
384 .slave = &omap34xx_sr1_hwmod,
386 .addr = omap3_sr1_addr_space,
387 .user = OCP_USER_MPU,
390 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
391 .master = &omap3xxx_l4_core_hwmod,
392 .slave = &omap36xx_sr1_hwmod,
394 .addr = omap3_sr1_addr_space,
395 .user = OCP_USER_MPU,
398 /* L4 CORE -> SR1 interface */
399 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
401 .pa_start = OMAP34XX_SR2_BASE,
402 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
403 .flags = ADDR_TYPE_RT,
408 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
409 .master = &omap3xxx_l4_core_hwmod,
410 .slave = &omap34xx_sr2_hwmod,
412 .addr = omap3_sr2_addr_space,
413 .user = OCP_USER_MPU,
416 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
417 .master = &omap3xxx_l4_core_hwmod,
418 .slave = &omap36xx_sr2_hwmod,
420 .addr = omap3_sr2_addr_space,
421 .user = OCP_USER_MPU,
425 * usbhsotg interface data
428 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
430 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
431 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
432 .flags = ADDR_TYPE_RT
437 /* l4_core -> usbhsotg */
438 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
439 .master = &omap3xxx_l4_core_hwmod,
440 .slave = &omap3xxx_usbhsotg_hwmod,
442 .addr = omap3xxx_usbhsotg_addrs,
443 .user = OCP_USER_MPU,
446 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
447 &omap3xxx_usbhsotg__l3,
450 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
451 &omap3xxx_l4_core__usbhsotg,
454 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
456 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
457 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
458 .flags = ADDR_TYPE_RT
463 /* l4_core -> usbhsotg */
464 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
465 .master = &omap3xxx_l4_core_hwmod,
466 .slave = &am35xx_usbhsotg_hwmod,
468 .addr = am35xx_usbhsotg_addrs,
469 .user = OCP_USER_MPU,
472 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
473 &am35xx_usbhsotg__l3,
476 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
477 &am35xx_l4_core__usbhsotg,
479 /* Slave interfaces on the L4_CORE interconnect */
480 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
481 &omap3xxx_l3_main__l4_core,
485 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
487 .class = &l4_hwmod_class,
488 .slaves = omap3xxx_l4_core_slaves,
489 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
490 .flags = HWMOD_NO_IDLEST,
493 /* Slave interfaces on the L4_PER interconnect */
494 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
495 &omap3xxx_l3_main__l4_per,
499 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
501 .class = &l4_hwmod_class,
502 .slaves = omap3xxx_l4_per_slaves,
503 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
504 .flags = HWMOD_NO_IDLEST,
507 /* Slave interfaces on the L4_WKUP interconnect */
508 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
509 &omap3xxx_l4_core__l4_wkup,
513 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
515 .class = &l4_hwmod_class,
516 .slaves = omap3xxx_l4_wkup_slaves,
517 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
518 .flags = HWMOD_NO_IDLEST,
521 /* Master interfaces on the MPU device */
522 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
523 &omap3xxx_mpu__l3_main,
527 static struct omap_hwmod omap3xxx_mpu_hwmod = {
529 .class = &mpu_hwmod_class,
530 .main_clk = "arm_fck",
531 .masters = omap3xxx_mpu_masters,
532 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
536 * IVA2_2 interface data
539 /* IVA2 <- L3 interface */
540 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
541 .master = &omap3xxx_l3_main_hwmod,
542 .slave = &omap3xxx_iva_hwmod,
544 .user = OCP_USER_MPU | OCP_USER_SDMA,
547 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
555 static struct omap_hwmod omap3xxx_iva_hwmod = {
557 .class = &iva_hwmod_class,
558 .masters = omap3xxx_iva_masters,
559 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
563 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
567 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
568 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
569 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
570 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
571 .sysc_fields = &omap_hwmod_sysc_type1,
574 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
576 .sysc = &omap3xxx_timer_1ms_sysc,
577 .rev = OMAP_TIMER_IP_VERSION_1,
580 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
584 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
585 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
586 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
587 .sysc_fields = &omap_hwmod_sysc_type1,
590 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
592 .sysc = &omap3xxx_timer_sysc,
593 .rev = OMAP_TIMER_IP_VERSION_1,
596 /* secure timers dev attribute */
597 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
598 .timer_capability = OMAP_TIMER_SECURE,
601 /* always-on timers dev attribute */
602 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
603 .timer_capability = OMAP_TIMER_ALWON,
606 /* pwm timers dev attribute */
607 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
608 .timer_capability = OMAP_TIMER_HAS_PWM,
612 static struct omap_hwmod omap3xxx_timer1_hwmod;
614 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
616 .pa_start = 0x48318000,
617 .pa_end = 0x48318000 + SZ_1K - 1,
618 .flags = ADDR_TYPE_RT
623 /* l4_wkup -> timer1 */
624 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
625 .master = &omap3xxx_l4_wkup_hwmod,
626 .slave = &omap3xxx_timer1_hwmod,
628 .addr = omap3xxx_timer1_addrs,
629 .user = OCP_USER_MPU | OCP_USER_SDMA,
632 /* timer1 slave port */
633 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
634 &omap3xxx_l4_wkup__timer1,
638 static struct omap_hwmod omap3xxx_timer1_hwmod = {
640 .mpu_irqs = omap2_timer1_mpu_irqs,
641 .main_clk = "gpt1_fck",
645 .module_bit = OMAP3430_EN_GPT1_SHIFT,
646 .module_offs = WKUP_MOD,
648 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
651 .dev_attr = &capability_alwon_dev_attr,
652 .slaves = omap3xxx_timer1_slaves,
653 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
654 .class = &omap3xxx_timer_1ms_hwmod_class,
658 static struct omap_hwmod omap3xxx_timer2_hwmod;
660 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
662 .pa_start = 0x49032000,
663 .pa_end = 0x49032000 + SZ_1K - 1,
664 .flags = ADDR_TYPE_RT
669 /* l4_per -> timer2 */
670 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
671 .master = &omap3xxx_l4_per_hwmod,
672 .slave = &omap3xxx_timer2_hwmod,
674 .addr = omap3xxx_timer2_addrs,
675 .user = OCP_USER_MPU | OCP_USER_SDMA,
678 /* timer2 slave port */
679 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
680 &omap3xxx_l4_per__timer2,
684 static struct omap_hwmod omap3xxx_timer2_hwmod = {
686 .mpu_irqs = omap2_timer2_mpu_irqs,
687 .main_clk = "gpt2_fck",
691 .module_bit = OMAP3430_EN_GPT2_SHIFT,
692 .module_offs = OMAP3430_PER_MOD,
694 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
697 .dev_attr = &capability_alwon_dev_attr,
698 .slaves = omap3xxx_timer2_slaves,
699 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
700 .class = &omap3xxx_timer_1ms_hwmod_class,
704 static struct omap_hwmod omap3xxx_timer3_hwmod;
706 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
708 .pa_start = 0x49034000,
709 .pa_end = 0x49034000 + SZ_1K - 1,
710 .flags = ADDR_TYPE_RT
715 /* l4_per -> timer3 */
716 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
717 .master = &omap3xxx_l4_per_hwmod,
718 .slave = &omap3xxx_timer3_hwmod,
720 .addr = omap3xxx_timer3_addrs,
721 .user = OCP_USER_MPU | OCP_USER_SDMA,
724 /* timer3 slave port */
725 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
726 &omap3xxx_l4_per__timer3,
730 static struct omap_hwmod omap3xxx_timer3_hwmod = {
732 .mpu_irqs = omap2_timer3_mpu_irqs,
733 .main_clk = "gpt3_fck",
737 .module_bit = OMAP3430_EN_GPT3_SHIFT,
738 .module_offs = OMAP3430_PER_MOD,
740 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
743 .dev_attr = &capability_alwon_dev_attr,
744 .slaves = omap3xxx_timer3_slaves,
745 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
746 .class = &omap3xxx_timer_hwmod_class,
750 static struct omap_hwmod omap3xxx_timer4_hwmod;
752 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
754 .pa_start = 0x49036000,
755 .pa_end = 0x49036000 + SZ_1K - 1,
756 .flags = ADDR_TYPE_RT
761 /* l4_per -> timer4 */
762 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
763 .master = &omap3xxx_l4_per_hwmod,
764 .slave = &omap3xxx_timer4_hwmod,
766 .addr = omap3xxx_timer4_addrs,
767 .user = OCP_USER_MPU | OCP_USER_SDMA,
770 /* timer4 slave port */
771 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
772 &omap3xxx_l4_per__timer4,
776 static struct omap_hwmod omap3xxx_timer4_hwmod = {
778 .mpu_irqs = omap2_timer4_mpu_irqs,
779 .main_clk = "gpt4_fck",
783 .module_bit = OMAP3430_EN_GPT4_SHIFT,
784 .module_offs = OMAP3430_PER_MOD,
786 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
789 .dev_attr = &capability_alwon_dev_attr,
790 .slaves = omap3xxx_timer4_slaves,
791 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
792 .class = &omap3xxx_timer_hwmod_class,
796 static struct omap_hwmod omap3xxx_timer5_hwmod;
798 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
800 .pa_start = 0x49038000,
801 .pa_end = 0x49038000 + SZ_1K - 1,
802 .flags = ADDR_TYPE_RT
807 /* l4_per -> timer5 */
808 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
809 .master = &omap3xxx_l4_per_hwmod,
810 .slave = &omap3xxx_timer5_hwmod,
812 .addr = omap3xxx_timer5_addrs,
813 .user = OCP_USER_MPU | OCP_USER_SDMA,
816 /* timer5 slave port */
817 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
818 &omap3xxx_l4_per__timer5,
822 static struct omap_hwmod omap3xxx_timer5_hwmod = {
824 .mpu_irqs = omap2_timer5_mpu_irqs,
825 .main_clk = "gpt5_fck",
829 .module_bit = OMAP3430_EN_GPT5_SHIFT,
830 .module_offs = OMAP3430_PER_MOD,
832 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
835 .dev_attr = &capability_alwon_dev_attr,
836 .slaves = omap3xxx_timer5_slaves,
837 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
838 .class = &omap3xxx_timer_hwmod_class,
842 static struct omap_hwmod omap3xxx_timer6_hwmod;
844 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
846 .pa_start = 0x4903A000,
847 .pa_end = 0x4903A000 + SZ_1K - 1,
848 .flags = ADDR_TYPE_RT
853 /* l4_per -> timer6 */
854 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
855 .master = &omap3xxx_l4_per_hwmod,
856 .slave = &omap3xxx_timer6_hwmod,
858 .addr = omap3xxx_timer6_addrs,
859 .user = OCP_USER_MPU | OCP_USER_SDMA,
862 /* timer6 slave port */
863 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
864 &omap3xxx_l4_per__timer6,
868 static struct omap_hwmod omap3xxx_timer6_hwmod = {
870 .mpu_irqs = omap2_timer6_mpu_irqs,
871 .main_clk = "gpt6_fck",
875 .module_bit = OMAP3430_EN_GPT6_SHIFT,
876 .module_offs = OMAP3430_PER_MOD,
878 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
881 .dev_attr = &capability_alwon_dev_attr,
882 .slaves = omap3xxx_timer6_slaves,
883 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
884 .class = &omap3xxx_timer_hwmod_class,
888 static struct omap_hwmod omap3xxx_timer7_hwmod;
890 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
892 .pa_start = 0x4903C000,
893 .pa_end = 0x4903C000 + SZ_1K - 1,
894 .flags = ADDR_TYPE_RT
899 /* l4_per -> timer7 */
900 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
901 .master = &omap3xxx_l4_per_hwmod,
902 .slave = &omap3xxx_timer7_hwmod,
904 .addr = omap3xxx_timer7_addrs,
905 .user = OCP_USER_MPU | OCP_USER_SDMA,
908 /* timer7 slave port */
909 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
910 &omap3xxx_l4_per__timer7,
914 static struct omap_hwmod omap3xxx_timer7_hwmod = {
916 .mpu_irqs = omap2_timer7_mpu_irqs,
917 .main_clk = "gpt7_fck",
921 .module_bit = OMAP3430_EN_GPT7_SHIFT,
922 .module_offs = OMAP3430_PER_MOD,
924 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
927 .dev_attr = &capability_alwon_dev_attr,
928 .slaves = omap3xxx_timer7_slaves,
929 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
930 .class = &omap3xxx_timer_hwmod_class,
934 static struct omap_hwmod omap3xxx_timer8_hwmod;
936 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
938 .pa_start = 0x4903E000,
939 .pa_end = 0x4903E000 + SZ_1K - 1,
940 .flags = ADDR_TYPE_RT
945 /* l4_per -> timer8 */
946 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
947 .master = &omap3xxx_l4_per_hwmod,
948 .slave = &omap3xxx_timer8_hwmod,
950 .addr = omap3xxx_timer8_addrs,
951 .user = OCP_USER_MPU | OCP_USER_SDMA,
954 /* timer8 slave port */
955 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
956 &omap3xxx_l4_per__timer8,
960 static struct omap_hwmod omap3xxx_timer8_hwmod = {
962 .mpu_irqs = omap2_timer8_mpu_irqs,
963 .main_clk = "gpt8_fck",
967 .module_bit = OMAP3430_EN_GPT8_SHIFT,
968 .module_offs = OMAP3430_PER_MOD,
970 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
973 .dev_attr = &capability_pwm_dev_attr,
974 .slaves = omap3xxx_timer8_slaves,
975 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
976 .class = &omap3xxx_timer_hwmod_class,
980 static struct omap_hwmod omap3xxx_timer9_hwmod;
982 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
984 .pa_start = 0x49040000,
985 .pa_end = 0x49040000 + SZ_1K - 1,
986 .flags = ADDR_TYPE_RT
991 /* l4_per -> timer9 */
992 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
993 .master = &omap3xxx_l4_per_hwmod,
994 .slave = &omap3xxx_timer9_hwmod,
996 .addr = omap3xxx_timer9_addrs,
997 .user = OCP_USER_MPU | OCP_USER_SDMA,
1000 /* timer9 slave port */
1001 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1002 &omap3xxx_l4_per__timer9,
1006 static struct omap_hwmod omap3xxx_timer9_hwmod = {
1008 .mpu_irqs = omap2_timer9_mpu_irqs,
1009 .main_clk = "gpt9_fck",
1013 .module_bit = OMAP3430_EN_GPT9_SHIFT,
1014 .module_offs = OMAP3430_PER_MOD,
1016 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1019 .dev_attr = &capability_pwm_dev_attr,
1020 .slaves = omap3xxx_timer9_slaves,
1021 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
1022 .class = &omap3xxx_timer_hwmod_class,
1026 static struct omap_hwmod omap3xxx_timer10_hwmod;
1028 /* l4_core -> timer10 */
1029 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1030 .master = &omap3xxx_l4_core_hwmod,
1031 .slave = &omap3xxx_timer10_hwmod,
1033 .addr = omap2_timer10_addrs,
1034 .user = OCP_USER_MPU | OCP_USER_SDMA,
1037 /* timer10 slave port */
1038 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1039 &omap3xxx_l4_core__timer10,
1043 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1045 .mpu_irqs = omap2_timer10_mpu_irqs,
1046 .main_clk = "gpt10_fck",
1050 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1051 .module_offs = CORE_MOD,
1053 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1056 .dev_attr = &capability_pwm_dev_attr,
1057 .slaves = omap3xxx_timer10_slaves,
1058 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1059 .class = &omap3xxx_timer_1ms_hwmod_class,
1063 static struct omap_hwmod omap3xxx_timer11_hwmod;
1065 /* l4_core -> timer11 */
1066 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1067 .master = &omap3xxx_l4_core_hwmod,
1068 .slave = &omap3xxx_timer11_hwmod,
1070 .addr = omap2_timer11_addrs,
1071 .user = OCP_USER_MPU | OCP_USER_SDMA,
1074 /* timer11 slave port */
1075 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1076 &omap3xxx_l4_core__timer11,
1080 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1082 .mpu_irqs = omap2_timer11_mpu_irqs,
1083 .main_clk = "gpt11_fck",
1087 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1088 .module_offs = CORE_MOD,
1090 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1093 .dev_attr = &capability_pwm_dev_attr,
1094 .slaves = omap3xxx_timer11_slaves,
1095 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1096 .class = &omap3xxx_timer_hwmod_class,
1100 static struct omap_hwmod omap3xxx_timer12_hwmod;
1101 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1106 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1108 .pa_start = 0x48304000,
1109 .pa_end = 0x48304000 + SZ_1K - 1,
1110 .flags = ADDR_TYPE_RT
1115 /* l4_core -> timer12 */
1116 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1117 .master = &omap3xxx_l4_core_hwmod,
1118 .slave = &omap3xxx_timer12_hwmod,
1120 .addr = omap3xxx_timer12_addrs,
1121 .user = OCP_USER_MPU | OCP_USER_SDMA,
1124 /* timer12 slave port */
1125 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1126 &omap3xxx_l4_core__timer12,
1130 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1132 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1133 .main_clk = "gpt12_fck",
1137 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1138 .module_offs = WKUP_MOD,
1140 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1143 .dev_attr = &capability_secure_dev_attr,
1144 .slaves = omap3xxx_timer12_slaves,
1145 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1146 .class = &omap3xxx_timer_hwmod_class,
1149 /* l4_wkup -> wd_timer2 */
1150 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1152 .pa_start = 0x48314000,
1153 .pa_end = 0x4831407f,
1154 .flags = ADDR_TYPE_RT
1159 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1160 .master = &omap3xxx_l4_wkup_hwmod,
1161 .slave = &omap3xxx_wd_timer2_hwmod,
1163 .addr = omap3xxx_wd_timer2_addrs,
1164 .user = OCP_USER_MPU | OCP_USER_SDMA,
1169 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1170 * overflow condition
1173 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1175 .sysc_offs = 0x0010,
1176 .syss_offs = 0x0014,
1177 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1178 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1179 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1180 SYSS_HAS_RESET_STATUS),
1181 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1182 .sysc_fields = &omap_hwmod_sysc_type1,
1186 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1190 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1191 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1192 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1193 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1194 .sysc_fields = &omap_hwmod_sysc_type1,
1197 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1199 .sysc = &omap3xxx_wd_timer_sysc,
1200 .pre_shutdown = &omap2_wd_timer_disable
1204 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1205 &omap3xxx_l4_wkup__wd_timer2,
1208 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1209 .name = "wd_timer2",
1210 .class = &omap3xxx_wd_timer_hwmod_class,
1211 .main_clk = "wdt2_fck",
1215 .module_bit = OMAP3430_EN_WDT2_SHIFT,
1216 .module_offs = WKUP_MOD,
1218 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1221 .slaves = omap3xxx_wd_timer2_slaves,
1222 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1224 * XXX: Use software supervised mode, HW supervised smartidle seems to
1225 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1227 .flags = HWMOD_SWSUP_SIDLE,
1232 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1233 &omap3_l4_core__uart1,
1236 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1238 .mpu_irqs = omap2_uart1_mpu_irqs,
1239 .sdma_reqs = omap2_uart1_sdma_reqs,
1240 .main_clk = "uart1_fck",
1243 .module_offs = CORE_MOD,
1245 .module_bit = OMAP3430_EN_UART1_SHIFT,
1247 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1250 .slaves = omap3xxx_uart1_slaves,
1251 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1252 .class = &omap2_uart_class,
1257 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1258 &omap3_l4_core__uart2,
1261 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1263 .mpu_irqs = omap2_uart2_mpu_irqs,
1264 .sdma_reqs = omap2_uart2_sdma_reqs,
1265 .main_clk = "uart2_fck",
1268 .module_offs = CORE_MOD,
1270 .module_bit = OMAP3430_EN_UART2_SHIFT,
1272 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1275 .slaves = omap3xxx_uart2_slaves,
1276 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1277 .class = &omap2_uart_class,
1282 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1283 &omap3_l4_per__uart3,
1286 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1288 .mpu_irqs = omap2_uart3_mpu_irqs,
1289 .sdma_reqs = omap2_uart3_sdma_reqs,
1290 .main_clk = "uart3_fck",
1293 .module_offs = OMAP3430_PER_MOD,
1295 .module_bit = OMAP3430_EN_UART3_SHIFT,
1297 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1300 .slaves = omap3xxx_uart3_slaves,
1301 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1302 .class = &omap2_uart_class,
1307 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1308 { .irq = INT_36XX_UART4_IRQ, },
1312 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1313 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1314 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1318 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1319 &omap36xx_l4_per__uart4,
1322 static struct omap_hwmod omap36xx_uart4_hwmod = {
1324 .mpu_irqs = uart4_mpu_irqs,
1325 .sdma_reqs = uart4_sdma_reqs,
1326 .main_clk = "uart4_fck",
1327 .flags = HWMOD_SWSUP_SIDLE,
1330 .module_offs = OMAP3430_PER_MOD,
1332 .module_bit = OMAP3630_EN_UART4_SHIFT,
1334 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1337 .slaves = omap3xxx_uart4_slaves,
1338 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1339 .class = &omap2_uart_class,
1342 static struct omap_hwmod_class i2c_class = {
1345 .rev = OMAP_I2C_IP_VERSION_1,
1346 .reset = &omap_i2c_reset,
1349 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1350 { .name = "dispc", .dma_req = 5 },
1351 { .name = "dsi1", .dma_req = 74 },
1356 /* dss master ports */
1357 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1361 /* l4_core -> dss */
1362 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1363 .master = &omap3xxx_l4_core_hwmod,
1364 .slave = &omap3430es1_dss_core_hwmod,
1366 .addr = omap2_dss_addrs,
1369 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1370 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1371 .flags = OMAP_FIREWALL_L4,
1374 .user = OCP_USER_MPU | OCP_USER_SDMA,
1377 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1378 .master = &omap3xxx_l4_core_hwmod,
1379 .slave = &omap3xxx_dss_core_hwmod,
1381 .addr = omap2_dss_addrs,
1384 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1385 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1386 .flags = OMAP_FIREWALL_L4,
1389 .user = OCP_USER_MPU | OCP_USER_SDMA,
1392 /* dss slave ports */
1393 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1394 &omap3430es1_l4_core__dss,
1397 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1398 &omap3xxx_l4_core__dss,
1401 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1403 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1404 * driver does not use these clocks.
1406 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1407 { .role = "tv_clk", .clk = "dss_tv_fck" },
1408 /* required only on OMAP3430 */
1409 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1412 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1414 .class = &omap2_dss_hwmod_class,
1415 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1416 .sdma_reqs = omap3xxx_dss_sdma_chs,
1420 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1421 .module_offs = OMAP3430_DSS_MOD,
1423 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1426 .opt_clks = dss_opt_clks,
1427 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1428 .slaves = omap3430es1_dss_slaves,
1429 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1430 .masters = omap3xxx_dss_masters,
1431 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1432 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1435 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1437 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1438 .class = &omap2_dss_hwmod_class,
1439 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1440 .sdma_reqs = omap3xxx_dss_sdma_chs,
1444 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1445 .module_offs = OMAP3430_DSS_MOD,
1447 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1448 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1451 .opt_clks = dss_opt_clks,
1452 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1453 .slaves = omap3xxx_dss_slaves,
1454 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1455 .masters = omap3xxx_dss_masters,
1456 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1461 * display controller
1464 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
1466 .sysc_offs = 0x0010,
1467 .syss_offs = 0x0014,
1468 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1469 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1470 SYSC_HAS_ENAWAKEUP),
1471 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1472 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1473 .sysc_fields = &omap_hwmod_sysc_type1,
1476 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1478 .sysc = &omap3_dispc_sysc,
1481 /* l4_core -> dss_dispc */
1482 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1483 .master = &omap3xxx_l4_core_hwmod,
1484 .slave = &omap3xxx_dss_dispc_hwmod,
1486 .addr = omap2_dss_dispc_addrs,
1489 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1490 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1491 .flags = OMAP_FIREWALL_L4,
1494 .user = OCP_USER_MPU | OCP_USER_SDMA,
1497 /* dss_dispc slave ports */
1498 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1499 &omap3xxx_l4_core__dss_dispc,
1502 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1503 .name = "dss_dispc",
1504 .class = &omap3_dispc_hwmod_class,
1505 .mpu_irqs = omap2_dispc_irqs,
1506 .main_clk = "dss1_alwon_fck",
1510 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1511 .module_offs = OMAP3430_DSS_MOD,
1514 .slaves = omap3xxx_dss_dispc_slaves,
1515 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1516 .flags = HWMOD_NO_IDLEST,
1517 .dev_attr = &omap2_3_dss_dispc_dev_attr
1522 * display serial interface controller
1525 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1529 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1535 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1537 .pa_start = 0x4804FC00,
1538 .pa_end = 0x4804FFFF,
1539 .flags = ADDR_TYPE_RT
1544 /* l4_core -> dss_dsi1 */
1545 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1546 .master = &omap3xxx_l4_core_hwmod,
1547 .slave = &omap3xxx_dss_dsi1_hwmod,
1549 .addr = omap3xxx_dss_dsi1_addrs,
1552 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1553 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1554 .flags = OMAP_FIREWALL_L4,
1557 .user = OCP_USER_MPU | OCP_USER_SDMA,
1560 /* dss_dsi1 slave ports */
1561 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1562 &omap3xxx_l4_core__dss_dsi1,
1565 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1566 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1569 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1571 .class = &omap3xxx_dsi_hwmod_class,
1572 .mpu_irqs = omap3xxx_dsi1_irqs,
1573 .main_clk = "dss1_alwon_fck",
1577 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1578 .module_offs = OMAP3430_DSS_MOD,
1581 .opt_clks = dss_dsi1_opt_clks,
1582 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1583 .slaves = omap3xxx_dss_dsi1_slaves,
1584 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1585 .flags = HWMOD_NO_IDLEST,
1588 /* l4_core -> dss_rfbi */
1589 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1590 .master = &omap3xxx_l4_core_hwmod,
1591 .slave = &omap3xxx_dss_rfbi_hwmod,
1593 .addr = omap2_dss_rfbi_addrs,
1596 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1597 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1598 .flags = OMAP_FIREWALL_L4,
1601 .user = OCP_USER_MPU | OCP_USER_SDMA,
1604 /* dss_rfbi slave ports */
1605 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1606 &omap3xxx_l4_core__dss_rfbi,
1609 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1610 { .role = "ick", .clk = "dss_ick" },
1613 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1615 .class = &omap2_rfbi_hwmod_class,
1616 .main_clk = "dss1_alwon_fck",
1620 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1621 .module_offs = OMAP3430_DSS_MOD,
1624 .opt_clks = dss_rfbi_opt_clks,
1625 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1626 .slaves = omap3xxx_dss_rfbi_slaves,
1627 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1628 .flags = HWMOD_NO_IDLEST,
1631 /* l4_core -> dss_venc */
1632 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1633 .master = &omap3xxx_l4_core_hwmod,
1634 .slave = &omap3xxx_dss_venc_hwmod,
1636 .addr = omap2_dss_venc_addrs,
1639 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1640 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1641 .flags = OMAP_FIREWALL_L4,
1644 .flags = OCPIF_SWSUP_IDLE,
1645 .user = OCP_USER_MPU | OCP_USER_SDMA,
1648 /* dss_venc slave ports */
1649 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1650 &omap3xxx_l4_core__dss_venc,
1653 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1654 /* required only on OMAP3430 */
1655 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1658 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1660 .class = &omap2_venc_hwmod_class,
1661 .main_clk = "dss_tv_fck",
1665 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1666 .module_offs = OMAP3430_DSS_MOD,
1669 .opt_clks = dss_venc_opt_clks,
1670 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
1671 .slaves = omap3xxx_dss_venc_slaves,
1672 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1673 .flags = HWMOD_NO_IDLEST,
1678 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1679 .fifo_depth = 8, /* bytes */
1680 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1681 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1682 OMAP_I2C_FLAG_BUS_SHIFT_2,
1685 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1686 &omap3_l4_core__i2c1,
1689 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1691 .flags = HWMOD_16BIT_REG,
1692 .mpu_irqs = omap2_i2c1_mpu_irqs,
1693 .sdma_reqs = omap2_i2c1_sdma_reqs,
1694 .main_clk = "i2c1_fck",
1697 .module_offs = CORE_MOD,
1699 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1701 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1704 .slaves = omap3xxx_i2c1_slaves,
1705 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1706 .class = &i2c_class,
1707 .dev_attr = &i2c1_dev_attr,
1712 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1713 .fifo_depth = 8, /* bytes */
1714 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1715 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1716 OMAP_I2C_FLAG_BUS_SHIFT_2,
1719 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1720 &omap3_l4_core__i2c2,
1723 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1725 .flags = HWMOD_16BIT_REG,
1726 .mpu_irqs = omap2_i2c2_mpu_irqs,
1727 .sdma_reqs = omap2_i2c2_sdma_reqs,
1728 .main_clk = "i2c2_fck",
1731 .module_offs = CORE_MOD,
1733 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1735 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1738 .slaves = omap3xxx_i2c2_slaves,
1739 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1740 .class = &i2c_class,
1741 .dev_attr = &i2c2_dev_attr,
1746 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1747 .fifo_depth = 64, /* bytes */
1748 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1749 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1750 OMAP_I2C_FLAG_BUS_SHIFT_2,
1753 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1754 { .irq = INT_34XX_I2C3_IRQ, },
1758 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1759 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1760 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1764 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1765 &omap3_l4_core__i2c3,
1768 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1770 .flags = HWMOD_16BIT_REG,
1771 .mpu_irqs = i2c3_mpu_irqs,
1772 .sdma_reqs = i2c3_sdma_reqs,
1773 .main_clk = "i2c3_fck",
1776 .module_offs = CORE_MOD,
1778 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1780 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1783 .slaves = omap3xxx_i2c3_slaves,
1784 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1785 .class = &i2c_class,
1786 .dev_attr = &i2c3_dev_attr,
1789 /* l4_wkup -> gpio1 */
1790 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1792 .pa_start = 0x48310000,
1793 .pa_end = 0x483101ff,
1794 .flags = ADDR_TYPE_RT
1799 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1800 .master = &omap3xxx_l4_wkup_hwmod,
1801 .slave = &omap3xxx_gpio1_hwmod,
1802 .addr = omap3xxx_gpio1_addrs,
1803 .user = OCP_USER_MPU | OCP_USER_SDMA,
1806 /* l4_per -> gpio2 */
1807 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1809 .pa_start = 0x49050000,
1810 .pa_end = 0x490501ff,
1811 .flags = ADDR_TYPE_RT
1816 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1817 .master = &omap3xxx_l4_per_hwmod,
1818 .slave = &omap3xxx_gpio2_hwmod,
1819 .addr = omap3xxx_gpio2_addrs,
1820 .user = OCP_USER_MPU | OCP_USER_SDMA,
1823 /* l4_per -> gpio3 */
1824 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1826 .pa_start = 0x49052000,
1827 .pa_end = 0x490521ff,
1828 .flags = ADDR_TYPE_RT
1833 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1834 .master = &omap3xxx_l4_per_hwmod,
1835 .slave = &omap3xxx_gpio3_hwmod,
1836 .addr = omap3xxx_gpio3_addrs,
1837 .user = OCP_USER_MPU | OCP_USER_SDMA,
1840 /* l4_per -> gpio4 */
1841 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1843 .pa_start = 0x49054000,
1844 .pa_end = 0x490541ff,
1845 .flags = ADDR_TYPE_RT
1850 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1851 .master = &omap3xxx_l4_per_hwmod,
1852 .slave = &omap3xxx_gpio4_hwmod,
1853 .addr = omap3xxx_gpio4_addrs,
1854 .user = OCP_USER_MPU | OCP_USER_SDMA,
1857 /* l4_per -> gpio5 */
1858 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1860 .pa_start = 0x49056000,
1861 .pa_end = 0x490561ff,
1862 .flags = ADDR_TYPE_RT
1867 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1868 .master = &omap3xxx_l4_per_hwmod,
1869 .slave = &omap3xxx_gpio5_hwmod,
1870 .addr = omap3xxx_gpio5_addrs,
1871 .user = OCP_USER_MPU | OCP_USER_SDMA,
1874 /* l4_per -> gpio6 */
1875 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1877 .pa_start = 0x49058000,
1878 .pa_end = 0x490581ff,
1879 .flags = ADDR_TYPE_RT
1884 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1885 .master = &omap3xxx_l4_per_hwmod,
1886 .slave = &omap3xxx_gpio6_hwmod,
1887 .addr = omap3xxx_gpio6_addrs,
1888 .user = OCP_USER_MPU | OCP_USER_SDMA,
1893 * general purpose io module
1896 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1898 .sysc_offs = 0x0010,
1899 .syss_offs = 0x0014,
1900 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1901 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1902 SYSS_HAS_RESET_STATUS),
1903 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1904 .sysc_fields = &omap_hwmod_sysc_type1,
1907 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1909 .sysc = &omap3xxx_gpio_sysc,
1914 static struct omap_gpio_dev_attr gpio_dev_attr = {
1920 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1921 { .role = "dbclk", .clk = "gpio1_dbck", },
1924 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1925 &omap3xxx_l4_wkup__gpio1,
1928 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1930 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1931 .mpu_irqs = omap2_gpio1_irqs,
1932 .main_clk = "gpio1_ick",
1933 .opt_clks = gpio1_opt_clks,
1934 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1938 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1939 .module_offs = WKUP_MOD,
1941 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1944 .slaves = omap3xxx_gpio1_slaves,
1945 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1946 .class = &omap3xxx_gpio_hwmod_class,
1947 .dev_attr = &gpio_dev_attr,
1951 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1952 { .role = "dbclk", .clk = "gpio2_dbck", },
1955 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1956 &omap3xxx_l4_per__gpio2,
1959 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1961 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1962 .mpu_irqs = omap2_gpio2_irqs,
1963 .main_clk = "gpio2_ick",
1964 .opt_clks = gpio2_opt_clks,
1965 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1969 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1970 .module_offs = OMAP3430_PER_MOD,
1972 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1975 .slaves = omap3xxx_gpio2_slaves,
1976 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1977 .class = &omap3xxx_gpio_hwmod_class,
1978 .dev_attr = &gpio_dev_attr,
1982 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1983 { .role = "dbclk", .clk = "gpio3_dbck", },
1986 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1987 &omap3xxx_l4_per__gpio3,
1990 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1992 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1993 .mpu_irqs = omap2_gpio3_irqs,
1994 .main_clk = "gpio3_ick",
1995 .opt_clks = gpio3_opt_clks,
1996 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
2000 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2001 .module_offs = OMAP3430_PER_MOD,
2003 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2006 .slaves = omap3xxx_gpio3_slaves,
2007 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2008 .class = &omap3xxx_gpio_hwmod_class,
2009 .dev_attr = &gpio_dev_attr,
2013 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2014 { .role = "dbclk", .clk = "gpio4_dbck", },
2017 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2018 &omap3xxx_l4_per__gpio4,
2021 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2023 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2024 .mpu_irqs = omap2_gpio4_irqs,
2025 .main_clk = "gpio4_ick",
2026 .opt_clks = gpio4_opt_clks,
2027 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2031 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2032 .module_offs = OMAP3430_PER_MOD,
2034 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2037 .slaves = omap3xxx_gpio4_slaves,
2038 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2039 .class = &omap3xxx_gpio_hwmod_class,
2040 .dev_attr = &gpio_dev_attr,
2044 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2045 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2049 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2050 { .role = "dbclk", .clk = "gpio5_dbck", },
2053 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2054 &omap3xxx_l4_per__gpio5,
2057 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2059 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2060 .mpu_irqs = omap3xxx_gpio5_irqs,
2061 .main_clk = "gpio5_ick",
2062 .opt_clks = gpio5_opt_clks,
2063 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2067 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2068 .module_offs = OMAP3430_PER_MOD,
2070 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2073 .slaves = omap3xxx_gpio5_slaves,
2074 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2075 .class = &omap3xxx_gpio_hwmod_class,
2076 .dev_attr = &gpio_dev_attr,
2080 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2081 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2085 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2086 { .role = "dbclk", .clk = "gpio6_dbck", },
2089 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2090 &omap3xxx_l4_per__gpio6,
2093 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2095 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2096 .mpu_irqs = omap3xxx_gpio6_irqs,
2097 .main_clk = "gpio6_ick",
2098 .opt_clks = gpio6_opt_clks,
2099 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2103 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2104 .module_offs = OMAP3430_PER_MOD,
2106 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2109 .slaves = omap3xxx_gpio6_slaves,
2110 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2111 .class = &omap3xxx_gpio_hwmod_class,
2112 .dev_attr = &gpio_dev_attr,
2115 /* dma_system -> L3 */
2116 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2117 .master = &omap3xxx_dma_system_hwmod,
2118 .slave = &omap3xxx_l3_main_hwmod,
2119 .clk = "core_l3_ick",
2120 .user = OCP_USER_MPU | OCP_USER_SDMA,
2123 /* dma attributes */
2124 static struct omap_dma_dev_attr dma_dev_attr = {
2125 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2126 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2130 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2132 .sysc_offs = 0x002c,
2133 .syss_offs = 0x0028,
2134 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2135 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2136 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2137 SYSS_HAS_RESET_STATUS),
2138 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2139 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2140 .sysc_fields = &omap_hwmod_sysc_type1,
2143 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2145 .sysc = &omap3xxx_dma_sysc,
2149 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2151 .pa_start = 0x48056000,
2152 .pa_end = 0x48056fff,
2153 .flags = ADDR_TYPE_RT
2158 /* dma_system master ports */
2159 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2160 &omap3xxx_dma_system__l3,
2163 /* l4_cfg -> dma_system */
2164 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2165 .master = &omap3xxx_l4_core_hwmod,
2166 .slave = &omap3xxx_dma_system_hwmod,
2167 .clk = "core_l4_ick",
2168 .addr = omap3xxx_dma_system_addrs,
2169 .user = OCP_USER_MPU | OCP_USER_SDMA,
2172 /* dma_system slave ports */
2173 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2174 &omap3xxx_l4_core__dma_system,
2177 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2179 .class = &omap3xxx_dma_hwmod_class,
2180 .mpu_irqs = omap2_dma_system_irqs,
2181 .main_clk = "core_l3_ick",
2184 .module_offs = CORE_MOD,
2186 .module_bit = OMAP3430_ST_SDMA_SHIFT,
2188 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2191 .slaves = omap3xxx_dma_system_slaves,
2192 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2193 .masters = omap3xxx_dma_system_masters,
2194 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2195 .dev_attr = &dma_dev_attr,
2196 .flags = HWMOD_NO_IDLEST,
2201 * multi channel buffered serial port controller
2204 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2205 .sysc_offs = 0x008c,
2206 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2207 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2208 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2209 .sysc_fields = &omap_hwmod_sysc_type1,
2213 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2215 .sysc = &omap3xxx_mcbsp_sysc,
2216 .rev = MCBSP_CONFIG_TYPE3,
2220 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2221 { .name = "irq", .irq = 16 },
2222 { .name = "tx", .irq = 59 },
2223 { .name = "rx", .irq = 60 },
2227 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2230 .pa_start = 0x48074000,
2231 .pa_end = 0x480740ff,
2232 .flags = ADDR_TYPE_RT
2237 /* l4_core -> mcbsp1 */
2238 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2239 .master = &omap3xxx_l4_core_hwmod,
2240 .slave = &omap3xxx_mcbsp1_hwmod,
2241 .clk = "mcbsp1_ick",
2242 .addr = omap3xxx_mcbsp1_addrs,
2243 .user = OCP_USER_MPU | OCP_USER_SDMA,
2246 /* mcbsp1 slave ports */
2247 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2248 &omap3xxx_l4_core__mcbsp1,
2251 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2253 .class = &omap3xxx_mcbsp_hwmod_class,
2254 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2255 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2256 .main_clk = "mcbsp1_fck",
2260 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2261 .module_offs = CORE_MOD,
2263 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2266 .slaves = omap3xxx_mcbsp1_slaves,
2267 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2271 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2272 { .name = "irq", .irq = 17 },
2273 { .name = "tx", .irq = 62 },
2274 { .name = "rx", .irq = 63 },
2278 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2281 .pa_start = 0x49022000,
2282 .pa_end = 0x490220ff,
2283 .flags = ADDR_TYPE_RT
2288 /* l4_per -> mcbsp2 */
2289 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2290 .master = &omap3xxx_l4_per_hwmod,
2291 .slave = &omap3xxx_mcbsp2_hwmod,
2292 .clk = "mcbsp2_ick",
2293 .addr = omap3xxx_mcbsp2_addrs,
2294 .user = OCP_USER_MPU | OCP_USER_SDMA,
2297 /* mcbsp2 slave ports */
2298 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2299 &omap3xxx_l4_per__mcbsp2,
2302 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2303 .sidetone = "mcbsp2_sidetone",
2306 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2308 .class = &omap3xxx_mcbsp_hwmod_class,
2309 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2310 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2311 .main_clk = "mcbsp2_fck",
2315 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2316 .module_offs = OMAP3430_PER_MOD,
2318 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2321 .slaves = omap3xxx_mcbsp2_slaves,
2322 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2323 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2327 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2328 { .name = "irq", .irq = 22 },
2329 { .name = "tx", .irq = 89 },
2330 { .name = "rx", .irq = 90 },
2334 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2337 .pa_start = 0x49024000,
2338 .pa_end = 0x490240ff,
2339 .flags = ADDR_TYPE_RT
2344 /* l4_per -> mcbsp3 */
2345 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2346 .master = &omap3xxx_l4_per_hwmod,
2347 .slave = &omap3xxx_mcbsp3_hwmod,
2348 .clk = "mcbsp3_ick",
2349 .addr = omap3xxx_mcbsp3_addrs,
2350 .user = OCP_USER_MPU | OCP_USER_SDMA,
2353 /* mcbsp3 slave ports */
2354 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2355 &omap3xxx_l4_per__mcbsp3,
2358 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2359 .sidetone = "mcbsp3_sidetone",
2362 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2364 .class = &omap3xxx_mcbsp_hwmod_class,
2365 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2366 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
2367 .main_clk = "mcbsp3_fck",
2371 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2372 .module_offs = OMAP3430_PER_MOD,
2374 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2377 .slaves = omap3xxx_mcbsp3_slaves,
2378 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2379 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2383 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2384 { .name = "irq", .irq = 23 },
2385 { .name = "tx", .irq = 54 },
2386 { .name = "rx", .irq = 55 },
2390 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2391 { .name = "rx", .dma_req = 20 },
2392 { .name = "tx", .dma_req = 19 },
2396 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2399 .pa_start = 0x49026000,
2400 .pa_end = 0x490260ff,
2401 .flags = ADDR_TYPE_RT
2406 /* l4_per -> mcbsp4 */
2407 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2408 .master = &omap3xxx_l4_per_hwmod,
2409 .slave = &omap3xxx_mcbsp4_hwmod,
2410 .clk = "mcbsp4_ick",
2411 .addr = omap3xxx_mcbsp4_addrs,
2412 .user = OCP_USER_MPU | OCP_USER_SDMA,
2415 /* mcbsp4 slave ports */
2416 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2417 &omap3xxx_l4_per__mcbsp4,
2420 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2422 .class = &omap3xxx_mcbsp_hwmod_class,
2423 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2424 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2425 .main_clk = "mcbsp4_fck",
2429 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2430 .module_offs = OMAP3430_PER_MOD,
2432 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2435 .slaves = omap3xxx_mcbsp4_slaves,
2436 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2440 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2441 { .name = "irq", .irq = 27 },
2442 { .name = "tx", .irq = 81 },
2443 { .name = "rx", .irq = 82 },
2447 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2448 { .name = "rx", .dma_req = 22 },
2449 { .name = "tx", .dma_req = 21 },
2453 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2456 .pa_start = 0x48096000,
2457 .pa_end = 0x480960ff,
2458 .flags = ADDR_TYPE_RT
2463 /* l4_core -> mcbsp5 */
2464 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2465 .master = &omap3xxx_l4_core_hwmod,
2466 .slave = &omap3xxx_mcbsp5_hwmod,
2467 .clk = "mcbsp5_ick",
2468 .addr = omap3xxx_mcbsp5_addrs,
2469 .user = OCP_USER_MPU | OCP_USER_SDMA,
2472 /* mcbsp5 slave ports */
2473 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2474 &omap3xxx_l4_core__mcbsp5,
2477 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2479 .class = &omap3xxx_mcbsp_hwmod_class,
2480 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2481 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2482 .main_clk = "mcbsp5_fck",
2486 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2487 .module_offs = CORE_MOD,
2489 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2492 .slaves = omap3xxx_mcbsp5_slaves,
2493 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2495 /* 'mcbsp sidetone' class */
2497 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2498 .sysc_offs = 0x0010,
2499 .sysc_flags = SYSC_HAS_AUTOIDLE,
2500 .sysc_fields = &omap_hwmod_sysc_type1,
2503 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2504 .name = "mcbsp_sidetone",
2505 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2508 /* mcbsp2_sidetone */
2509 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2510 { .name = "irq", .irq = 4 },
2514 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2517 .pa_start = 0x49028000,
2518 .pa_end = 0x490280ff,
2519 .flags = ADDR_TYPE_RT
2524 /* l4_per -> mcbsp2_sidetone */
2525 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2526 .master = &omap3xxx_l4_per_hwmod,
2527 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2528 .clk = "mcbsp2_ick",
2529 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2530 .user = OCP_USER_MPU,
2533 /* mcbsp2_sidetone slave ports */
2534 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2535 &omap3xxx_l4_per__mcbsp2_sidetone,
2538 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2539 .name = "mcbsp2_sidetone",
2540 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2541 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2542 .main_clk = "mcbsp2_fck",
2546 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2547 .module_offs = OMAP3430_PER_MOD,
2549 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2552 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2553 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2556 /* mcbsp3_sidetone */
2557 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2558 { .name = "irq", .irq = 5 },
2562 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2565 .pa_start = 0x4902A000,
2566 .pa_end = 0x4902A0ff,
2567 .flags = ADDR_TYPE_RT
2572 /* l4_per -> mcbsp3_sidetone */
2573 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2574 .master = &omap3xxx_l4_per_hwmod,
2575 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2576 .clk = "mcbsp3_ick",
2577 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2578 .user = OCP_USER_MPU,
2581 /* mcbsp3_sidetone slave ports */
2582 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2583 &omap3xxx_l4_per__mcbsp3_sidetone,
2586 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2587 .name = "mcbsp3_sidetone",
2588 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2589 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2590 .main_clk = "mcbsp3_fck",
2594 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2595 .module_offs = OMAP3430_PER_MOD,
2597 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2600 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2601 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2606 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2610 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2612 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2613 .clockact = CLOCKACT_TEST_ICLK,
2614 .sysc_fields = &omap34xx_sr_sysc_fields,
2617 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2618 .name = "smartreflex",
2619 .sysc = &omap34xx_sr_sysc,
2623 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2628 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2630 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2631 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2633 .sysc_fields = &omap36xx_sr_sysc_fields,
2636 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2637 .name = "smartreflex",
2638 .sysc = &omap36xx_sr_sysc,
2643 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
2644 .sensor_voltdm_name = "mpu_iva",
2647 static struct omap_hwmod_ocp_if *omap34xx_sr1_slaves[] = {
2648 &omap34xx_l4_core__sr1,
2651 static struct omap_hwmod omap34xx_sr1_hwmod = {
2653 .class = &omap34xx_smartreflex_hwmod_class,
2654 .main_clk = "sr1_fck",
2658 .module_bit = OMAP3430_EN_SR1_SHIFT,
2659 .module_offs = WKUP_MOD,
2661 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2664 .slaves = omap34xx_sr1_slaves,
2665 .slaves_cnt = ARRAY_SIZE(omap34xx_sr1_slaves),
2666 .dev_attr = &sr1_dev_attr,
2667 .mpu_irqs = omap3_smartreflex_mpu_irqs,
2668 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2671 static struct omap_hwmod_ocp_if *omap36xx_sr1_slaves[] = {
2672 &omap36xx_l4_core__sr1,
2675 static struct omap_hwmod omap36xx_sr1_hwmod = {
2677 .class = &omap36xx_smartreflex_hwmod_class,
2678 .main_clk = "sr1_fck",
2682 .module_bit = OMAP3430_EN_SR1_SHIFT,
2683 .module_offs = WKUP_MOD,
2685 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2688 .slaves = omap36xx_sr1_slaves,
2689 .slaves_cnt = ARRAY_SIZE(omap36xx_sr1_slaves),
2690 .dev_attr = &sr1_dev_attr,
2691 .mpu_irqs = omap3_smartreflex_mpu_irqs,
2695 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
2696 .sensor_voltdm_name = "core",
2699 static struct omap_hwmod_ocp_if *omap34xx_sr2_slaves[] = {
2700 &omap34xx_l4_core__sr2,
2703 static struct omap_hwmod omap34xx_sr2_hwmod = {
2705 .class = &omap34xx_smartreflex_hwmod_class,
2706 .main_clk = "sr2_fck",
2710 .module_bit = OMAP3430_EN_SR2_SHIFT,
2711 .module_offs = WKUP_MOD,
2713 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2716 .slaves = omap34xx_sr2_slaves,
2717 .slaves_cnt = ARRAY_SIZE(omap34xx_sr2_slaves),
2718 .dev_attr = &sr2_dev_attr,
2719 .mpu_irqs = omap3_smartreflex_core_irqs,
2720 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2723 static struct omap_hwmod_ocp_if *omap36xx_sr2_slaves[] = {
2724 &omap36xx_l4_core__sr2,
2727 static struct omap_hwmod omap36xx_sr2_hwmod = {
2729 .class = &omap36xx_smartreflex_hwmod_class,
2730 .main_clk = "sr2_fck",
2734 .module_bit = OMAP3430_EN_SR2_SHIFT,
2735 .module_offs = WKUP_MOD,
2737 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2740 .slaves = omap36xx_sr2_slaves,
2741 .slaves_cnt = ARRAY_SIZE(omap36xx_sr2_slaves),
2742 .dev_attr = &sr2_dev_attr,
2743 .mpu_irqs = omap3_smartreflex_core_irqs,
2748 * mailbox module allowing communication between the on-chip processors
2749 * using a queued mailbox-interrupt mechanism.
2752 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2756 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2757 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2758 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2759 .sysc_fields = &omap_hwmod_sysc_type1,
2762 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2764 .sysc = &omap3xxx_mailbox_sysc,
2767 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2768 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2773 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2775 .pa_start = 0x48094000,
2776 .pa_end = 0x480941ff,
2777 .flags = ADDR_TYPE_RT,
2782 /* l4_core -> mailbox */
2783 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2784 .master = &omap3xxx_l4_core_hwmod,
2785 .slave = &omap3xxx_mailbox_hwmod,
2786 .addr = omap3xxx_mailbox_addrs,
2787 .user = OCP_USER_MPU | OCP_USER_SDMA,
2790 /* mailbox slave ports */
2791 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2792 &omap3xxx_l4_core__mailbox,
2795 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2797 .class = &omap3xxx_mailbox_hwmod_class,
2798 .mpu_irqs = omap3xxx_mailbox_irqs,
2799 .main_clk = "mailboxes_ick",
2803 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2804 .module_offs = CORE_MOD,
2806 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2809 .slaves = omap3xxx_mailbox_slaves,
2810 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2813 /* l4 core -> mcspi1 interface */
2814 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2815 .master = &omap3xxx_l4_core_hwmod,
2816 .slave = &omap34xx_mcspi1,
2817 .clk = "mcspi1_ick",
2818 .addr = omap2_mcspi1_addr_space,
2819 .user = OCP_USER_MPU | OCP_USER_SDMA,
2822 /* l4 core -> mcspi2 interface */
2823 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2824 .master = &omap3xxx_l4_core_hwmod,
2825 .slave = &omap34xx_mcspi2,
2826 .clk = "mcspi2_ick",
2827 .addr = omap2_mcspi2_addr_space,
2828 .user = OCP_USER_MPU | OCP_USER_SDMA,
2831 /* l4 core -> mcspi3 interface */
2832 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2833 .master = &omap3xxx_l4_core_hwmod,
2834 .slave = &omap34xx_mcspi3,
2835 .clk = "mcspi3_ick",
2836 .addr = omap2430_mcspi3_addr_space,
2837 .user = OCP_USER_MPU | OCP_USER_SDMA,
2840 /* l4 core -> mcspi4 interface */
2841 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2843 .pa_start = 0x480ba000,
2844 .pa_end = 0x480ba0ff,
2845 .flags = ADDR_TYPE_RT,
2850 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2851 .master = &omap3xxx_l4_core_hwmod,
2852 .slave = &omap34xx_mcspi4,
2853 .clk = "mcspi4_ick",
2854 .addr = omap34xx_mcspi4_addr_space,
2855 .user = OCP_USER_MPU | OCP_USER_SDMA,
2860 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2864 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2866 .sysc_offs = 0x0010,
2867 .syss_offs = 0x0014,
2868 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2869 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2870 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2871 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2872 .sysc_fields = &omap_hwmod_sysc_type1,
2875 static struct omap_hwmod_class omap34xx_mcspi_class = {
2877 .sysc = &omap34xx_mcspi_sysc,
2878 .rev = OMAP3_MCSPI_REV,
2882 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2883 &omap34xx_l4_core__mcspi1,
2886 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2887 .num_chipselect = 4,
2890 static struct omap_hwmod omap34xx_mcspi1 = {
2892 .mpu_irqs = omap2_mcspi1_mpu_irqs,
2893 .sdma_reqs = omap2_mcspi1_sdma_reqs,
2894 .main_clk = "mcspi1_fck",
2897 .module_offs = CORE_MOD,
2899 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2901 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2904 .slaves = omap34xx_mcspi1_slaves,
2905 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2906 .class = &omap34xx_mcspi_class,
2907 .dev_attr = &omap_mcspi1_dev_attr,
2911 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2912 &omap34xx_l4_core__mcspi2,
2915 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2916 .num_chipselect = 2,
2919 static struct omap_hwmod omap34xx_mcspi2 = {
2921 .mpu_irqs = omap2_mcspi2_mpu_irqs,
2922 .sdma_reqs = omap2_mcspi2_sdma_reqs,
2923 .main_clk = "mcspi2_fck",
2926 .module_offs = CORE_MOD,
2928 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2930 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2933 .slaves = omap34xx_mcspi2_slaves,
2934 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2935 .class = &omap34xx_mcspi_class,
2936 .dev_attr = &omap_mcspi2_dev_attr,
2940 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2941 { .name = "irq", .irq = 91 }, /* 91 */
2945 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2946 { .name = "tx0", .dma_req = 15 },
2947 { .name = "rx0", .dma_req = 16 },
2948 { .name = "tx1", .dma_req = 23 },
2949 { .name = "rx1", .dma_req = 24 },
2953 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2954 &omap34xx_l4_core__mcspi3,
2957 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2958 .num_chipselect = 2,
2961 static struct omap_hwmod omap34xx_mcspi3 = {
2963 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
2964 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
2965 .main_clk = "mcspi3_fck",
2968 .module_offs = CORE_MOD,
2970 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2972 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2975 .slaves = omap34xx_mcspi3_slaves,
2976 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2977 .class = &omap34xx_mcspi_class,
2978 .dev_attr = &omap_mcspi3_dev_attr,
2982 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2983 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2987 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2988 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2989 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2993 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2994 &omap34xx_l4_core__mcspi4,
2997 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2998 .num_chipselect = 1,
3001 static struct omap_hwmod omap34xx_mcspi4 = {
3003 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
3004 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
3005 .main_clk = "mcspi4_fck",
3008 .module_offs = CORE_MOD,
3010 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3012 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3015 .slaves = omap34xx_mcspi4_slaves,
3016 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3017 .class = &omap34xx_mcspi_class,
3018 .dev_attr = &omap_mcspi4_dev_attr,
3022 struct omap_hwmod_class omap34xx_bandgap_ts_class = {
3023 .name = "bandgap_ts",
3026 static struct omap_hwmod_addr_space omap3xxx_bandgap_ts_addrs[] = {
3029 .pa_start = 0x48002524,
3030 .pa_end = 0x48002524 + 4,
3031 .flags = ADDR_TYPE_RT
3036 static struct omap_hwmod omap34xx_bandgap_ts;
3038 /* l4_core -> bandgap */
3039 static struct omap_hwmod_ocp_if omap3xxx_l4_core__bandgap_ts = {
3040 .master = &omap3xxx_l4_core_hwmod,
3041 .slave = &omap34xx_bandgap_ts,
3042 .addr = omap3xxx_bandgap_ts_addrs,
3043 .user = OCP_USER_MPU,
3046 static struct omap_hwmod_ocp_if *omap3xxx_bandgap_ts_slaves[] = {
3047 &omap3xxx_l4_core__bandgap_ts,
3050 static struct omap_hwmod omap34xx_bandgap_ts = {
3051 .name = "bandgap_ts",
3052 .main_clk = "ts_fck",
3053 .slaves = omap3xxx_bandgap_ts_slaves,
3054 .slaves_cnt = ARRAY_SIZE(omap3xxx_bandgap_ts_slaves),
3055 .class = &omap34xx_bandgap_ts_class,
3056 .flags = HWMOD_NO_IDLEST,
3062 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3064 .sysc_offs = 0x0404,
3065 .syss_offs = 0x0408,
3066 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3067 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3069 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3070 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3071 .sysc_fields = &omap_hwmod_sysc_type1,
3074 static struct omap_hwmod_class usbotg_class = {
3076 .sysc = &omap3xxx_usbhsotg_sysc,
3079 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3081 { .name = "mc", .irq = 92 },
3082 { .name = "dma", .irq = 93 },
3086 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3087 .name = "usb_otg_hs",
3088 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
3089 .main_clk = "hsotgusb_ick",
3093 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3094 .module_offs = CORE_MOD,
3096 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3097 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3100 .masters = omap3xxx_usbhsotg_masters,
3101 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3102 .slaves = omap3xxx_usbhsotg_slaves,
3103 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3104 .class = &usbotg_class,
3107 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
3108 * broken when autoidle is enabled
3109 * workaround is to disable the autoidle bit at module level.
3111 * Enabling the device in any other MIDLEMODE setting but force-idle
3112 * causes core_pwrdm not enter idle states at least on OMAP3630.
3113 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
3114 * signal when MIDLEMODE is set to force-idle.
3116 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3117 | HWMOD_FORCE_MSTANDBY,
3121 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3123 { .name = "mc", .irq = 71 },
3127 static struct omap_hwmod_class am35xx_usbotg_class = {
3128 .name = "am35xx_usbotg",
3132 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3133 .name = "am35x_otg_hs",
3134 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3140 .masters = am35xx_usbhsotg_masters,
3141 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3142 .slaves = am35xx_usbhsotg_slaves,
3143 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3144 .class = &am35xx_usbotg_class,
3147 /* MMC/SD/SDIO common */
3149 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3153 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3154 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3155 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3156 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3157 .sysc_fields = &omap_hwmod_sysc_type1,
3160 static struct omap_hwmod_class omap34xx_mmc_class = {
3162 .sysc = &omap34xx_mmc_sysc,
3167 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3172 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3173 { .name = "tx", .dma_req = 61, },
3174 { .name = "rx", .dma_req = 62, },
3178 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3179 { .role = "dbck", .clk = "omap_32k_fck", },
3182 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3183 &omap3xxx_l4_core__mmc1,
3186 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3187 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3190 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3191 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
3192 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
3193 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
3196 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
3198 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3199 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3200 .opt_clks = omap34xx_mmc1_opt_clks,
3201 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3202 .main_clk = "mmchs1_fck",
3205 .module_offs = CORE_MOD,
3207 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3209 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3212 .dev_attr = &mmc1_pre_es3_dev_attr,
3213 .slaves = omap3xxx_mmc1_slaves,
3214 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3215 .class = &omap34xx_mmc_class,
3218 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
3220 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3221 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3222 .opt_clks = omap34xx_mmc1_opt_clks,
3223 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3224 .main_clk = "mmchs1_fck",
3227 .module_offs = CORE_MOD,
3229 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3231 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3234 .dev_attr = &mmc1_dev_attr,
3235 .slaves = omap3xxx_mmc1_slaves,
3236 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3237 .class = &omap34xx_mmc_class,
3242 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3243 { .irq = INT_24XX_MMC2_IRQ, },
3247 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3248 { .name = "tx", .dma_req = 47, },
3249 { .name = "rx", .dma_req = 48, },
3253 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3254 { .role = "dbck", .clk = "omap_32k_fck", },
3257 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3258 &omap3xxx_l4_core__mmc2,
3261 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3262 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
3263 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
3266 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
3268 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3269 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3270 .opt_clks = omap34xx_mmc2_opt_clks,
3271 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3272 .main_clk = "mmchs2_fck",
3275 .module_offs = CORE_MOD,
3277 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3279 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3282 .dev_attr = &mmc2_pre_es3_dev_attr,
3283 .slaves = omap3xxx_mmc2_slaves,
3284 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3285 .class = &omap34xx_mmc_class,
3288 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
3290 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3291 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3292 .opt_clks = omap34xx_mmc2_opt_clks,
3293 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3294 .main_clk = "mmchs2_fck",
3297 .module_offs = CORE_MOD,
3299 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3301 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3304 .slaves = omap3xxx_mmc2_slaves,
3305 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3306 .class = &omap34xx_mmc_class,
3311 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3316 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3317 { .name = "tx", .dma_req = 77, },
3318 { .name = "rx", .dma_req = 78, },
3322 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3323 { .role = "dbck", .clk = "omap_32k_fck", },
3326 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3327 &omap3xxx_l4_core__mmc3,
3330 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3332 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3333 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3334 .opt_clks = omap34xx_mmc3_opt_clks,
3335 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3336 .main_clk = "mmchs3_fck",
3340 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3342 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3345 .slaves = omap3xxx_mmc3_slaves,
3346 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3347 .class = &omap34xx_mmc_class,
3350 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3351 &omap3xxx_l3_main_hwmod,
3352 &omap3xxx_l4_core_hwmod,
3353 &omap3xxx_l4_per_hwmod,
3354 &omap3xxx_l4_wkup_hwmod,
3355 &omap3xxx_mmc3_hwmod,
3356 &omap3xxx_mpu_hwmod,
3358 &omap3xxx_timer1_hwmod,
3359 &omap3xxx_timer2_hwmod,
3360 &omap3xxx_timer3_hwmod,
3361 &omap3xxx_timer4_hwmod,
3362 &omap3xxx_timer5_hwmod,
3363 &omap3xxx_timer6_hwmod,
3364 &omap3xxx_timer7_hwmod,
3365 &omap3xxx_timer8_hwmod,
3366 &omap3xxx_timer9_hwmod,
3367 &omap3xxx_timer10_hwmod,
3368 &omap3xxx_timer11_hwmod,
3370 &omap3xxx_wd_timer2_hwmod,
3371 &omap3xxx_uart1_hwmod,
3372 &omap3xxx_uart2_hwmod,
3373 &omap3xxx_uart3_hwmod,
3376 &omap3xxx_i2c1_hwmod,
3377 &omap3xxx_i2c2_hwmod,
3378 &omap3xxx_i2c3_hwmod,
3381 &omap3xxx_gpio1_hwmod,
3382 &omap3xxx_gpio2_hwmod,
3383 &omap3xxx_gpio3_hwmod,
3384 &omap3xxx_gpio4_hwmod,
3385 &omap3xxx_gpio5_hwmod,
3386 &omap3xxx_gpio6_hwmod,
3388 /* dma_system class*/
3389 &omap3xxx_dma_system_hwmod,
3392 &omap3xxx_mcbsp1_hwmod,
3393 &omap3xxx_mcbsp2_hwmod,
3394 &omap3xxx_mcbsp3_hwmod,
3395 &omap3xxx_mcbsp4_hwmod,
3396 &omap3xxx_mcbsp5_hwmod,
3397 &omap3xxx_mcbsp2_sidetone_hwmod,
3398 &omap3xxx_mcbsp3_sidetone_hwmod,
3407 &omap34xx_bandgap_ts,
3412 /* GP-only hwmods */
3413 static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
3414 &omap3xxx_timer12_hwmod,
3418 /* 3430ES1-only hwmods */
3419 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
3420 &omap3430es1_dss_core_hwmod,
3424 /* 3430ES2+-only hwmods */
3425 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
3426 &omap3xxx_dss_core_hwmod,
3427 &omap3xxx_usbhsotg_hwmod,
3431 /* <= 3430ES3-only hwmods */
3432 static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
3433 &omap3xxx_pre_es3_mmc1_hwmod,
3434 &omap3xxx_pre_es3_mmc2_hwmod,
3438 /* 3430ES3+-only hwmods */
3439 static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
3440 &omap3xxx_es3plus_mmc1_hwmod,
3441 &omap3xxx_es3plus_mmc2_hwmod,
3445 /* 34xx-only hwmods (all ES revisions) */
3446 static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
3447 &omap3xxx_iva_hwmod,
3448 &omap34xx_sr1_hwmod,
3449 &omap34xx_sr2_hwmod,
3450 &omap3xxx_mailbox_hwmod,
3454 /* 36xx-only hwmods (all ES revisions) */
3455 static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
3456 &omap3xxx_iva_hwmod,
3457 &omap36xx_uart4_hwmod,
3458 &omap3xxx_dss_core_hwmod,
3459 &omap36xx_sr1_hwmod,
3460 &omap36xx_sr2_hwmod,
3461 &omap3xxx_usbhsotg_hwmod,
3462 &omap3xxx_mailbox_hwmod,
3463 &omap3xxx_es3plus_mmc1_hwmod,
3464 &omap3xxx_es3plus_mmc2_hwmod,
3468 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3469 &omap3xxx_dss_core_hwmod, /* XXX ??? */
3470 &am35xx_usbhsotg_hwmod,
3471 &omap3xxx_es3plus_mmc1_hwmod,
3472 &omap3xxx_es3plus_mmc2_hwmod,
3476 static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
3478 &omap3xxx_dss_dispc_hwmod,
3479 &omap3xxx_dss_dsi1_hwmod,
3480 &omap3xxx_dss_rfbi_hwmod,
3481 &omap3xxx_dss_venc_hwmod,
3485 int __init omap3xxx_hwmod_init(void)
3488 struct omap_hwmod **h = NULL;
3491 /* Register hwmods common to all OMAP3 */
3492 r = omap_hwmod_register(omap3xxx_hwmods);
3496 /* Register GP-only hwmods. */
3497 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3498 r = omap_hwmod_register(omap3xxx_gp_hwmods);
3506 * Register hwmods common to individual OMAP3 families, all
3507 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3508 * All possible revisions should be included in this conditional.
3510 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3511 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3512 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3513 h = omap34xx_hwmods;
3514 } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3516 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3517 rev == OMAP3630_REV_ES1_2) {
3518 h = omap36xx_hwmods;
3520 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3524 r = omap_hwmod_register(h);
3529 * Register hwmods specific to certain ES levels of a
3530 * particular family of silicon (e.g., 34xx ES1.0)
3533 if (rev == OMAP3430_REV_ES1_0) {
3534 h = omap3430es1_hwmods;
3535 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3536 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3537 rev == OMAP3430_REV_ES3_1_2) {
3538 h = omap3430es2plus_hwmods;
3542 r = omap_hwmod_register(h);
3548 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3549 rev == OMAP3430_REV_ES2_1) {
3550 h = omap3430_pre_es3_hwmods;
3551 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3552 rev == OMAP3430_REV_ES3_1_2) {
3553 h = omap3430_es3plus_hwmods;
3557 r = omap_hwmod_register(h);
3562 * DSS code presumes that dss_core hwmod is handled first,
3563 * _before_ any other DSS related hwmods so register common
3564 * DSS hwmods last to ensure that dss_core is already registered.
3565 * Otherwise some change things may happen, for ex. if dispc
3566 * is handled before dss_core and DSS is enabled in bootloader
3567 * DIPSC will be reset with outputs enabled which sometimes leads
3568 * to unrecoverable L3 error.
3570 r = omap_hwmod_register(omap3xxx_dss_hwmods);