arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "smartreflex.h"
  33 #include "prm-regbits-34xx.h"
  34 #include "cm-regbits-34xx.h"
  35 #include "wd_timer.h"
  36 #include <mach/am35xx.h>
  37
  38 /*
  39  * OMAP3xxx hardware module integration data
  40  *
  41  * ALl of the data in this section should be autogeneratable from the
  42  * TI hardware database or other technical documentation.  Data that
  43  * is driver-specific or driver-kernel integration-specific belongs
  44  * elsewhere.
  45  */
  46
  47 static struct omap_hwmod omap3xxx_mpu_hwmod;
  48 static struct omap_hwmod omap3xxx_iva_hwmod;
  49 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  51 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  52 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  53 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  58 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  61 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  67 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  68 static struct omap_hwmod omap34xx_sr1_hwmod;
  69 static struct omap_hwmod omap36xx_sr1_hwmod;
  70 static struct omap_hwmod omap34xx_sr2_hwmod;
  71 static struct omap_hwmod omap36xx_sr2_hwmod;
  72 static struct omap_hwmod omap34xx_mcspi1;
  73 static struct omap_hwmod omap34xx_mcspi2;
  74 static struct omap_hwmod omap34xx_mcspi3;
  75 static struct omap_hwmod omap34xx_mcspi4;
  76 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  77 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  78 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  79 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  80
  81 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  82
  83 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  87 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  88 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  89 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  90
  91 /* L3 -> L4_CORE interface */
  92 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  93         .master = &omap3xxx_l3_main_hwmod,
  94         .slave  = &omap3xxx_l4_core_hwmod,
  95         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  96 };
  97
  98 /* L3 -> L4_PER interface */
  99 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
 100         .master = &omap3xxx_l3_main_hwmod,
 101         .slave  = &omap3xxx_l4_per_hwmod,
 102         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 103 };
 104
 105 /* L3 taret configuration and error log registers */
 106 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 107         { .irq = INT_34XX_L3_DBG_IRQ },
 108         { .irq = INT_34XX_L3_APP_IRQ },
 109         { .irq = -1 }
 110 };
 111
 112 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 113         {
 114                 .pa_start       = 0x68000000,
 115                 .pa_end         = 0x6800ffff,
 116                 .flags          = ADDR_TYPE_RT,
 117         },
 118         { }
 119 };
 120
 121 /* MPU -> L3 interface */
 122 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 123         .master   = &omap3xxx_mpu_hwmod,
 124         .slave    = &omap3xxx_l3_main_hwmod,
 125         .addr     = omap3xxx_l3_main_addrs,
 126         .user   = OCP_USER_MPU,
 127 };
 128
 129 /* Slave interfaces on the L3 interconnect */
 130 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 131         &omap3xxx_mpu__l3_main,
 132 };
 133
 134 /* DSS -> l3 */
 135 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 136         .master         = &omap3xxx_dss_core_hwmod,
 137         .slave          = &omap3xxx_l3_main_hwmod,
 138         .fw = {
 139                 .omap2 = {
 140                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 141                         .flags  = OMAP_FIREWALL_L3,
 142                 }
 143         },
 144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 145 };
 146
 147 /* Master interfaces on the L3 interconnect */
 148 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 149         &omap3xxx_l3_main__l4_core,
 150         &omap3xxx_l3_main__l4_per,
 151 };
 152
 153 /* L3 */
 154 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 155         .name           = "l3_main",
 156         .class          = &l3_hwmod_class,
 157         .mpu_irqs       = omap3xxx_l3_main_irqs,
 158         .masters        = omap3xxx_l3_main_masters,
 159         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 160         .slaves         = omap3xxx_l3_main_slaves,
 161         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 162         .flags          = HWMOD_NO_IDLEST,
 163 };
 164
 165 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 166 static struct omap_hwmod omap3xxx_uart1_hwmod;
 167 static struct omap_hwmod omap3xxx_uart2_hwmod;
 168 static struct omap_hwmod omap3xxx_uart3_hwmod;
 169 static struct omap_hwmod omap36xx_uart4_hwmod;
 170 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 171
 172 /* l3_core -> usbhsotg interface */
 173 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 174         .master         = &omap3xxx_usbhsotg_hwmod,
 175         .slave          = &omap3xxx_l3_main_hwmod,
 176         .clk            = "core_l3_ick",
 177         .user           = OCP_USER_MPU,
 178 };
 179
 180 /* l3_core -> am35xx_usbhsotg interface */
 181 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 182         .master         = &am35xx_usbhsotg_hwmod,
 183         .slave          = &omap3xxx_l3_main_hwmod,
 184         .clk            = "core_l3_ick",
 185         .user           = OCP_USER_MPU,
 186 };
 187 /* L4_CORE -> L4_WKUP interface */
 188 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 189         .master = &omap3xxx_l4_core_hwmod,
 190         .slave  = &omap3xxx_l4_wkup_hwmod,
 191         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 192 };
 193
 194 /* L4 CORE -> MMC1 interface */
 195 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 196         .master         = &omap3xxx_l4_core_hwmod,
 197         .slave          = &omap3xxx_mmc1_hwmod,
 198         .clk            = "mmchs1_ick",
 199         .addr           = omap2430_mmc1_addr_space,
 200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 201         .flags          = OMAP_FIREWALL_L4
 202 };
 203
 204 /* L4 CORE -> MMC2 interface */
 205 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 206         .master         = &omap3xxx_l4_core_hwmod,
 207         .slave          = &omap3xxx_mmc2_hwmod,
 208         .clk            = "mmchs2_ick",
 209         .addr           = omap2430_mmc2_addr_space,
 210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 211         .flags          = OMAP_FIREWALL_L4
 212 };
 213
 214 /* L4 CORE -> MMC3 interface */
 215 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 216         {
 217                 .pa_start       = 0x480ad000,
 218                 .pa_end         = 0x480ad1ff,
 219                 .flags          = ADDR_TYPE_RT,
 220         },
 221         { }
 222 };
 223
 224 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 225         .master         = &omap3xxx_l4_core_hwmod,
 226         .slave          = &omap3xxx_mmc3_hwmod,
 227         .clk            = "mmchs3_ick",
 228         .addr           = omap3xxx_mmc3_addr_space,
 229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 230         .flags          = OMAP_FIREWALL_L4
 231 };
 232
 233 /* L4 CORE -> UART1 interface */
 234 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 235         {
 236                 .pa_start       = OMAP3_UART1_BASE,
 237                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 238                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 239         },
 240         { }
 241 };
 242
 243 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 244         .master         = &omap3xxx_l4_core_hwmod,
 245         .slave          = &omap3xxx_uart1_hwmod,
 246         .clk            = "uart1_ick",
 247         .addr           = omap3xxx_uart1_addr_space,
 248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 249 };
 250
 251 /* L4 CORE -> UART2 interface */
 252 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 253         {
 254                 .pa_start       = OMAP3_UART2_BASE,
 255                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 256                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 257         },
 258         { }
 259 };
 260
 261 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 262         .master         = &omap3xxx_l4_core_hwmod,
 263         .slave          = &omap3xxx_uart2_hwmod,
 264         .clk            = "uart2_ick",
 265         .addr           = omap3xxx_uart2_addr_space,
 266         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 267 };
 268
 269 /* L4 PER -> UART3 interface */
 270 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 271         {
 272                 .pa_start       = OMAP3_UART3_BASE,
 273                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 274                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 275         },
 276         { }
 277 };
 278
 279 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 280         .master         = &omap3xxx_l4_per_hwmod,
 281         .slave          = &omap3xxx_uart3_hwmod,
 282         .clk            = "uart3_ick",
 283         .addr           = omap3xxx_uart3_addr_space,
 284         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 285 };
 286
 287 /* L4 PER -> UART4 interface */
 288 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
 289         {
 290                 .pa_start       = OMAP3_UART4_BASE,
 291                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 292                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 293         },
 294         { }
 295 };
 296
 297 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
 298         .master         = &omap3xxx_l4_per_hwmod,
 299         .slave          = &omap36xx_uart4_hwmod,
 300         .clk            = "uart4_ick",
 301         .addr           = omap36xx_uart4_addr_space,
 302         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 303 };
 304
 305 /* L4 CORE -> I2C1 interface */
 306 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 307         .master         = &omap3xxx_l4_core_hwmod,
 308         .slave          = &omap3xxx_i2c1_hwmod,
 309         .clk            = "i2c1_ick",
 310         .addr           = omap2_i2c1_addr_space,
 311         .fw = {
 312                 .omap2 = {
 313                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 314                         .l4_prot_group = 7,
 315                         .flags  = OMAP_FIREWALL_L4,
 316                 }
 317         },
 318         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 319 };
 320
 321 /* L4 CORE -> I2C2 interface */
 322 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 323         .master         = &omap3xxx_l4_core_hwmod,
 324         .slave          = &omap3xxx_i2c2_hwmod,
 325         .clk            = "i2c2_ick",
 326         .addr           = omap2_i2c2_addr_space,
 327         .fw = {
 328                 .omap2 = {
 329                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 330                         .l4_prot_group = 7,
 331                         .flags = OMAP_FIREWALL_L4,
 332                 }
 333         },
 334         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 335 };
 336
 337 /* L4 CORE -> I2C3 interface */
 338 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 339         {
 340                 .pa_start       = 0x48060000,
 341                 .pa_end         = 0x48060000 + SZ_128 - 1,
 342                 .flags          = ADDR_TYPE_RT,
 343         },
 344         { }
 345 };
 346
 347 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 348         .master         = &omap3xxx_l4_core_hwmod,
 349         .slave          = &omap3xxx_i2c3_hwmod,
 350         .clk            = "i2c3_ick",
 351         .addr           = omap3xxx_i2c3_addr_space,
 352         .fw = {
 353                 .omap2 = {
 354                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 355                         .l4_prot_group = 7,
 356                         .flags = OMAP_FIREWALL_L4,
 357                 }
 358         },
 359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 360 };
 361
 362 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
 363         { .irq = 18},
 364         { .irq = -1 }
 365 };
 366
 367 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
 368         { .irq = 19},
 369         { .irq = -1 }
 370 };
 371
 372 /* L4 CORE -> SR1 interface */
 373 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 374         {
 375                 .pa_start       = OMAP34XX_SR1_BASE,
 376                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 377                 .flags          = ADDR_TYPE_RT,
 378         },
 379         { }
 380 };
 381
 382 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
 383         .master         = &omap3xxx_l4_core_hwmod,
 384         .slave          = &omap34xx_sr1_hwmod,
 385         .clk            = "sr_l4_ick",
 386         .addr           = omap3_sr1_addr_space,
 387         .user           = OCP_USER_MPU,
 388 };
 389
 390 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
 391         .master         = &omap3xxx_l4_core_hwmod,
 392         .slave          = &omap36xx_sr1_hwmod,
 393         .clk            = "sr_l4_ick",
 394         .addr           = omap3_sr1_addr_space,
 395         .user           = OCP_USER_MPU,
 396 };
 397
 398 /* L4 CORE -> SR1 interface */
 399 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 400         {
 401                 .pa_start       = OMAP34XX_SR2_BASE,
 402                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 403                 .flags          = ADDR_TYPE_RT,
 404         },
 405         { }
 406 };
 407
 408 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
 409         .master         = &omap3xxx_l4_core_hwmod,
 410         .slave          = &omap34xx_sr2_hwmod,
 411         .clk            = "sr_l4_ick",
 412         .addr           = omap3_sr2_addr_space,
 413         .user           = OCP_USER_MPU,
 414 };
 415
 416 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
 417         .master         = &omap3xxx_l4_core_hwmod,
 418         .slave          = &omap36xx_sr2_hwmod,
 419         .clk            = "sr_l4_ick",
 420         .addr           = omap3_sr2_addr_space,
 421         .user           = OCP_USER_MPU,
 422 };
 423
 424 /*
 425 * usbhsotg interface data
 426 */
 427
 428 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 429         {
 430                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 431                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 432                 .flags          = ADDR_TYPE_RT
 433         },
 434         { }
 435 };
 436
 437 /* l4_core -> usbhsotg  */
 438 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 439         .master         = &omap3xxx_l4_core_hwmod,
 440         .slave          = &omap3xxx_usbhsotg_hwmod,
 441         .clk            = "l4_ick",
 442         .addr           = omap3xxx_usbhsotg_addrs,
 443         .user           = OCP_USER_MPU,
 444 };
 445
 446 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 447         &omap3xxx_usbhsotg__l3,
 448 };
 449
 450 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 451         &omap3xxx_l4_core__usbhsotg,
 452 };
 453
 454 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 455         {
 456                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 457                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 458                 .flags          = ADDR_TYPE_RT
 459         },
 460         { }
 461 };
 462
 463 /* l4_core -> usbhsotg  */
 464 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 465         .master         = &omap3xxx_l4_core_hwmod,
 466         .slave          = &am35xx_usbhsotg_hwmod,
 467         .clk            = "l4_ick",
 468         .addr           = am35xx_usbhsotg_addrs,
 469         .user           = OCP_USER_MPU,
 470 };
 471
 472 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 473         &am35xx_usbhsotg__l3,
 474 };
 475
 476 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 477         &am35xx_l4_core__usbhsotg,
 478 };
 479 /* Slave interfaces on the L4_CORE interconnect */
 480 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 481         &omap3xxx_l3_main__l4_core,
 482 };
 483
 484 /* L4 CORE */
 485 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 486         .name           = "l4_core",
 487         .class          = &l4_hwmod_class,
 488         .slaves         = omap3xxx_l4_core_slaves,
 489         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 490         .flags          = HWMOD_NO_IDLEST,
 491 };
 492
 493 /* Slave interfaces on the L4_PER interconnect */
 494 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 495         &omap3xxx_l3_main__l4_per,
 496 };
 497
 498 /* L4 PER */
 499 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 500         .name           = "l4_per",
 501         .class          = &l4_hwmod_class,
 502         .slaves         = omap3xxx_l4_per_slaves,
 503         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 504         .flags          = HWMOD_NO_IDLEST,
 505 };
 506
 507 /* Slave interfaces on the L4_WKUP interconnect */
 508 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 509         &omap3xxx_l4_core__l4_wkup,
 510 };
 511
 512 /* L4 WKUP */
 513 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 514         .name           = "l4_wkup",
 515         .class          = &l4_hwmod_class,
 516         .slaves         = omap3xxx_l4_wkup_slaves,
 517         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 518         .flags          = HWMOD_NO_IDLEST,
 519 };
 520
 521 /* Master interfaces on the MPU device */
 522 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 523         &omap3xxx_mpu__l3_main,
 524 };
 525
 526 /* MPU */
 527 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 528         .name           = "mpu",
 529         .class          = &mpu_hwmod_class,
 530         .main_clk       = "arm_fck",
 531         .masters        = omap3xxx_mpu_masters,
 532         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 533 };
 534
 535 /*
 536  * IVA2_2 interface data
 537  */
 538
 539 /* IVA2 <- L3 interface */
 540 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 541         .master         = &omap3xxx_l3_main_hwmod,
 542         .slave          = &omap3xxx_iva_hwmod,
 543         .clk            = "iva2_ck",
 544         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 545 };
 546
 547 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 548         &omap3xxx_l3__iva,
 549 };
 550
 551 /*
 552  * IVA2 (IVA2)
 553  */
 554
 555 static struct omap_hwmod omap3xxx_iva_hwmod = {
 556         .name           = "iva",
 557         .class          = &iva_hwmod_class,
 558         .masters        = omap3xxx_iva_masters,
 559         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 560 };
 561
 562 /* timer class */
 563 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 564         .rev_offs       = 0x0000,
 565         .sysc_offs      = 0x0010,
 566         .syss_offs      = 0x0014,
 567         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 568                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 569                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 570         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 571         .sysc_fields    = &omap_hwmod_sysc_type1,
 572 };
 573
 574 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 575         .name = "timer",
 576         .sysc = &omap3xxx_timer_1ms_sysc,
 577         .rev = OMAP_TIMER_IP_VERSION_1,
 578 };
 579
 580 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 581         .rev_offs       = 0x0000,
 582         .sysc_offs      = 0x0010,
 583         .syss_offs      = 0x0014,
 584         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 585                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 586         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 587         .sysc_fields    = &omap_hwmod_sysc_type1,
 588 };
 589
 590 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 591         .name = "timer",
 592         .sysc = &omap3xxx_timer_sysc,
 593         .rev =  OMAP_TIMER_IP_VERSION_1,
 594 };
 595
 596 /* secure timers dev attribute */
 597 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 598         .timer_capability       = OMAP_TIMER_SECURE,
 599 };
 600
 601 /* always-on timers dev attribute */
 602 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 603         .timer_capability       = OMAP_TIMER_ALWON,
 604 };
 605
 606 /* pwm timers dev attribute */
 607 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 608         .timer_capability       = OMAP_TIMER_HAS_PWM,
 609 };
 610
 611 /* timer1 */
 612 static struct omap_hwmod omap3xxx_timer1_hwmod;
 613
 614 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 615         {
 616                 .pa_start       = 0x48318000,
 617                 .pa_end         = 0x48318000 + SZ_1K - 1,
 618                 .flags          = ADDR_TYPE_RT
 619         },
 620         { }
 621 };
 622
 623 /* l4_wkup -> timer1 */
 624 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 625         .master         = &omap3xxx_l4_wkup_hwmod,
 626         .slave          = &omap3xxx_timer1_hwmod,
 627         .clk            = "gpt1_ick",
 628         .addr           = omap3xxx_timer1_addrs,
 629         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 630 };
 631
 632 /* timer1 slave port */
 633 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 634         &omap3xxx_l4_wkup__timer1,
 635 };
 636
 637 /* timer1 hwmod */
 638 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 639         .name           = "timer1",
 640         .mpu_irqs       = omap2_timer1_mpu_irqs,
 641         .main_clk       = "gpt1_fck",
 642         .prcm           = {
 643                 .omap2 = {
 644                         .prcm_reg_id = 1,
 645                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 646                         .module_offs = WKUP_MOD,
 647                         .idlest_reg_id = 1,
 648                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 649                 },
 650         },
 651         .dev_attr       = &capability_alwon_dev_attr,
 652         .slaves         = omap3xxx_timer1_slaves,
 653         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 654         .class          = &omap3xxx_timer_1ms_hwmod_class,
 655 };
 656
 657 /* timer2 */
 658 static struct omap_hwmod omap3xxx_timer2_hwmod;
 659
 660 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 661         {
 662                 .pa_start       = 0x49032000,
 663                 .pa_end         = 0x49032000 + SZ_1K - 1,
 664                 .flags          = ADDR_TYPE_RT
 665         },
 666         { }
 667 };
 668
 669 /* l4_per -> timer2 */
 670 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 671         .master         = &omap3xxx_l4_per_hwmod,
 672         .slave          = &omap3xxx_timer2_hwmod,
 673         .clk            = "gpt2_ick",
 674         .addr           = omap3xxx_timer2_addrs,
 675         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 676 };
 677
 678 /* timer2 slave port */
 679 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 680         &omap3xxx_l4_per__timer2,
 681 };
 682
 683 /* timer2 hwmod */
 684 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 685         .name           = "timer2",
 686         .mpu_irqs       = omap2_timer2_mpu_irqs,
 687         .main_clk       = "gpt2_fck",
 688         .prcm           = {
 689                 .omap2 = {
 690                         .prcm_reg_id = 1,
 691                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 692                         .module_offs = OMAP3430_PER_MOD,
 693                         .idlest_reg_id = 1,
 694                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 695                 },
 696         },
 697         .dev_attr       = &capability_alwon_dev_attr,
 698         .slaves         = omap3xxx_timer2_slaves,
 699         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 700         .class          = &omap3xxx_timer_1ms_hwmod_class,
 701 };
 702
 703 /* timer3 */
 704 static struct omap_hwmod omap3xxx_timer3_hwmod;
 705
 706 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 707         {
 708                 .pa_start       = 0x49034000,
 709                 .pa_end         = 0x49034000 + SZ_1K - 1,
 710                 .flags          = ADDR_TYPE_RT
 711         },
 712         { }
 713 };
 714
 715 /* l4_per -> timer3 */
 716 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 717         .master         = &omap3xxx_l4_per_hwmod,
 718         .slave          = &omap3xxx_timer3_hwmod,
 719         .clk            = "gpt3_ick",
 720         .addr           = omap3xxx_timer3_addrs,
 721         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 722 };
 723
 724 /* timer3 slave port */
 725 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 726         &omap3xxx_l4_per__timer3,
 727 };
 728
 729 /* timer3 hwmod */
 730 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 731         .name           = "timer3",
 732         .mpu_irqs       = omap2_timer3_mpu_irqs,
 733         .main_clk       = "gpt3_fck",
 734         .prcm           = {
 735                 .omap2 = {
 736                         .prcm_reg_id = 1,
 737                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 738                         .module_offs = OMAP3430_PER_MOD,
 739                         .idlest_reg_id = 1,
 740                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 741                 },
 742         },
 743         .dev_attr       = &capability_alwon_dev_attr,
 744         .slaves         = omap3xxx_timer3_slaves,
 745         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 746         .class          = &omap3xxx_timer_hwmod_class,
 747 };
 748
 749 /* timer4 */
 750 static struct omap_hwmod omap3xxx_timer4_hwmod;
 751
 752 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 753         {
 754                 .pa_start       = 0x49036000,
 755                 .pa_end         = 0x49036000 + SZ_1K - 1,
 756                 .flags          = ADDR_TYPE_RT
 757         },
 758         { }
 759 };
 760
 761 /* l4_per -> timer4 */
 762 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 763         .master         = &omap3xxx_l4_per_hwmod,
 764         .slave          = &omap3xxx_timer4_hwmod,
 765         .clk            = "gpt4_ick",
 766         .addr           = omap3xxx_timer4_addrs,
 767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 768 };
 769
 770 /* timer4 slave port */
 771 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 772         &omap3xxx_l4_per__timer4,
 773 };
 774
 775 /* timer4 hwmod */
 776 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 777         .name           = "timer4",
 778         .mpu_irqs       = omap2_timer4_mpu_irqs,
 779         .main_clk       = "gpt4_fck",
 780         .prcm           = {
 781                 .omap2 = {
 782                         .prcm_reg_id = 1,
 783                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 784                         .module_offs = OMAP3430_PER_MOD,
 785                         .idlest_reg_id = 1,
 786                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 787                 },
 788         },
 789         .dev_attr       = &capability_alwon_dev_attr,
 790         .slaves         = omap3xxx_timer4_slaves,
 791         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 792         .class          = &omap3xxx_timer_hwmod_class,
 793 };
 794
 795 /* timer5 */
 796 static struct omap_hwmod omap3xxx_timer5_hwmod;
 797
 798 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 799         {
 800                 .pa_start       = 0x49038000,
 801                 .pa_end         = 0x49038000 + SZ_1K - 1,
 802                 .flags          = ADDR_TYPE_RT
 803         },
 804         { }
 805 };
 806
 807 /* l4_per -> timer5 */
 808 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 809         .master         = &omap3xxx_l4_per_hwmod,
 810         .slave          = &omap3xxx_timer5_hwmod,
 811         .clk            = "gpt5_ick",
 812         .addr           = omap3xxx_timer5_addrs,
 813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 814 };
 815
 816 /* timer5 slave port */
 817 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 818         &omap3xxx_l4_per__timer5,
 819 };
 820
 821 /* timer5 hwmod */
 822 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 823         .name           = "timer5",
 824         .mpu_irqs       = omap2_timer5_mpu_irqs,
 825         .main_clk       = "gpt5_fck",
 826         .prcm           = {
 827                 .omap2 = {
 828                         .prcm_reg_id = 1,
 829                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 830                         .module_offs = OMAP3430_PER_MOD,
 831                         .idlest_reg_id = 1,
 832                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 833                 },
 834         },
 835         .dev_attr       = &capability_alwon_dev_attr,
 836         .slaves         = omap3xxx_timer5_slaves,
 837         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 838         .class          = &omap3xxx_timer_hwmod_class,
 839 };
 840
 841 /* timer6 */
 842 static struct omap_hwmod omap3xxx_timer6_hwmod;
 843
 844 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 845         {
 846                 .pa_start       = 0x4903A000,
 847                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 848                 .flags          = ADDR_TYPE_RT
 849         },
 850         { }
 851 };
 852
 853 /* l4_per -> timer6 */
 854 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 855         .master         = &omap3xxx_l4_per_hwmod,
 856         .slave          = &omap3xxx_timer6_hwmod,
 857         .clk            = "gpt6_ick",
 858         .addr           = omap3xxx_timer6_addrs,
 859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 860 };
 861
 862 /* timer6 slave port */
 863 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 864         &omap3xxx_l4_per__timer6,
 865 };
 866
 867 /* timer6 hwmod */
 868 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 869         .name           = "timer6",
 870         .mpu_irqs       = omap2_timer6_mpu_irqs,
 871         .main_clk       = "gpt6_fck",
 872         .prcm           = {
 873                 .omap2 = {
 874                         .prcm_reg_id = 1,
 875                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 876                         .module_offs = OMAP3430_PER_MOD,
 877                         .idlest_reg_id = 1,
 878                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 879                 },
 880         },
 881         .dev_attr       = &capability_alwon_dev_attr,
 882         .slaves         = omap3xxx_timer6_slaves,
 883         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 884         .class          = &omap3xxx_timer_hwmod_class,
 885 };
 886
 887 /* timer7 */
 888 static struct omap_hwmod omap3xxx_timer7_hwmod;
 889
 890 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 891         {
 892                 .pa_start       = 0x4903C000,
 893                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 894                 .flags          = ADDR_TYPE_RT
 895         },
 896         { }
 897 };
 898
 899 /* l4_per -> timer7 */
 900 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 901         .master         = &omap3xxx_l4_per_hwmod,
 902         .slave          = &omap3xxx_timer7_hwmod,
 903         .clk            = "gpt7_ick",
 904         .addr           = omap3xxx_timer7_addrs,
 905         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 906 };
 907
 908 /* timer7 slave port */
 909 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 910         &omap3xxx_l4_per__timer7,
 911 };
 912
 913 /* timer7 hwmod */
 914 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 915         .name           = "timer7",
 916         .mpu_irqs       = omap2_timer7_mpu_irqs,
 917         .main_clk       = "gpt7_fck",
 918         .prcm           = {
 919                 .omap2 = {
 920                         .prcm_reg_id = 1,
 921                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 922                         .module_offs = OMAP3430_PER_MOD,
 923                         .idlest_reg_id = 1,
 924                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 925                 },
 926         },
 927         .dev_attr       = &capability_alwon_dev_attr,
 928         .slaves         = omap3xxx_timer7_slaves,
 929         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 930         .class          = &omap3xxx_timer_hwmod_class,
 931 };
 932
 933 /* timer8 */
 934 static struct omap_hwmod omap3xxx_timer8_hwmod;
 935
 936 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 937         {
 938                 .pa_start       = 0x4903E000,
 939                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 940                 .flags          = ADDR_TYPE_RT
 941         },
 942         { }
 943 };
 944
 945 /* l4_per -> timer8 */
 946 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 947         .master         = &omap3xxx_l4_per_hwmod,
 948         .slave          = &omap3xxx_timer8_hwmod,
 949         .clk            = "gpt8_ick",
 950         .addr           = omap3xxx_timer8_addrs,
 951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 952 };
 953
 954 /* timer8 slave port */
 955 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 956         &omap3xxx_l4_per__timer8,
 957 };
 958
 959 /* timer8 hwmod */
 960 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 961         .name           = "timer8",
 962         .mpu_irqs       = omap2_timer8_mpu_irqs,
 963         .main_clk       = "gpt8_fck",
 964         .prcm           = {
 965                 .omap2 = {
 966                         .prcm_reg_id = 1,
 967                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 968                         .module_offs = OMAP3430_PER_MOD,
 969                         .idlest_reg_id = 1,
 970                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 971                 },
 972         },
 973         .dev_attr       = &capability_pwm_dev_attr,
 974         .slaves         = omap3xxx_timer8_slaves,
 975         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
 976         .class          = &omap3xxx_timer_hwmod_class,
 977 };
 978
 979 /* timer9 */
 980 static struct omap_hwmod omap3xxx_timer9_hwmod;
 981
 982 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
 983         {
 984                 .pa_start       = 0x49040000,
 985                 .pa_end         = 0x49040000 + SZ_1K - 1,
 986                 .flags          = ADDR_TYPE_RT
 987         },
 988         { }
 989 };
 990
 991 /* l4_per -> timer9 */
 992 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
 993         .master         = &omap3xxx_l4_per_hwmod,
 994         .slave          = &omap3xxx_timer9_hwmod,
 995         .clk            = "gpt9_ick",
 996         .addr           = omap3xxx_timer9_addrs,
 997         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 998 };
 999
1000 /* timer9 slave port */
1001 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1002         &omap3xxx_l4_per__timer9,
1003 };
1004
1005 /* timer9 hwmod */
1006 static struct omap_hwmod omap3xxx_timer9_hwmod = {
1007         .name           = "timer9",
1008         .mpu_irqs       = omap2_timer9_mpu_irqs,
1009         .main_clk       = "gpt9_fck",
1010         .prcm           = {
1011                 .omap2 = {
1012                         .prcm_reg_id = 1,
1013                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
1014                         .module_offs = OMAP3430_PER_MOD,
1015                         .idlest_reg_id = 1,
1016                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1017                 },
1018         },
1019         .dev_attr       = &capability_pwm_dev_attr,
1020         .slaves         = omap3xxx_timer9_slaves,
1021         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
1022         .class          = &omap3xxx_timer_hwmod_class,
1023 };
1024
1025 /* timer10 */
1026 static struct omap_hwmod omap3xxx_timer10_hwmod;
1027
1028 /* l4_core -> timer10 */
1029 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1030         .master         = &omap3xxx_l4_core_hwmod,
1031         .slave          = &omap3xxx_timer10_hwmod,
1032         .clk            = "gpt10_ick",
1033         .addr           = omap2_timer10_addrs,
1034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1035 };
1036
1037 /* timer10 slave port */
1038 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1039         &omap3xxx_l4_core__timer10,
1040 };
1041
1042 /* timer10 hwmod */
1043 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1044         .name           = "timer10",
1045         .mpu_irqs       = omap2_timer10_mpu_irqs,
1046         .main_clk       = "gpt10_fck",
1047         .prcm           = {
1048                 .omap2 = {
1049                         .prcm_reg_id = 1,
1050                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1051                         .module_offs = CORE_MOD,
1052                         .idlest_reg_id = 1,
1053                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1054                 },
1055         },
1056         .dev_attr       = &capability_pwm_dev_attr,
1057         .slaves         = omap3xxx_timer10_slaves,
1058         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1059         .class          = &omap3xxx_timer_1ms_hwmod_class,
1060 };
1061
1062 /* timer11 */
1063 static struct omap_hwmod omap3xxx_timer11_hwmod;
1064
1065 /* l4_core -> timer11 */
1066 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1067         .master         = &omap3xxx_l4_core_hwmod,
1068         .slave          = &omap3xxx_timer11_hwmod,
1069         .clk            = "gpt11_ick",
1070         .addr           = omap2_timer11_addrs,
1071         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1072 };
1073
1074 /* timer11 slave port */
1075 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1076         &omap3xxx_l4_core__timer11,
1077 };
1078
1079 /* timer11 hwmod */
1080 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1081         .name           = "timer11",
1082         .mpu_irqs       = omap2_timer11_mpu_irqs,
1083         .main_clk       = "gpt11_fck",
1084         .prcm           = {
1085                 .omap2 = {
1086                         .prcm_reg_id = 1,
1087                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1088                         .module_offs = CORE_MOD,
1089                         .idlest_reg_id = 1,
1090                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1091                 },
1092         },
1093         .dev_attr       = &capability_pwm_dev_attr,
1094         .slaves         = omap3xxx_timer11_slaves,
1095         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1096         .class          = &omap3xxx_timer_hwmod_class,
1097 };
1098
1099 /* timer12 */
1100 static struct omap_hwmod omap3xxx_timer12_hwmod;
1101 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1102         { .irq = 95, },
1103         { .irq = -1 }
1104 };
1105
1106 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1107         {
1108                 .pa_start       = 0x48304000,
1109                 .pa_end         = 0x48304000 + SZ_1K - 1,
1110                 .flags          = ADDR_TYPE_RT
1111         },
1112         { }
1113 };
1114
1115 /* l4_core -> timer12 */
1116 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1117         .master         = &omap3xxx_l4_core_hwmod,
1118         .slave          = &omap3xxx_timer12_hwmod,
1119         .clk            = "gpt12_ick",
1120         .addr           = omap3xxx_timer12_addrs,
1121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1122 };
1123
1124 /* timer12 slave port */
1125 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1126         &omap3xxx_l4_core__timer12,
1127 };
1128
1129 /* timer12 hwmod */
1130 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1131         .name           = "timer12",
1132         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1133         .main_clk       = "gpt12_fck",
1134         .prcm           = {
1135                 .omap2 = {
1136                         .prcm_reg_id = 1,
1137                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1138                         .module_offs = WKUP_MOD,
1139                         .idlest_reg_id = 1,
1140                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1141                 },
1142         },
1143         .dev_attr       = &capability_secure_dev_attr,
1144         .slaves         = omap3xxx_timer12_slaves,
1145         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1146         .class          = &omap3xxx_timer_hwmod_class,
1147 };
1148
1149 /* l4_wkup -> wd_timer2 */
1150 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1151         {
1152                 .pa_start       = 0x48314000,
1153                 .pa_end         = 0x4831407f,
1154                 .flags          = ADDR_TYPE_RT
1155         },
1156         { }
1157 };
1158
1159 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1160         .master         = &omap3xxx_l4_wkup_hwmod,
1161         .slave          = &omap3xxx_wd_timer2_hwmod,
1162         .clk            = "wdt2_ick",
1163         .addr           = omap3xxx_wd_timer2_addrs,
1164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1165 };
1166
1167 /*
1168  * 'wd_timer' class
1169  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1170  * overflow condition
1171  */
1172
1173 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1174         .rev_offs       = 0x0000,
1175         .sysc_offs      = 0x0010,
1176         .syss_offs      = 0x0014,
1177         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1178                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1179                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1180                            SYSS_HAS_RESET_STATUS),
1181         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1182         .sysc_fields    = &omap_hwmod_sysc_type1,
1183 };
1184
1185 /* I2C common */
1186 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1187         .rev_offs       = 0x00,
1188         .sysc_offs      = 0x20,
1189         .syss_offs      = 0x10,
1190         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1191                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1192                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1193         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1194         .sysc_fields    = &omap_hwmod_sysc_type1,
1195 };
1196
1197 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1198         .name           = "wd_timer",
1199         .sysc           = &omap3xxx_wd_timer_sysc,
1200         .pre_shutdown   = &omap2_wd_timer_disable
1201 };
1202
1203 /* wd_timer2 */
1204 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1205         &omap3xxx_l4_wkup__wd_timer2,
1206 };
1207
1208 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1209         .name           = "wd_timer2",
1210         .class          = &omap3xxx_wd_timer_hwmod_class,
1211         .main_clk       = "wdt2_fck",
1212         .prcm           = {
1213                 .omap2 = {
1214                         .prcm_reg_id = 1,
1215                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1216                         .module_offs = WKUP_MOD,
1217                         .idlest_reg_id = 1,
1218                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1219                 },
1220         },
1221         .slaves         = omap3xxx_wd_timer2_slaves,
1222         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1223         /*
1224          * XXX: Use software supervised mode, HW supervised smartidle seems to
1225          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1226          */
1227         .flags          = HWMOD_SWSUP_SIDLE,
1228 };
1229
1230 /* UART1 */
1231
1232 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1233         &omap3_l4_core__uart1,
1234 };
1235
1236 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1237         .name           = "uart1",
1238         .mpu_irqs       = omap2_uart1_mpu_irqs,
1239         .sdma_reqs      = omap2_uart1_sdma_reqs,
1240         .main_clk       = "uart1_fck",
1241         .prcm           = {
1242                 .omap2 = {
1243                         .module_offs = CORE_MOD,
1244                         .prcm_reg_id = 1,
1245                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1246                         .idlest_reg_id = 1,
1247                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1248                 },
1249         },
1250         .slaves         = omap3xxx_uart1_slaves,
1251         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1252         .class          = &omap2_uart_class,
1253 };
1254
1255 /* UART2 */
1256
1257 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1258         &omap3_l4_core__uart2,
1259 };
1260
1261 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1262         .name           = "uart2",
1263         .mpu_irqs       = omap2_uart2_mpu_irqs,
1264         .sdma_reqs      = omap2_uart2_sdma_reqs,
1265         .main_clk       = "uart2_fck",
1266         .prcm           = {
1267                 .omap2 = {
1268                         .module_offs = CORE_MOD,
1269                         .prcm_reg_id = 1,
1270                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1271                         .idlest_reg_id = 1,
1272                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1273                 },
1274         },
1275         .slaves         = omap3xxx_uart2_slaves,
1276         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1277         .class          = &omap2_uart_class,
1278 };
1279
1280 /* UART3 */
1281
1282 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1283         &omap3_l4_per__uart3,
1284 };
1285
1286 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1287         .name           = "uart3",
1288         .mpu_irqs       = omap2_uart3_mpu_irqs,
1289         .sdma_reqs      = omap2_uart3_sdma_reqs,
1290         .main_clk       = "uart3_fck",
1291         .prcm           = {
1292                 .omap2 = {
1293                         .module_offs = OMAP3430_PER_MOD,
1294                         .prcm_reg_id = 1,
1295                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1296                         .idlest_reg_id = 1,
1297                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1298                 },
1299         },
1300         .slaves         = omap3xxx_uart3_slaves,
1301         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1302         .class          = &omap2_uart_class,
1303 };
1304
1305 /* UART4 */
1306
1307 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1308         { .irq = INT_36XX_UART4_IRQ, },
1309         { .irq = -1 }
1310 };
1311
1312 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1313         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1314         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1315         { .dma_req = -1 }
1316 };
1317
1318 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1319         &omap36xx_l4_per__uart4,
1320 };
1321
1322 static struct omap_hwmod omap36xx_uart4_hwmod = {
1323         .name           = "uart4",
1324         .mpu_irqs       = uart4_mpu_irqs,
1325         .sdma_reqs      = uart4_sdma_reqs,
1326         .main_clk       = "uart4_fck",
1327         .flags          = HWMOD_SWSUP_SIDLE,
1328         .prcm           = {
1329                 .omap2 = {
1330                         .module_offs = OMAP3430_PER_MOD,
1331                         .prcm_reg_id = 1,
1332                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1333                         .idlest_reg_id = 1,
1334                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1335                 },
1336         },
1337         .slaves         = omap3xxx_uart4_slaves,
1338         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1339         .class          = &omap2_uart_class,
1340 };
1341
1342 static struct omap_hwmod_class i2c_class = {
1343         .name   = "i2c",
1344         .sysc   = &i2c_sysc,
1345         .rev    = OMAP_I2C_IP_VERSION_1,
1346         .reset  = &omap_i2c_reset,
1347 };
1348
1349 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1350         { .name = "dispc", .dma_req = 5 },
1351         { .name = "dsi1", .dma_req = 74 },
1352         { .dma_req = -1 }
1353 };
1354
1355 /* dss */
1356 /* dss master ports */
1357 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1358         &omap3xxx_dss__l3,
1359 };
1360
1361 /* l4_core -> dss */
1362 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1363         .master         = &omap3xxx_l4_core_hwmod,
1364         .slave          = &omap3430es1_dss_core_hwmod,
1365         .clk            = "dss_ick",
1366         .addr           = omap2_dss_addrs,
1367         .fw = {
1368                 .omap2 = {
1369                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1370                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1371                         .flags  = OMAP_FIREWALL_L4,
1372                 }
1373         },
1374         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1375 };
1376
1377 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1378         .master         = &omap3xxx_l4_core_hwmod,
1379         .slave          = &omap3xxx_dss_core_hwmod,
1380         .clk            = "dss_ick",
1381         .addr           = omap2_dss_addrs,
1382         .fw = {
1383                 .omap2 = {
1384                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1385                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1386                         .flags  = OMAP_FIREWALL_L4,
1387                 }
1388         },
1389         .flags          = OCPIF_SWSUP_IDLE,
1390         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1391 };
1392
1393 /* dss slave ports */
1394 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1395         &omap3430es1_l4_core__dss,
1396 };
1397
1398 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1399         &omap3xxx_l4_core__dss,
1400 };
1401
1402 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1403         /*
1404          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1405          * driver does not use these clocks.
1406          */
1407         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1408         { .role = "tv_clk", .clk = "dss_tv_fck" },
1409         /* required only on OMAP3430 */
1410         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1411 };
1412
1413 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1414         .name           = "dss_core",
1415         .class          = &omap2_dss_hwmod_class,
1416         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1417         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1418         .prcm           = {
1419                 .omap2 = {
1420                         .prcm_reg_id = 1,
1421                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1422                         .module_offs = OMAP3430_DSS_MOD,
1423                         .idlest_reg_id = 1,
1424                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1425                 },
1426         },
1427         .opt_clks       = dss_opt_clks,
1428         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1429         .slaves         = omap3430es1_dss_slaves,
1430         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1431         .masters        = omap3xxx_dss_masters,
1432         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1433         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1434 };
1435
1436 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1437         .name           = "dss_core",
1438         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1439         .class          = &omap2_dss_hwmod_class,
1440         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1441         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1442         .prcm           = {
1443                 .omap2 = {
1444                         .prcm_reg_id = 1,
1445                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1446                         .module_offs = OMAP3430_DSS_MOD,
1447                         .idlest_reg_id = 1,
1448                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1449                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1450                 },
1451         },
1452         .opt_clks       = dss_opt_clks,
1453         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1454         .slaves         = omap3xxx_dss_slaves,
1455         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1456         .masters        = omap3xxx_dss_masters,
1457         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1458 };
1459
1460 /*
1461  * 'dispc' class
1462  * display controller
1463  */
1464
1465 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
1466         .rev_offs       = 0x0000,
1467         .sysc_offs      = 0x0010,
1468         .syss_offs      = 0x0014,
1469         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1470                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1471                            SYSC_HAS_ENAWAKEUP),
1472         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1473                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1474         .sysc_fields    = &omap_hwmod_sysc_type1,
1475 };
1476
1477 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1478         .name   = "dispc",
1479         .sysc   = &omap3_dispc_sysc,
1480 };
1481
1482 /* l4_core -> dss_dispc */
1483 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1484         .master         = &omap3xxx_l4_core_hwmod,
1485         .slave          = &omap3xxx_dss_dispc_hwmod,
1486         .clk            = "dss_ick",
1487         .addr           = omap2_dss_dispc_addrs,
1488         .fw = {
1489                 .omap2 = {
1490                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1491                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1492                         .flags  = OMAP_FIREWALL_L4,
1493                 }
1494         },
1495         .flags          = OCPIF_SWSUP_IDLE,
1496         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1497 };
1498
1499 /* dss_dispc slave ports */
1500 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1501         &omap3xxx_l4_core__dss_dispc,
1502 };
1503
1504 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1505         .name           = "dss_dispc",
1506         .class          = &omap3_dispc_hwmod_class,
1507         .mpu_irqs       = omap2_dispc_irqs,
1508         .main_clk       = "dss1_alwon_fck",
1509         .prcm           = {
1510                 .omap2 = {
1511                         .prcm_reg_id = 1,
1512                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1513                         .module_offs = OMAP3430_DSS_MOD,
1514                 },
1515         },
1516         .slaves         = omap3xxx_dss_dispc_slaves,
1517         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1518         .flags          = HWMOD_NO_IDLEST,
1519         .dev_attr       = &omap2_3_dss_dispc_dev_attr
1520 };
1521
1522 /*
1523  * 'dsi' class
1524  * display serial interface controller
1525  */
1526
1527 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1528         .name = "dsi",
1529 };
1530
1531 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1532         { .irq = 25 },
1533         { .irq = -1 }
1534 };
1535
1536 /* dss_dsi1 */
1537 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1538         {
1539                 .pa_start       = 0x4804FC00,
1540                 .pa_end         = 0x4804FFFF,
1541                 .flags          = ADDR_TYPE_RT
1542         },
1543         { }
1544 };
1545
1546 /* l4_core -> dss_dsi1 */
1547 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1548         .master         = &omap3xxx_l4_core_hwmod,
1549         .slave          = &omap3xxx_dss_dsi1_hwmod,
1550         .clk            = "dss_ick",
1551         .addr           = omap3xxx_dss_dsi1_addrs,
1552         .fw = {
1553                 .omap2 = {
1554                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1555                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1556                         .flags  = OMAP_FIREWALL_L4,
1557                 }
1558         },
1559         .flags          = OCPIF_SWSUP_IDLE,
1560         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1561 };
1562
1563 /* dss_dsi1 slave ports */
1564 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1565         &omap3xxx_l4_core__dss_dsi1,
1566 };
1567
1568 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1569         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1570 };
1571
1572 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1573         .name           = "dss_dsi1",
1574         .class          = &omap3xxx_dsi_hwmod_class,
1575         .mpu_irqs       = omap3xxx_dsi1_irqs,
1576         .main_clk       = "dss1_alwon_fck",
1577         .prcm           = {
1578                 .omap2 = {
1579                         .prcm_reg_id = 1,
1580                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1581                         .module_offs = OMAP3430_DSS_MOD,
1582                 },
1583         },
1584         .opt_clks       = dss_dsi1_opt_clks,
1585         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1586         .slaves         = omap3xxx_dss_dsi1_slaves,
1587         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1588         .flags          = HWMOD_NO_IDLEST,
1589 };
1590
1591 /* l4_core -> dss_rfbi */
1592 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1593         .master         = &omap3xxx_l4_core_hwmod,
1594         .slave          = &omap3xxx_dss_rfbi_hwmod,
1595         .clk            = "dss_ick",
1596         .addr           = omap2_dss_rfbi_addrs,
1597         .fw = {
1598                 .omap2 = {
1599                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1600                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1601                         .flags  = OMAP_FIREWALL_L4,
1602                 }
1603         },
1604         .flags          = OCPIF_SWSUP_IDLE,
1605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1606 };
1607
1608 /* dss_rfbi slave ports */
1609 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1610         &omap3xxx_l4_core__dss_rfbi,
1611 };
1612
1613 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1614         { .role = "ick", .clk = "dss_ick" },
1615 };
1616
1617 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1618         .name           = "dss_rfbi",
1619         .class          = &omap2_rfbi_hwmod_class,
1620         .main_clk       = "dss1_alwon_fck",
1621         .prcm           = {
1622                 .omap2 = {
1623                         .prcm_reg_id = 1,
1624                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1625                         .module_offs = OMAP3430_DSS_MOD,
1626                 },
1627         },
1628         .opt_clks       = dss_rfbi_opt_clks,
1629         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1630         .slaves         = omap3xxx_dss_rfbi_slaves,
1631         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1632         .flags          = HWMOD_NO_IDLEST,
1633 };
1634
1635 /* l4_core -> dss_venc */
1636 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1637         .master         = &omap3xxx_l4_core_hwmod,
1638         .slave          = &omap3xxx_dss_venc_hwmod,
1639         .clk            = "dss_ick",
1640         .addr           = omap2_dss_venc_addrs,
1641         .fw = {
1642                 .omap2 = {
1643                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1644                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1645                         .flags  = OMAP_FIREWALL_L4,
1646                 }
1647         },
1648         .flags          = OCPIF_SWSUP_IDLE,
1649         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1650 };
1651
1652 /* dss_venc slave ports */
1653 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1654         &omap3xxx_l4_core__dss_venc,
1655 };
1656
1657 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1658         /* required only on OMAP3430 */
1659         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1660 };
1661
1662 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1663         .name           = "dss_venc",
1664         .class          = &omap2_venc_hwmod_class,
1665         .main_clk       = "dss_tv_fck",
1666         .prcm           = {
1667                 .omap2 = {
1668                         .prcm_reg_id = 1,
1669                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1670                         .module_offs = OMAP3430_DSS_MOD,
1671                 },
1672         },
1673         .opt_clks       = dss_venc_opt_clks,
1674         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
1675         .slaves         = omap3xxx_dss_venc_slaves,
1676         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1677         .flags          = HWMOD_NO_IDLEST,
1678 };
1679
1680 /* I2C1 */
1681
1682 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1683         .fifo_depth     = 8, /* bytes */
1684         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1685                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1686                           OMAP_I2C_FLAG_BUS_SHIFT_2,
1687 };
1688
1689 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1690         &omap3_l4_core__i2c1,
1691 };
1692
1693 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1694         .name           = "i2c1",
1695         .flags          = HWMOD_16BIT_REG,
1696         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1697         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1698         .main_clk       = "i2c1_fck",
1699         .prcm           = {
1700                 .omap2 = {
1701                         .module_offs = CORE_MOD,
1702                         .prcm_reg_id = 1,
1703                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1704                         .idlest_reg_id = 1,
1705                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1706                 },
1707         },
1708         .slaves         = omap3xxx_i2c1_slaves,
1709         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1710         .class          = &i2c_class,
1711         .dev_attr       = &i2c1_dev_attr,
1712 };
1713
1714 /* I2C2 */
1715
1716 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1717         .fifo_depth     = 8, /* bytes */
1718         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1719                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1720                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1721 };
1722
1723 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1724         &omap3_l4_core__i2c2,
1725 };
1726
1727 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1728         .name           = "i2c2",
1729         .flags          = HWMOD_16BIT_REG,
1730         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1731         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1732         .main_clk       = "i2c2_fck",
1733         .prcm           = {
1734                 .omap2 = {
1735                         .module_offs = CORE_MOD,
1736                         .prcm_reg_id = 1,
1737                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1738                         .idlest_reg_id = 1,
1739                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1740                 },
1741         },
1742         .slaves         = omap3xxx_i2c2_slaves,
1743         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1744         .class          = &i2c_class,
1745         .dev_attr       = &i2c2_dev_attr,
1746 };
1747
1748 /* I2C3 */
1749
1750 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1751         .fifo_depth     = 64, /* bytes */
1752         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1753                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1754                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1755 };
1756
1757 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1758         { .irq = INT_34XX_I2C3_IRQ, },
1759         { .irq = -1 }
1760 };
1761
1762 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1763         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1764         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1765         { .dma_req = -1 }
1766 };
1767
1768 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1769         &omap3_l4_core__i2c3,
1770 };
1771
1772 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1773         .name           = "i2c3",
1774         .flags          = HWMOD_16BIT_REG,
1775         .mpu_irqs       = i2c3_mpu_irqs,
1776         .sdma_reqs      = i2c3_sdma_reqs,
1777         .main_clk       = "i2c3_fck",
1778         .prcm           = {
1779                 .omap2 = {
1780                         .module_offs = CORE_MOD,
1781                         .prcm_reg_id = 1,
1782                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1783                         .idlest_reg_id = 1,
1784                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1785                 },
1786         },
1787         .slaves         = omap3xxx_i2c3_slaves,
1788         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1789         .class          = &i2c_class,
1790         .dev_attr       = &i2c3_dev_attr,
1791 };
1792
1793 /* l4_wkup -> gpio1 */
1794 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1795         {
1796                 .pa_start       = 0x48310000,
1797                 .pa_end         = 0x483101ff,
1798                 .flags          = ADDR_TYPE_RT
1799         },
1800         { }
1801 };
1802
1803 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1804         .master         = &omap3xxx_l4_wkup_hwmod,
1805         .slave          = &omap3xxx_gpio1_hwmod,
1806         .addr           = omap3xxx_gpio1_addrs,
1807         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1808 };
1809
1810 /* l4_per -> gpio2 */
1811 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1812         {
1813                 .pa_start       = 0x49050000,
1814                 .pa_end         = 0x490501ff,
1815                 .flags          = ADDR_TYPE_RT
1816         },
1817         { }
1818 };
1819
1820 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1821         .master         = &omap3xxx_l4_per_hwmod,
1822         .slave          = &omap3xxx_gpio2_hwmod,
1823         .addr           = omap3xxx_gpio2_addrs,
1824         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1825 };
1826
1827 /* l4_per -> gpio3 */
1828 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1829         {
1830                 .pa_start       = 0x49052000,
1831                 .pa_end         = 0x490521ff,
1832                 .flags          = ADDR_TYPE_RT
1833         },
1834         { }
1835 };
1836
1837 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1838         .master         = &omap3xxx_l4_per_hwmod,
1839         .slave          = &omap3xxx_gpio3_hwmod,
1840         .addr           = omap3xxx_gpio3_addrs,
1841         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1842 };
1843
1844 /* l4_per -> gpio4 */
1845 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1846         {
1847                 .pa_start       = 0x49054000,
1848                 .pa_end         = 0x490541ff,
1849                 .flags          = ADDR_TYPE_RT
1850         },
1851         { }
1852 };
1853
1854 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1855         .master         = &omap3xxx_l4_per_hwmod,
1856         .slave          = &omap3xxx_gpio4_hwmod,
1857         .addr           = omap3xxx_gpio4_addrs,
1858         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1859 };
1860
1861 /* l4_per -> gpio5 */
1862 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1863         {
1864                 .pa_start       = 0x49056000,
1865                 .pa_end         = 0x490561ff,
1866                 .flags          = ADDR_TYPE_RT
1867         },
1868         { }
1869 };
1870
1871 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1872         .master         = &omap3xxx_l4_per_hwmod,
1873         .slave          = &omap3xxx_gpio5_hwmod,
1874         .addr           = omap3xxx_gpio5_addrs,
1875         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1876 };
1877
1878 /* l4_per -> gpio6 */
1879 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1880         {
1881                 .pa_start       = 0x49058000,
1882                 .pa_end         = 0x490581ff,
1883                 .flags          = ADDR_TYPE_RT
1884         },
1885         { }
1886 };
1887
1888 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1889         .master         = &omap3xxx_l4_per_hwmod,
1890         .slave          = &omap3xxx_gpio6_hwmod,
1891         .addr           = omap3xxx_gpio6_addrs,
1892         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1893 };
1894
1895 /*
1896  * 'gpio' class
1897  * general purpose io module
1898  */
1899
1900 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1901         .rev_offs       = 0x0000,
1902         .sysc_offs      = 0x0010,
1903         .syss_offs      = 0x0014,
1904         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1905                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1906                            SYSS_HAS_RESET_STATUS),
1907         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1908         .sysc_fields    = &omap_hwmod_sysc_type1,
1909 };
1910
1911 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1912         .name = "gpio",
1913         .sysc = &omap3xxx_gpio_sysc,
1914         .rev = 1,
1915 };
1916
1917 /* gpio_dev_attr*/
1918 static struct omap_gpio_dev_attr gpio_dev_attr = {
1919         .bank_width = 32,
1920         .dbck_flag = true,
1921 };
1922
1923 /* gpio1 */
1924 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1925         { .role = "dbclk", .clk = "gpio1_dbck", },
1926 };
1927
1928 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1929         &omap3xxx_l4_wkup__gpio1,
1930 };
1931
1932 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1933         .name           = "gpio1",
1934         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1935         .mpu_irqs       = omap2_gpio1_irqs,
1936         .main_clk       = "gpio1_ick",
1937         .opt_clks       = gpio1_opt_clks,
1938         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1939         .prcm           = {
1940                 .omap2 = {
1941                         .prcm_reg_id = 1,
1942                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1943                         .module_offs = WKUP_MOD,
1944                         .idlest_reg_id = 1,
1945                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1946                 },
1947         },
1948         .slaves         = omap3xxx_gpio1_slaves,
1949         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1950         .class          = &omap3xxx_gpio_hwmod_class,
1951         .dev_attr       = &gpio_dev_attr,
1952 };
1953
1954 /* gpio2 */
1955 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1956         { .role = "dbclk", .clk = "gpio2_dbck", },
1957 };
1958
1959 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1960         &omap3xxx_l4_per__gpio2,
1961 };
1962
1963 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1964         .name           = "gpio2",
1965         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1966         .mpu_irqs       = omap2_gpio2_irqs,
1967         .main_clk       = "gpio2_ick",
1968         .opt_clks       = gpio2_opt_clks,
1969         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1970         .prcm           = {
1971                 .omap2 = {
1972                         .prcm_reg_id = 1,
1973                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1974                         .module_offs = OMAP3430_PER_MOD,
1975                         .idlest_reg_id = 1,
1976                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1977                 },
1978         },
1979         .slaves         = omap3xxx_gpio2_slaves,
1980         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1981         .class          = &omap3xxx_gpio_hwmod_class,
1982         .dev_attr       = &gpio_dev_attr,
1983 };
1984
1985 /* gpio3 */
1986 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1987         { .role = "dbclk", .clk = "gpio3_dbck", },
1988 };
1989
1990 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1991         &omap3xxx_l4_per__gpio3,
1992 };
1993
1994 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1995         .name           = "gpio3",
1996         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1997         .mpu_irqs       = omap2_gpio3_irqs,
1998         .main_clk       = "gpio3_ick",
1999         .opt_clks       = gpio3_opt_clks,
2000         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
2001         .prcm           = {
2002                 .omap2 = {
2003                         .prcm_reg_id = 1,
2004                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2005                         .module_offs = OMAP3430_PER_MOD,
2006                         .idlest_reg_id = 1,
2007                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2008                 },
2009         },
2010         .slaves         = omap3xxx_gpio3_slaves,
2011         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2012         .class          = &omap3xxx_gpio_hwmod_class,
2013         .dev_attr       = &gpio_dev_attr,
2014 };
2015
2016 /* gpio4 */
2017 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2018         { .role = "dbclk", .clk = "gpio4_dbck", },
2019 };
2020
2021 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2022         &omap3xxx_l4_per__gpio4,
2023 };
2024
2025 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2026         .name           = "gpio4",
2027         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2028         .mpu_irqs       = omap2_gpio4_irqs,
2029         .main_clk       = "gpio4_ick",
2030         .opt_clks       = gpio4_opt_clks,
2031         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2032         .prcm           = {
2033                 .omap2 = {
2034                         .prcm_reg_id = 1,
2035                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2036                         .module_offs = OMAP3430_PER_MOD,
2037                         .idlest_reg_id = 1,
2038                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2039                 },
2040         },
2041         .slaves         = omap3xxx_gpio4_slaves,
2042         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2043         .class          = &omap3xxx_gpio_hwmod_class,
2044         .dev_attr       = &gpio_dev_attr,
2045 };
2046
2047 /* gpio5 */
2048 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2049         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2050         { .irq = -1 }
2051 };
2052
2053 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2054         { .role = "dbclk", .clk = "gpio5_dbck", },
2055 };
2056
2057 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2058         &omap3xxx_l4_per__gpio5,
2059 };
2060
2061 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2062         .name           = "gpio5",
2063         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2064         .mpu_irqs       = omap3xxx_gpio5_irqs,
2065         .main_clk       = "gpio5_ick",
2066         .opt_clks       = gpio5_opt_clks,
2067         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2068         .prcm           = {
2069                 .omap2 = {
2070                         .prcm_reg_id = 1,
2071                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2072                         .module_offs = OMAP3430_PER_MOD,
2073                         .idlest_reg_id = 1,
2074                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2075                 },
2076         },
2077         .slaves         = omap3xxx_gpio5_slaves,
2078         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2079         .class          = &omap3xxx_gpio_hwmod_class,
2080         .dev_attr       = &gpio_dev_attr,
2081 };
2082
2083 /* gpio6 */
2084 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2085         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2086         { .irq = -1 }
2087 };
2088
2089 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2090         { .role = "dbclk", .clk = "gpio6_dbck", },
2091 };
2092
2093 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2094         &omap3xxx_l4_per__gpio6,
2095 };
2096
2097 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2098         .name           = "gpio6",
2099         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2100         .mpu_irqs       = omap3xxx_gpio6_irqs,
2101         .main_clk       = "gpio6_ick",
2102         .opt_clks       = gpio6_opt_clks,
2103         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2104         .prcm           = {
2105                 .omap2 = {
2106                         .prcm_reg_id = 1,
2107                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2108                         .module_offs = OMAP3430_PER_MOD,
2109                         .idlest_reg_id = 1,
2110                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2111                 },
2112         },
2113         .slaves         = omap3xxx_gpio6_slaves,
2114         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2115         .class          = &omap3xxx_gpio_hwmod_class,
2116         .dev_attr       = &gpio_dev_attr,
2117 };
2118
2119 /* dma_system -> L3 */
2120 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2121         .master         = &omap3xxx_dma_system_hwmod,
2122         .slave          = &omap3xxx_l3_main_hwmod,
2123         .clk            = "core_l3_ick",
2124         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2125 };
2126
2127 /* dma attributes */
2128 static struct omap_dma_dev_attr dma_dev_attr = {
2129         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2130                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2131         .lch_count = 32,
2132 };
2133
2134 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2135         .rev_offs       = 0x0000,
2136         .sysc_offs      = 0x002c,
2137         .syss_offs      = 0x0028,
2138         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2139                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2140                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2141                            SYSS_HAS_RESET_STATUS),
2142         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2143                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2144         .sysc_fields    = &omap_hwmod_sysc_type1,
2145 };
2146
2147 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2148         .name = "dma",
2149         .sysc = &omap3xxx_dma_sysc,
2150 };
2151
2152 /* dma_system */
2153 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2154         {
2155                 .pa_start       = 0x48056000,
2156                 .pa_end         = 0x48056fff,
2157                 .flags          = ADDR_TYPE_RT
2158         },
2159         { }
2160 };
2161
2162 /* dma_system master ports */
2163 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2164         &omap3xxx_dma_system__l3,
2165 };
2166
2167 /* l4_cfg -> dma_system */
2168 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2169         .master         = &omap3xxx_l4_core_hwmod,
2170         .slave          = &omap3xxx_dma_system_hwmod,
2171         .clk            = "core_l4_ick",
2172         .addr           = omap3xxx_dma_system_addrs,
2173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2174 };
2175
2176 /* dma_system slave ports */
2177 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2178         &omap3xxx_l4_core__dma_system,
2179 };
2180
2181 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2182         .name           = "dma",
2183         .class          = &omap3xxx_dma_hwmod_class,
2184         .mpu_irqs       = omap2_dma_system_irqs,
2185         .main_clk       = "core_l3_ick",
2186         .prcm = {
2187                 .omap2 = {
2188                         .module_offs            = CORE_MOD,
2189                         .prcm_reg_id            = 1,
2190                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2191                         .idlest_reg_id          = 1,
2192                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2193                 },
2194         },
2195         .slaves         = omap3xxx_dma_system_slaves,
2196         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2197         .masters        = omap3xxx_dma_system_masters,
2198         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2199         .dev_attr       = &dma_dev_attr,
2200         .flags          = HWMOD_NO_IDLEST,
2201 };
2202
2203 /*
2204  * 'mcbsp' class
2205  * multi channel buffered serial port controller
2206  */
2207
2208 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2209         .sysc_offs      = 0x008c,
2210         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2211                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2212         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2213         .sysc_fields    = &omap_hwmod_sysc_type1,
2214         .clockact       = 0x2,
2215 };
2216
2217 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2218         .name = "mcbsp",
2219         .sysc = &omap3xxx_mcbsp_sysc,
2220         .rev  = MCBSP_CONFIG_TYPE3,
2221 };
2222
2223 /* mcbsp1 */
2224 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2225         { .name = "irq", .irq = 16 },
2226         { .name = "tx", .irq = 59 },
2227         { .name = "rx", .irq = 60 },
2228         { .irq = -1 }
2229 };
2230
2231 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2232         {
2233                 .name           = "mpu",
2234                 .pa_start       = 0x48074000,
2235                 .pa_end         = 0x480740ff,
2236                 .flags          = ADDR_TYPE_RT
2237         },
2238         { }
2239 };
2240
2241 /* l4_core -> mcbsp1 */
2242 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2243         .master         = &omap3xxx_l4_core_hwmod,
2244         .slave          = &omap3xxx_mcbsp1_hwmod,
2245         .clk            = "mcbsp1_ick",
2246         .addr           = omap3xxx_mcbsp1_addrs,
2247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2248 };
2249
2250 /* mcbsp1 slave ports */
2251 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2252         &omap3xxx_l4_core__mcbsp1,
2253 };
2254
2255 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2256         .name           = "mcbsp1",
2257         .class          = &omap3xxx_mcbsp_hwmod_class,
2258         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2259         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
2260         .main_clk       = "mcbsp1_fck",
2261         .prcm           = {
2262                 .omap2 = {
2263                         .prcm_reg_id = 1,
2264                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2265                         .module_offs = CORE_MOD,
2266                         .idlest_reg_id = 1,
2267                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2268                 },
2269         },
2270         .slaves         = omap3xxx_mcbsp1_slaves,
2271         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2272 };
2273
2274 /* mcbsp2 */
2275 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2276         { .name = "irq", .irq = 17 },
2277         { .name = "tx", .irq = 62 },
2278         { .name = "rx", .irq = 63 },
2279         { .irq = -1 }
2280 };
2281
2282 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2283         {
2284                 .name           = "mpu",
2285                 .pa_start       = 0x49022000,
2286                 .pa_end         = 0x490220ff,
2287                 .flags          = ADDR_TYPE_RT
2288         },
2289         { }
2290 };
2291
2292 /* l4_per -> mcbsp2 */
2293 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2294         .master         = &omap3xxx_l4_per_hwmod,
2295         .slave          = &omap3xxx_mcbsp2_hwmod,
2296         .clk            = "mcbsp2_ick",
2297         .addr           = omap3xxx_mcbsp2_addrs,
2298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2299 };
2300
2301 /* mcbsp2 slave ports */
2302 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2303         &omap3xxx_l4_per__mcbsp2,
2304 };
2305
2306 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2307         .sidetone       = "mcbsp2_sidetone",
2308 };
2309
2310 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2311         .name           = "mcbsp2",
2312         .class          = &omap3xxx_mcbsp_hwmod_class,
2313         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2314         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
2315         .main_clk       = "mcbsp2_fck",
2316         .prcm           = {
2317                 .omap2 = {
2318                         .prcm_reg_id = 1,
2319                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2320                         .module_offs = OMAP3430_PER_MOD,
2321                         .idlest_reg_id = 1,
2322                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2323                 },
2324         },
2325         .slaves         = omap3xxx_mcbsp2_slaves,
2326         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2327         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2328 };
2329
2330 /* mcbsp3 */
2331 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2332         { .name = "irq", .irq = 22 },
2333         { .name = "tx", .irq = 89 },
2334         { .name = "rx", .irq = 90 },
2335         { .irq = -1 }
2336 };
2337
2338 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2339         {
2340                 .name           = "mpu",
2341                 .pa_start       = 0x49024000,
2342                 .pa_end         = 0x490240ff,
2343                 .flags          = ADDR_TYPE_RT
2344         },
2345         { }
2346 };
2347
2348 /* l4_per -> mcbsp3 */
2349 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2350         .master         = &omap3xxx_l4_per_hwmod,
2351         .slave          = &omap3xxx_mcbsp3_hwmod,
2352         .clk            = "mcbsp3_ick",
2353         .addr           = omap3xxx_mcbsp3_addrs,
2354         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2355 };
2356
2357 /* mcbsp3 slave ports */
2358 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2359         &omap3xxx_l4_per__mcbsp3,
2360 };
2361
2362 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2363         .sidetone       = "mcbsp3_sidetone",
2364 };
2365
2366 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2367         .name           = "mcbsp3",
2368         .class          = &omap3xxx_mcbsp_hwmod_class,
2369         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2370         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
2371         .main_clk       = "mcbsp3_fck",
2372         .prcm           = {
2373                 .omap2 = {
2374                         .prcm_reg_id = 1,
2375                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2376                         .module_offs = OMAP3430_PER_MOD,
2377                         .idlest_reg_id = 1,
2378                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2379                 },
2380         },
2381         .slaves         = omap3xxx_mcbsp3_slaves,
2382         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2383         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2384 };
2385
2386 /* mcbsp4 */
2387 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2388         { .name = "irq", .irq = 23 },
2389         { .name = "tx", .irq = 54 },
2390         { .name = "rx", .irq = 55 },
2391         { .irq = -1 }
2392 };
2393
2394 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2395         { .name = "rx", .dma_req = 20 },
2396         { .name = "tx", .dma_req = 19 },
2397         { .dma_req = -1 }
2398 };
2399
2400 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2401         {
2402                 .name           = "mpu",
2403                 .pa_start       = 0x49026000,
2404                 .pa_end         = 0x490260ff,
2405                 .flags          = ADDR_TYPE_RT
2406         },
2407         { }
2408 };
2409
2410 /* l4_per -> mcbsp4 */
2411 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2412         .master         = &omap3xxx_l4_per_hwmod,
2413         .slave          = &omap3xxx_mcbsp4_hwmod,
2414         .clk            = "mcbsp4_ick",
2415         .addr           = omap3xxx_mcbsp4_addrs,
2416         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2417 };
2418
2419 /* mcbsp4 slave ports */
2420 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2421         &omap3xxx_l4_per__mcbsp4,
2422 };
2423
2424 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2425         .name           = "mcbsp4",
2426         .class          = &omap3xxx_mcbsp_hwmod_class,
2427         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2428         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2429         .main_clk       = "mcbsp4_fck",
2430         .prcm           = {
2431                 .omap2 = {
2432                         .prcm_reg_id = 1,
2433                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2434                         .module_offs = OMAP3430_PER_MOD,
2435                         .idlest_reg_id = 1,
2436                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2437                 },
2438         },
2439         .slaves         = omap3xxx_mcbsp4_slaves,
2440         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2441 };
2442
2443 /* mcbsp5 */
2444 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2445         { .name = "irq", .irq = 27 },
2446         { .name = "tx", .irq = 81 },
2447         { .name = "rx", .irq = 82 },
2448         { .irq = -1 }
2449 };
2450
2451 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2452         { .name = "rx", .dma_req = 22 },
2453         { .name = "tx", .dma_req = 21 },
2454         { .dma_req = -1 }
2455 };
2456
2457 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2458         {
2459                 .name           = "mpu",
2460                 .pa_start       = 0x48096000,
2461                 .pa_end         = 0x480960ff,
2462                 .flags          = ADDR_TYPE_RT
2463         },
2464         { }
2465 };
2466
2467 /* l4_core -> mcbsp5 */
2468 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2469         .master         = &omap3xxx_l4_core_hwmod,
2470         .slave          = &omap3xxx_mcbsp5_hwmod,
2471         .clk            = "mcbsp5_ick",
2472         .addr           = omap3xxx_mcbsp5_addrs,
2473         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2474 };
2475
2476 /* mcbsp5 slave ports */
2477 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2478         &omap3xxx_l4_core__mcbsp5,
2479 };
2480
2481 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2482         .name           = "mcbsp5",
2483         .class          = &omap3xxx_mcbsp_hwmod_class,
2484         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2485         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2486         .main_clk       = "mcbsp5_fck",
2487         .prcm           = {
2488                 .omap2 = {
2489                         .prcm_reg_id = 1,
2490                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2491                         .module_offs = CORE_MOD,
2492                         .idlest_reg_id = 1,
2493                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2494                 },
2495         },
2496         .slaves         = omap3xxx_mcbsp5_slaves,
2497         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2498 };
2499 /* 'mcbsp sidetone' class */
2500
2501 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2502         .sysc_offs      = 0x0010,
2503         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2504         .sysc_fields    = &omap_hwmod_sysc_type1,
2505 };
2506
2507 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2508         .name = "mcbsp_sidetone",
2509         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2510 };
2511
2512 /* mcbsp2_sidetone */
2513 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2514         { .name = "irq", .irq = 4 },
2515         { .irq = -1 }
2516 };
2517
2518 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2519         {
2520                 .name           = "sidetone",
2521                 .pa_start       = 0x49028000,
2522                 .pa_end         = 0x490280ff,
2523                 .flags          = ADDR_TYPE_RT
2524         },
2525         { }
2526 };
2527
2528 /* l4_per -> mcbsp2_sidetone */
2529 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2530         .master         = &omap3xxx_l4_per_hwmod,
2531         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2532         .clk            = "mcbsp2_ick",
2533         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2534         .user           = OCP_USER_MPU,
2535 };
2536
2537 /* mcbsp2_sidetone slave ports */
2538 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2539         &omap3xxx_l4_per__mcbsp2_sidetone,
2540 };
2541
2542 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2543         .name           = "mcbsp2_sidetone",
2544         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2545         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2546         .main_clk       = "mcbsp2_fck",
2547         .prcm           = {
2548                 .omap2 = {
2549                         .prcm_reg_id = 1,
2550                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2551                         .module_offs = OMAP3430_PER_MOD,
2552                         .idlest_reg_id = 1,
2553                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2554                 },
2555         },
2556         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2557         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2558 };
2559
2560 /* mcbsp3_sidetone */
2561 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2562         { .name = "irq", .irq = 5 },
2563         { .irq = -1 }
2564 };
2565
2566 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2567         {
2568                 .name           = "sidetone",
2569                 .pa_start       = 0x4902A000,
2570                 .pa_end         = 0x4902A0ff,
2571                 .flags          = ADDR_TYPE_RT
2572         },
2573         { }
2574 };
2575
2576 /* l4_per -> mcbsp3_sidetone */
2577 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2578         .master         = &omap3xxx_l4_per_hwmod,
2579         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2580         .clk            = "mcbsp3_ick",
2581         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2582         .user           = OCP_USER_MPU,
2583 };
2584
2585 /* mcbsp3_sidetone slave ports */
2586 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2587         &omap3xxx_l4_per__mcbsp3_sidetone,
2588 };
2589
2590 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2591         .name           = "mcbsp3_sidetone",
2592         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2593         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2594         .main_clk       = "mcbsp3_fck",
2595         .prcm           = {
2596                 .omap2 = {
2597                         .prcm_reg_id = 1,
2598                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2599                         .module_offs = OMAP3430_PER_MOD,
2600                         .idlest_reg_id = 1,
2601                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2602                 },
2603         },
2604         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2605         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2606 };
2607
2608
2609 /* SR common */
2610 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2611         .clkact_shift   = 20,
2612 };
2613
2614 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2615         .sysc_offs      = 0x24,
2616         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2617         .clockact       = CLOCKACT_TEST_ICLK,
2618         .sysc_fields    = &omap34xx_sr_sysc_fields,
2619 };
2620
2621 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2622         .name = "smartreflex",
2623         .sysc = &omap34xx_sr_sysc,
2624         .rev  = 1,
2625 };
2626
2627 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2628         .sidle_shift    = 24,
2629         .enwkup_shift   = 26
2630 };
2631
2632 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2633         .sysc_offs      = 0x38,
2634         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2635         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2636                         SYSC_NO_CACHE),
2637         .sysc_fields    = &omap36xx_sr_sysc_fields,
2638 };
2639
2640 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2641         .name = "smartreflex",
2642         .sysc = &omap36xx_sr_sysc,
2643         .rev  = 2,
2644 };
2645
2646 /* SR1 */
2647 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
2648         .sensor_voltdm_name   = "mpu_iva",
2649 };
2650
2651 static struct omap_hwmod_ocp_if *omap34xx_sr1_slaves[] = {
2652         &omap34xx_l4_core__sr1,
2653 };
2654
2655 static struct omap_hwmod omap34xx_sr1_hwmod = {
2656         .name           = "sr1",
2657         .class          = &omap34xx_smartreflex_hwmod_class,
2658         .main_clk       = "sr1_fck",
2659         .prcm           = {
2660                 .omap2 = {
2661                         .prcm_reg_id = 1,
2662                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2663                         .module_offs = WKUP_MOD,
2664                         .idlest_reg_id = 1,
2665                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2666                 },
2667         },
2668         .slaves         = omap34xx_sr1_slaves,
2669         .slaves_cnt     = ARRAY_SIZE(omap34xx_sr1_slaves),
2670         .dev_attr       = &sr1_dev_attr,
2671         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
2672         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2673 };
2674
2675 static struct omap_hwmod_ocp_if *omap36xx_sr1_slaves[] = {
2676         &omap36xx_l4_core__sr1,
2677 };
2678
2679 static struct omap_hwmod omap36xx_sr1_hwmod = {
2680         .name           = "sr1",
2681         .class          = &omap36xx_smartreflex_hwmod_class,
2682         .main_clk       = "sr1_fck",
2683         .prcm           = {
2684                 .omap2 = {
2685                         .prcm_reg_id = 1,
2686                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2687                         .module_offs = WKUP_MOD,
2688                         .idlest_reg_id = 1,
2689                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2690                 },
2691         },
2692         .slaves         = omap36xx_sr1_slaves,
2693         .slaves_cnt     = ARRAY_SIZE(omap36xx_sr1_slaves),
2694         .dev_attr       = &sr1_dev_attr,
2695         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
2696 };
2697
2698 /* SR2 */
2699 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
2700         .sensor_voltdm_name     = "core",
2701 };
2702
2703 static struct omap_hwmod_ocp_if *omap34xx_sr2_slaves[] = {
2704         &omap34xx_l4_core__sr2,
2705 };
2706
2707 static struct omap_hwmod omap34xx_sr2_hwmod = {
2708         .name           = "sr2",
2709         .class          = &omap34xx_smartreflex_hwmod_class,
2710         .main_clk       = "sr2_fck",
2711         .prcm           = {
2712                 .omap2 = {
2713                         .prcm_reg_id = 1,
2714                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2715                         .module_offs = WKUP_MOD,
2716                         .idlest_reg_id = 1,
2717                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2718                 },
2719         },
2720         .slaves         = omap34xx_sr2_slaves,
2721         .slaves_cnt     = ARRAY_SIZE(omap34xx_sr2_slaves),
2722         .dev_attr       = &sr2_dev_attr,
2723         .mpu_irqs       = omap3_smartreflex_core_irqs,
2724         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2725 };
2726
2727 static struct omap_hwmod_ocp_if *omap36xx_sr2_slaves[] = {
2728         &omap36xx_l4_core__sr2,
2729 };
2730
2731 static struct omap_hwmod omap36xx_sr2_hwmod = {
2732         .name           = "sr2",
2733         .class          = &omap36xx_smartreflex_hwmod_class,
2734         .main_clk       = "sr2_fck",
2735         .prcm           = {
2736                 .omap2 = {
2737                         .prcm_reg_id = 1,
2738                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2739                         .module_offs = WKUP_MOD,
2740                         .idlest_reg_id = 1,
2741                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2742                 },
2743         },
2744         .slaves         = omap36xx_sr2_slaves,
2745         .slaves_cnt     = ARRAY_SIZE(omap36xx_sr2_slaves),
2746         .dev_attr       = &sr2_dev_attr,
2747         .mpu_irqs       = omap3_smartreflex_core_irqs,
2748 };
2749
2750 /*
2751  * 'mailbox' class
2752  * mailbox module allowing communication between the on-chip processors
2753  * using a queued mailbox-interrupt mechanism.
2754  */
2755
2756 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2757         .rev_offs       = 0x000,
2758         .sysc_offs      = 0x010,
2759         .syss_offs      = 0x014,
2760         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2761                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2762         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2763         .sysc_fields    = &omap_hwmod_sysc_type1,
2764 };
2765
2766 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2767         .name = "mailbox",
2768         .sysc = &omap3xxx_mailbox_sysc,
2769 };
2770
2771 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2772 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2773         { .irq = 26 },
2774         { .irq = -1 }
2775 };
2776
2777 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2778         {
2779                 .pa_start       = 0x48094000,
2780                 .pa_end         = 0x480941ff,
2781                 .flags          = ADDR_TYPE_RT,
2782         },
2783         { }
2784 };
2785
2786 /* l4_core -> mailbox */
2787 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2788         .master         = &omap3xxx_l4_core_hwmod,
2789         .slave          = &omap3xxx_mailbox_hwmod,
2790         .addr           = omap3xxx_mailbox_addrs,
2791         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2792 };
2793
2794 /* mailbox slave ports */
2795 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2796         &omap3xxx_l4_core__mailbox,
2797 };
2798
2799 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2800         .name           = "mailbox",
2801         .class          = &omap3xxx_mailbox_hwmod_class,
2802         .mpu_irqs       = omap3xxx_mailbox_irqs,
2803         .main_clk       = "mailboxes_ick",
2804         .prcm           = {
2805                 .omap2 = {
2806                         .prcm_reg_id = 1,
2807                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2808                         .module_offs = CORE_MOD,
2809                         .idlest_reg_id = 1,
2810                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2811                 },
2812         },
2813         .slaves         = omap3xxx_mailbox_slaves,
2814         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2815 };
2816
2817 /* l4 core -> mcspi1 interface */
2818 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2819         .master         = &omap3xxx_l4_core_hwmod,
2820         .slave          = &omap34xx_mcspi1,
2821         .clk            = "mcspi1_ick",
2822         .addr           = omap2_mcspi1_addr_space,
2823         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2824 };
2825
2826 /* l4 core -> mcspi2 interface */
2827 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2828         .master         = &omap3xxx_l4_core_hwmod,
2829         .slave          = &omap34xx_mcspi2,
2830         .clk            = "mcspi2_ick",
2831         .addr           = omap2_mcspi2_addr_space,
2832         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2833 };
2834
2835 /* l4 core -> mcspi3 interface */
2836 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2837         .master         = &omap3xxx_l4_core_hwmod,
2838         .slave          = &omap34xx_mcspi3,
2839         .clk            = "mcspi3_ick",
2840         .addr           = omap2430_mcspi3_addr_space,
2841         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2842 };
2843
2844 /* l4 core -> mcspi4 interface */
2845 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2846         {
2847                 .pa_start       = 0x480ba000,
2848                 .pa_end         = 0x480ba0ff,
2849                 .flags          = ADDR_TYPE_RT,
2850         },
2851         { }
2852 };
2853
2854 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2855         .master         = &omap3xxx_l4_core_hwmod,
2856         .slave          = &omap34xx_mcspi4,
2857         .clk            = "mcspi4_ick",
2858         .addr           = omap34xx_mcspi4_addr_space,
2859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2860 };
2861
2862 /*
2863  * 'mcspi' class
2864  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2865  * bus
2866  */
2867
2868 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2869         .rev_offs       = 0x0000,
2870         .sysc_offs      = 0x0010,
2871         .syss_offs      = 0x0014,
2872         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2873                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2874                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2875         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2876         .sysc_fields    = &omap_hwmod_sysc_type1,
2877 };
2878
2879 static struct omap_hwmod_class omap34xx_mcspi_class = {
2880         .name = "mcspi",
2881         .sysc = &omap34xx_mcspi_sysc,
2882         .rev = OMAP3_MCSPI_REV,
2883 };
2884
2885 /* mcspi1 */
2886 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2887         &omap34xx_l4_core__mcspi1,
2888 };
2889
2890 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2891         .num_chipselect = 4,
2892 };
2893
2894 static struct omap_hwmod omap34xx_mcspi1 = {
2895         .name           = "mcspi1",
2896         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
2897         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
2898         .main_clk       = "mcspi1_fck",
2899         .prcm           = {
2900                 .omap2 = {
2901                         .module_offs = CORE_MOD,
2902                         .prcm_reg_id = 1,
2903                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2904                         .idlest_reg_id = 1,
2905                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2906                 },
2907         },
2908         .slaves         = omap34xx_mcspi1_slaves,
2909         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2910         .class          = &omap34xx_mcspi_class,
2911         .dev_attr       = &omap_mcspi1_dev_attr,
2912 };
2913
2914 /* mcspi2 */
2915 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2916         &omap34xx_l4_core__mcspi2,
2917 };
2918
2919 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2920         .num_chipselect = 2,
2921 };
2922
2923 static struct omap_hwmod omap34xx_mcspi2 = {
2924         .name           = "mcspi2",
2925         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
2926         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
2927         .main_clk       = "mcspi2_fck",
2928         .prcm           = {
2929                 .omap2 = {
2930                         .module_offs = CORE_MOD,
2931                         .prcm_reg_id = 1,
2932                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2933                         .idlest_reg_id = 1,
2934                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2935                 },
2936         },
2937         .slaves         = omap34xx_mcspi2_slaves,
2938         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2939         .class          = &omap34xx_mcspi_class,
2940         .dev_attr       = &omap_mcspi2_dev_attr,
2941 };
2942
2943 /* mcspi3 */
2944 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2945         { .name = "irq", .irq = 91 }, /* 91 */
2946         { .irq = -1 }
2947 };
2948
2949 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2950         { .name = "tx0", .dma_req = 15 },
2951         { .name = "rx0", .dma_req = 16 },
2952         { .name = "tx1", .dma_req = 23 },
2953         { .name = "rx1", .dma_req = 24 },
2954         { .dma_req = -1 }
2955 };
2956
2957 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2958         &omap34xx_l4_core__mcspi3,
2959 };
2960
2961 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2962         .num_chipselect = 2,
2963 };
2964
2965 static struct omap_hwmod omap34xx_mcspi3 = {
2966         .name           = "mcspi3",
2967         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
2968         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
2969         .main_clk       = "mcspi3_fck",
2970         .prcm           = {
2971                 .omap2 = {
2972                         .module_offs = CORE_MOD,
2973                         .prcm_reg_id = 1,
2974                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2975                         .idlest_reg_id = 1,
2976                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2977                 },
2978         },
2979         .slaves         = omap34xx_mcspi3_slaves,
2980         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2981         .class          = &omap34xx_mcspi_class,
2982         .dev_attr       = &omap_mcspi3_dev_attr,
2983 };
2984
2985 /* SPI4 */
2986 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2987         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2988         { .irq = -1 }
2989 };
2990
2991 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2992         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2993         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2994         { .dma_req = -1 }
2995 };
2996
2997 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2998         &omap34xx_l4_core__mcspi4,
2999 };
3000
3001 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3002         .num_chipselect = 1,
3003 };
3004
3005 static struct omap_hwmod omap34xx_mcspi4 = {
3006         .name           = "mcspi4",
3007         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
3008         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
3009         .main_clk       = "mcspi4_fck",
3010         .prcm           = {
3011                 .omap2 = {
3012                         .module_offs = CORE_MOD,
3013                         .prcm_reg_id = 1,
3014                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3015                         .idlest_reg_id = 1,
3016                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3017                 },
3018         },
3019         .slaves         = omap34xx_mcspi4_slaves,
3020         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3021         .class          = &omap34xx_mcspi_class,
3022         .dev_attr       = &omap_mcspi4_dev_attr,
3023 };
3024
3025 /* temp. sensor */
3026 struct omap_hwmod_class omap34xx_bandgap_ts_class = {
3027         .name   = "bandgap_ts",
3028 };
3029
3030 static struct omap_hwmod_addr_space omap3xxx_bandgap_ts_addrs[] = {
3031         {
3032                 .name           = "mpu",
3033                 .pa_start       = 0x48002524,
3034                 .pa_end         = 0x48002524 + 4,
3035                 .flags          = ADDR_TYPE_RT
3036         },
3037         { }
3038 };
3039
3040 static struct omap_hwmod omap34xx_bandgap_ts;
3041
3042 /* l4_core -> bandgap */
3043 static struct omap_hwmod_ocp_if omap3xxx_l4_core__bandgap_ts = {
3044         .master         = &omap3xxx_l4_core_hwmod,
3045         .slave          = &omap34xx_bandgap_ts,
3046         .addr           = omap3xxx_bandgap_ts_addrs,
3047         .user           = OCP_USER_MPU,
3048 };
3049
3050 static struct omap_hwmod_ocp_if *omap3xxx_bandgap_ts_slaves[] = {
3051         &omap3xxx_l4_core__bandgap_ts,
3052 };
3053
3054 static struct omap_hwmod omap34xx_bandgap_ts = {
3055         .name           = "bandgap_ts",
3056         .main_clk       = "ts_fck",
3057         .slaves         = omap3xxx_bandgap_ts_slaves,
3058         .slaves_cnt     = ARRAY_SIZE(omap3xxx_bandgap_ts_slaves),
3059         .class          = &omap34xx_bandgap_ts_class,
3060         .flags          = HWMOD_NO_IDLEST,
3061 };
3062
3063 /*
3064  * usbhsotg
3065  */
3066 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3067         .rev_offs       = 0x0400,
3068         .sysc_offs      = 0x0404,
3069         .syss_offs      = 0x0408,
3070         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3071                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3072                           SYSC_HAS_AUTOIDLE),
3073         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3074                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3075         .sysc_fields    = &omap_hwmod_sysc_type1,
3076 };
3077
3078 static struct omap_hwmod_class usbotg_class = {
3079         .name = "usbotg",
3080         .sysc = &omap3xxx_usbhsotg_sysc,
3081 };
3082 /* usb_otg_hs */
3083 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3084
3085         { .name = "mc", .irq = 92 },
3086         { .name = "dma", .irq = 93 },
3087         { .irq = -1 }
3088 };
3089
3090 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3091         .name           = "usb_otg_hs",
3092         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
3093         .main_clk       = "hsotgusb_ick",
3094         .prcm           = {
3095                 .omap2 = {
3096                         .prcm_reg_id = 1,
3097                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3098                         .module_offs = CORE_MOD,
3099                         .idlest_reg_id = 1,
3100                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3101                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3102                 },
3103         },
3104         .masters        = omap3xxx_usbhsotg_masters,
3105         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3106         .slaves         = omap3xxx_usbhsotg_slaves,
3107         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3108         .class          = &usbotg_class,
3109
3110         /*
3111          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
3112          * broken when autoidle is enabled
3113          * workaround is to disable the autoidle bit at module level.
3114          *
3115          * Enabling the device in any other MIDLEMODE setting but force-idle
3116          * causes core_pwrdm not enter idle states at least on OMAP3630.
3117          * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
3118          * signal when MIDLEMODE is set to force-idle.
3119          */
3120         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3121                                 | HWMOD_FORCE_MSTANDBY,
3122 };
3123
3124 /* usb_otg_hs */
3125 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3126
3127         { .name = "mc", .irq = 71 },
3128         { .irq = -1 }
3129 };
3130
3131 static struct omap_hwmod_class am35xx_usbotg_class = {
3132         .name = "am35xx_usbotg",
3133         .sysc = NULL,
3134 };
3135
3136 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3137         .name           = "am35x_otg_hs",
3138         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3139         .main_clk       = NULL,
3140         .prcm = {
3141                 .omap2 = {
3142                 },
3143         },
3144         .masters        = am35xx_usbhsotg_masters,
3145         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3146         .slaves         = am35xx_usbhsotg_slaves,
3147         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3148         .class          = &am35xx_usbotg_class,
3149 };
3150
3151 /* MMC/SD/SDIO common */
3152
3153 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3154         .rev_offs       = 0x1fc,
3155         .sysc_offs      = 0x10,
3156         .syss_offs      = 0x14,
3157         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3158                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3159                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3160         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3161         .sysc_fields    = &omap_hwmod_sysc_type1,
3162 };
3163
3164 static struct omap_hwmod_class omap34xx_mmc_class = {
3165         .name = "mmc",
3166         .sysc = &omap34xx_mmc_sysc,
3167 };
3168
3169 /* MMC/SD/SDIO1 */
3170
3171 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3172         { .irq = 83, },
3173         { .irq = -1 }
3174 };
3175
3176 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3177         { .name = "tx", .dma_req = 61, },
3178         { .name = "rx", .dma_req = 62, },
3179         { .dma_req = -1 }
3180 };
3181
3182 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3183         { .role = "dbck", .clk = "omap_32k_fck", },
3184 };
3185
3186 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3187         &omap3xxx_l4_core__mmc1,
3188 };
3189
3190 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3191         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3192 };
3193
3194 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3195 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
3196         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
3197                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
3198 };
3199
3200 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
3201         .name           = "mmc1",
3202         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3203         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3204         .opt_clks       = omap34xx_mmc1_opt_clks,
3205         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3206         .main_clk       = "mmchs1_fck",
3207         .prcm           = {
3208                 .omap2 = {
3209                         .module_offs = CORE_MOD,
3210                         .prcm_reg_id = 1,
3211                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3212                         .idlest_reg_id = 1,
3213                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3214                 },
3215         },
3216         .dev_attr       = &mmc1_pre_es3_dev_attr,
3217         .slaves         = omap3xxx_mmc1_slaves,
3218         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3219         .class          = &omap34xx_mmc_class,
3220 };
3221
3222 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
3223         .name           = "mmc1",
3224         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3225         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3226         .opt_clks       = omap34xx_mmc1_opt_clks,
3227         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3228         .main_clk       = "mmchs1_fck",
3229         .prcm           = {
3230                 .omap2 = {
3231                         .module_offs = CORE_MOD,
3232                         .prcm_reg_id = 1,
3233                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3234                         .idlest_reg_id = 1,
3235                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3236                 },
3237         },
3238         .dev_attr       = &mmc1_dev_attr,
3239         .slaves         = omap3xxx_mmc1_slaves,
3240         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3241         .class          = &omap34xx_mmc_class,
3242 };
3243
3244 /* MMC/SD/SDIO2 */
3245
3246 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3247         { .irq = INT_24XX_MMC2_IRQ, },
3248         { .irq = -1 }
3249 };
3250
3251 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3252         { .name = "tx", .dma_req = 47, },
3253         { .name = "rx", .dma_req = 48, },
3254         { .dma_req = -1 }
3255 };
3256
3257 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3258         { .role = "dbck", .clk = "omap_32k_fck", },
3259 };
3260
3261 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3262         &omap3xxx_l4_core__mmc2,
3263 };
3264
3265 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3266 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
3267         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
3268 };
3269
3270 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
3271         .name           = "mmc2",
3272         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3273         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3274         .opt_clks       = omap34xx_mmc2_opt_clks,
3275         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3276         .main_clk       = "mmchs2_fck",
3277         .prcm           = {
3278                 .omap2 = {
3279                         .module_offs = CORE_MOD,
3280                         .prcm_reg_id = 1,
3281                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3282                         .idlest_reg_id = 1,
3283                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3284                 },
3285         },
3286         .dev_attr       = &mmc2_pre_es3_dev_attr,
3287         .slaves         = omap3xxx_mmc2_slaves,
3288         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3289         .class          = &omap34xx_mmc_class,
3290 };
3291
3292 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
3293         .name           = "mmc2",
3294         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3295         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3296         .opt_clks       = omap34xx_mmc2_opt_clks,
3297         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3298         .main_clk       = "mmchs2_fck",
3299         .prcm           = {
3300                 .omap2 = {
3301                         .module_offs = CORE_MOD,
3302                         .prcm_reg_id = 1,
3303                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3304                         .idlest_reg_id = 1,
3305                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3306                 },
3307         },
3308         .slaves         = omap3xxx_mmc2_slaves,
3309         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3310         .class          = &omap34xx_mmc_class,
3311 };
3312
3313 /* MMC/SD/SDIO3 */
3314
3315 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3316         { .irq = 94, },
3317         { .irq = -1 }
3318 };
3319
3320 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3321         { .name = "tx", .dma_req = 77, },
3322         { .name = "rx", .dma_req = 78, },
3323         { .dma_req = -1 }
3324 };
3325
3326 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3327         { .role = "dbck", .clk = "omap_32k_fck", },
3328 };
3329
3330 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3331         &omap3xxx_l4_core__mmc3,
3332 };
3333
3334 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3335         .name           = "mmc3",
3336         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3337         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3338         .opt_clks       = omap34xx_mmc3_opt_clks,
3339         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3340         .main_clk       = "mmchs3_fck",
3341         .prcm           = {
3342                 .omap2 = {
3343                         .prcm_reg_id = 1,
3344                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3345                         .idlest_reg_id = 1,
3346                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3347                 },
3348         },
3349         .slaves         = omap3xxx_mmc3_slaves,
3350         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3351         .class          = &omap34xx_mmc_class,
3352 };
3353
3354 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3355         &omap3xxx_l3_main_hwmod,
3356         &omap3xxx_l4_core_hwmod,
3357         &omap3xxx_l4_per_hwmod,
3358         &omap3xxx_l4_wkup_hwmod,
3359         &omap3xxx_mmc3_hwmod,
3360         &omap3xxx_mpu_hwmod,
3361
3362         &omap3xxx_timer1_hwmod,
3363         &omap3xxx_timer2_hwmod,
3364         &omap3xxx_timer3_hwmod,
3365         &omap3xxx_timer4_hwmod,
3366         &omap3xxx_timer5_hwmod,
3367         &omap3xxx_timer6_hwmod,
3368         &omap3xxx_timer7_hwmod,
3369         &omap3xxx_timer8_hwmod,
3370         &omap3xxx_timer9_hwmod,
3371         &omap3xxx_timer10_hwmod,
3372         &omap3xxx_timer11_hwmod,
3373
3374         &omap3xxx_wd_timer2_hwmod,
3375         &omap3xxx_uart1_hwmod,
3376         &omap3xxx_uart2_hwmod,
3377         &omap3xxx_uart3_hwmod,
3378
3379         /* i2c class */
3380         &omap3xxx_i2c1_hwmod,
3381         &omap3xxx_i2c2_hwmod,
3382         &omap3xxx_i2c3_hwmod,
3383
3384         /* gpio class */
3385         &omap3xxx_gpio1_hwmod,
3386         &omap3xxx_gpio2_hwmod,
3387         &omap3xxx_gpio3_hwmod,
3388         &omap3xxx_gpio4_hwmod,
3389         &omap3xxx_gpio5_hwmod,
3390         &omap3xxx_gpio6_hwmod,
3391
3392         /* dma_system class*/
3393         &omap3xxx_dma_system_hwmod,
3394
3395         /* mcbsp class */
3396         &omap3xxx_mcbsp1_hwmod,
3397         &omap3xxx_mcbsp2_hwmod,
3398         &omap3xxx_mcbsp3_hwmod,
3399         &omap3xxx_mcbsp4_hwmod,
3400         &omap3xxx_mcbsp5_hwmod,
3401         &omap3xxx_mcbsp2_sidetone_hwmod,
3402         &omap3xxx_mcbsp3_sidetone_hwmod,
3403
3404
3405         /* mcspi class */
3406         &omap34xx_mcspi1,
3407         &omap34xx_mcspi2,
3408         &omap34xx_mcspi3,
3409         &omap34xx_mcspi4,
3410
3411         &omap34xx_bandgap_ts,
3412
3413         NULL,
3414 };
3415
3416 /* GP-only hwmods */
3417 static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
3418         &omap3xxx_timer12_hwmod,
3419         NULL
3420 };
3421
3422 /* 3430ES1-only hwmods */
3423 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
3424         &omap3430es1_dss_core_hwmod,
3425         NULL
3426 };
3427
3428 /* 3430ES2+-only hwmods */
3429 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
3430         &omap3xxx_dss_core_hwmod,
3431         &omap3xxx_usbhsotg_hwmod,
3432         NULL
3433 };
3434
3435 /* <= 3430ES3-only hwmods */
3436 static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
3437         &omap3xxx_pre_es3_mmc1_hwmod,
3438         &omap3xxx_pre_es3_mmc2_hwmod,
3439         NULL
3440 };
3441
3442 /* 3430ES3+-only hwmods */
3443 static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
3444         &omap3xxx_es3plus_mmc1_hwmod,
3445         &omap3xxx_es3plus_mmc2_hwmod,
3446         NULL
3447 };
3448
3449 /* 34xx-only hwmods (all ES revisions) */
3450 static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
3451         &omap3xxx_iva_hwmod,
3452         &omap34xx_sr1_hwmod,
3453         &omap34xx_sr2_hwmod,
3454         &omap3xxx_mailbox_hwmod,
3455         NULL
3456 };
3457
3458 /* 36xx-only hwmods (all ES revisions) */
3459 static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
3460         &omap3xxx_iva_hwmod,
3461         &omap36xx_uart4_hwmod,
3462         &omap3xxx_dss_core_hwmod,
3463         &omap36xx_sr1_hwmod,
3464         &omap36xx_sr2_hwmod,
3465         &omap3xxx_usbhsotg_hwmod,
3466         &omap3xxx_mailbox_hwmod,
3467         &omap3xxx_es3plus_mmc1_hwmod,
3468         &omap3xxx_es3plus_mmc2_hwmod,
3469         NULL
3470 };
3471
3472 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3473         &omap3xxx_dss_core_hwmod, /* XXX ??? */
3474         &am35xx_usbhsotg_hwmod,
3475         &omap3xxx_es3plus_mmc1_hwmod,
3476         &omap3xxx_es3plus_mmc2_hwmod,
3477         NULL
3478 };
3479
3480 static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
3481         /* dss class */
3482         &omap3xxx_dss_dispc_hwmod,
3483         &omap3xxx_dss_dsi1_hwmod,
3484         &omap3xxx_dss_rfbi_hwmod,
3485         &omap3xxx_dss_venc_hwmod,
3486         NULL
3487 };
3488
3489 int __init omap3xxx_hwmod_init(void)
3490 {
3491         int r;
3492         struct omap_hwmod **h = NULL;
3493         unsigned int rev;
3494
3495         /* Register hwmods common to all OMAP3 */
3496         r = omap_hwmod_register(omap3xxx_hwmods);
3497         if (r < 0)
3498                 return r;
3499
3500         /* Register GP-only hwmods. */
3501         if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3502                 r = omap_hwmod_register(omap3xxx_gp_hwmods);
3503                 if (r < 0)
3504                         return r;
3505         }
3506
3507         rev = omap_rev();
3508
3509         /*
3510          * Register hwmods common to individual OMAP3 families, all
3511          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3512          * All possible revisions should be included in this conditional.
3513          */
3514         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3515             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3516             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3517                 h = omap34xx_hwmods;
3518         } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3519                 h = am35xx_hwmods;
3520         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3521                    rev == OMAP3630_REV_ES1_2) {
3522                 h = omap36xx_hwmods;
3523         } else {
3524                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3525                 return -EINVAL;
3526         };
3527
3528         r = omap_hwmod_register(h);
3529         if (r < 0)
3530                 return r;
3531
3532         /*
3533          * Register hwmods specific to certain ES levels of a
3534          * particular family of silicon (e.g., 34xx ES1.0)
3535          */
3536         h = NULL;
3537         if (rev == OMAP3430_REV_ES1_0) {
3538                 h = omap3430es1_hwmods;
3539         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3540                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3541                    rev == OMAP3430_REV_ES3_1_2) {
3542                 h = omap3430es2plus_hwmods;
3543         };
3544
3545         if (h) {
3546                 r = omap_hwmod_register(h);
3547                 if (r < 0)
3548                         return r;
3549         }
3550
3551         h = NULL;
3552         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3553             rev == OMAP3430_REV_ES2_1) {
3554                 h = omap3430_pre_es3_hwmods;
3555         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3556                    rev == OMAP3430_REV_ES3_1_2) {
3557                 h = omap3430_es3plus_hwmods;
3558         };
3559
3560         if (h)
3561                 r = omap_hwmod_register(h);
3562         if (r < 0)
3563                 return r;
3564
3565         /*
3566          * DSS code presumes that dss_core hwmod is handled first,
3567          * _before_ any other DSS related hwmods so register common
3568          * DSS hwmods last to ensure that dss_core is already registered.
3569          * Otherwise some change things may happen, for ex. if dispc
3570          * is handled before dss_core and DSS is enabled in bootloader
3571          * DIPSC will be reset with outputs enabled which sometimes leads
3572          * to unrecoverable L3 error.
3573          */
3574         r = omap_hwmod_register(omap3xxx_dss_hwmods);
3575
3576         return r;
3577 }