arch/arm/mach-omap2/omap_hwmod_2420_data.c

   1 /*
   2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcspi.h>
  22 #include <plat/dmtimer.h>
  23 #include <plat/l3_2xxx.h>
  24 #include <plat/l4_2xxx.h>
  25
  26 #include "omap_hwmod_common_data.h"
  27
  28 #include "cm-regbits-24xx.h"
  29 #include "prm-regbits-24xx.h"
  30 #include "wd_timer.h"
  31
  32 /*
  33  * OMAP2420 hardware module integration data
  34  *
  35  * ALl of the data in this section should be autogeneratable from the
  36  * TI hardware database or other technical documentation.  Data that
  37  * is driver-specific or driver-kernel integration-specific belongs
  38  * elsewhere.
  39  */
  40
  41 static struct omap_hwmod omap2420_mpu_hwmod;
  42 static struct omap_hwmod omap2420_iva_hwmod;
  43 static struct omap_hwmod omap2420_l3_main_hwmod;
  44 static struct omap_hwmod omap2420_l4_core_hwmod;
  45 static struct omap_hwmod omap2420_dss_core_hwmod;
  46 static struct omap_hwmod omap2420_dss_dispc_hwmod;
  47 static struct omap_hwmod omap2420_dss_rfbi_hwmod;
  48 static struct omap_hwmod omap2420_dss_venc_hwmod;
  49 static struct omap_hwmod omap2420_wd_timer2_hwmod;
  50 static struct omap_hwmod omap2420_gpio1_hwmod;
  51 static struct omap_hwmod omap2420_gpio2_hwmod;
  52 static struct omap_hwmod omap2420_gpio3_hwmod;
  53 static struct omap_hwmod omap2420_gpio4_hwmod;
  54 static struct omap_hwmod omap2420_dma_system_hwmod;
  55 static struct omap_hwmod omap2420_mcspi1_hwmod;
  56 static struct omap_hwmod omap2420_mcspi2_hwmod;
  57
  58 /* L3 -> L4_CORE interface */
  59 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
  60         .master = &omap2420_l3_main_hwmod,
  61         .slave  = &omap2420_l4_core_hwmod,
  62         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  63 };
  64
  65 /* MPU -> L3 interface */
  66 static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
  67         .master = &omap2420_mpu_hwmod,
  68         .slave  = &omap2420_l3_main_hwmod,
  69         .user   = OCP_USER_MPU,
  70 };
  71
  72 /* Slave interfaces on the L3 interconnect */
  73 static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
  74         &omap2420_mpu__l3_main,
  75 };
  76
  77 /* DSS -> l3 */
  78 static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
  79         .master         = &omap2420_dss_core_hwmod,
  80         .slave          = &omap2420_l3_main_hwmod,
  81         .fw = {
  82                 .omap2 = {
  83                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  84                         .flags  = OMAP_FIREWALL_L3,
  85                 }
  86         },
  87         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  88 };
  89
  90 /* Master interfaces on the L3 interconnect */
  91 static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
  92         &omap2420_l3_main__l4_core,
  93 };
  94
  95 /* L3 */
  96 static struct omap_hwmod omap2420_l3_main_hwmod = {
  97         .name           = "l3_main",
  98         .class          = &l3_hwmod_class,
  99         .masters        = omap2420_l3_main_masters,
 100         .masters_cnt    = ARRAY_SIZE(omap2420_l3_main_masters),
 101         .slaves         = omap2420_l3_main_slaves,
 102         .slaves_cnt     = ARRAY_SIZE(omap2420_l3_main_slaves),
 103         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 104         .flags          = HWMOD_NO_IDLEST,
 105 };
 106
 107 static struct omap_hwmod omap2420_l4_wkup_hwmod;
 108 static struct omap_hwmod omap2420_uart1_hwmod;
 109 static struct omap_hwmod omap2420_uart2_hwmod;
 110 static struct omap_hwmod omap2420_uart3_hwmod;
 111 static struct omap_hwmod omap2420_i2c1_hwmod;
 112 static struct omap_hwmod omap2420_i2c2_hwmod;
 113 static struct omap_hwmod omap2420_mcbsp1_hwmod;
 114 static struct omap_hwmod omap2420_mcbsp2_hwmod;
 115
 116 /* l4 core -> mcspi1 interface */
 117 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
 118         .master         = &omap2420_l4_core_hwmod,
 119         .slave          = &omap2420_mcspi1_hwmod,
 120         .clk            = "mcspi1_ick",
 121         .addr           = omap2_mcspi1_addr_space,
 122         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 123 };
 124
 125 /* l4 core -> mcspi2 interface */
 126 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
 127         .master         = &omap2420_l4_core_hwmod,
 128         .slave          = &omap2420_mcspi2_hwmod,
 129         .clk            = "mcspi2_ick",
 130         .addr           = omap2_mcspi2_addr_space,
 131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 132 };
 133
 134 /* L4_CORE -> L4_WKUP interface */
 135 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
 136         .master = &omap2420_l4_core_hwmod,
 137         .slave  = &omap2420_l4_wkup_hwmod,
 138         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 139 };
 140
 141 /* L4 CORE -> UART1 interface */
 142 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 143         .master         = &omap2420_l4_core_hwmod,
 144         .slave          = &omap2420_uart1_hwmod,
 145         .clk            = "uart1_ick",
 146         .addr           = omap2xxx_uart1_addr_space,
 147         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 148 };
 149
 150 /* L4 CORE -> UART2 interface */
 151 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 152         .master         = &omap2420_l4_core_hwmod,
 153         .slave          = &omap2420_uart2_hwmod,
 154         .clk            = "uart2_ick",
 155         .addr           = omap2xxx_uart2_addr_space,
 156         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 157 };
 158
 159 /* L4 PER -> UART3 interface */
 160 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 161         .master         = &omap2420_l4_core_hwmod,
 162         .slave          = &omap2420_uart3_hwmod,
 163         .clk            = "uart3_ick",
 164         .addr           = omap2xxx_uart3_addr_space,
 165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 166 };
 167
 168 /* L4 CORE -> I2C1 interface */
 169 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 170         .master         = &omap2420_l4_core_hwmod,
 171         .slave          = &omap2420_i2c1_hwmod,
 172         .clk            = "i2c1_ick",
 173         .addr           = omap2_i2c1_addr_space,
 174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 175 };
 176
 177 /* L4 CORE -> I2C2 interface */
 178 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 179         .master         = &omap2420_l4_core_hwmod,
 180         .slave          = &omap2420_i2c2_hwmod,
 181         .clk            = "i2c2_ick",
 182         .addr           = omap2_i2c2_addr_space,
 183         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 184 };
 185
 186 /* Slave interfaces on the L4_CORE interconnect */
 187 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 188         &omap2420_l3_main__l4_core,
 189 };
 190
 191 /* Master interfaces on the L4_CORE interconnect */
 192 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
 193         &omap2420_l4_core__l4_wkup,
 194         &omap2_l4_core__uart1,
 195         &omap2_l4_core__uart2,
 196         &omap2_l4_core__uart3,
 197         &omap2420_l4_core__i2c1,
 198         &omap2420_l4_core__i2c2
 199 };
 200
 201 /* L4 CORE */
 202 static struct omap_hwmod omap2420_l4_core_hwmod = {
 203         .name           = "l4_core",
 204         .class          = &l4_hwmod_class,
 205         .masters        = omap2420_l4_core_masters,
 206         .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
 207         .slaves         = omap2420_l4_core_slaves,
 208         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
 209         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 210         .flags          = HWMOD_NO_IDLEST,
 211 };
 212
 213 /* Slave interfaces on the L4_WKUP interconnect */
 214 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
 215         &omap2420_l4_core__l4_wkup,
 216 };
 217
 218 /* Master interfaces on the L4_WKUP interconnect */
 219 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
 220 };
 221
 222 /* L4 WKUP */
 223 static struct omap_hwmod omap2420_l4_wkup_hwmod = {
 224         .name           = "l4_wkup",
 225         .class          = &l4_hwmod_class,
 226         .masters        = omap2420_l4_wkup_masters,
 227         .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
 228         .slaves         = omap2420_l4_wkup_slaves,
 229         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
 230         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 231         .flags          = HWMOD_NO_IDLEST,
 232 };
 233
 234 /* Master interfaces on the MPU device */
 235 static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
 236         &omap2420_mpu__l3_main,
 237 };
 238
 239 /* MPU */
 240 static struct omap_hwmod omap2420_mpu_hwmod = {
 241         .name           = "mpu",
 242         .class          = &mpu_hwmod_class,
 243         .main_clk       = "mpu_ck",
 244         .masters        = omap2420_mpu_masters,
 245         .masters_cnt    = ARRAY_SIZE(omap2420_mpu_masters),
 246         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 247 };
 248
 249 /*
 250  * IVA1 interface data
 251  */
 252
 253 /* IVA <- L3 interface */
 254 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 255         .master         = &omap2420_l3_main_hwmod,
 256         .slave          = &omap2420_iva_hwmod,
 257         .clk            = "iva1_ifck",
 258         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 259 };
 260
 261 static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
 262         &omap2420_l3__iva,
 263 };
 264
 265 /*
 266  * IVA2 (IVA2)
 267  */
 268
 269 static struct omap_hwmod omap2420_iva_hwmod = {
 270         .name           = "iva",
 271         .class          = &iva_hwmod_class,
 272         .masters        = omap2420_iva_masters,
 273         .masters_cnt    = ARRAY_SIZE(omap2420_iva_masters),
 274         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 275 };
 276
 277 /* timer1 */
 278 static struct omap_hwmod omap2420_timer1_hwmod;
 279
 280 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
 281         {
 282                 .pa_start       = 0x48028000,
 283                 .pa_end         = 0x48028000 + SZ_1K - 1,
 284                 .flags          = ADDR_TYPE_RT
 285         },
 286         { }
 287 };
 288
 289 /* l4_wkup -> timer1 */
 290 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
 291         .master         = &omap2420_l4_wkup_hwmod,
 292         .slave          = &omap2420_timer1_hwmod,
 293         .clk            = "gpt1_ick",
 294         .addr           = omap2420_timer1_addrs,
 295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 296 };
 297
 298 /* timer1 slave port */
 299 static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
 300         &omap2420_l4_wkup__timer1,
 301 };
 302
 303 /* timer1 hwmod */
 304 static struct omap_hwmod omap2420_timer1_hwmod = {
 305         .name           = "timer1",
 306         .mpu_irqs       = omap2_timer1_mpu_irqs,
 307         .main_clk       = "gpt1_fck",
 308         .prcm           = {
 309                 .omap2 = {
 310                         .prcm_reg_id = 1,
 311                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 312                         .module_offs = WKUP_MOD,
 313                         .idlest_reg_id = 1,
 314                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 315                 },
 316         },
 317         .slaves         = omap2420_timer1_slaves,
 318         .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
 319         .class          = &omap2xxx_timer_hwmod_class,
 320         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 321 };
 322
 323 /* timer2 */
 324 static struct omap_hwmod omap2420_timer2_hwmod;
 325
 326 /* l4_core -> timer2 */
 327 static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
 328         .master         = &omap2420_l4_core_hwmod,
 329         .slave          = &omap2420_timer2_hwmod,
 330         .clk            = "gpt2_ick",
 331         .addr           = omap2xxx_timer2_addrs,
 332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 333 };
 334
 335 /* timer2 slave port */
 336 static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
 337         &omap2420_l4_core__timer2,
 338 };
 339
 340 /* timer2 hwmod */
 341 static struct omap_hwmod omap2420_timer2_hwmod = {
 342         .name           = "timer2",
 343         .mpu_irqs       = omap2_timer2_mpu_irqs,
 344         .main_clk       = "gpt2_fck",
 345         .prcm           = {
 346                 .omap2 = {
 347                         .prcm_reg_id = 1,
 348                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 349                         .module_offs = CORE_MOD,
 350                         .idlest_reg_id = 1,
 351                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 352                 },
 353         },
 354         .slaves         = omap2420_timer2_slaves,
 355         .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
 356         .class          = &omap2xxx_timer_hwmod_class,
 357         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 358 };
 359
 360 /* timer3 */
 361 static struct omap_hwmod omap2420_timer3_hwmod;
 362
 363 /* l4_core -> timer3 */
 364 static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
 365         .master         = &omap2420_l4_core_hwmod,
 366         .slave          = &omap2420_timer3_hwmod,
 367         .clk            = "gpt3_ick",
 368         .addr           = omap2xxx_timer3_addrs,
 369         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 370 };
 371
 372 /* timer3 slave port */
 373 static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
 374         &omap2420_l4_core__timer3,
 375 };
 376
 377 /* timer3 hwmod */
 378 static struct omap_hwmod omap2420_timer3_hwmod = {
 379         .name           = "timer3",
 380         .mpu_irqs       = omap2_timer3_mpu_irqs,
 381         .main_clk       = "gpt3_fck",
 382         .prcm           = {
 383                 .omap2 = {
 384                         .prcm_reg_id = 1,
 385                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 386                         .module_offs = CORE_MOD,
 387                         .idlest_reg_id = 1,
 388                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 389                 },
 390         },
 391         .slaves         = omap2420_timer3_slaves,
 392         .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
 393         .class          = &omap2xxx_timer_hwmod_class,
 394         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 395 };
 396
 397 /* timer4 */
 398 static struct omap_hwmod omap2420_timer4_hwmod;
 399
 400 /* l4_core -> timer4 */
 401 static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
 402         .master         = &omap2420_l4_core_hwmod,
 403         .slave          = &omap2420_timer4_hwmod,
 404         .clk            = "gpt4_ick",
 405         .addr           = omap2xxx_timer4_addrs,
 406         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 407 };
 408
 409 /* timer4 slave port */
 410 static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
 411         &omap2420_l4_core__timer4,
 412 };
 413
 414 /* timer4 hwmod */
 415 static struct omap_hwmod omap2420_timer4_hwmod = {
 416         .name           = "timer4",
 417         .mpu_irqs       = omap2_timer4_mpu_irqs,
 418         .main_clk       = "gpt4_fck",
 419         .prcm           = {
 420                 .omap2 = {
 421                         .prcm_reg_id = 1,
 422                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 423                         .module_offs = CORE_MOD,
 424                         .idlest_reg_id = 1,
 425                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 426                 },
 427         },
 428         .slaves         = omap2420_timer4_slaves,
 429         .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
 430         .class          = &omap2xxx_timer_hwmod_class,
 431         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 432 };
 433
 434 /* timer5 */
 435 static struct omap_hwmod omap2420_timer5_hwmod;
 436
 437 /* l4_core -> timer5 */
 438 static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
 439         .master         = &omap2420_l4_core_hwmod,
 440         .slave          = &omap2420_timer5_hwmod,
 441         .clk            = "gpt5_ick",
 442         .addr           = omap2xxx_timer5_addrs,
 443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 444 };
 445
 446 /* timer5 slave port */
 447 static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
 448         &omap2420_l4_core__timer5,
 449 };
 450
 451 /* timer5 hwmod */
 452 static struct omap_hwmod omap2420_timer5_hwmod = {
 453         .name           = "timer5",
 454         .mpu_irqs       = omap2_timer5_mpu_irqs,
 455         .main_clk       = "gpt5_fck",
 456         .prcm           = {
 457                 .omap2 = {
 458                         .prcm_reg_id = 1,
 459                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 460                         .module_offs = CORE_MOD,
 461                         .idlest_reg_id = 1,
 462                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 463                 },
 464         },
 465         .slaves         = omap2420_timer5_slaves,
 466         .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
 467         .class          = &omap2xxx_timer_hwmod_class,
 468         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 469 };
 470
 471
 472 /* timer6 */
 473 static struct omap_hwmod omap2420_timer6_hwmod;
 474
 475 /* l4_core -> timer6 */
 476 static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
 477         .master         = &omap2420_l4_core_hwmod,
 478         .slave          = &omap2420_timer6_hwmod,
 479         .clk            = "gpt6_ick",
 480         .addr           = omap2xxx_timer6_addrs,
 481         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 482 };
 483
 484 /* timer6 slave port */
 485 static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
 486         &omap2420_l4_core__timer6,
 487 };
 488
 489 /* timer6 hwmod */
 490 static struct omap_hwmod omap2420_timer6_hwmod = {
 491         .name           = "timer6",
 492         .mpu_irqs       = omap2_timer6_mpu_irqs,
 493         .main_clk       = "gpt6_fck",
 494         .prcm           = {
 495                 .omap2 = {
 496                         .prcm_reg_id = 1,
 497                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 498                         .module_offs = CORE_MOD,
 499                         .idlest_reg_id = 1,
 500                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 501                 },
 502         },
 503         .slaves         = omap2420_timer6_slaves,
 504         .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
 505         .class          = &omap2xxx_timer_hwmod_class,
 506         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 507 };
 508
 509 /* timer7 */
 510 static struct omap_hwmod omap2420_timer7_hwmod;
 511
 512 /* l4_core -> timer7 */
 513 static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
 514         .master         = &omap2420_l4_core_hwmod,
 515         .slave          = &omap2420_timer7_hwmod,
 516         .clk            = "gpt7_ick",
 517         .addr           = omap2xxx_timer7_addrs,
 518         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 519 };
 520
 521 /* timer7 slave port */
 522 static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
 523         &omap2420_l4_core__timer7,
 524 };
 525
 526 /* timer7 hwmod */
 527 static struct omap_hwmod omap2420_timer7_hwmod = {
 528         .name           = "timer7",
 529         .mpu_irqs       = omap2_timer7_mpu_irqs,
 530         .main_clk       = "gpt7_fck",
 531         .prcm           = {
 532                 .omap2 = {
 533                         .prcm_reg_id = 1,
 534                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 535                         .module_offs = CORE_MOD,
 536                         .idlest_reg_id = 1,
 537                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 538                 },
 539         },
 540         .slaves         = omap2420_timer7_slaves,
 541         .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
 542         .class          = &omap2xxx_timer_hwmod_class,
 543         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 544 };
 545
 546 /* timer8 */
 547 static struct omap_hwmod omap2420_timer8_hwmod;
 548
 549 /* l4_core -> timer8 */
 550 static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
 551         .master         = &omap2420_l4_core_hwmod,
 552         .slave          = &omap2420_timer8_hwmod,
 553         .clk            = "gpt8_ick",
 554         .addr           = omap2xxx_timer8_addrs,
 555         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 556 };
 557
 558 /* timer8 slave port */
 559 static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
 560         &omap2420_l4_core__timer8,
 561 };
 562
 563 /* timer8 hwmod */
 564 static struct omap_hwmod omap2420_timer8_hwmod = {
 565         .name           = "timer8",
 566         .mpu_irqs       = omap2_timer8_mpu_irqs,
 567         .main_clk       = "gpt8_fck",
 568         .prcm           = {
 569                 .omap2 = {
 570                         .prcm_reg_id = 1,
 571                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 572                         .module_offs = CORE_MOD,
 573                         .idlest_reg_id = 1,
 574                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 575                 },
 576         },
 577         .slaves         = omap2420_timer8_slaves,
 578         .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
 579         .class          = &omap2xxx_timer_hwmod_class,
 580         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 581 };
 582
 583 /* timer9 */
 584 static struct omap_hwmod omap2420_timer9_hwmod;
 585
 586 /* l4_core -> timer9 */
 587 static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
 588         .master         = &omap2420_l4_core_hwmod,
 589         .slave          = &omap2420_timer9_hwmod,
 590         .clk            = "gpt9_ick",
 591         .addr           = omap2xxx_timer9_addrs,
 592         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 593 };
 594
 595 /* timer9 slave port */
 596 static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
 597         &omap2420_l4_core__timer9,
 598 };
 599
 600 /* timer9 hwmod */
 601 static struct omap_hwmod omap2420_timer9_hwmod = {
 602         .name           = "timer9",
 603         .mpu_irqs       = omap2_timer9_mpu_irqs,
 604         .main_clk       = "gpt9_fck",
 605         .prcm           = {
 606                 .omap2 = {
 607                         .prcm_reg_id = 1,
 608                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 609                         .module_offs = CORE_MOD,
 610                         .idlest_reg_id = 1,
 611                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 612                 },
 613         },
 614         .slaves         = omap2420_timer9_slaves,
 615         .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
 616         .class          = &omap2xxx_timer_hwmod_class,
 617         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 618 };
 619
 620 /* timer10 */
 621 static struct omap_hwmod omap2420_timer10_hwmod;
 622
 623 /* l4_core -> timer10 */
 624 static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
 625         .master         = &omap2420_l4_core_hwmod,
 626         .slave          = &omap2420_timer10_hwmod,
 627         .clk            = "gpt10_ick",
 628         .addr           = omap2_timer10_addrs,
 629         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 630 };
 631
 632 /* timer10 slave port */
 633 static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
 634         &omap2420_l4_core__timer10,
 635 };
 636
 637 /* timer10 hwmod */
 638 static struct omap_hwmod omap2420_timer10_hwmod = {
 639         .name           = "timer10",
 640         .mpu_irqs       = omap2_timer10_mpu_irqs,
 641         .main_clk       = "gpt10_fck",
 642         .prcm           = {
 643                 .omap2 = {
 644                         .prcm_reg_id = 1,
 645                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 646                         .module_offs = CORE_MOD,
 647                         .idlest_reg_id = 1,
 648                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 649                 },
 650         },
 651         .slaves         = omap2420_timer10_slaves,
 652         .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
 653         .class          = &omap2xxx_timer_hwmod_class,
 654         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 655 };
 656
 657 /* timer11 */
 658 static struct omap_hwmod omap2420_timer11_hwmod;
 659
 660 /* l4_core -> timer11 */
 661 static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
 662         .master         = &omap2420_l4_core_hwmod,
 663         .slave          = &omap2420_timer11_hwmod,
 664         .clk            = "gpt11_ick",
 665         .addr           = omap2_timer11_addrs,
 666         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 667 };
 668
 669 /* timer11 slave port */
 670 static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
 671         &omap2420_l4_core__timer11,
 672 };
 673
 674 /* timer11 hwmod */
 675 static struct omap_hwmod omap2420_timer11_hwmod = {
 676         .name           = "timer11",
 677         .mpu_irqs       = omap2_timer11_mpu_irqs,
 678         .main_clk       = "gpt11_fck",
 679         .prcm           = {
 680                 .omap2 = {
 681                         .prcm_reg_id = 1,
 682                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 683                         .module_offs = CORE_MOD,
 684                         .idlest_reg_id = 1,
 685                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 686                 },
 687         },
 688         .slaves         = omap2420_timer11_slaves,
 689         .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
 690         .class          = &omap2xxx_timer_hwmod_class,
 691         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 692 };
 693
 694 /* timer12 */
 695 static struct omap_hwmod omap2420_timer12_hwmod;
 696
 697 /* l4_core -> timer12 */
 698 static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
 699         .master         = &omap2420_l4_core_hwmod,
 700         .slave          = &omap2420_timer12_hwmod,
 701         .clk            = "gpt12_ick",
 702         .addr           = omap2xxx_timer12_addrs,
 703         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 704 };
 705
 706 /* timer12 slave port */
 707 static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
 708         &omap2420_l4_core__timer12,
 709 };
 710
 711 /* timer12 hwmod */
 712 static struct omap_hwmod omap2420_timer12_hwmod = {
 713         .name           = "timer12",
 714         .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
 715         .main_clk       = "gpt12_fck",
 716         .prcm           = {
 717                 .omap2 = {
 718                         .prcm_reg_id = 1,
 719                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 720                         .module_offs = CORE_MOD,
 721                         .idlest_reg_id = 1,
 722                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 723                 },
 724         },
 725         .slaves         = omap2420_timer12_slaves,
 726         .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
 727         .class          = &omap2xxx_timer_hwmod_class,
 728         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 729 };
 730
 731 /* l4_wkup -> wd_timer2 */
 732 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 733         {
 734                 .pa_start       = 0x48022000,
 735                 .pa_end         = 0x4802207f,
 736                 .flags          = ADDR_TYPE_RT
 737         },
 738         { }
 739 };
 740
 741 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 742         .master         = &omap2420_l4_wkup_hwmod,
 743         .slave          = &omap2420_wd_timer2_hwmod,
 744         .clk            = "mpu_wdt_ick",
 745         .addr           = omap2420_wd_timer2_addrs,
 746         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 747 };
 748
 749 /* wd_timer2 */
 750 static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
 751         &omap2420_l4_wkup__wd_timer2,
 752 };
 753
 754 static struct omap_hwmod omap2420_wd_timer2_hwmod = {
 755         .name           = "wd_timer2",
 756         .class          = &omap2xxx_wd_timer_hwmod_class,
 757         .main_clk       = "mpu_wdt_fck",
 758         .prcm           = {
 759                 .omap2 = {
 760                         .prcm_reg_id = 1,
 761                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 762                         .module_offs = WKUP_MOD,
 763                         .idlest_reg_id = 1,
 764                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 765                 },
 766         },
 767         .slaves         = omap2420_wd_timer2_slaves,
 768         .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
 769         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 770 };
 771
 772 /* UART1 */
 773
 774 static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
 775         &omap2_l4_core__uart1,
 776 };
 777
 778 static struct omap_hwmod omap2420_uart1_hwmod = {
 779         .name           = "uart1",
 780         .mpu_irqs       = omap2_uart1_mpu_irqs,
 781         .sdma_reqs      = omap2_uart1_sdma_reqs,
 782         .main_clk       = "uart1_fck",
 783         .prcm           = {
 784                 .omap2 = {
 785                         .module_offs = CORE_MOD,
 786                         .prcm_reg_id = 1,
 787                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 788                         .idlest_reg_id = 1,
 789                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 790                 },
 791         },
 792         .slaves         = omap2420_uart1_slaves,
 793         .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
 794         .class          = &omap2_uart_class,
 795         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 796 };
 797
 798 /* UART2 */
 799
 800 static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
 801         &omap2_l4_core__uart2,
 802 };
 803
 804 static struct omap_hwmod omap2420_uart2_hwmod = {
 805         .name           = "uart2",
 806         .mpu_irqs       = omap2_uart2_mpu_irqs,
 807         .sdma_reqs      = omap2_uart2_sdma_reqs,
 808         .main_clk       = "uart2_fck",
 809         .prcm           = {
 810                 .omap2 = {
 811                         .module_offs = CORE_MOD,
 812                         .prcm_reg_id = 1,
 813                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 814                         .idlest_reg_id = 1,
 815                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 816                 },
 817         },
 818         .slaves         = omap2420_uart2_slaves,
 819         .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
 820         .class          = &omap2_uart_class,
 821         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 822 };
 823
 824 /* UART3 */
 825
 826 static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
 827         &omap2_l4_core__uart3,
 828 };
 829
 830 static struct omap_hwmod omap2420_uart3_hwmod = {
 831         .name           = "uart3",
 832         .mpu_irqs       = omap2_uart3_mpu_irqs,
 833         .sdma_reqs      = omap2_uart3_sdma_reqs,
 834         .main_clk       = "uart3_fck",
 835         .prcm           = {
 836                 .omap2 = {
 837                         .module_offs = CORE_MOD,
 838                         .prcm_reg_id = 2,
 839                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 840                         .idlest_reg_id = 2,
 841                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 842                 },
 843         },
 844         .slaves         = omap2420_uart3_slaves,
 845         .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
 846         .class          = &omap2_uart_class,
 847         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 848 };
 849
 850 /* dss */
 851 /* dss master ports */
 852 static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
 853         &omap2420_dss__l3,
 854 };
 855
 856 /* l4_core -> dss */
 857 static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
 858         .master         = &omap2420_l4_core_hwmod,
 859         .slave          = &omap2420_dss_core_hwmod,
 860         .clk            = "dss_ick",
 861         .addr           = omap2_dss_addrs,
 862         .fw = {
 863                 .omap2 = {
 864                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
 865                         .flags  = OMAP_FIREWALL_L4,
 866                 }
 867         },
 868         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 869 };
 870
 871 /* dss slave ports */
 872 static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
 873         &omap2420_l4_core__dss,
 874 };
 875
 876 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 877         { .role = "tv_clk", .clk = "dss_54m_fck" },
 878         { .role = "sys_clk", .clk = "dss2_fck" },
 879 };
 880
 881 static struct omap_hwmod omap2420_dss_core_hwmod = {
 882         .name           = "dss_core",
 883         .class          = &omap2_dss_hwmod_class,
 884         .main_clk       = "dss1_fck", /* instead of dss_fck */
 885         .sdma_reqs      = omap2xxx_dss_sdma_chs,
 886         .prcm           = {
 887                 .omap2 = {
 888                         .prcm_reg_id = 1,
 889                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 890                         .module_offs = CORE_MOD,
 891                         .idlest_reg_id = 1,
 892                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 893                 },
 894         },
 895         .opt_clks       = dss_opt_clks,
 896         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 897         .slaves         = omap2420_dss_slaves,
 898         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_slaves),
 899         .masters        = omap2420_dss_masters,
 900         .masters_cnt    = ARRAY_SIZE(omap2420_dss_masters),
 901         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 902         .flags          = HWMOD_NO_IDLEST,
 903 };
 904
 905 /* l4_core -> dss_dispc */
 906 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
 907         .master         = &omap2420_l4_core_hwmod,
 908         .slave          = &omap2420_dss_dispc_hwmod,
 909         .clk            = "dss_ick",
 910         .addr           = omap2_dss_dispc_addrs,
 911         .fw = {
 912                 .omap2 = {
 913                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
 914                         .flags  = OMAP_FIREWALL_L4,
 915                 }
 916         },
 917         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 918 };
 919
 920 /* dss_dispc slave ports */
 921 static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
 922         &omap2420_l4_core__dss_dispc,
 923 };
 924
 925 static struct omap_hwmod omap2420_dss_dispc_hwmod = {
 926         .name           = "dss_dispc",
 927         .class          = &omap2_dispc_hwmod_class,
 928         .mpu_irqs       = omap2_dispc_irqs,
 929         .main_clk       = "dss1_fck",
 930         .prcm           = {
 931                 .omap2 = {
 932                         .prcm_reg_id = 1,
 933                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 934                         .module_offs = CORE_MOD,
 935                         .idlest_reg_id = 1,
 936                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 937                 },
 938         },
 939         .slaves         = omap2420_dss_dispc_slaves,
 940         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_dispc_slaves),
 941         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 942         .flags          = HWMOD_NO_IDLEST,
 943 };
 944
 945 /* l4_core -> dss_rfbi */
 946 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
 947         .master         = &omap2420_l4_core_hwmod,
 948         .slave          = &omap2420_dss_rfbi_hwmod,
 949         .clk            = "dss_ick",
 950         .addr           = omap2_dss_rfbi_addrs,
 951         .fw = {
 952                 .omap2 = {
 953                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
 954                         .flags  = OMAP_FIREWALL_L4,
 955                 }
 956         },
 957         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 958 };
 959
 960 /* dss_rfbi slave ports */
 961 static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
 962         &omap2420_l4_core__dss_rfbi,
 963 };
 964
 965 static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
 966         .name           = "dss_rfbi",
 967         .class          = &omap2_rfbi_hwmod_class,
 968         .main_clk       = "dss1_fck",
 969         .prcm           = {
 970                 .omap2 = {
 971                         .prcm_reg_id = 1,
 972                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 973                         .module_offs = CORE_MOD,
 974                 },
 975         },
 976         .slaves         = omap2420_dss_rfbi_slaves,
 977         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
 978         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 979         .flags          = HWMOD_NO_IDLEST,
 980 };
 981
 982 /* l4_core -> dss_venc */
 983 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
 984         .master         = &omap2420_l4_core_hwmod,
 985         .slave          = &omap2420_dss_venc_hwmod,
 986         .clk            = "dss_54m_fck",
 987         .addr           = omap2_dss_venc_addrs,
 988         .fw = {
 989                 .omap2 = {
 990                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
 991                         .flags  = OMAP_FIREWALL_L4,
 992                 }
 993         },
 994         .flags          = OCPIF_SWSUP_IDLE,
 995         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 996 };
 997
 998 /* dss_venc slave ports */
 999 static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
1000         &omap2420_l4_core__dss_venc,
1001 };
1002
1003 static struct omap_hwmod omap2420_dss_venc_hwmod = {
1004         .name           = "dss_venc",
1005         .class          = &omap2_venc_hwmod_class,
1006         .main_clk       = "dss1_fck",
1007         .prcm           = {
1008                 .omap2 = {
1009                         .prcm_reg_id = 1,
1010                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1011                         .module_offs = CORE_MOD,
1012                 },
1013         },
1014         .slaves         = omap2420_dss_venc_slaves,
1015         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_venc_slaves),
1016         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1017         .flags          = HWMOD_NO_IDLEST,
1018 };
1019
1020 /* I2C common */
1021 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1022         .rev_offs       = 0x00,
1023         .sysc_offs      = 0x20,
1024         .syss_offs      = 0x10,
1025         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1026         .sysc_fields    = &omap_hwmod_sysc_type1,
1027 };
1028
1029 static struct omap_hwmod_class i2c_class = {
1030         .name           = "i2c",
1031         .sysc           = &i2c_sysc,
1032 };
1033
1034 static struct omap_i2c_dev_attr i2c_dev_attr;
1035
1036 /* I2C1 */
1037
1038 static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1039         &omap2420_l4_core__i2c1,
1040 };
1041
1042 static struct omap_hwmod omap2420_i2c1_hwmod = {
1043         .name           = "i2c1",
1044         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1045         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1046         .main_clk       = "i2c1_fck",
1047         .prcm           = {
1048                 .omap2 = {
1049                         .module_offs = CORE_MOD,
1050                         .prcm_reg_id = 1,
1051                         .module_bit = OMAP2420_EN_I2C1_SHIFT,
1052                         .idlest_reg_id = 1,
1053                         .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
1054                 },
1055         },
1056         .slaves         = omap2420_i2c1_slaves,
1057         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c1_slaves),
1058         .class          = &i2c_class,
1059         .dev_attr       = &i2c_dev_attr,
1060         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1061         .flags          = HWMOD_16BIT_REG,
1062 };
1063
1064 /* I2C2 */
1065
1066 static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
1067         &omap2420_l4_core__i2c2,
1068 };
1069
1070 static struct omap_hwmod omap2420_i2c2_hwmod = {
1071         .name           = "i2c2",
1072         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1073         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1074         .main_clk       = "i2c2_fck",
1075         .prcm           = {
1076                 .omap2 = {
1077                         .module_offs = CORE_MOD,
1078                         .prcm_reg_id = 1,
1079                         .module_bit = OMAP2420_EN_I2C2_SHIFT,
1080                         .idlest_reg_id = 1,
1081                         .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
1082                 },
1083         },
1084         .slaves         = omap2420_i2c2_slaves,
1085         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c2_slaves),
1086         .class          = &i2c_class,
1087         .dev_attr       = &i2c_dev_attr,
1088         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1089         .flags          = HWMOD_16BIT_REG,
1090 };
1091
1092 /* l4_wkup -> gpio1 */
1093 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1094         {
1095                 .pa_start       = 0x48018000,
1096                 .pa_end         = 0x480181ff,
1097                 .flags          = ADDR_TYPE_RT
1098         },
1099         { }
1100 };
1101
1102 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
1103         .master         = &omap2420_l4_wkup_hwmod,
1104         .slave          = &omap2420_gpio1_hwmod,
1105         .clk            = "gpios_ick",
1106         .addr           = omap2420_gpio1_addr_space,
1107         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1108 };
1109
1110 /* l4_wkup -> gpio2 */
1111 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
1112         {
1113                 .pa_start       = 0x4801a000,
1114                 .pa_end         = 0x4801a1ff,
1115                 .flags          = ADDR_TYPE_RT
1116         },
1117         { }
1118 };
1119
1120 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
1121         .master         = &omap2420_l4_wkup_hwmod,
1122         .slave          = &omap2420_gpio2_hwmod,
1123         .clk            = "gpios_ick",
1124         .addr           = omap2420_gpio2_addr_space,
1125         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1126 };
1127
1128 /* l4_wkup -> gpio3 */
1129 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
1130         {
1131                 .pa_start       = 0x4801c000,
1132                 .pa_end         = 0x4801c1ff,
1133                 .flags          = ADDR_TYPE_RT
1134         },
1135         { }
1136 };
1137
1138 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
1139         .master         = &omap2420_l4_wkup_hwmod,
1140         .slave          = &omap2420_gpio3_hwmod,
1141         .clk            = "gpios_ick",
1142         .addr           = omap2420_gpio3_addr_space,
1143         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1144 };
1145
1146 /* l4_wkup -> gpio4 */
1147 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
1148         {
1149                 .pa_start       = 0x4801e000,
1150                 .pa_end         = 0x4801e1ff,
1151                 .flags          = ADDR_TYPE_RT
1152         },
1153         { }
1154 };
1155
1156 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
1157         .master         = &omap2420_l4_wkup_hwmod,
1158         .slave          = &omap2420_gpio4_hwmod,
1159         .clk            = "gpios_ick",
1160         .addr           = omap2420_gpio4_addr_space,
1161         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1162 };
1163
1164 /* gpio dev_attr */
1165 static struct omap_gpio_dev_attr gpio_dev_attr = {
1166         .bank_width = 32,
1167         .dbck_flag = false,
1168 };
1169
1170 /* gpio1 */
1171 static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1172         &omap2420_l4_wkup__gpio1,
1173 };
1174
1175 static struct omap_hwmod omap2420_gpio1_hwmod = {
1176         .name           = "gpio1",
1177         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1178         .mpu_irqs       = omap2_gpio1_irqs,
1179         .main_clk       = "gpios_fck",
1180         .prcm           = {
1181                 .omap2 = {
1182                         .prcm_reg_id = 1,
1183                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1184                         .module_offs = WKUP_MOD,
1185                         .idlest_reg_id = 1,
1186                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1187                 },
1188         },
1189         .slaves         = omap2420_gpio1_slaves,
1190         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
1191         .class          = &omap2xxx_gpio_hwmod_class,
1192         .dev_attr       = &gpio_dev_attr,
1193         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1194 };
1195
1196 /* gpio2 */
1197 static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1198         &omap2420_l4_wkup__gpio2,
1199 };
1200
1201 static struct omap_hwmod omap2420_gpio2_hwmod = {
1202         .name           = "gpio2",
1203         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1204         .mpu_irqs       = omap2_gpio2_irqs,
1205         .main_clk       = "gpios_fck",
1206         .prcm           = {
1207                 .omap2 = {
1208                         .prcm_reg_id = 1,
1209                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1210                         .module_offs = WKUP_MOD,
1211                         .idlest_reg_id = 1,
1212                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1213                 },
1214         },
1215         .slaves         = omap2420_gpio2_slaves,
1216         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
1217         .class          = &omap2xxx_gpio_hwmod_class,
1218         .dev_attr       = &gpio_dev_attr,
1219         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1220 };
1221
1222 /* gpio3 */
1223 static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1224         &omap2420_l4_wkup__gpio3,
1225 };
1226
1227 static struct omap_hwmod omap2420_gpio3_hwmod = {
1228         .name           = "gpio3",
1229         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1230         .mpu_irqs       = omap2_gpio3_irqs,
1231         .main_clk       = "gpios_fck",
1232         .prcm           = {
1233                 .omap2 = {
1234                         .prcm_reg_id = 1,
1235                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1236                         .module_offs = WKUP_MOD,
1237                         .idlest_reg_id = 1,
1238                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1239                 },
1240         },
1241         .slaves         = omap2420_gpio3_slaves,
1242         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
1243         .class          = &omap2xxx_gpio_hwmod_class,
1244         .dev_attr       = &gpio_dev_attr,
1245         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1246 };
1247
1248 /* gpio4 */
1249 static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1250         &omap2420_l4_wkup__gpio4,
1251 };
1252
1253 static struct omap_hwmod omap2420_gpio4_hwmod = {
1254         .name           = "gpio4",
1255         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1256         .mpu_irqs       = omap2_gpio4_irqs,
1257         .main_clk       = "gpios_fck",
1258         .prcm           = {
1259                 .omap2 = {
1260                         .prcm_reg_id = 1,
1261                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1262                         .module_offs = WKUP_MOD,
1263                         .idlest_reg_id = 1,
1264                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1265                 },
1266         },
1267         .slaves         = omap2420_gpio4_slaves,
1268         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
1269         .class          = &omap2xxx_gpio_hwmod_class,
1270         .dev_attr       = &gpio_dev_attr,
1271         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1272 };
1273
1274 /* dma attributes */
1275 static struct omap_dma_dev_attr dma_dev_attr = {
1276         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1277                                                 IS_CSSA_32 | IS_CDSA_32,
1278         .lch_count = 32,
1279 };
1280
1281 /* dma_system -> L3 */
1282 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
1283         .master         = &omap2420_dma_system_hwmod,
1284         .slave          = &omap2420_l3_main_hwmod,
1285         .clk            = "core_l3_ck",
1286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1287 };
1288
1289 /* dma_system master ports */
1290 static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
1291         &omap2420_dma_system__l3,
1292 };
1293
1294 /* l4_core -> dma_system */
1295 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
1296         .master         = &omap2420_l4_core_hwmod,
1297         .slave          = &omap2420_dma_system_hwmod,
1298         .clk            = "sdma_ick",
1299         .addr           = omap2_dma_system_addrs,
1300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1301 };
1302
1303 /* dma_system slave ports */
1304 static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
1305         &omap2420_l4_core__dma_system,
1306 };
1307
1308 static struct omap_hwmod omap2420_dma_system_hwmod = {
1309         .name           = "dma",
1310         .class          = &omap2xxx_dma_hwmod_class,
1311         .mpu_irqs       = omap2_dma_system_irqs,
1312         .main_clk       = "core_l3_ck",
1313         .slaves         = omap2420_dma_system_slaves,
1314         .slaves_cnt     = ARRAY_SIZE(omap2420_dma_system_slaves),
1315         .masters        = omap2420_dma_system_masters,
1316         .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
1317         .dev_attr       = &dma_dev_attr,
1318         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1319         .flags          = HWMOD_NO_IDLEST,
1320 };
1321
1322 /* mailbox */
1323 static struct omap_hwmod omap2420_mailbox_hwmod;
1324 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1325         { .name = "dsp", .irq = 26 },
1326         { .name = "iva", .irq = 34 },
1327         { .irq = -1 }
1328 };
1329
1330 /* l4_core -> mailbox */
1331 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1332         .master         = &omap2420_l4_core_hwmod,
1333         .slave          = &omap2420_mailbox_hwmod,
1334         .addr           = omap2_mailbox_addrs,
1335         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1336 };
1337
1338 /* mailbox slave ports */
1339 static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1340         &omap2420_l4_core__mailbox,
1341 };
1342
1343 static struct omap_hwmod omap2420_mailbox_hwmod = {
1344         .name           = "mailbox",
1345         .class          = &omap2xxx_mailbox_hwmod_class,
1346         .mpu_irqs       = omap2420_mailbox_irqs,
1347         .main_clk       = "mailboxes_ick",
1348         .prcm           = {
1349                 .omap2 = {
1350                         .prcm_reg_id = 1,
1351                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1352                         .module_offs = CORE_MOD,
1353                         .idlest_reg_id = 1,
1354                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1355                 },
1356         },
1357         .slaves         = omap2420_mailbox_slaves,
1358         .slaves_cnt     = ARRAY_SIZE(omap2420_mailbox_slaves),
1359         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1360 };
1361
1362 /* mcspi1 */
1363 static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
1364         &omap2420_l4_core__mcspi1,
1365 };
1366
1367 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1368         .num_chipselect = 4,
1369 };
1370
1371 static struct omap_hwmod omap2420_mcspi1_hwmod = {
1372         .name           = "mcspi1_hwmod",
1373         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1374         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1375         .main_clk       = "mcspi1_fck",
1376         .prcm           = {
1377                 .omap2 = {
1378                         .module_offs = CORE_MOD,
1379                         .prcm_reg_id = 1,
1380                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1381                         .idlest_reg_id = 1,
1382                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1383                 },
1384         },
1385         .slaves         = omap2420_mcspi1_slaves,
1386         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi1_slaves),
1387         .class          = &omap2xxx_mcspi_class,
1388         .dev_attr       = &omap_mcspi1_dev_attr,
1389         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1390 };
1391
1392 /* mcspi2 */
1393 static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
1394         &omap2420_l4_core__mcspi2,
1395 };
1396
1397 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1398         .num_chipselect = 2,
1399 };
1400
1401 static struct omap_hwmod omap2420_mcspi2_hwmod = {
1402         .name           = "mcspi2_hwmod",
1403         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1404         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1405         .main_clk       = "mcspi2_fck",
1406         .prcm           = {
1407                 .omap2 = {
1408                         .module_offs = CORE_MOD,
1409                         .prcm_reg_id = 1,
1410                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1411                         .idlest_reg_id = 1,
1412                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1413                 },
1414         },
1415         .slaves         = omap2420_mcspi2_slaves,
1416         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi2_slaves),
1417         .class          = &omap2xxx_mcspi_class,
1418         .dev_attr       = &omap_mcspi2_dev_attr,
1419         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1420 };
1421
1422 /*
1423  * 'mcbsp' class
1424  * multi channel buffered serial port controller
1425  */
1426
1427 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
1428         .name = "mcbsp",
1429 };
1430
1431 /* mcbsp1 */
1432 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
1433         { .name = "tx", .irq = 59 },
1434         { .name = "rx", .irq = 60 },
1435         { .irq = -1 }
1436 };
1437
1438 /* l4_core -> mcbsp1 */
1439 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
1440         .master         = &omap2420_l4_core_hwmod,
1441         .slave          = &omap2420_mcbsp1_hwmod,
1442         .clk            = "mcbsp1_ick",
1443         .addr           = omap2_mcbsp1_addrs,
1444         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1445 };
1446
1447 /* mcbsp1 slave ports */
1448 static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
1449         &omap2420_l4_core__mcbsp1,
1450 };
1451
1452 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
1453         .name           = "mcbsp1",
1454         .class          = &omap2420_mcbsp_hwmod_class,
1455         .mpu_irqs       = omap2420_mcbsp1_irqs,
1456         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1457         .main_clk       = "mcbsp1_fck",
1458         .prcm           = {
1459                 .omap2 = {
1460                         .prcm_reg_id = 1,
1461                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1462                         .module_offs = CORE_MOD,
1463                         .idlest_reg_id = 1,
1464                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1465                 },
1466         },
1467         .slaves         = omap2420_mcbsp1_slaves,
1468         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp1_slaves),
1469         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1470 };
1471
1472 /* mcbsp2 */
1473 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
1474         { .name = "tx", .irq = 62 },
1475         { .name = "rx", .irq = 63 },
1476         { .irq = -1 }
1477 };
1478
1479 /* l4_core -> mcbsp2 */
1480 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
1481         .master         = &omap2420_l4_core_hwmod,
1482         .slave          = &omap2420_mcbsp2_hwmod,
1483         .clk            = "mcbsp2_ick",
1484         .addr           = omap2xxx_mcbsp2_addrs,
1485         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1486 };
1487
1488 /* mcbsp2 slave ports */
1489 static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
1490         &omap2420_l4_core__mcbsp2,
1491 };
1492
1493 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
1494         .name           = "mcbsp2",
1495         .class          = &omap2420_mcbsp_hwmod_class,
1496         .mpu_irqs       = omap2420_mcbsp2_irqs,
1497         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1498         .main_clk       = "mcbsp2_fck",
1499         .prcm           = {
1500                 .omap2 = {
1501                         .prcm_reg_id = 1,
1502                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1503                         .module_offs = CORE_MOD,
1504                         .idlest_reg_id = 1,
1505                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1506                 },
1507         },
1508         .slaves         = omap2420_mcbsp2_slaves,
1509         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp2_slaves),
1510         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1511 };
1512
1513 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1514         &omap2420_l3_main_hwmod,
1515         &omap2420_l4_core_hwmod,
1516         &omap2420_l4_wkup_hwmod,
1517         &omap2420_mpu_hwmod,
1518         &omap2420_iva_hwmod,
1519
1520         &omap2420_timer1_hwmod,
1521         &omap2420_timer2_hwmod,
1522         &omap2420_timer3_hwmod,
1523         &omap2420_timer4_hwmod,
1524         &omap2420_timer5_hwmod,
1525         &omap2420_timer6_hwmod,
1526         &omap2420_timer7_hwmod,
1527         &omap2420_timer8_hwmod,
1528         &omap2420_timer9_hwmod,
1529         &omap2420_timer10_hwmod,
1530         &omap2420_timer11_hwmod,
1531         &omap2420_timer12_hwmod,
1532
1533         &omap2420_wd_timer2_hwmod,
1534         &omap2420_uart1_hwmod,
1535         &omap2420_uart2_hwmod,
1536         &omap2420_uart3_hwmod,
1537         /* dss class */
1538         &omap2420_dss_core_hwmod,
1539         &omap2420_dss_dispc_hwmod,
1540         &omap2420_dss_rfbi_hwmod,
1541         &omap2420_dss_venc_hwmod,
1542         /* i2c class */
1543         &omap2420_i2c1_hwmod,
1544         &omap2420_i2c2_hwmod,
1545
1546         /* gpio class */
1547         &omap2420_gpio1_hwmod,
1548         &omap2420_gpio2_hwmod,
1549         &omap2420_gpio3_hwmod,
1550         &omap2420_gpio4_hwmod,
1551
1552         /* dma_system class*/
1553         &omap2420_dma_system_hwmod,
1554
1555         /* mailbox class */
1556         &omap2420_mailbox_hwmod,
1557
1558         /* mcbsp class */
1559         &omap2420_mcbsp1_hwmod,
1560         &omap2420_mcbsp2_hwmod,
1561
1562         /* mcspi class */
1563         &omap2420_mcspi1_hwmod,
1564         &omap2420_mcspi2_hwmod,
1565         NULL,
1566 };
1567
1568 int __init omap2420_hwmod_init(void)
1569 {
1570         return omap_hwmod_register(omap2420_hwmods);
1571 }