arch/arm/mach-omap2/omap_hwmod_2420_data.c

   1 /*
   2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcspi.h>
  22 #include <plat/dmtimer.h>
  23 #include <plat/l3_2xxx.h>
  24 #include <plat/l4_2xxx.h>
  25
  26 #include "omap_hwmod_common_data.h"
  27
  28 #include "cm-regbits-24xx.h"
  29 #include "prm-regbits-24xx.h"
  30 #include "wd_timer.h"
  31
  32 /*
  33  * OMAP2420 hardware module integration data
  34  *
  35  * ALl of the data in this section should be autogeneratable from the
  36  * TI hardware database or other technical documentation.  Data that
  37  * is driver-specific or driver-kernel integration-specific belongs
  38  * elsewhere.
  39  */
  40
  41 static struct omap_hwmod omap2420_mpu_hwmod;
  42 static struct omap_hwmod omap2420_iva_hwmod;
  43 static struct omap_hwmod omap2420_l3_main_hwmod;
  44 static struct omap_hwmod omap2420_l4_core_hwmod;
  45 static struct omap_hwmod omap2420_dss_core_hwmod;
  46 static struct omap_hwmod omap2420_dss_dispc_hwmod;
  47 static struct omap_hwmod omap2420_dss_rfbi_hwmod;
  48 static struct omap_hwmod omap2420_dss_venc_hwmod;
  49 static struct omap_hwmod omap2420_wd_timer2_hwmod;
  50 static struct omap_hwmod omap2420_gpio1_hwmod;
  51 static struct omap_hwmod omap2420_gpio2_hwmod;
  52 static struct omap_hwmod omap2420_gpio3_hwmod;
  53 static struct omap_hwmod omap2420_gpio4_hwmod;
  54 static struct omap_hwmod omap2420_dma_system_hwmod;
  55 static struct omap_hwmod omap2420_mcspi1_hwmod;
  56 static struct omap_hwmod omap2420_mcspi2_hwmod;
  57
  58 /* L3 -> L4_CORE interface */
  59 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
  60         .master = &omap2420_l3_main_hwmod,
  61         .slave  = &omap2420_l4_core_hwmod,
  62         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  63 };
  64
  65 /* MPU -> L3 interface */
  66 static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
  67         .master = &omap2420_mpu_hwmod,
  68         .slave  = &omap2420_l3_main_hwmod,
  69         .user   = OCP_USER_MPU,
  70 };
  71
  72 /* Slave interfaces on the L3 interconnect */
  73 static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
  74         &omap2420_mpu__l3_main,
  75 };
  76
  77 /* DSS -> l3 */
  78 static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
  79         .master         = &omap2420_dss_core_hwmod,
  80         .slave          = &omap2420_l3_main_hwmod,
  81         .fw = {
  82                 .omap2 = {
  83                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  84                         .flags  = OMAP_FIREWALL_L3,
  85                 }
  86         },
  87         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  88 };
  89
  90 /* Master interfaces on the L3 interconnect */
  91 static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
  92         &omap2420_l3_main__l4_core,
  93 };
  94
  95 /* L3 */
  96 static struct omap_hwmod omap2420_l3_main_hwmod = {
  97         .name           = "l3_main",
  98         .class          = &l3_hwmod_class,
  99         .masters        = omap2420_l3_main_masters,
 100         .masters_cnt    = ARRAY_SIZE(omap2420_l3_main_masters),
 101         .slaves         = omap2420_l3_main_slaves,
 102         .slaves_cnt     = ARRAY_SIZE(omap2420_l3_main_slaves),
 103         .flags          = HWMOD_NO_IDLEST,
 104 };
 105
 106 static struct omap_hwmod omap2420_l4_wkup_hwmod;
 107 static struct omap_hwmod omap2420_uart1_hwmod;
 108 static struct omap_hwmod omap2420_uart2_hwmod;
 109 static struct omap_hwmod omap2420_uart3_hwmod;
 110 static struct omap_hwmod omap2420_i2c1_hwmod;
 111 static struct omap_hwmod omap2420_i2c2_hwmod;
 112 static struct omap_hwmod omap2420_mcbsp1_hwmod;
 113 static struct omap_hwmod omap2420_mcbsp2_hwmod;
 114
 115 /* l4 core -> mcspi1 interface */
 116 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
 117         .master         = &omap2420_l4_core_hwmod,
 118         .slave          = &omap2420_mcspi1_hwmod,
 119         .clk            = "mcspi1_ick",
 120         .addr           = omap2_mcspi1_addr_space,
 121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 122 };
 123
 124 /* l4 core -> mcspi2 interface */
 125 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
 126         .master         = &omap2420_l4_core_hwmod,
 127         .slave          = &omap2420_mcspi2_hwmod,
 128         .clk            = "mcspi2_ick",
 129         .addr           = omap2_mcspi2_addr_space,
 130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 131 };
 132
 133 /* L4_CORE -> L4_WKUP interface */
 134 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
 135         .master = &omap2420_l4_core_hwmod,
 136         .slave  = &omap2420_l4_wkup_hwmod,
 137         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 138 };
 139
 140 /* L4 CORE -> UART1 interface */
 141 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 142         .master         = &omap2420_l4_core_hwmod,
 143         .slave          = &omap2420_uart1_hwmod,
 144         .clk            = "uart1_ick",
 145         .addr           = omap2xxx_uart1_addr_space,
 146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 147 };
 148
 149 /* L4 CORE -> UART2 interface */
 150 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 151         .master         = &omap2420_l4_core_hwmod,
 152         .slave          = &omap2420_uart2_hwmod,
 153         .clk            = "uart2_ick",
 154         .addr           = omap2xxx_uart2_addr_space,
 155         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 156 };
 157
 158 /* L4 PER -> UART3 interface */
 159 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 160         .master         = &omap2420_l4_core_hwmod,
 161         .slave          = &omap2420_uart3_hwmod,
 162         .clk            = "uart3_ick",
 163         .addr           = omap2xxx_uart3_addr_space,
 164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 165 };
 166
 167 /* L4 CORE -> I2C1 interface */
 168 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 169         .master         = &omap2420_l4_core_hwmod,
 170         .slave          = &omap2420_i2c1_hwmod,
 171         .clk            = "i2c1_ick",
 172         .addr           = omap2_i2c1_addr_space,
 173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 174 };
 175
 176 /* L4 CORE -> I2C2 interface */
 177 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 178         .master         = &omap2420_l4_core_hwmod,
 179         .slave          = &omap2420_i2c2_hwmod,
 180         .clk            = "i2c2_ick",
 181         .addr           = omap2_i2c2_addr_space,
 182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 183 };
 184
 185 /* Slave interfaces on the L4_CORE interconnect */
 186 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 187         &omap2420_l3_main__l4_core,
 188 };
 189
 190 /* Master interfaces on the L4_CORE interconnect */
 191 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
 192         &omap2420_l4_core__l4_wkup,
 193         &omap2_l4_core__uart1,
 194         &omap2_l4_core__uart2,
 195         &omap2_l4_core__uart3,
 196         &omap2420_l4_core__i2c1,
 197         &omap2420_l4_core__i2c2
 198 };
 199
 200 /* L4 CORE */
 201 static struct omap_hwmod omap2420_l4_core_hwmod = {
 202         .name           = "l4_core",
 203         .class          = &l4_hwmod_class,
 204         .masters        = omap2420_l4_core_masters,
 205         .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
 206         .slaves         = omap2420_l4_core_slaves,
 207         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
 208         .flags          = HWMOD_NO_IDLEST,
 209 };
 210
 211 /* Slave interfaces on the L4_WKUP interconnect */
 212 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
 213         &omap2420_l4_core__l4_wkup,
 214 };
 215
 216 /* Master interfaces on the L4_WKUP interconnect */
 217 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
 218 };
 219
 220 /* L4 WKUP */
 221 static struct omap_hwmod omap2420_l4_wkup_hwmod = {
 222         .name           = "l4_wkup",
 223         .class          = &l4_hwmod_class,
 224         .masters        = omap2420_l4_wkup_masters,
 225         .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
 226         .slaves         = omap2420_l4_wkup_slaves,
 227         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
 228         .flags          = HWMOD_NO_IDLEST,
 229 };
 230
 231 /* Master interfaces on the MPU device */
 232 static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
 233         &omap2420_mpu__l3_main,
 234 };
 235
 236 /* MPU */
 237 static struct omap_hwmod omap2420_mpu_hwmod = {
 238         .name           = "mpu",
 239         .class          = &mpu_hwmod_class,
 240         .main_clk       = "mpu_ck",
 241         .masters        = omap2420_mpu_masters,
 242         .masters_cnt    = ARRAY_SIZE(omap2420_mpu_masters),
 243 };
 244
 245 /*
 246  * IVA1 interface data
 247  */
 248
 249 /* IVA <- L3 interface */
 250 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 251         .master         = &omap2420_l3_main_hwmod,
 252         .slave          = &omap2420_iva_hwmod,
 253         .clk            = "iva1_ifck",
 254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 255 };
 256
 257 static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
 258         &omap2420_l3__iva,
 259 };
 260
 261 /*
 262  * IVA2 (IVA2)
 263  */
 264
 265 static struct omap_hwmod omap2420_iva_hwmod = {
 266         .name           = "iva",
 267         .class          = &iva_hwmod_class,
 268         .masters        = omap2420_iva_masters,
 269         .masters_cnt    = ARRAY_SIZE(omap2420_iva_masters),
 270 };
 271
 272 /* timer1 */
 273 static struct omap_hwmod omap2420_timer1_hwmod;
 274
 275 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
 276         {
 277                 .pa_start       = 0x48028000,
 278                 .pa_end         = 0x48028000 + SZ_1K - 1,
 279                 .flags          = ADDR_TYPE_RT
 280         },
 281         { }
 282 };
 283
 284 /* l4_wkup -> timer1 */
 285 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
 286         .master         = &omap2420_l4_wkup_hwmod,
 287         .slave          = &omap2420_timer1_hwmod,
 288         .clk            = "gpt1_ick",
 289         .addr           = omap2420_timer1_addrs,
 290         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 291 };
 292
 293 /* timer1 slave port */
 294 static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
 295         &omap2420_l4_wkup__timer1,
 296 };
 297
 298 /* timer1 hwmod */
 299 static struct omap_hwmod omap2420_timer1_hwmod = {
 300         .name           = "timer1",
 301         .mpu_irqs       = omap2_timer1_mpu_irqs,
 302         .main_clk       = "gpt1_fck",
 303         .prcm           = {
 304                 .omap2 = {
 305                         .prcm_reg_id = 1,
 306                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 307                         .module_offs = WKUP_MOD,
 308                         .idlest_reg_id = 1,
 309                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 310                 },
 311         },
 312         .slaves         = omap2420_timer1_slaves,
 313         .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
 314         .class          = &omap2xxx_timer_hwmod_class,
 315 };
 316
 317 /* timer2 */
 318 static struct omap_hwmod omap2420_timer2_hwmod;
 319
 320 /* l4_core -> timer2 */
 321 static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
 322         .master         = &omap2420_l4_core_hwmod,
 323         .slave          = &omap2420_timer2_hwmod,
 324         .clk            = "gpt2_ick",
 325         .addr           = omap2xxx_timer2_addrs,
 326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 327 };
 328
 329 /* timer2 slave port */
 330 static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
 331         &omap2420_l4_core__timer2,
 332 };
 333
 334 /* timer2 hwmod */
 335 static struct omap_hwmod omap2420_timer2_hwmod = {
 336         .name           = "timer2",
 337         .mpu_irqs       = omap2_timer2_mpu_irqs,
 338         .main_clk       = "gpt2_fck",
 339         .prcm           = {
 340                 .omap2 = {
 341                         .prcm_reg_id = 1,
 342                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 343                         .module_offs = CORE_MOD,
 344                         .idlest_reg_id = 1,
 345                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 346                 },
 347         },
 348         .slaves         = omap2420_timer2_slaves,
 349         .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
 350         .class          = &omap2xxx_timer_hwmod_class,
 351 };
 352
 353 /* timer3 */
 354 static struct omap_hwmod omap2420_timer3_hwmod;
 355
 356 /* l4_core -> timer3 */
 357 static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
 358         .master         = &omap2420_l4_core_hwmod,
 359         .slave          = &omap2420_timer3_hwmod,
 360         .clk            = "gpt3_ick",
 361         .addr           = omap2xxx_timer3_addrs,
 362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 363 };
 364
 365 /* timer3 slave port */
 366 static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
 367         &omap2420_l4_core__timer3,
 368 };
 369
 370 /* timer3 hwmod */
 371 static struct omap_hwmod omap2420_timer3_hwmod = {
 372         .name           = "timer3",
 373         .mpu_irqs       = omap2_timer3_mpu_irqs,
 374         .main_clk       = "gpt3_fck",
 375         .prcm           = {
 376                 .omap2 = {
 377                         .prcm_reg_id = 1,
 378                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 379                         .module_offs = CORE_MOD,
 380                         .idlest_reg_id = 1,
 381                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 382                 },
 383         },
 384         .slaves         = omap2420_timer3_slaves,
 385         .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
 386         .class          = &omap2xxx_timer_hwmod_class,
 387 };
 388
 389 /* timer4 */
 390 static struct omap_hwmod omap2420_timer4_hwmod;
 391
 392 /* l4_core -> timer4 */
 393 static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
 394         .master         = &omap2420_l4_core_hwmod,
 395         .slave          = &omap2420_timer4_hwmod,
 396         .clk            = "gpt4_ick",
 397         .addr           = omap2xxx_timer4_addrs,
 398         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 399 };
 400
 401 /* timer4 slave port */
 402 static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
 403         &omap2420_l4_core__timer4,
 404 };
 405
 406 /* timer4 hwmod */
 407 static struct omap_hwmod omap2420_timer4_hwmod = {
 408         .name           = "timer4",
 409         .mpu_irqs       = omap2_timer4_mpu_irqs,
 410         .main_clk       = "gpt4_fck",
 411         .prcm           = {
 412                 .omap2 = {
 413                         .prcm_reg_id = 1,
 414                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 415                         .module_offs = CORE_MOD,
 416                         .idlest_reg_id = 1,
 417                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 418                 },
 419         },
 420         .slaves         = omap2420_timer4_slaves,
 421         .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
 422         .class          = &omap2xxx_timer_hwmod_class,
 423 };
 424
 425 /* timer5 */
 426 static struct omap_hwmod omap2420_timer5_hwmod;
 427
 428 /* l4_core -> timer5 */
 429 static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
 430         .master         = &omap2420_l4_core_hwmod,
 431         .slave          = &omap2420_timer5_hwmod,
 432         .clk            = "gpt5_ick",
 433         .addr           = omap2xxx_timer5_addrs,
 434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 435 };
 436
 437 /* timer5 slave port */
 438 static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
 439         &omap2420_l4_core__timer5,
 440 };
 441
 442 /* timer5 hwmod */
 443 static struct omap_hwmod omap2420_timer5_hwmod = {
 444         .name           = "timer5",
 445         .mpu_irqs       = omap2_timer5_mpu_irqs,
 446         .main_clk       = "gpt5_fck",
 447         .prcm           = {
 448                 .omap2 = {
 449                         .prcm_reg_id = 1,
 450                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 451                         .module_offs = CORE_MOD,
 452                         .idlest_reg_id = 1,
 453                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 454                 },
 455         },
 456         .slaves         = omap2420_timer5_slaves,
 457         .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
 458         .class          = &omap2xxx_timer_hwmod_class,
 459 };
 460
 461
 462 /* timer6 */
 463 static struct omap_hwmod omap2420_timer6_hwmod;
 464
 465 /* l4_core -> timer6 */
 466 static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
 467         .master         = &omap2420_l4_core_hwmod,
 468         .slave          = &omap2420_timer6_hwmod,
 469         .clk            = "gpt6_ick",
 470         .addr           = omap2xxx_timer6_addrs,
 471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 472 };
 473
 474 /* timer6 slave port */
 475 static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
 476         &omap2420_l4_core__timer6,
 477 };
 478
 479 /* timer6 hwmod */
 480 static struct omap_hwmod omap2420_timer6_hwmod = {
 481         .name           = "timer6",
 482         .mpu_irqs       = omap2_timer6_mpu_irqs,
 483         .main_clk       = "gpt6_fck",
 484         .prcm           = {
 485                 .omap2 = {
 486                         .prcm_reg_id = 1,
 487                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 488                         .module_offs = CORE_MOD,
 489                         .idlest_reg_id = 1,
 490                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 491                 },
 492         },
 493         .slaves         = omap2420_timer6_slaves,
 494         .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
 495         .class          = &omap2xxx_timer_hwmod_class,
 496 };
 497
 498 /* timer7 */
 499 static struct omap_hwmod omap2420_timer7_hwmod;
 500
 501 /* l4_core -> timer7 */
 502 static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
 503         .master         = &omap2420_l4_core_hwmod,
 504         .slave          = &omap2420_timer7_hwmod,
 505         .clk            = "gpt7_ick",
 506         .addr           = omap2xxx_timer7_addrs,
 507         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 508 };
 509
 510 /* timer7 slave port */
 511 static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
 512         &omap2420_l4_core__timer7,
 513 };
 514
 515 /* timer7 hwmod */
 516 static struct omap_hwmod omap2420_timer7_hwmod = {
 517         .name           = "timer7",
 518         .mpu_irqs       = omap2_timer7_mpu_irqs,
 519         .main_clk       = "gpt7_fck",
 520         .prcm           = {
 521                 .omap2 = {
 522                         .prcm_reg_id = 1,
 523                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 524                         .module_offs = CORE_MOD,
 525                         .idlest_reg_id = 1,
 526                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 527                 },
 528         },
 529         .slaves         = omap2420_timer7_slaves,
 530         .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
 531         .class          = &omap2xxx_timer_hwmod_class,
 532 };
 533
 534 /* timer8 */
 535 static struct omap_hwmod omap2420_timer8_hwmod;
 536
 537 /* l4_core -> timer8 */
 538 static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
 539         .master         = &omap2420_l4_core_hwmod,
 540         .slave          = &omap2420_timer8_hwmod,
 541         .clk            = "gpt8_ick",
 542         .addr           = omap2xxx_timer8_addrs,
 543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 544 };
 545
 546 /* timer8 slave port */
 547 static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
 548         &omap2420_l4_core__timer8,
 549 };
 550
 551 /* timer8 hwmod */
 552 static struct omap_hwmod omap2420_timer8_hwmod = {
 553         .name           = "timer8",
 554         .mpu_irqs       = omap2_timer8_mpu_irqs,
 555         .main_clk       = "gpt8_fck",
 556         .prcm           = {
 557                 .omap2 = {
 558                         .prcm_reg_id = 1,
 559                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 560                         .module_offs = CORE_MOD,
 561                         .idlest_reg_id = 1,
 562                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 563                 },
 564         },
 565         .slaves         = omap2420_timer8_slaves,
 566         .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
 567         .class          = &omap2xxx_timer_hwmod_class,
 568 };
 569
 570 /* timer9 */
 571 static struct omap_hwmod omap2420_timer9_hwmod;
 572
 573 /* l4_core -> timer9 */
 574 static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
 575         .master         = &omap2420_l4_core_hwmod,
 576         .slave          = &omap2420_timer9_hwmod,
 577         .clk            = "gpt9_ick",
 578         .addr           = omap2xxx_timer9_addrs,
 579         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 580 };
 581
 582 /* timer9 slave port */
 583 static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
 584         &omap2420_l4_core__timer9,
 585 };
 586
 587 /* timer9 hwmod */
 588 static struct omap_hwmod omap2420_timer9_hwmod = {
 589         .name           = "timer9",
 590         .mpu_irqs       = omap2_timer9_mpu_irqs,
 591         .main_clk       = "gpt9_fck",
 592         .prcm           = {
 593                 .omap2 = {
 594                         .prcm_reg_id = 1,
 595                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 596                         .module_offs = CORE_MOD,
 597                         .idlest_reg_id = 1,
 598                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 599                 },
 600         },
 601         .slaves         = omap2420_timer9_slaves,
 602         .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
 603         .class          = &omap2xxx_timer_hwmod_class,
 604 };
 605
 606 /* timer10 */
 607 static struct omap_hwmod omap2420_timer10_hwmod;
 608
 609 /* l4_core -> timer10 */
 610 static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
 611         .master         = &omap2420_l4_core_hwmod,
 612         .slave          = &omap2420_timer10_hwmod,
 613         .clk            = "gpt10_ick",
 614         .addr           = omap2_timer10_addrs,
 615         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 616 };
 617
 618 /* timer10 slave port */
 619 static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
 620         &omap2420_l4_core__timer10,
 621 };
 622
 623 /* timer10 hwmod */
 624 static struct omap_hwmod omap2420_timer10_hwmod = {
 625         .name           = "timer10",
 626         .mpu_irqs       = omap2_timer10_mpu_irqs,
 627         .main_clk       = "gpt10_fck",
 628         .prcm           = {
 629                 .omap2 = {
 630                         .prcm_reg_id = 1,
 631                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 632                         .module_offs = CORE_MOD,
 633                         .idlest_reg_id = 1,
 634                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 635                 },
 636         },
 637         .slaves         = omap2420_timer10_slaves,
 638         .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
 639         .class          = &omap2xxx_timer_hwmod_class,
 640 };
 641
 642 /* timer11 */
 643 static struct omap_hwmod omap2420_timer11_hwmod;
 644
 645 /* l4_core -> timer11 */
 646 static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
 647         .master         = &omap2420_l4_core_hwmod,
 648         .slave          = &omap2420_timer11_hwmod,
 649         .clk            = "gpt11_ick",
 650         .addr           = omap2_timer11_addrs,
 651         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 652 };
 653
 654 /* timer11 slave port */
 655 static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
 656         &omap2420_l4_core__timer11,
 657 };
 658
 659 /* timer11 hwmod */
 660 static struct omap_hwmod omap2420_timer11_hwmod = {
 661         .name           = "timer11",
 662         .mpu_irqs       = omap2_timer11_mpu_irqs,
 663         .main_clk       = "gpt11_fck",
 664         .prcm           = {
 665                 .omap2 = {
 666                         .prcm_reg_id = 1,
 667                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 668                         .module_offs = CORE_MOD,
 669                         .idlest_reg_id = 1,
 670                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 671                 },
 672         },
 673         .slaves         = omap2420_timer11_slaves,
 674         .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
 675         .class          = &omap2xxx_timer_hwmod_class,
 676 };
 677
 678 /* timer12 */
 679 static struct omap_hwmod omap2420_timer12_hwmod;
 680
 681 /* l4_core -> timer12 */
 682 static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
 683         .master         = &omap2420_l4_core_hwmod,
 684         .slave          = &omap2420_timer12_hwmod,
 685         .clk            = "gpt12_ick",
 686         .addr           = omap2xxx_timer12_addrs,
 687         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 688 };
 689
 690 /* timer12 slave port */
 691 static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
 692         &omap2420_l4_core__timer12,
 693 };
 694
 695 /* timer12 hwmod */
 696 static struct omap_hwmod omap2420_timer12_hwmod = {
 697         .name           = "timer12",
 698         .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
 699         .main_clk       = "gpt12_fck",
 700         .prcm           = {
 701                 .omap2 = {
 702                         .prcm_reg_id = 1,
 703                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 704                         .module_offs = CORE_MOD,
 705                         .idlest_reg_id = 1,
 706                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 707                 },
 708         },
 709         .slaves         = omap2420_timer12_slaves,
 710         .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
 711         .class          = &omap2xxx_timer_hwmod_class,
 712 };
 713
 714 /* l4_wkup -> wd_timer2 */
 715 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 716         {
 717                 .pa_start       = 0x48022000,
 718                 .pa_end         = 0x4802207f,
 719                 .flags          = ADDR_TYPE_RT
 720         },
 721         { }
 722 };
 723
 724 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 725         .master         = &omap2420_l4_wkup_hwmod,
 726         .slave          = &omap2420_wd_timer2_hwmod,
 727         .clk            = "mpu_wdt_ick",
 728         .addr           = omap2420_wd_timer2_addrs,
 729         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 730 };
 731
 732 /* wd_timer2 */
 733 static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
 734         &omap2420_l4_wkup__wd_timer2,
 735 };
 736
 737 static struct omap_hwmod omap2420_wd_timer2_hwmod = {
 738         .name           = "wd_timer2",
 739         .class          = &omap2xxx_wd_timer_hwmod_class,
 740         .main_clk       = "mpu_wdt_fck",
 741         .prcm           = {
 742                 .omap2 = {
 743                         .prcm_reg_id = 1,
 744                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 745                         .module_offs = WKUP_MOD,
 746                         .idlest_reg_id = 1,
 747                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 748                 },
 749         },
 750         .slaves         = omap2420_wd_timer2_slaves,
 751         .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
 752 };
 753
 754 /* UART1 */
 755
 756 static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
 757         &omap2_l4_core__uart1,
 758 };
 759
 760 static struct omap_hwmod omap2420_uart1_hwmod = {
 761         .name           = "uart1",
 762         .mpu_irqs       = omap2_uart1_mpu_irqs,
 763         .sdma_reqs      = omap2_uart1_sdma_reqs,
 764         .main_clk       = "uart1_fck",
 765         .prcm           = {
 766                 .omap2 = {
 767                         .module_offs = CORE_MOD,
 768                         .prcm_reg_id = 1,
 769                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 770                         .idlest_reg_id = 1,
 771                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 772                 },
 773         },
 774         .slaves         = omap2420_uart1_slaves,
 775         .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
 776         .class          = &omap2_uart_class,
 777 };
 778
 779 /* UART2 */
 780
 781 static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
 782         &omap2_l4_core__uart2,
 783 };
 784
 785 static struct omap_hwmod omap2420_uart2_hwmod = {
 786         .name           = "uart2",
 787         .mpu_irqs       = omap2_uart2_mpu_irqs,
 788         .sdma_reqs      = omap2_uart2_sdma_reqs,
 789         .main_clk       = "uart2_fck",
 790         .prcm           = {
 791                 .omap2 = {
 792                         .module_offs = CORE_MOD,
 793                         .prcm_reg_id = 1,
 794                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 795                         .idlest_reg_id = 1,
 796                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 797                 },
 798         },
 799         .slaves         = omap2420_uart2_slaves,
 800         .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
 801         .class          = &omap2_uart_class,
 802 };
 803
 804 /* UART3 */
 805
 806 static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
 807         &omap2_l4_core__uart3,
 808 };
 809
 810 static struct omap_hwmod omap2420_uart3_hwmod = {
 811         .name           = "uart3",
 812         .mpu_irqs       = omap2_uart3_mpu_irqs,
 813         .sdma_reqs      = omap2_uart3_sdma_reqs,
 814         .main_clk       = "uart3_fck",
 815         .prcm           = {
 816                 .omap2 = {
 817                         .module_offs = CORE_MOD,
 818                         .prcm_reg_id = 2,
 819                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 820                         .idlest_reg_id = 2,
 821                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 822                 },
 823         },
 824         .slaves         = omap2420_uart3_slaves,
 825         .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
 826         .class          = &omap2_uart_class,
 827 };
 828
 829 /* dss */
 830 /* dss master ports */
 831 static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
 832         &omap2420_dss__l3,
 833 };
 834
 835 /* l4_core -> dss */
 836 static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
 837         .master         = &omap2420_l4_core_hwmod,
 838         .slave          = &omap2420_dss_core_hwmod,
 839         .clk            = "dss_ick",
 840         .addr           = omap2_dss_addrs,
 841         .fw = {
 842                 .omap2 = {
 843                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
 844                         .flags  = OMAP_FIREWALL_L4,
 845                 }
 846         },
 847         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 848 };
 849
 850 /* dss slave ports */
 851 static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
 852         &omap2420_l4_core__dss,
 853 };
 854
 855 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 856         { .role = "tv_clk", .clk = "dss_54m_fck" },
 857         { .role = "sys_clk", .clk = "dss2_fck" },
 858 };
 859
 860 static struct omap_hwmod omap2420_dss_core_hwmod = {
 861         .name           = "dss_core",
 862         .class          = &omap2_dss_hwmod_class,
 863         .main_clk       = "dss1_fck", /* instead of dss_fck */
 864         .sdma_reqs      = omap2xxx_dss_sdma_chs,
 865         .prcm           = {
 866                 .omap2 = {
 867                         .prcm_reg_id = 1,
 868                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 869                         .module_offs = CORE_MOD,
 870                         .idlest_reg_id = 1,
 871                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 872                 },
 873         },
 874         .opt_clks       = dss_opt_clks,
 875         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 876         .slaves         = omap2420_dss_slaves,
 877         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_slaves),
 878         .masters        = omap2420_dss_masters,
 879         .masters_cnt    = ARRAY_SIZE(omap2420_dss_masters),
 880         .flags          = HWMOD_NO_IDLEST,
 881 };
 882
 883 /* l4_core -> dss_dispc */
 884 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
 885         .master         = &omap2420_l4_core_hwmod,
 886         .slave          = &omap2420_dss_dispc_hwmod,
 887         .clk            = "dss_ick",
 888         .addr           = omap2_dss_dispc_addrs,
 889         .fw = {
 890                 .omap2 = {
 891                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
 892                         .flags  = OMAP_FIREWALL_L4,
 893                 }
 894         },
 895         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 896 };
 897
 898 /* dss_dispc slave ports */
 899 static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
 900         &omap2420_l4_core__dss_dispc,
 901 };
 902
 903 static struct omap_hwmod omap2420_dss_dispc_hwmod = {
 904         .name           = "dss_dispc",
 905         .class          = &omap2_dispc_hwmod_class,
 906         .mpu_irqs       = omap2_dispc_irqs,
 907         .main_clk       = "dss1_fck",
 908         .prcm           = {
 909                 .omap2 = {
 910                         .prcm_reg_id = 1,
 911                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 912                         .module_offs = CORE_MOD,
 913                         .idlest_reg_id = 1,
 914                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 915                 },
 916         },
 917         .slaves         = omap2420_dss_dispc_slaves,
 918         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_dispc_slaves),
 919         .flags          = HWMOD_NO_IDLEST,
 920 };
 921
 922 /* l4_core -> dss_rfbi */
 923 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
 924         .master         = &omap2420_l4_core_hwmod,
 925         .slave          = &omap2420_dss_rfbi_hwmod,
 926         .clk            = "dss_ick",
 927         .addr           = omap2_dss_rfbi_addrs,
 928         .fw = {
 929                 .omap2 = {
 930                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
 931                         .flags  = OMAP_FIREWALL_L4,
 932                 }
 933         },
 934         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 935 };
 936
 937 /* dss_rfbi slave ports */
 938 static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
 939         &omap2420_l4_core__dss_rfbi,
 940 };
 941
 942 static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
 943         .name           = "dss_rfbi",
 944         .class          = &omap2_rfbi_hwmod_class,
 945         .main_clk       = "dss1_fck",
 946         .prcm           = {
 947                 .omap2 = {
 948                         .prcm_reg_id = 1,
 949                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 950                         .module_offs = CORE_MOD,
 951                 },
 952         },
 953         .slaves         = omap2420_dss_rfbi_slaves,
 954         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
 955         .flags          = HWMOD_NO_IDLEST,
 956 };
 957
 958 /* l4_core -> dss_venc */
 959 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
 960         .master         = &omap2420_l4_core_hwmod,
 961         .slave          = &omap2420_dss_venc_hwmod,
 962         .clk            = "dss_54m_fck",
 963         .addr           = omap2_dss_venc_addrs,
 964         .fw = {
 965                 .omap2 = {
 966                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
 967                         .flags  = OMAP_FIREWALL_L4,
 968                 }
 969         },
 970         .flags          = OCPIF_SWSUP_IDLE,
 971         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 972 };
 973
 974 /* dss_venc slave ports */
 975 static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
 976         &omap2420_l4_core__dss_venc,
 977 };
 978
 979 static struct omap_hwmod omap2420_dss_venc_hwmod = {
 980         .name           = "dss_venc",
 981         .class          = &omap2_venc_hwmod_class,
 982         .main_clk       = "dss1_fck",
 983         .prcm           = {
 984                 .omap2 = {
 985                         .prcm_reg_id = 1,
 986                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 987                         .module_offs = CORE_MOD,
 988                 },
 989         },
 990         .slaves         = omap2420_dss_venc_slaves,
 991         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_venc_slaves),
 992         .flags          = HWMOD_NO_IDLEST,
 993 };
 994
 995 /* I2C common */
 996 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 997         .rev_offs       = 0x00,
 998         .sysc_offs      = 0x20,
 999         .syss_offs      = 0x10,
1000         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1001         .sysc_fields    = &omap_hwmod_sysc_type1,
1002 };
1003
1004 static struct omap_hwmod_class i2c_class = {
1005         .name           = "i2c",
1006         .sysc           = &i2c_sysc,
1007         .rev            = OMAP_I2C_IP_VERSION_1,
1008         .reset          = &omap_i2c_reset,
1009 };
1010
1011 static struct omap_i2c_dev_attr i2c_dev_attr = {
1012         .flags          = OMAP_I2C_FLAG_NO_FIFO |
1013                           OMAP_I2C_FLAG_SIMPLE_CLOCK |
1014                           OMAP_I2C_FLAG_16BIT_DATA_REG |
1015                           OMAP_I2C_FLAG_BUS_SHIFT_2,
1016 };
1017
1018 /* I2C1 */
1019
1020 static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1021         &omap2420_l4_core__i2c1,
1022 };
1023
1024 static struct omap_hwmod omap2420_i2c1_hwmod = {
1025         .name           = "i2c1",
1026         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1027         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1028         .main_clk       = "i2c1_fck",
1029         .prcm           = {
1030                 .omap2 = {
1031                         .module_offs = CORE_MOD,
1032                         .prcm_reg_id = 1,
1033                         .module_bit = OMAP2420_EN_I2C1_SHIFT,
1034                         .idlest_reg_id = 1,
1035                         .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
1036                 },
1037         },
1038         .slaves         = omap2420_i2c1_slaves,
1039         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c1_slaves),
1040         .class          = &i2c_class,
1041         .dev_attr       = &i2c_dev_attr,
1042         .flags          = HWMOD_16BIT_REG,
1043 };
1044
1045 /* I2C2 */
1046
1047 static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
1048         &omap2420_l4_core__i2c2,
1049 };
1050
1051 static struct omap_hwmod omap2420_i2c2_hwmod = {
1052         .name           = "i2c2",
1053         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1054         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1055         .main_clk       = "i2c2_fck",
1056         .prcm           = {
1057                 .omap2 = {
1058                         .module_offs = CORE_MOD,
1059                         .prcm_reg_id = 1,
1060                         .module_bit = OMAP2420_EN_I2C2_SHIFT,
1061                         .idlest_reg_id = 1,
1062                         .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
1063                 },
1064         },
1065         .slaves         = omap2420_i2c2_slaves,
1066         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c2_slaves),
1067         .class          = &i2c_class,
1068         .dev_attr       = &i2c_dev_attr,
1069         .flags          = HWMOD_16BIT_REG,
1070 };
1071
1072 /* l4_wkup -> gpio1 */
1073 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1074         {
1075                 .pa_start       = 0x48018000,
1076                 .pa_end         = 0x480181ff,
1077                 .flags          = ADDR_TYPE_RT
1078         },
1079         { }
1080 };
1081
1082 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
1083         .master         = &omap2420_l4_wkup_hwmod,
1084         .slave          = &omap2420_gpio1_hwmod,
1085         .clk            = "gpios_ick",
1086         .addr           = omap2420_gpio1_addr_space,
1087         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1088 };
1089
1090 /* l4_wkup -> gpio2 */
1091 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
1092         {
1093                 .pa_start       = 0x4801a000,
1094                 .pa_end         = 0x4801a1ff,
1095                 .flags          = ADDR_TYPE_RT
1096         },
1097         { }
1098 };
1099
1100 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
1101         .master         = &omap2420_l4_wkup_hwmod,
1102         .slave          = &omap2420_gpio2_hwmod,
1103         .clk            = "gpios_ick",
1104         .addr           = omap2420_gpio2_addr_space,
1105         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1106 };
1107
1108 /* l4_wkup -> gpio3 */
1109 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
1110         {
1111                 .pa_start       = 0x4801c000,
1112                 .pa_end         = 0x4801c1ff,
1113                 .flags          = ADDR_TYPE_RT
1114         },
1115         { }
1116 };
1117
1118 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
1119         .master         = &omap2420_l4_wkup_hwmod,
1120         .slave          = &omap2420_gpio3_hwmod,
1121         .clk            = "gpios_ick",
1122         .addr           = omap2420_gpio3_addr_space,
1123         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1124 };
1125
1126 /* l4_wkup -> gpio4 */
1127 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
1128         {
1129                 .pa_start       = 0x4801e000,
1130                 .pa_end         = 0x4801e1ff,
1131                 .flags          = ADDR_TYPE_RT
1132         },
1133         { }
1134 };
1135
1136 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
1137         .master         = &omap2420_l4_wkup_hwmod,
1138         .slave          = &omap2420_gpio4_hwmod,
1139         .clk            = "gpios_ick",
1140         .addr           = omap2420_gpio4_addr_space,
1141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1142 };
1143
1144 /* gpio dev_attr */
1145 static struct omap_gpio_dev_attr gpio_dev_attr = {
1146         .bank_width = 32,
1147         .dbck_flag = false,
1148 };
1149
1150 /* gpio1 */
1151 static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1152         &omap2420_l4_wkup__gpio1,
1153 };
1154
1155 static struct omap_hwmod omap2420_gpio1_hwmod = {
1156         .name           = "gpio1",
1157         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1158         .mpu_irqs       = omap2_gpio1_irqs,
1159         .main_clk       = "gpios_fck",
1160         .prcm           = {
1161                 .omap2 = {
1162                         .prcm_reg_id = 1,
1163                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1164                         .module_offs = WKUP_MOD,
1165                         .idlest_reg_id = 1,
1166                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1167                 },
1168         },
1169         .slaves         = omap2420_gpio1_slaves,
1170         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
1171         .class          = &omap2xxx_gpio_hwmod_class,
1172         .dev_attr       = &gpio_dev_attr,
1173 };
1174
1175 /* gpio2 */
1176 static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1177         &omap2420_l4_wkup__gpio2,
1178 };
1179
1180 static struct omap_hwmod omap2420_gpio2_hwmod = {
1181         .name           = "gpio2",
1182         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1183         .mpu_irqs       = omap2_gpio2_irqs,
1184         .main_clk       = "gpios_fck",
1185         .prcm           = {
1186                 .omap2 = {
1187                         .prcm_reg_id = 1,
1188                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1189                         .module_offs = WKUP_MOD,
1190                         .idlest_reg_id = 1,
1191                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1192                 },
1193         },
1194         .slaves         = omap2420_gpio2_slaves,
1195         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
1196         .class          = &omap2xxx_gpio_hwmod_class,
1197         .dev_attr       = &gpio_dev_attr,
1198 };
1199
1200 /* gpio3 */
1201 static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1202         &omap2420_l4_wkup__gpio3,
1203 };
1204
1205 static struct omap_hwmod omap2420_gpio3_hwmod = {
1206         .name           = "gpio3",
1207         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1208         .mpu_irqs       = omap2_gpio3_irqs,
1209         .main_clk       = "gpios_fck",
1210         .prcm           = {
1211                 .omap2 = {
1212                         .prcm_reg_id = 1,
1213                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1214                         .module_offs = WKUP_MOD,
1215                         .idlest_reg_id = 1,
1216                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1217                 },
1218         },
1219         .slaves         = omap2420_gpio3_slaves,
1220         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
1221         .class          = &omap2xxx_gpio_hwmod_class,
1222         .dev_attr       = &gpio_dev_attr,
1223 };
1224
1225 /* gpio4 */
1226 static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1227         &omap2420_l4_wkup__gpio4,
1228 };
1229
1230 static struct omap_hwmod omap2420_gpio4_hwmod = {
1231         .name           = "gpio4",
1232         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1233         .mpu_irqs       = omap2_gpio4_irqs,
1234         .main_clk       = "gpios_fck",
1235         .prcm           = {
1236                 .omap2 = {
1237                         .prcm_reg_id = 1,
1238                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1239                         .module_offs = WKUP_MOD,
1240                         .idlest_reg_id = 1,
1241                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1242                 },
1243         },
1244         .slaves         = omap2420_gpio4_slaves,
1245         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
1246         .class          = &omap2xxx_gpio_hwmod_class,
1247         .dev_attr       = &gpio_dev_attr,
1248 };
1249
1250 /* dma attributes */
1251 static struct omap_dma_dev_attr dma_dev_attr = {
1252         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1253                                                 IS_CSSA_32 | IS_CDSA_32,
1254         .lch_count = 32,
1255 };
1256
1257 /* dma_system -> L3 */
1258 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
1259         .master         = &omap2420_dma_system_hwmod,
1260         .slave          = &omap2420_l3_main_hwmod,
1261         .clk            = "core_l3_ck",
1262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1263 };
1264
1265 /* dma_system master ports */
1266 static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
1267         &omap2420_dma_system__l3,
1268 };
1269
1270 /* l4_core -> dma_system */
1271 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
1272         .master         = &omap2420_l4_core_hwmod,
1273         .slave          = &omap2420_dma_system_hwmod,
1274         .clk            = "sdma_ick",
1275         .addr           = omap2_dma_system_addrs,
1276         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1277 };
1278
1279 /* dma_system slave ports */
1280 static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
1281         &omap2420_l4_core__dma_system,
1282 };
1283
1284 static struct omap_hwmod omap2420_dma_system_hwmod = {
1285         .name           = "dma",
1286         .class          = &omap2xxx_dma_hwmod_class,
1287         .mpu_irqs       = omap2_dma_system_irqs,
1288         .main_clk       = "core_l3_ck",
1289         .slaves         = omap2420_dma_system_slaves,
1290         .slaves_cnt     = ARRAY_SIZE(omap2420_dma_system_slaves),
1291         .masters        = omap2420_dma_system_masters,
1292         .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
1293         .dev_attr       = &dma_dev_attr,
1294         .flags          = HWMOD_NO_IDLEST,
1295 };
1296
1297 /* mailbox */
1298 static struct omap_hwmod omap2420_mailbox_hwmod;
1299 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1300         { .name = "dsp", .irq = 26 },
1301         { .name = "iva", .irq = 34 },
1302         { .irq = -1 }
1303 };
1304
1305 /* l4_core -> mailbox */
1306 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1307         .master         = &omap2420_l4_core_hwmod,
1308         .slave          = &omap2420_mailbox_hwmod,
1309         .addr           = omap2_mailbox_addrs,
1310         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1311 };
1312
1313 /* mailbox slave ports */
1314 static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1315         &omap2420_l4_core__mailbox,
1316 };
1317
1318 static struct omap_hwmod omap2420_mailbox_hwmod = {
1319         .name           = "mailbox",
1320         .class          = &omap2xxx_mailbox_hwmod_class,
1321         .mpu_irqs       = omap2420_mailbox_irqs,
1322         .main_clk       = "mailboxes_ick",
1323         .prcm           = {
1324                 .omap2 = {
1325                         .prcm_reg_id = 1,
1326                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1327                         .module_offs = CORE_MOD,
1328                         .idlest_reg_id = 1,
1329                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1330                 },
1331         },
1332         .slaves         = omap2420_mailbox_slaves,
1333         .slaves_cnt     = ARRAY_SIZE(omap2420_mailbox_slaves),
1334 };
1335
1336 /* mcspi1 */
1337 static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
1338         &omap2420_l4_core__mcspi1,
1339 };
1340
1341 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1342         .num_chipselect = 4,
1343 };
1344
1345 static struct omap_hwmod omap2420_mcspi1_hwmod = {
1346         .name           = "mcspi1_hwmod",
1347         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1348         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1349         .main_clk       = "mcspi1_fck",
1350         .prcm           = {
1351                 .omap2 = {
1352                         .module_offs = CORE_MOD,
1353                         .prcm_reg_id = 1,
1354                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1355                         .idlest_reg_id = 1,
1356                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1357                 },
1358         },
1359         .slaves         = omap2420_mcspi1_slaves,
1360         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi1_slaves),
1361         .class          = &omap2xxx_mcspi_class,
1362         .dev_attr       = &omap_mcspi1_dev_attr,
1363 };
1364
1365 /* mcspi2 */
1366 static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
1367         &omap2420_l4_core__mcspi2,
1368 };
1369
1370 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1371         .num_chipselect = 2,
1372 };
1373
1374 static struct omap_hwmod omap2420_mcspi2_hwmod = {
1375         .name           = "mcspi2_hwmod",
1376         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1377         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1378         .main_clk       = "mcspi2_fck",
1379         .prcm           = {
1380                 .omap2 = {
1381                         .module_offs = CORE_MOD,
1382                         .prcm_reg_id = 1,
1383                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1384                         .idlest_reg_id = 1,
1385                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1386                 },
1387         },
1388         .slaves         = omap2420_mcspi2_slaves,
1389         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi2_slaves),
1390         .class          = &omap2xxx_mcspi_class,
1391         .dev_attr       = &omap_mcspi2_dev_attr,
1392 };
1393
1394 /*
1395  * 'mcbsp' class
1396  * multi channel buffered serial port controller
1397  */
1398
1399 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
1400         .name = "mcbsp",
1401 };
1402
1403 /* mcbsp1 */
1404 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
1405         { .name = "tx", .irq = 59 },
1406         { .name = "rx", .irq = 60 },
1407         { .irq = -1 }
1408 };
1409
1410 /* l4_core -> mcbsp1 */
1411 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
1412         .master         = &omap2420_l4_core_hwmod,
1413         .slave          = &omap2420_mcbsp1_hwmod,
1414         .clk            = "mcbsp1_ick",
1415         .addr           = omap2_mcbsp1_addrs,
1416         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1417 };
1418
1419 /* mcbsp1 slave ports */
1420 static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
1421         &omap2420_l4_core__mcbsp1,
1422 };
1423
1424 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
1425         .name           = "mcbsp1",
1426         .class          = &omap2420_mcbsp_hwmod_class,
1427         .mpu_irqs       = omap2420_mcbsp1_irqs,
1428         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1429         .main_clk       = "mcbsp1_fck",
1430         .prcm           = {
1431                 .omap2 = {
1432                         .prcm_reg_id = 1,
1433                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1434                         .module_offs = CORE_MOD,
1435                         .idlest_reg_id = 1,
1436                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1437                 },
1438         },
1439         .slaves         = omap2420_mcbsp1_slaves,
1440         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp1_slaves),
1441 };
1442
1443 /* mcbsp2 */
1444 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
1445         { .name = "tx", .irq = 62 },
1446         { .name = "rx", .irq = 63 },
1447         { .irq = -1 }
1448 };
1449
1450 /* l4_core -> mcbsp2 */
1451 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
1452         .master         = &omap2420_l4_core_hwmod,
1453         .slave          = &omap2420_mcbsp2_hwmod,
1454         .clk            = "mcbsp2_ick",
1455         .addr           = omap2xxx_mcbsp2_addrs,
1456         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1457 };
1458
1459 /* mcbsp2 slave ports */
1460 static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
1461         &omap2420_l4_core__mcbsp2,
1462 };
1463
1464 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
1465         .name           = "mcbsp2",
1466         .class          = &omap2420_mcbsp_hwmod_class,
1467         .mpu_irqs       = omap2420_mcbsp2_irqs,
1468         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1469         .main_clk       = "mcbsp2_fck",
1470         .prcm           = {
1471                 .omap2 = {
1472                         .prcm_reg_id = 1,
1473                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1474                         .module_offs = CORE_MOD,
1475                         .idlest_reg_id = 1,
1476                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1477                 },
1478         },
1479         .slaves         = omap2420_mcbsp2_slaves,
1480         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp2_slaves),
1481 };
1482
1483 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1484         &omap2420_l3_main_hwmod,
1485         &omap2420_l4_core_hwmod,
1486         &omap2420_l4_wkup_hwmod,
1487         &omap2420_mpu_hwmod,
1488         &omap2420_iva_hwmod,
1489
1490         &omap2420_timer1_hwmod,
1491         &omap2420_timer2_hwmod,
1492         &omap2420_timer3_hwmod,
1493         &omap2420_timer4_hwmod,
1494         &omap2420_timer5_hwmod,
1495         &omap2420_timer6_hwmod,
1496         &omap2420_timer7_hwmod,
1497         &omap2420_timer8_hwmod,
1498         &omap2420_timer9_hwmod,
1499         &omap2420_timer10_hwmod,
1500         &omap2420_timer11_hwmod,
1501         &omap2420_timer12_hwmod,
1502
1503         &omap2420_wd_timer2_hwmod,
1504         &omap2420_uart1_hwmod,
1505         &omap2420_uart2_hwmod,
1506         &omap2420_uart3_hwmod,
1507         /* dss class */
1508         &omap2420_dss_core_hwmod,
1509         &omap2420_dss_dispc_hwmod,
1510         &omap2420_dss_rfbi_hwmod,
1511         &omap2420_dss_venc_hwmod,
1512         /* i2c class */
1513         &omap2420_i2c1_hwmod,
1514         &omap2420_i2c2_hwmod,
1515
1516         /* gpio class */
1517         &omap2420_gpio1_hwmod,
1518         &omap2420_gpio2_hwmod,
1519         &omap2420_gpio3_hwmod,
1520         &omap2420_gpio4_hwmod,
1521
1522         /* dma_system class*/
1523         &omap2420_dma_system_hwmod,
1524
1525         /* mailbox class */
1526         &omap2420_mailbox_hwmod,
1527
1528         /* mcbsp class */
1529         &omap2420_mcbsp1_hwmod,
1530         &omap2420_mcbsp2_hwmod,
1531
1532         /* mcspi class */
1533         &omap2420_mcspi1_hwmod,
1534         &omap2420_mcspi2_hwmod,
1535         NULL,
1536 };
1537
1538 int __init omap2420_hwmod_init(void)
1539 {
1540         return omap_hwmod_register(omap2420_hwmods);
1541 }