arch/arm/mach-omap2/omap_hwmod_2420_data.c

   1 /*
   2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcspi.h>
  22 #include <plat/dmtimer.h>
  23 #include <plat/l3_2xxx.h>
  24 #include <plat/l4_2xxx.h>
  25
  26 #include "omap_hwmod_common_data.h"
  27
  28 #include "cm-regbits-24xx.h"
  29 #include "prm-regbits-24xx.h"
  30 #include "wd_timer.h"
  31
  32 /*
  33  * OMAP2420 hardware module integration data
  34  *
  35  * ALl of the data in this section should be autogeneratable from the
  36  * TI hardware database or other technical documentation.  Data that
  37  * is driver-specific or driver-kernel integration-specific belongs
  38  * elsewhere.
  39  */
  40
  41 static struct omap_hwmod omap2420_mpu_hwmod;
  42 static struct omap_hwmod omap2420_iva_hwmod;
  43 static struct omap_hwmod omap2420_l3_main_hwmod;
  44 static struct omap_hwmod omap2420_l4_core_hwmod;
  45 static struct omap_hwmod omap2420_dss_core_hwmod;
  46 static struct omap_hwmod omap2420_dss_dispc_hwmod;
  47 static struct omap_hwmod omap2420_dss_rfbi_hwmod;
  48 static struct omap_hwmod omap2420_dss_venc_hwmod;
  49 static struct omap_hwmod omap2420_wd_timer2_hwmod;
  50 static struct omap_hwmod omap2420_gpio1_hwmod;
  51 static struct omap_hwmod omap2420_gpio2_hwmod;
  52 static struct omap_hwmod omap2420_gpio3_hwmod;
  53 static struct omap_hwmod omap2420_gpio4_hwmod;
  54 static struct omap_hwmod omap2420_dma_system_hwmod;
  55 static struct omap_hwmod omap2420_mcspi1_hwmod;
  56 static struct omap_hwmod omap2420_mcspi2_hwmod;
  57
  58 /* L3 -> L4_CORE interface */
  59 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
  60         .master = &omap2420_l3_main_hwmod,
  61         .slave  = &omap2420_l4_core_hwmod,
  62         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  63 };
  64
  65 /* MPU -> L3 interface */
  66 static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
  67         .master = &omap2420_mpu_hwmod,
  68         .slave  = &omap2420_l3_main_hwmod,
  69         .user   = OCP_USER_MPU,
  70 };
  71
  72 /* Slave interfaces on the L3 interconnect */
  73 static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
  74         &omap2420_mpu__l3_main,
  75 };
  76
  77 /* DSS -> l3 */
  78 static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
  79         .master         = &omap2420_dss_core_hwmod,
  80         .slave          = &omap2420_l3_main_hwmod,
  81         .fw = {
  82                 .omap2 = {
  83                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  84                         .flags  = OMAP_FIREWALL_L3,
  85                 }
  86         },
  87         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  88 };
  89
  90 /* Master interfaces on the L3 interconnect */
  91 static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
  92         &omap2420_l3_main__l4_core,
  93 };
  94
  95 /* L3 */
  96 static struct omap_hwmod omap2420_l3_main_hwmod = {
  97         .name           = "l3_main",
  98         .class          = &l3_hwmod_class,
  99         .masters        = omap2420_l3_main_masters,
 100         .masters_cnt    = ARRAY_SIZE(omap2420_l3_main_masters),
 101         .slaves         = omap2420_l3_main_slaves,
 102         .slaves_cnt     = ARRAY_SIZE(omap2420_l3_main_slaves),
 103         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 104         .flags          = HWMOD_NO_IDLEST,
 105 };
 106
 107 static struct omap_hwmod omap2420_l4_wkup_hwmod;
 108 static struct omap_hwmod omap2420_uart1_hwmod;
 109 static struct omap_hwmod omap2420_uart2_hwmod;
 110 static struct omap_hwmod omap2420_uart3_hwmod;
 111 static struct omap_hwmod omap2420_i2c1_hwmod;
 112 static struct omap_hwmod omap2420_i2c2_hwmod;
 113 static struct omap_hwmod omap2420_mcbsp1_hwmod;
 114 static struct omap_hwmod omap2420_mcbsp2_hwmod;
 115
 116 /* l4 core -> mcspi1 interface */
 117 static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
 118         {
 119                 .pa_start       = 0x48098000,
 120                 .pa_end         = 0x480980ff,
 121                 .flags          = ADDR_TYPE_RT,
 122         },
 123 };
 124
 125 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
 126         .master         = &omap2420_l4_core_hwmod,
 127         .slave          = &omap2420_mcspi1_hwmod,
 128         .clk            = "mcspi1_ick",
 129         .addr           = omap2420_mcspi1_addr_space,
 130         .addr_cnt       = ARRAY_SIZE(omap2420_mcspi1_addr_space),
 131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 132 };
 133
 134 /* l4 core -> mcspi2 interface */
 135 static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
 136         {
 137                 .pa_start       = 0x4809a000,
 138                 .pa_end         = 0x4809a0ff,
 139                 .flags          = ADDR_TYPE_RT,
 140         },
 141 };
 142
 143 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
 144         .master         = &omap2420_l4_core_hwmod,
 145         .slave          = &omap2420_mcspi2_hwmod,
 146         .clk            = "mcspi2_ick",
 147         .addr           = omap2420_mcspi2_addr_space,
 148         .addr_cnt       = ARRAY_SIZE(omap2420_mcspi2_addr_space),
 149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 150 };
 151
 152 /* L4_CORE -> L4_WKUP interface */
 153 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
 154         .master = &omap2420_l4_core_hwmod,
 155         .slave  = &omap2420_l4_wkup_hwmod,
 156         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 157 };
 158
 159 /* L4 CORE -> UART1 interface */
 160 static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
 161         {
 162                 .pa_start       = OMAP2_UART1_BASE,
 163                 .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
 164                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 165         },
 166 };
 167
 168 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 169         .master         = &omap2420_l4_core_hwmod,
 170         .slave          = &omap2420_uart1_hwmod,
 171         .clk            = "uart1_ick",
 172         .addr           = omap2420_uart1_addr_space,
 173         .addr_cnt       = ARRAY_SIZE(omap2420_uart1_addr_space),
 174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 175 };
 176
 177 /* L4 CORE -> UART2 interface */
 178 static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
 179         {
 180                 .pa_start       = OMAP2_UART2_BASE,
 181                 .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
 182                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 183         },
 184 };
 185
 186 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 187         .master         = &omap2420_l4_core_hwmod,
 188         .slave          = &omap2420_uart2_hwmod,
 189         .clk            = "uart2_ick",
 190         .addr           = omap2420_uart2_addr_space,
 191         .addr_cnt       = ARRAY_SIZE(omap2420_uart2_addr_space),
 192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 193 };
 194
 195 /* L4 PER -> UART3 interface */
 196 static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
 197         {
 198                 .pa_start       = OMAP2_UART3_BASE,
 199                 .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
 200                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 201         },
 202 };
 203
 204 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 205         .master         = &omap2420_l4_core_hwmod,
 206         .slave          = &omap2420_uart3_hwmod,
 207         .clk            = "uart3_ick",
 208         .addr           = omap2420_uart3_addr_space,
 209         .addr_cnt       = ARRAY_SIZE(omap2420_uart3_addr_space),
 210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 211 };
 212
 213 /* I2C IP block address space length (in bytes) */
 214 #define OMAP2_I2C_AS_LEN                128
 215
 216 /* L4 CORE -> I2C1 interface */
 217 static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
 218         {
 219                 .pa_start       = 0x48070000,
 220                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
 221                 .flags          = ADDR_TYPE_RT,
 222         },
 223 };
 224
 225 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 226         .master         = &omap2420_l4_core_hwmod,
 227         .slave          = &omap2420_i2c1_hwmod,
 228         .clk            = "i2c1_ick",
 229         .addr           = omap2420_i2c1_addr_space,
 230         .addr_cnt       = ARRAY_SIZE(omap2420_i2c1_addr_space),
 231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 232 };
 233
 234 /* L4 CORE -> I2C2 interface */
 235 static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
 236         {
 237                 .pa_start       = 0x48072000,
 238                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 239                 .flags          = ADDR_TYPE_RT,
 240         },
 241 };
 242
 243 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 244         .master         = &omap2420_l4_core_hwmod,
 245         .slave          = &omap2420_i2c2_hwmod,
 246         .clk            = "i2c2_ick",
 247         .addr           = omap2420_i2c2_addr_space,
 248         .addr_cnt       = ARRAY_SIZE(omap2420_i2c2_addr_space),
 249         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 250 };
 251
 252 /* Slave interfaces on the L4_CORE interconnect */
 253 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 254         &omap2420_l3_main__l4_core,
 255 };
 256
 257 /* Master interfaces on the L4_CORE interconnect */
 258 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
 259         &omap2420_l4_core__l4_wkup,
 260         &omap2_l4_core__uart1,
 261         &omap2_l4_core__uart2,
 262         &omap2_l4_core__uart3,
 263         &omap2420_l4_core__i2c1,
 264         &omap2420_l4_core__i2c2
 265 };
 266
 267 /* L4 CORE */
 268 static struct omap_hwmod omap2420_l4_core_hwmod = {
 269         .name           = "l4_core",
 270         .class          = &l4_hwmod_class,
 271         .masters        = omap2420_l4_core_masters,
 272         .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
 273         .slaves         = omap2420_l4_core_slaves,
 274         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
 275         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 276         .flags          = HWMOD_NO_IDLEST,
 277 };
 278
 279 /* Slave interfaces on the L4_WKUP interconnect */
 280 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
 281         &omap2420_l4_core__l4_wkup,
 282 };
 283
 284 /* Master interfaces on the L4_WKUP interconnect */
 285 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
 286 };
 287
 288 /* L4 WKUP */
 289 static struct omap_hwmod omap2420_l4_wkup_hwmod = {
 290         .name           = "l4_wkup",
 291         .class          = &l4_hwmod_class,
 292         .masters        = omap2420_l4_wkup_masters,
 293         .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
 294         .slaves         = omap2420_l4_wkup_slaves,
 295         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
 296         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 297         .flags          = HWMOD_NO_IDLEST,
 298 };
 299
 300 /* Master interfaces on the MPU device */
 301 static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
 302         &omap2420_mpu__l3_main,
 303 };
 304
 305 /* MPU */
 306 static struct omap_hwmod omap2420_mpu_hwmod = {
 307         .name           = "mpu",
 308         .class          = &mpu_hwmod_class,
 309         .main_clk       = "mpu_ck",
 310         .masters        = omap2420_mpu_masters,
 311         .masters_cnt    = ARRAY_SIZE(omap2420_mpu_masters),
 312         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 313 };
 314
 315 /*
 316  * IVA1 interface data
 317  */
 318
 319 /* IVA <- L3 interface */
 320 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 321         .master         = &omap2420_l3_main_hwmod,
 322         .slave          = &omap2420_iva_hwmod,
 323         .clk            = "iva1_ifck",
 324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 325 };
 326
 327 static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
 328         &omap2420_l3__iva,
 329 };
 330
 331 /*
 332  * IVA2 (IVA2)
 333  */
 334
 335 static struct omap_hwmod omap2420_iva_hwmod = {
 336         .name           = "iva",
 337         .class          = &iva_hwmod_class,
 338         .masters        = omap2420_iva_masters,
 339         .masters_cnt    = ARRAY_SIZE(omap2420_iva_masters),
 340         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 341 };
 342
 343 /* Timer Common */
 344 static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
 345         .rev_offs       = 0x0000,
 346         .sysc_offs      = 0x0010,
 347         .syss_offs      = 0x0014,
 348         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 349                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 350                            SYSC_HAS_AUTOIDLE),
 351         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 352         .sysc_fields    = &omap_hwmod_sysc_type1,
 353 };
 354
 355 static struct omap_hwmod_class omap2420_timer_hwmod_class = {
 356         .name = "timer",
 357         .sysc = &omap2420_timer_sysc,
 358         .rev = OMAP_TIMER_IP_VERSION_1,
 359 };
 360
 361 /* timer1 */
 362 static struct omap_hwmod omap2420_timer1_hwmod;
 363 static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
 364         { .irq = 37, },
 365 };
 366
 367 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
 368         {
 369                 .pa_start       = 0x48028000,
 370                 .pa_end         = 0x48028000 + SZ_1K - 1,
 371                 .flags          = ADDR_TYPE_RT
 372         },
 373 };
 374
 375 /* l4_wkup -> timer1 */
 376 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
 377         .master         = &omap2420_l4_wkup_hwmod,
 378         .slave          = &omap2420_timer1_hwmod,
 379         .clk            = "gpt1_ick",
 380         .addr           = omap2420_timer1_addrs,
 381         .addr_cnt       = ARRAY_SIZE(omap2420_timer1_addrs),
 382         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 383 };
 384
 385 /* timer1 slave port */
 386 static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
 387         &omap2420_l4_wkup__timer1,
 388 };
 389
 390 /* timer1 hwmod */
 391 static struct omap_hwmod omap2420_timer1_hwmod = {
 392         .name           = "timer1",
 393         .mpu_irqs       = omap2420_timer1_mpu_irqs,
 394         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
 395         .main_clk       = "gpt1_fck",
 396         .prcm           = {
 397                 .omap2 = {
 398                         .prcm_reg_id = 1,
 399                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 400                         .module_offs = WKUP_MOD,
 401                         .idlest_reg_id = 1,
 402                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 403                 },
 404         },
 405         .slaves         = omap2420_timer1_slaves,
 406         .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
 407         .class          = &omap2420_timer_hwmod_class,
 408         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 409 };
 410
 411 /* timer2 */
 412 static struct omap_hwmod omap2420_timer2_hwmod;
 413 static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
 414         { .irq = 38, },
 415 };
 416
 417 static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
 418         {
 419                 .pa_start       = 0x4802a000,
 420                 .pa_end         = 0x4802a000 + SZ_1K - 1,
 421                 .flags          = ADDR_TYPE_RT
 422         },
 423 };
 424
 425 /* l4_core -> timer2 */
 426 static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
 427         .master         = &omap2420_l4_core_hwmod,
 428         .slave          = &omap2420_timer2_hwmod,
 429         .clk            = "gpt2_ick",
 430         .addr           = omap2420_timer2_addrs,
 431         .addr_cnt       = ARRAY_SIZE(omap2420_timer2_addrs),
 432         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 433 };
 434
 435 /* timer2 slave port */
 436 static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
 437         &omap2420_l4_core__timer2,
 438 };
 439
 440 /* timer2 hwmod */
 441 static struct omap_hwmod omap2420_timer2_hwmod = {
 442         .name           = "timer2",
 443         .mpu_irqs       = omap2420_timer2_mpu_irqs,
 444         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
 445         .main_clk       = "gpt2_fck",
 446         .prcm           = {
 447                 .omap2 = {
 448                         .prcm_reg_id = 1,
 449                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 450                         .module_offs = CORE_MOD,
 451                         .idlest_reg_id = 1,
 452                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 453                 },
 454         },
 455         .slaves         = omap2420_timer2_slaves,
 456         .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
 457         .class          = &omap2420_timer_hwmod_class,
 458         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 459 };
 460
 461 /* timer3 */
 462 static struct omap_hwmod omap2420_timer3_hwmod;
 463 static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
 464         { .irq = 39, },
 465 };
 466
 467 static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
 468         {
 469                 .pa_start       = 0x48078000,
 470                 .pa_end         = 0x48078000 + SZ_1K - 1,
 471                 .flags          = ADDR_TYPE_RT
 472         },
 473 };
 474
 475 /* l4_core -> timer3 */
 476 static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
 477         .master         = &omap2420_l4_core_hwmod,
 478         .slave          = &omap2420_timer3_hwmod,
 479         .clk            = "gpt3_ick",
 480         .addr           = omap2420_timer3_addrs,
 481         .addr_cnt       = ARRAY_SIZE(omap2420_timer3_addrs),
 482         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 483 };
 484
 485 /* timer3 slave port */
 486 static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
 487         &omap2420_l4_core__timer3,
 488 };
 489
 490 /* timer3 hwmod */
 491 static struct omap_hwmod omap2420_timer3_hwmod = {
 492         .name           = "timer3",
 493         .mpu_irqs       = omap2420_timer3_mpu_irqs,
 494         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
 495         .main_clk       = "gpt3_fck",
 496         .prcm           = {
 497                 .omap2 = {
 498                         .prcm_reg_id = 1,
 499                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 500                         .module_offs = CORE_MOD,
 501                         .idlest_reg_id = 1,
 502                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 503                 },
 504         },
 505         .slaves         = omap2420_timer3_slaves,
 506         .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
 507         .class          = &omap2420_timer_hwmod_class,
 508         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 509 };
 510
 511 /* timer4 */
 512 static struct omap_hwmod omap2420_timer4_hwmod;
 513 static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
 514         { .irq = 40, },
 515 };
 516
 517 static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
 518         {
 519                 .pa_start       = 0x4807a000,
 520                 .pa_end         = 0x4807a000 + SZ_1K - 1,
 521                 .flags          = ADDR_TYPE_RT
 522         },
 523 };
 524
 525 /* l4_core -> timer4 */
 526 static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
 527         .master         = &omap2420_l4_core_hwmod,
 528         .slave          = &omap2420_timer4_hwmod,
 529         .clk            = "gpt4_ick",
 530         .addr           = omap2420_timer4_addrs,
 531         .addr_cnt       = ARRAY_SIZE(omap2420_timer4_addrs),
 532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 533 };
 534
 535 /* timer4 slave port */
 536 static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
 537         &omap2420_l4_core__timer4,
 538 };
 539
 540 /* timer4 hwmod */
 541 static struct omap_hwmod omap2420_timer4_hwmod = {
 542         .name           = "timer4",
 543         .mpu_irqs       = omap2420_timer4_mpu_irqs,
 544         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
 545         .main_clk       = "gpt4_fck",
 546         .prcm           = {
 547                 .omap2 = {
 548                         .prcm_reg_id = 1,
 549                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 550                         .module_offs = CORE_MOD,
 551                         .idlest_reg_id = 1,
 552                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 553                 },
 554         },
 555         .slaves         = omap2420_timer4_slaves,
 556         .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
 557         .class          = &omap2420_timer_hwmod_class,
 558         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 559 };
 560
 561 /* timer5 */
 562 static struct omap_hwmod omap2420_timer5_hwmod;
 563 static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
 564         { .irq = 41, },
 565 };
 566
 567 static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
 568         {
 569                 .pa_start       = 0x4807c000,
 570                 .pa_end         = 0x4807c000 + SZ_1K - 1,
 571                 .flags          = ADDR_TYPE_RT
 572         },
 573 };
 574
 575 /* l4_core -> timer5 */
 576 static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
 577         .master         = &omap2420_l4_core_hwmod,
 578         .slave          = &omap2420_timer5_hwmod,
 579         .clk            = "gpt5_ick",
 580         .addr           = omap2420_timer5_addrs,
 581         .addr_cnt       = ARRAY_SIZE(omap2420_timer5_addrs),
 582         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 583 };
 584
 585 /* timer5 slave port */
 586 static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
 587         &omap2420_l4_core__timer5,
 588 };
 589
 590 /* timer5 hwmod */
 591 static struct omap_hwmod omap2420_timer5_hwmod = {
 592         .name           = "timer5",
 593         .mpu_irqs       = omap2420_timer5_mpu_irqs,
 594         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
 595         .main_clk       = "gpt5_fck",
 596         .prcm           = {
 597                 .omap2 = {
 598                         .prcm_reg_id = 1,
 599                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 600                         .module_offs = CORE_MOD,
 601                         .idlest_reg_id = 1,
 602                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 603                 },
 604         },
 605         .slaves         = omap2420_timer5_slaves,
 606         .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
 607         .class          = &omap2420_timer_hwmod_class,
 608         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 609 };
 610
 611
 612 /* timer6 */
 613 static struct omap_hwmod omap2420_timer6_hwmod;
 614 static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
 615         { .irq = 42, },
 616 };
 617
 618 static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
 619         {
 620                 .pa_start       = 0x4807e000,
 621                 .pa_end         = 0x4807e000 + SZ_1K - 1,
 622                 .flags          = ADDR_TYPE_RT
 623         },
 624 };
 625
 626 /* l4_core -> timer6 */
 627 static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
 628         .master         = &omap2420_l4_core_hwmod,
 629         .slave          = &omap2420_timer6_hwmod,
 630         .clk            = "gpt6_ick",
 631         .addr           = omap2420_timer6_addrs,
 632         .addr_cnt       = ARRAY_SIZE(omap2420_timer6_addrs),
 633         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 634 };
 635
 636 /* timer6 slave port */
 637 static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
 638         &omap2420_l4_core__timer6,
 639 };
 640
 641 /* timer6 hwmod */
 642 static struct omap_hwmod omap2420_timer6_hwmod = {
 643         .name           = "timer6",
 644         .mpu_irqs       = omap2420_timer6_mpu_irqs,
 645         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
 646         .main_clk       = "gpt6_fck",
 647         .prcm           = {
 648                 .omap2 = {
 649                         .prcm_reg_id = 1,
 650                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 651                         .module_offs = CORE_MOD,
 652                         .idlest_reg_id = 1,
 653                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 654                 },
 655         },
 656         .slaves         = omap2420_timer6_slaves,
 657         .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
 658         .class          = &omap2420_timer_hwmod_class,
 659         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 660 };
 661
 662 /* timer7 */
 663 static struct omap_hwmod omap2420_timer7_hwmod;
 664 static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
 665         { .irq = 43, },
 666 };
 667
 668 static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
 669         {
 670                 .pa_start       = 0x48080000,
 671                 .pa_end         = 0x48080000 + SZ_1K - 1,
 672                 .flags          = ADDR_TYPE_RT
 673         },
 674 };
 675
 676 /* l4_core -> timer7 */
 677 static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
 678         .master         = &omap2420_l4_core_hwmod,
 679         .slave          = &omap2420_timer7_hwmod,
 680         .clk            = "gpt7_ick",
 681         .addr           = omap2420_timer7_addrs,
 682         .addr_cnt       = ARRAY_SIZE(omap2420_timer7_addrs),
 683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 684 };
 685
 686 /* timer7 slave port */
 687 static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
 688         &omap2420_l4_core__timer7,
 689 };
 690
 691 /* timer7 hwmod */
 692 static struct omap_hwmod omap2420_timer7_hwmod = {
 693         .name           = "timer7",
 694         .mpu_irqs       = omap2420_timer7_mpu_irqs,
 695         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
 696         .main_clk       = "gpt7_fck",
 697         .prcm           = {
 698                 .omap2 = {
 699                         .prcm_reg_id = 1,
 700                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 701                         .module_offs = CORE_MOD,
 702                         .idlest_reg_id = 1,
 703                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 704                 },
 705         },
 706         .slaves         = omap2420_timer7_slaves,
 707         .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
 708         .class          = &omap2420_timer_hwmod_class,
 709         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 710 };
 711
 712 /* timer8 */
 713 static struct omap_hwmod omap2420_timer8_hwmod;
 714 static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
 715         { .irq = 44, },
 716 };
 717
 718 static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
 719         {
 720                 .pa_start       = 0x48082000,
 721                 .pa_end         = 0x48082000 + SZ_1K - 1,
 722                 .flags          = ADDR_TYPE_RT
 723         },
 724 };
 725
 726 /* l4_core -> timer8 */
 727 static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
 728         .master         = &omap2420_l4_core_hwmod,
 729         .slave          = &omap2420_timer8_hwmod,
 730         .clk            = "gpt8_ick",
 731         .addr           = omap2420_timer8_addrs,
 732         .addr_cnt       = ARRAY_SIZE(omap2420_timer8_addrs),
 733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 734 };
 735
 736 /* timer8 slave port */
 737 static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
 738         &omap2420_l4_core__timer8,
 739 };
 740
 741 /* timer8 hwmod */
 742 static struct omap_hwmod omap2420_timer8_hwmod = {
 743         .name           = "timer8",
 744         .mpu_irqs       = omap2420_timer8_mpu_irqs,
 745         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
 746         .main_clk       = "gpt8_fck",
 747         .prcm           = {
 748                 .omap2 = {
 749                         .prcm_reg_id = 1,
 750                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 751                         .module_offs = CORE_MOD,
 752                         .idlest_reg_id = 1,
 753                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 754                 },
 755         },
 756         .slaves         = omap2420_timer8_slaves,
 757         .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
 758         .class          = &omap2420_timer_hwmod_class,
 759         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 760 };
 761
 762 /* timer9 */
 763 static struct omap_hwmod omap2420_timer9_hwmod;
 764 static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
 765         { .irq = 45, },
 766 };
 767
 768 static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
 769         {
 770                 .pa_start       = 0x48084000,
 771                 .pa_end         = 0x48084000 + SZ_1K - 1,
 772                 .flags          = ADDR_TYPE_RT
 773         },
 774 };
 775
 776 /* l4_core -> timer9 */
 777 static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
 778         .master         = &omap2420_l4_core_hwmod,
 779         .slave          = &omap2420_timer9_hwmod,
 780         .clk            = "gpt9_ick",
 781         .addr           = omap2420_timer9_addrs,
 782         .addr_cnt       = ARRAY_SIZE(omap2420_timer9_addrs),
 783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 784 };
 785
 786 /* timer9 slave port */
 787 static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
 788         &omap2420_l4_core__timer9,
 789 };
 790
 791 /* timer9 hwmod */
 792 static struct omap_hwmod omap2420_timer9_hwmod = {
 793         .name           = "timer9",
 794         .mpu_irqs       = omap2420_timer9_mpu_irqs,
 795         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
 796         .main_clk       = "gpt9_fck",
 797         .prcm           = {
 798                 .omap2 = {
 799                         .prcm_reg_id = 1,
 800                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 801                         .module_offs = CORE_MOD,
 802                         .idlest_reg_id = 1,
 803                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 804                 },
 805         },
 806         .slaves         = omap2420_timer9_slaves,
 807         .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
 808         .class          = &omap2420_timer_hwmod_class,
 809         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 810 };
 811
 812 /* timer10 */
 813 static struct omap_hwmod omap2420_timer10_hwmod;
 814 static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
 815         { .irq = 46, },
 816 };
 817
 818 static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
 819         {
 820                 .pa_start       = 0x48086000,
 821                 .pa_end         = 0x48086000 + SZ_1K - 1,
 822                 .flags          = ADDR_TYPE_RT
 823         },
 824 };
 825
 826 /* l4_core -> timer10 */
 827 static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
 828         .master         = &omap2420_l4_core_hwmod,
 829         .slave          = &omap2420_timer10_hwmod,
 830         .clk            = "gpt10_ick",
 831         .addr           = omap2420_timer10_addrs,
 832         .addr_cnt       = ARRAY_SIZE(omap2420_timer10_addrs),
 833         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 834 };
 835
 836 /* timer10 slave port */
 837 static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
 838         &omap2420_l4_core__timer10,
 839 };
 840
 841 /* timer10 hwmod */
 842 static struct omap_hwmod omap2420_timer10_hwmod = {
 843         .name           = "timer10",
 844         .mpu_irqs       = omap2420_timer10_mpu_irqs,
 845         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
 846         .main_clk       = "gpt10_fck",
 847         .prcm           = {
 848                 .omap2 = {
 849                         .prcm_reg_id = 1,
 850                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 851                         .module_offs = CORE_MOD,
 852                         .idlest_reg_id = 1,
 853                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 854                 },
 855         },
 856         .slaves         = omap2420_timer10_slaves,
 857         .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
 858         .class          = &omap2420_timer_hwmod_class,
 859         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 860 };
 861
 862 /* timer11 */
 863 static struct omap_hwmod omap2420_timer11_hwmod;
 864 static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
 865         { .irq = 47, },
 866 };
 867
 868 static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
 869         {
 870                 .pa_start       = 0x48088000,
 871                 .pa_end         = 0x48088000 + SZ_1K - 1,
 872                 .flags          = ADDR_TYPE_RT
 873         },
 874 };
 875
 876 /* l4_core -> timer11 */
 877 static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
 878         .master         = &omap2420_l4_core_hwmod,
 879         .slave          = &omap2420_timer11_hwmod,
 880         .clk            = "gpt11_ick",
 881         .addr           = omap2420_timer11_addrs,
 882         .addr_cnt       = ARRAY_SIZE(omap2420_timer11_addrs),
 883         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 884 };
 885
 886 /* timer11 slave port */
 887 static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
 888         &omap2420_l4_core__timer11,
 889 };
 890
 891 /* timer11 hwmod */
 892 static struct omap_hwmod omap2420_timer11_hwmod = {
 893         .name           = "timer11",
 894         .mpu_irqs       = omap2420_timer11_mpu_irqs,
 895         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
 896         .main_clk       = "gpt11_fck",
 897         .prcm           = {
 898                 .omap2 = {
 899                         .prcm_reg_id = 1,
 900                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 901                         .module_offs = CORE_MOD,
 902                         .idlest_reg_id = 1,
 903                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 904                 },
 905         },
 906         .slaves         = omap2420_timer11_slaves,
 907         .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
 908         .class          = &omap2420_timer_hwmod_class,
 909         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 910 };
 911
 912 /* timer12 */
 913 static struct omap_hwmod omap2420_timer12_hwmod;
 914 static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
 915         { .irq = 48, },
 916 };
 917
 918 static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
 919         {
 920                 .pa_start       = 0x4808a000,
 921                 .pa_end         = 0x4808a000 + SZ_1K - 1,
 922                 .flags          = ADDR_TYPE_RT
 923         },
 924 };
 925
 926 /* l4_core -> timer12 */
 927 static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
 928         .master         = &omap2420_l4_core_hwmod,
 929         .slave          = &omap2420_timer12_hwmod,
 930         .clk            = "gpt12_ick",
 931         .addr           = omap2420_timer12_addrs,
 932         .addr_cnt       = ARRAY_SIZE(omap2420_timer12_addrs),
 933         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 934 };
 935
 936 /* timer12 slave port */
 937 static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
 938         &omap2420_l4_core__timer12,
 939 };
 940
 941 /* timer12 hwmod */
 942 static struct omap_hwmod omap2420_timer12_hwmod = {
 943         .name           = "timer12",
 944         .mpu_irqs       = omap2420_timer12_mpu_irqs,
 945         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
 946         .main_clk       = "gpt12_fck",
 947         .prcm           = {
 948                 .omap2 = {
 949                         .prcm_reg_id = 1,
 950                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 951                         .module_offs = CORE_MOD,
 952                         .idlest_reg_id = 1,
 953                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 954                 },
 955         },
 956         .slaves         = omap2420_timer12_slaves,
 957         .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
 958         .class          = &omap2420_timer_hwmod_class,
 959         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 960 };
 961
 962 /* l4_wkup -> wd_timer2 */
 963 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 964         {
 965                 .pa_start       = 0x48022000,
 966                 .pa_end         = 0x4802207f,
 967                 .flags          = ADDR_TYPE_RT
 968         },
 969 };
 970
 971 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 972         .master         = &omap2420_l4_wkup_hwmod,
 973         .slave          = &omap2420_wd_timer2_hwmod,
 974         .clk            = "mpu_wdt_ick",
 975         .addr           = omap2420_wd_timer2_addrs,
 976         .addr_cnt       = ARRAY_SIZE(omap2420_wd_timer2_addrs),
 977         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 978 };
 979
 980 /*
 981  * 'wd_timer' class
 982  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 983  * overflow condition
 984  */
 985
 986 static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
 987         .rev_offs       = 0x0000,
 988         .sysc_offs      = 0x0010,
 989         .syss_offs      = 0x0014,
 990         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 991                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 992         .sysc_fields    = &omap_hwmod_sysc_type1,
 993 };
 994
 995 static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
 996         .name           = "wd_timer",
 997         .sysc           = &omap2420_wd_timer_sysc,
 998         .pre_shutdown   = &omap2_wd_timer_disable
 999 };
1000
1001 /* wd_timer2 */
1002 static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
1003         &omap2420_l4_wkup__wd_timer2,
1004 };
1005
1006 static struct omap_hwmod omap2420_wd_timer2_hwmod = {
1007         .name           = "wd_timer2",
1008         .class          = &omap2420_wd_timer_hwmod_class,
1009         .main_clk       = "mpu_wdt_fck",
1010         .prcm           = {
1011                 .omap2 = {
1012                         .prcm_reg_id = 1,
1013                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1014                         .module_offs = WKUP_MOD,
1015                         .idlest_reg_id = 1,
1016                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
1017                 },
1018         },
1019         .slaves         = omap2420_wd_timer2_slaves,
1020         .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
1021         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1022 };
1023
1024 /* UART */
1025
1026 static struct omap_hwmod_class_sysconfig uart_sysc = {
1027         .rev_offs       = 0x50,
1028         .sysc_offs      = 0x54,
1029         .syss_offs      = 0x58,
1030         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
1031                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1032                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1033         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1034         .sysc_fields    = &omap_hwmod_sysc_type1,
1035 };
1036
1037 static struct omap_hwmod_class uart_class = {
1038         .name = "uart",
1039         .sysc = &uart_sysc,
1040 };
1041
1042 /* UART1 */
1043
1044 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1045         { .irq = INT_24XX_UART1_IRQ, },
1046 };
1047
1048 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1049         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1050         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1051 };
1052
1053 static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
1054         &omap2_l4_core__uart1,
1055 };
1056
1057 static struct omap_hwmod omap2420_uart1_hwmod = {
1058         .name           = "uart1",
1059         .mpu_irqs       = uart1_mpu_irqs,
1060         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
1061         .sdma_reqs      = uart1_sdma_reqs,
1062         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
1063         .main_clk       = "uart1_fck",
1064         .prcm           = {
1065                 .omap2 = {
1066                         .module_offs = CORE_MOD,
1067                         .prcm_reg_id = 1,
1068                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
1069                         .idlest_reg_id = 1,
1070                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
1071                 },
1072         },
1073         .slaves         = omap2420_uart1_slaves,
1074         .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
1075         .class          = &uart_class,
1076         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1077 };
1078
1079 /* UART2 */
1080
1081 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1082         { .irq = INT_24XX_UART2_IRQ, },
1083 };
1084
1085 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1086         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1087         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1088 };
1089
1090 static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
1091         &omap2_l4_core__uart2,
1092 };
1093
1094 static struct omap_hwmod omap2420_uart2_hwmod = {
1095         .name           = "uart2",
1096         .mpu_irqs       = uart2_mpu_irqs,
1097         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
1098         .sdma_reqs      = uart2_sdma_reqs,
1099         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
1100         .main_clk       = "uart2_fck",
1101         .prcm           = {
1102                 .omap2 = {
1103                         .module_offs = CORE_MOD,
1104                         .prcm_reg_id = 1,
1105                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
1106                         .idlest_reg_id = 1,
1107                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
1108                 },
1109         },
1110         .slaves         = omap2420_uart2_slaves,
1111         .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
1112         .class          = &uart_class,
1113         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1114 };
1115
1116 /* UART3 */
1117
1118 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1119         { .irq = INT_24XX_UART3_IRQ, },
1120 };
1121
1122 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1123         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1124         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1125 };
1126
1127 static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
1128         &omap2_l4_core__uart3,
1129 };
1130
1131 static struct omap_hwmod omap2420_uart3_hwmod = {
1132         .name           = "uart3",
1133         .mpu_irqs       = uart3_mpu_irqs,
1134         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
1135         .sdma_reqs      = uart3_sdma_reqs,
1136         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
1137         .main_clk       = "uart3_fck",
1138         .prcm           = {
1139                 .omap2 = {
1140                         .module_offs = CORE_MOD,
1141                         .prcm_reg_id = 2,
1142                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
1143                         .idlest_reg_id = 2,
1144                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
1145                 },
1146         },
1147         .slaves         = omap2420_uart3_slaves,
1148         .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
1149         .class          = &uart_class,
1150         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1151 };
1152
1153 /*
1154  * 'dss' class
1155  * display sub-system
1156  */
1157
1158 static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
1159         .rev_offs       = 0x0000,
1160         .sysc_offs      = 0x0010,
1161         .syss_offs      = 0x0014,
1162         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1163         .sysc_fields    = &omap_hwmod_sysc_type1,
1164 };
1165
1166 static struct omap_hwmod_class omap2420_dss_hwmod_class = {
1167         .name = "dss",
1168         .sysc = &omap2420_dss_sysc,
1169 };
1170
1171 /* dss */
1172 static struct omap_hwmod_irq_info omap2420_dss_irqs[] = {
1173         { .irq = 25 },
1174 };
1175
1176 static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
1177         { .name = "dispc", .dma_req = 5 },
1178 };
1179
1180 /* dss */
1181 /* dss master ports */
1182 static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
1183         &omap2420_dss__l3,
1184 };
1185
1186 static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
1187         {
1188                 .pa_start       = 0x48050000,
1189                 .pa_end         = 0x480503FF,
1190                 .flags          = ADDR_TYPE_RT
1191         },
1192 };
1193
1194 /* l4_core -> dss */
1195 static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
1196         .master         = &omap2420_l4_core_hwmod,
1197         .slave          = &omap2420_dss_core_hwmod,
1198         .clk            = "dss_ick",
1199         .addr           = omap2420_dss_addrs,
1200         .addr_cnt       = ARRAY_SIZE(omap2420_dss_addrs),
1201         .fw = {
1202                 .omap2 = {
1203                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
1204                         .flags  = OMAP_FIREWALL_L4,
1205                 }
1206         },
1207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1208 };
1209
1210 /* dss slave ports */
1211 static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
1212         &omap2420_l4_core__dss,
1213 };
1214
1215 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1216         { .role = "tv_clk", .clk = "dss_54m_fck" },
1217         { .role = "sys_clk", .clk = "dss2_fck" },
1218 };
1219
1220 static struct omap_hwmod omap2420_dss_core_hwmod = {
1221         .name           = "dss_core",
1222         .class          = &omap2420_dss_hwmod_class,
1223         .main_clk       = "dss1_fck", /* instead of dss_fck */
1224         .mpu_irqs       = omap2420_dss_irqs,
1225         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_dss_irqs),
1226         .sdma_reqs      = omap2420_dss_sdma_chs,
1227         .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_dss_sdma_chs),
1228         .prcm           = {
1229                 .omap2 = {
1230                         .prcm_reg_id = 1,
1231                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1232                         .module_offs = CORE_MOD,
1233                         .idlest_reg_id = 1,
1234                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1235                 },
1236         },
1237         .opt_clks       = dss_opt_clks,
1238         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1239         .slaves         = omap2420_dss_slaves,
1240         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_slaves),
1241         .masters        = omap2420_dss_masters,
1242         .masters_cnt    = ARRAY_SIZE(omap2420_dss_masters),
1243         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1244         .flags          = HWMOD_NO_IDLEST,
1245 };
1246
1247 /*
1248  * 'dispc' class
1249  * display controller
1250  */
1251
1252 static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
1253         .rev_offs       = 0x0000,
1254         .sysc_offs      = 0x0010,
1255         .syss_offs      = 0x0014,
1256         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1257                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1258         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1259                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1260         .sysc_fields    = &omap_hwmod_sysc_type1,
1261 };
1262
1263 static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
1264         .name = "dispc",
1265         .sysc = &omap2420_dispc_sysc,
1266 };
1267
1268 static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
1269         {
1270                 .pa_start       = 0x48050400,
1271                 .pa_end         = 0x480507FF,
1272                 .flags          = ADDR_TYPE_RT
1273         },
1274 };
1275
1276 /* l4_core -> dss_dispc */
1277 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
1278         .master         = &omap2420_l4_core_hwmod,
1279         .slave          = &omap2420_dss_dispc_hwmod,
1280         .clk            = "dss_ick",
1281         .addr           = omap2420_dss_dispc_addrs,
1282         .addr_cnt       = ARRAY_SIZE(omap2420_dss_dispc_addrs),
1283         .fw = {
1284                 .omap2 = {
1285                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
1286                         .flags  = OMAP_FIREWALL_L4,
1287                 }
1288         },
1289         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1290 };
1291
1292 /* dss_dispc slave ports */
1293 static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
1294         &omap2420_l4_core__dss_dispc,
1295 };
1296
1297 static struct omap_hwmod omap2420_dss_dispc_hwmod = {
1298         .name           = "dss_dispc",
1299         .class          = &omap2420_dispc_hwmod_class,
1300         .main_clk       = "dss1_fck",
1301         .prcm           = {
1302                 .omap2 = {
1303                         .prcm_reg_id = 1,
1304                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1305                         .module_offs = CORE_MOD,
1306                         .idlest_reg_id = 1,
1307                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1308                 },
1309         },
1310         .slaves         = omap2420_dss_dispc_slaves,
1311         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_dispc_slaves),
1312         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1313         .flags          = HWMOD_NO_IDLEST,
1314 };
1315
1316 /*
1317  * 'rfbi' class
1318  * remote frame buffer interface
1319  */
1320
1321 static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
1322         .rev_offs       = 0x0000,
1323         .sysc_offs      = 0x0010,
1324         .syss_offs      = 0x0014,
1325         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1326                            SYSC_HAS_AUTOIDLE),
1327         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1328         .sysc_fields    = &omap_hwmod_sysc_type1,
1329 };
1330
1331 static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
1332         .name = "rfbi",
1333         .sysc = &omap2420_rfbi_sysc,
1334 };
1335
1336 static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
1337         {
1338                 .pa_start       = 0x48050800,
1339                 .pa_end         = 0x48050BFF,
1340                 .flags          = ADDR_TYPE_RT
1341         },
1342 };
1343
1344 /* l4_core -> dss_rfbi */
1345 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
1346         .master         = &omap2420_l4_core_hwmod,
1347         .slave          = &omap2420_dss_rfbi_hwmod,
1348         .clk            = "dss_ick",
1349         .addr           = omap2420_dss_rfbi_addrs,
1350         .addr_cnt       = ARRAY_SIZE(omap2420_dss_rfbi_addrs),
1351         .fw = {
1352                 .omap2 = {
1353                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
1354                         .flags  = OMAP_FIREWALL_L4,
1355                 }
1356         },
1357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1358 };
1359
1360 /* dss_rfbi slave ports */
1361 static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
1362         &omap2420_l4_core__dss_rfbi,
1363 };
1364
1365 static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
1366         .name           = "dss_rfbi",
1367         .class          = &omap2420_rfbi_hwmod_class,
1368         .main_clk       = "dss1_fck",
1369         .prcm           = {
1370                 .omap2 = {
1371                         .prcm_reg_id = 1,
1372                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1373                         .module_offs = CORE_MOD,
1374                 },
1375         },
1376         .slaves         = omap2420_dss_rfbi_slaves,
1377         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
1378         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1379         .flags          = HWMOD_NO_IDLEST,
1380 };
1381
1382 /*
1383  * 'venc' class
1384  * video encoder
1385  */
1386
1387 static struct omap_hwmod_class omap2420_venc_hwmod_class = {
1388         .name = "venc",
1389 };
1390
1391 /* dss_venc */
1392 static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
1393         {
1394                 .pa_start       = 0x48050C00,
1395                 .pa_end         = 0x48050FFF,
1396                 .flags          = ADDR_TYPE_RT
1397         },
1398 };
1399
1400 /* l4_core -> dss_venc */
1401 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
1402         .master         = &omap2420_l4_core_hwmod,
1403         .slave          = &omap2420_dss_venc_hwmod,
1404         .clk            = "dss_54m_fck",
1405         .addr           = omap2420_dss_venc_addrs,
1406         .addr_cnt       = ARRAY_SIZE(omap2420_dss_venc_addrs),
1407         .fw = {
1408                 .omap2 = {
1409                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
1410                         .flags  = OMAP_FIREWALL_L4,
1411                 }
1412         },
1413         .flags          = OCPIF_SWSUP_IDLE,
1414         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1415 };
1416
1417 /* dss_venc slave ports */
1418 static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
1419         &omap2420_l4_core__dss_venc,
1420 };
1421
1422 static struct omap_hwmod omap2420_dss_venc_hwmod = {
1423         .name           = "dss_venc",
1424         .class          = &omap2420_venc_hwmod_class,
1425         .main_clk       = "dss1_fck",
1426         .prcm           = {
1427                 .omap2 = {
1428                         .prcm_reg_id = 1,
1429                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1430                         .module_offs = CORE_MOD,
1431                 },
1432         },
1433         .slaves         = omap2420_dss_venc_slaves,
1434         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_venc_slaves),
1435         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1436         .flags          = HWMOD_NO_IDLEST,
1437 };
1438
1439 /* I2C common */
1440 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1441         .rev_offs       = 0x00,
1442         .sysc_offs      = 0x20,
1443         .syss_offs      = 0x10,
1444         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1445         .sysc_fields    = &omap_hwmod_sysc_type1,
1446 };
1447
1448 static struct omap_hwmod_class i2c_class = {
1449         .name           = "i2c",
1450         .sysc           = &i2c_sysc,
1451 };
1452
1453 static struct omap_i2c_dev_attr i2c_dev_attr;
1454
1455 /* I2C1 */
1456
1457 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1458         { .irq = INT_24XX_I2C1_IRQ, },
1459 };
1460
1461 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1462         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1463         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1464 };
1465
1466 static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1467         &omap2420_l4_core__i2c1,
1468 };
1469
1470 static struct omap_hwmod omap2420_i2c1_hwmod = {
1471         .name           = "i2c1",
1472         .mpu_irqs       = i2c1_mpu_irqs,
1473         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
1474         .sdma_reqs      = i2c1_sdma_reqs,
1475         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
1476         .main_clk       = "i2c1_fck",
1477         .prcm           = {
1478                 .omap2 = {
1479                         .module_offs = CORE_MOD,
1480                         .prcm_reg_id = 1,
1481                         .module_bit = OMAP2420_EN_I2C1_SHIFT,
1482                         .idlest_reg_id = 1,
1483                         .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
1484                 },
1485         },
1486         .slaves         = omap2420_i2c1_slaves,
1487         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c1_slaves),
1488         .class          = &i2c_class,
1489         .dev_attr       = &i2c_dev_attr,
1490         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1491         .flags          = HWMOD_16BIT_REG,
1492 };
1493
1494 /* I2C2 */
1495
1496 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1497         { .irq = INT_24XX_I2C2_IRQ, },
1498 };
1499
1500 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1501         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1502         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1503 };
1504
1505 static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
1506         &omap2420_l4_core__i2c2,
1507 };
1508
1509 static struct omap_hwmod omap2420_i2c2_hwmod = {
1510         .name           = "i2c2",
1511         .mpu_irqs       = i2c2_mpu_irqs,
1512         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
1513         .sdma_reqs      = i2c2_sdma_reqs,
1514         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
1515         .main_clk       = "i2c2_fck",
1516         .prcm           = {
1517                 .omap2 = {
1518                         .module_offs = CORE_MOD,
1519                         .prcm_reg_id = 1,
1520                         .module_bit = OMAP2420_EN_I2C2_SHIFT,
1521                         .idlest_reg_id = 1,
1522                         .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
1523                 },
1524         },
1525         .slaves         = omap2420_i2c2_slaves,
1526         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c2_slaves),
1527         .class          = &i2c_class,
1528         .dev_attr       = &i2c_dev_attr,
1529         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1530         .flags          = HWMOD_16BIT_REG,
1531 };
1532
1533 /* l4_wkup -> gpio1 */
1534 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1535         {
1536                 .pa_start       = 0x48018000,
1537                 .pa_end         = 0x480181ff,
1538                 .flags          = ADDR_TYPE_RT
1539         },
1540 };
1541
1542 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
1543         .master         = &omap2420_l4_wkup_hwmod,
1544         .slave          = &omap2420_gpio1_hwmod,
1545         .clk            = "gpios_ick",
1546         .addr           = omap2420_gpio1_addr_space,
1547         .addr_cnt       = ARRAY_SIZE(omap2420_gpio1_addr_space),
1548         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1549 };
1550
1551 /* l4_wkup -> gpio2 */
1552 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
1553         {
1554                 .pa_start       = 0x4801a000,
1555                 .pa_end         = 0x4801a1ff,
1556                 .flags          = ADDR_TYPE_RT
1557         },
1558 };
1559
1560 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
1561         .master         = &omap2420_l4_wkup_hwmod,
1562         .slave          = &omap2420_gpio2_hwmod,
1563         .clk            = "gpios_ick",
1564         .addr           = omap2420_gpio2_addr_space,
1565         .addr_cnt       = ARRAY_SIZE(omap2420_gpio2_addr_space),
1566         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1567 };
1568
1569 /* l4_wkup -> gpio3 */
1570 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
1571         {
1572                 .pa_start       = 0x4801c000,
1573                 .pa_end         = 0x4801c1ff,
1574                 .flags          = ADDR_TYPE_RT
1575         },
1576 };
1577
1578 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
1579         .master         = &omap2420_l4_wkup_hwmod,
1580         .slave          = &omap2420_gpio3_hwmod,
1581         .clk            = "gpios_ick",
1582         .addr           = omap2420_gpio3_addr_space,
1583         .addr_cnt       = ARRAY_SIZE(omap2420_gpio3_addr_space),
1584         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1585 };
1586
1587 /* l4_wkup -> gpio4 */
1588 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
1589         {
1590                 .pa_start       = 0x4801e000,
1591                 .pa_end         = 0x4801e1ff,
1592                 .flags          = ADDR_TYPE_RT
1593         },
1594 };
1595
1596 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
1597         .master         = &omap2420_l4_wkup_hwmod,
1598         .slave          = &omap2420_gpio4_hwmod,
1599         .clk            = "gpios_ick",
1600         .addr           = omap2420_gpio4_addr_space,
1601         .addr_cnt       = ARRAY_SIZE(omap2420_gpio4_addr_space),
1602         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1603 };
1604
1605 /* gpio dev_attr */
1606 static struct omap_gpio_dev_attr gpio_dev_attr = {
1607         .bank_width = 32,
1608         .dbck_flag = false,
1609 };
1610
1611 static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
1612         .rev_offs       = 0x0000,
1613         .sysc_offs      = 0x0010,
1614         .syss_offs      = 0x0014,
1615         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1616                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1617                            SYSS_HAS_RESET_STATUS),
1618         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1619         .sysc_fields    = &omap_hwmod_sysc_type1,
1620 };
1621
1622 /*
1623  * 'gpio' class
1624  * general purpose io module
1625  */
1626 static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
1627         .name = "gpio",
1628         .sysc = &omap242x_gpio_sysc,
1629         .rev = 0,
1630 };
1631
1632 /* gpio1 */
1633 static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
1634         { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
1635 };
1636
1637 static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1638         &omap2420_l4_wkup__gpio1,
1639 };
1640
1641 static struct omap_hwmod omap2420_gpio1_hwmod = {
1642         .name           = "gpio1",
1643         .mpu_irqs       = omap242x_gpio1_irqs,
1644         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio1_irqs),
1645         .main_clk       = "gpios_fck",
1646         .prcm           = {
1647                 .omap2 = {
1648                         .prcm_reg_id = 1,
1649                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1650                         .module_offs = WKUP_MOD,
1651                         .idlest_reg_id = 1,
1652                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1653                 },
1654         },
1655         .slaves         = omap2420_gpio1_slaves,
1656         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
1657         .class          = &omap242x_gpio_hwmod_class,
1658         .dev_attr       = &gpio_dev_attr,
1659         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1660 };
1661
1662 /* gpio2 */
1663 static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
1664         { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
1665 };
1666
1667 static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1668         &omap2420_l4_wkup__gpio2,
1669 };
1670
1671 static struct omap_hwmod omap2420_gpio2_hwmod = {
1672         .name           = "gpio2",
1673         .mpu_irqs       = omap242x_gpio2_irqs,
1674         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio2_irqs),
1675         .main_clk       = "gpios_fck",
1676         .prcm           = {
1677                 .omap2 = {
1678                         .prcm_reg_id = 1,
1679                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1680                         .module_offs = WKUP_MOD,
1681                         .idlest_reg_id = 1,
1682                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1683                 },
1684         },
1685         .slaves         = omap2420_gpio2_slaves,
1686         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
1687         .class          = &omap242x_gpio_hwmod_class,
1688         .dev_attr       = &gpio_dev_attr,
1689         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1690 };
1691
1692 /* gpio3 */
1693 static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
1694         { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
1695 };
1696
1697 static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1698         &omap2420_l4_wkup__gpio3,
1699 };
1700
1701 static struct omap_hwmod omap2420_gpio3_hwmod = {
1702         .name           = "gpio3",
1703         .mpu_irqs       = omap242x_gpio3_irqs,
1704         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio3_irqs),
1705         .main_clk       = "gpios_fck",
1706         .prcm           = {
1707                 .omap2 = {
1708                         .prcm_reg_id = 1,
1709                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1710                         .module_offs = WKUP_MOD,
1711                         .idlest_reg_id = 1,
1712                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1713                 },
1714         },
1715         .slaves         = omap2420_gpio3_slaves,
1716         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
1717         .class          = &omap242x_gpio_hwmod_class,
1718         .dev_attr       = &gpio_dev_attr,
1719         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1720 };
1721
1722 /* gpio4 */
1723 static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
1724         { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
1725 };
1726
1727 static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1728         &omap2420_l4_wkup__gpio4,
1729 };
1730
1731 static struct omap_hwmod omap2420_gpio4_hwmod = {
1732         .name           = "gpio4",
1733         .mpu_irqs       = omap242x_gpio4_irqs,
1734         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio4_irqs),
1735         .main_clk       = "gpios_fck",
1736         .prcm           = {
1737                 .omap2 = {
1738                         .prcm_reg_id = 1,
1739                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1740                         .module_offs = WKUP_MOD,
1741                         .idlest_reg_id = 1,
1742                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1743                 },
1744         },
1745         .slaves         = omap2420_gpio4_slaves,
1746         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
1747         .class          = &omap242x_gpio_hwmod_class,
1748         .dev_attr       = &gpio_dev_attr,
1749         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1750 };
1751
1752 /* system dma */
1753 static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
1754         .rev_offs       = 0x0000,
1755         .sysc_offs      = 0x002c,
1756         .syss_offs      = 0x0028,
1757         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1758                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1759                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1760         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1761         .sysc_fields    = &omap_hwmod_sysc_type1,
1762 };
1763
1764 static struct omap_hwmod_class omap2420_dma_hwmod_class = {
1765         .name = "dma",
1766         .sysc = &omap2420_dma_sysc,
1767 };
1768
1769 /* dma attributes */
1770 static struct omap_dma_dev_attr dma_dev_attr = {
1771         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1772                                                 IS_CSSA_32 | IS_CDSA_32,
1773         .lch_count = 32,
1774 };
1775
1776 static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
1777         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1778         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1779         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1780         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1781 };
1782
1783 static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
1784         {
1785                 .pa_start       = 0x48056000,
1786                 .pa_end         = 0x4a0560ff,
1787                 .flags          = ADDR_TYPE_RT
1788         },
1789 };
1790
1791 /* dma_system -> L3 */
1792 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
1793         .master         = &omap2420_dma_system_hwmod,
1794         .slave          = &omap2420_l3_main_hwmod,
1795         .clk            = "core_l3_ck",
1796         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1797 };
1798
1799 /* dma_system master ports */
1800 static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
1801         &omap2420_dma_system__l3,
1802 };
1803
1804 /* l4_core -> dma_system */
1805 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
1806         .master         = &omap2420_l4_core_hwmod,
1807         .slave          = &omap2420_dma_system_hwmod,
1808         .clk            = "sdma_ick",
1809         .addr           = omap2420_dma_system_addrs,
1810         .addr_cnt       = ARRAY_SIZE(omap2420_dma_system_addrs),
1811         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1812 };
1813
1814 /* dma_system slave ports */
1815 static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
1816         &omap2420_l4_core__dma_system,
1817 };
1818
1819 static struct omap_hwmod omap2420_dma_system_hwmod = {
1820         .name           = "dma",
1821         .class          = &omap2420_dma_hwmod_class,
1822         .mpu_irqs       = omap2420_dma_system_irqs,
1823         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_dma_system_irqs),
1824         .main_clk       = "core_l3_ck",
1825         .slaves         = omap2420_dma_system_slaves,
1826         .slaves_cnt     = ARRAY_SIZE(omap2420_dma_system_slaves),
1827         .masters        = omap2420_dma_system_masters,
1828         .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
1829         .dev_attr       = &dma_dev_attr,
1830         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1831         .flags          = HWMOD_NO_IDLEST,
1832 };
1833
1834 /*
1835  * 'mailbox' class
1836  * mailbox module allowing communication between the on-chip processors
1837  * using a queued mailbox-interrupt mechanism.
1838  */
1839
1840 static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
1841         .rev_offs       = 0x000,
1842         .sysc_offs      = 0x010,
1843         .syss_offs      = 0x014,
1844         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1845                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1846         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1847         .sysc_fields    = &omap_hwmod_sysc_type1,
1848 };
1849
1850 static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
1851         .name = "mailbox",
1852         .sysc = &omap2420_mailbox_sysc,
1853 };
1854
1855 /* mailbox */
1856 static struct omap_hwmod omap2420_mailbox_hwmod;
1857 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1858         { .name = "dsp", .irq = 26 },
1859         { .name = "iva", .irq = 34 },
1860 };
1861
1862 static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
1863         {
1864                 .pa_start       = 0x48094000,
1865                 .pa_end         = 0x480941ff,
1866                 .flags          = ADDR_TYPE_RT,
1867         },
1868 };
1869
1870 /* l4_core -> mailbox */
1871 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1872         .master         = &omap2420_l4_core_hwmod,
1873         .slave          = &omap2420_mailbox_hwmod,
1874         .addr           = omap2420_mailbox_addrs,
1875         .addr_cnt       = ARRAY_SIZE(omap2420_mailbox_addrs),
1876         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1877 };
1878
1879 /* mailbox slave ports */
1880 static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1881         &omap2420_l4_core__mailbox,
1882 };
1883
1884 static struct omap_hwmod omap2420_mailbox_hwmod = {
1885         .name           = "mailbox",
1886         .class          = &omap2420_mailbox_hwmod_class,
1887         .mpu_irqs       = omap2420_mailbox_irqs,
1888         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mailbox_irqs),
1889         .main_clk       = "mailboxes_ick",
1890         .prcm           = {
1891                 .omap2 = {
1892                         .prcm_reg_id = 1,
1893                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1894                         .module_offs = CORE_MOD,
1895                         .idlest_reg_id = 1,
1896                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1897                 },
1898         },
1899         .slaves         = omap2420_mailbox_slaves,
1900         .slaves_cnt     = ARRAY_SIZE(omap2420_mailbox_slaves),
1901         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1902 };
1903
1904 /*
1905  * 'mcspi' class
1906  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1907  * bus
1908  */
1909
1910 static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
1911         .rev_offs       = 0x0000,
1912         .sysc_offs      = 0x0010,
1913         .syss_offs      = 0x0014,
1914         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1915                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1916                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1917         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1918         .sysc_fields    = &omap_hwmod_sysc_type1,
1919 };
1920
1921 static struct omap_hwmod_class omap2420_mcspi_class = {
1922         .name = "mcspi",
1923         .sysc = &omap2420_mcspi_sysc,
1924         .rev = OMAP2_MCSPI_REV,
1925 };
1926
1927 /* mcspi1 */
1928 static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
1929         { .irq = 65 },
1930 };
1931
1932 static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
1933         { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
1934         { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
1935         { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
1936         { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
1937         { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
1938         { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
1939         { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
1940         { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
1941 };
1942
1943 static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
1944         &omap2420_l4_core__mcspi1,
1945 };
1946
1947 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1948         .num_chipselect = 4,
1949 };
1950
1951 static struct omap_hwmod omap2420_mcspi1_hwmod = {
1952         .name           = "mcspi1_hwmod",
1953         .mpu_irqs       = omap2420_mcspi1_mpu_irqs,
1954         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs),
1955         .sdma_reqs      = omap2420_mcspi1_sdma_reqs,
1956         .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
1957         .main_clk       = "mcspi1_fck",
1958         .prcm           = {
1959                 .omap2 = {
1960                         .module_offs = CORE_MOD,
1961                         .prcm_reg_id = 1,
1962                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1963                         .idlest_reg_id = 1,
1964                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1965                 },
1966         },
1967         .slaves         = omap2420_mcspi1_slaves,
1968         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi1_slaves),
1969         .class          = &omap2420_mcspi_class,
1970         .dev_attr       = &omap_mcspi1_dev_attr,
1971         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1972 };
1973
1974 /* mcspi2 */
1975 static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
1976         { .irq = 66 },
1977 };
1978
1979 static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
1980         { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
1981         { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
1982         { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
1983         { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
1984 };
1985
1986 static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
1987         &omap2420_l4_core__mcspi2,
1988 };
1989
1990 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1991         .num_chipselect = 2,
1992 };
1993
1994 static struct omap_hwmod omap2420_mcspi2_hwmod = {
1995         .name           = "mcspi2_hwmod",
1996         .mpu_irqs       = omap2420_mcspi2_mpu_irqs,
1997         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs),
1998         .sdma_reqs      = omap2420_mcspi2_sdma_reqs,
1999         .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
2000         .main_clk       = "mcspi2_fck",
2001         .prcm           = {
2002                 .omap2 = {
2003                         .module_offs = CORE_MOD,
2004                         .prcm_reg_id = 1,
2005                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
2006                         .idlest_reg_id = 1,
2007                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
2008                 },
2009         },
2010         .slaves         = omap2420_mcspi2_slaves,
2011         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi2_slaves),
2012         .class          = &omap2420_mcspi_class,
2013         .dev_attr       = &omap_mcspi2_dev_attr,
2014         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
2015 };
2016
2017 /*
2018  * 'mcbsp' class
2019  * multi channel buffered serial port controller
2020  */
2021
2022 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
2023         .name = "mcbsp",
2024 };
2025
2026 /* mcbsp1 */
2027 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
2028         { .name = "tx", .irq = 59 },
2029         { .name = "rx", .irq = 60 },
2030 };
2031
2032 static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
2033         { .name = "rx", .dma_req = 32 },
2034         { .name = "tx", .dma_req = 31 },
2035 };
2036
2037 static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
2038         {
2039                 .name           = "mpu",
2040                 .pa_start       = 0x48074000,
2041                 .pa_end         = 0x480740ff,
2042                 .flags          = ADDR_TYPE_RT
2043         },
2044 };
2045
2046 /* l4_core -> mcbsp1 */
2047 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
2048         .master         = &omap2420_l4_core_hwmod,
2049         .slave          = &omap2420_mcbsp1_hwmod,
2050         .clk            = "mcbsp1_ick",
2051         .addr           = omap2420_mcbsp1_addrs,
2052         .addr_cnt       = ARRAY_SIZE(omap2420_mcbsp1_addrs),
2053         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2054 };
2055
2056 /* mcbsp1 slave ports */
2057 static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
2058         &omap2420_l4_core__mcbsp1,
2059 };
2060
2061 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
2062         .name           = "mcbsp1",
2063         .class          = &omap2420_mcbsp_hwmod_class,
2064         .mpu_irqs       = omap2420_mcbsp1_irqs,
2065         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcbsp1_irqs),
2066         .sdma_reqs      = omap2420_mcbsp1_sdma_chs,
2067         .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
2068         .main_clk       = "mcbsp1_fck",
2069         .prcm           = {
2070                 .omap2 = {
2071                         .prcm_reg_id = 1,
2072                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
2073                         .module_offs = CORE_MOD,
2074                         .idlest_reg_id = 1,
2075                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
2076                 },
2077         },
2078         .slaves         = omap2420_mcbsp1_slaves,
2079         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp1_slaves),
2080         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
2081 };
2082
2083 /* mcbsp2 */
2084 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
2085         { .name = "tx", .irq = 62 },
2086         { .name = "rx", .irq = 63 },
2087 };
2088
2089 static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
2090         { .name = "rx", .dma_req = 34 },
2091         { .name = "tx", .dma_req = 33 },
2092 };
2093
2094 static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
2095         {
2096                 .name           = "mpu",
2097                 .pa_start       = 0x48076000,
2098                 .pa_end         = 0x480760ff,
2099                 .flags          = ADDR_TYPE_RT
2100         },
2101 };
2102
2103 /* l4_core -> mcbsp2 */
2104 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
2105         .master         = &omap2420_l4_core_hwmod,
2106         .slave          = &omap2420_mcbsp2_hwmod,
2107         .clk            = "mcbsp2_ick",
2108         .addr           = omap2420_mcbsp2_addrs,
2109         .addr_cnt       = ARRAY_SIZE(omap2420_mcbsp2_addrs),
2110         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2111 };
2112
2113 /* mcbsp2 slave ports */
2114 static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
2115         &omap2420_l4_core__mcbsp2,
2116 };
2117
2118 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
2119         .name           = "mcbsp2",
2120         .class          = &omap2420_mcbsp_hwmod_class,
2121         .mpu_irqs       = omap2420_mcbsp2_irqs,
2122         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcbsp2_irqs),
2123         .sdma_reqs      = omap2420_mcbsp2_sdma_chs,
2124         .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
2125         .main_clk       = "mcbsp2_fck",
2126         .prcm           = {
2127                 .omap2 = {
2128                         .prcm_reg_id = 1,
2129                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
2130                         .module_offs = CORE_MOD,
2131                         .idlest_reg_id = 1,
2132                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
2133                 },
2134         },
2135         .slaves         = omap2420_mcbsp2_slaves,
2136         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp2_slaves),
2137         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
2138 };
2139
2140 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
2141         &omap2420_l3_main_hwmod,
2142         &omap2420_l4_core_hwmod,
2143         &omap2420_l4_wkup_hwmod,
2144         &omap2420_mpu_hwmod,
2145         &omap2420_iva_hwmod,
2146
2147         &omap2420_timer1_hwmod,
2148         &omap2420_timer2_hwmod,
2149         &omap2420_timer3_hwmod,
2150         &omap2420_timer4_hwmod,
2151         &omap2420_timer5_hwmod,
2152         &omap2420_timer6_hwmod,
2153         &omap2420_timer7_hwmod,
2154         &omap2420_timer8_hwmod,
2155         &omap2420_timer9_hwmod,
2156         &omap2420_timer10_hwmod,
2157         &omap2420_timer11_hwmod,
2158         &omap2420_timer12_hwmod,
2159
2160         &omap2420_wd_timer2_hwmod,
2161         &omap2420_uart1_hwmod,
2162         &omap2420_uart2_hwmod,
2163         &omap2420_uart3_hwmod,
2164         /* dss class */
2165         &omap2420_dss_core_hwmod,
2166         &omap2420_dss_dispc_hwmod,
2167         &omap2420_dss_rfbi_hwmod,
2168         &omap2420_dss_venc_hwmod,
2169         /* i2c class */
2170         &omap2420_i2c1_hwmod,
2171         &omap2420_i2c2_hwmod,
2172
2173         /* gpio class */
2174         &omap2420_gpio1_hwmod,
2175         &omap2420_gpio2_hwmod,
2176         &omap2420_gpio3_hwmod,
2177         &omap2420_gpio4_hwmod,
2178
2179         /* dma_system class*/
2180         &omap2420_dma_system_hwmod,
2181
2182         /* mailbox class */
2183         &omap2420_mailbox_hwmod,
2184
2185         /* mcbsp class */
2186         &omap2420_mcbsp1_hwmod,
2187         &omap2420_mcbsp2_hwmod,
2188
2189         /* mcspi class */
2190         &omap2420_mcspi1_hwmod,
2191         &omap2420_mcspi2_hwmod,
2192         NULL,
2193 };
2194
2195 int __init omap2420_hwmod_init(void)
2196 {
2197         return omap_hwmod_register(omap2420_hwmods);
2198 }