arch/arm/mach-omap2/mcbsp.c

   1 /*
   2  * linux/arch/arm/mach-omap2/mcbsp.c
   3  *
   4  * Copyright (C) 2008 Instituto Nokia de Tecnologia
   5  * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Multichannel mode not supported.
  12  */
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/slab.h>
  20
  21 #include <mach/irqs.h>
  22 #include <plat/dma.h>
  23 #include <plat/cpu.h>
  24 #include <plat/mcbsp.h>
  25
  26
  27 #ifdef CONFIG_ARCH_OMAP2420
  28 static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
  29         {
  30                 .phys_base      = OMAP24XX_MCBSP1_BASE,
  31                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
  32                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
  33                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
  34                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
  35         },
  36         {
  37                 .phys_base      = OMAP24XX_MCBSP2_BASE,
  38                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
  39                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
  40                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
  41                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
  42         },
  43 };
  44 #define OMAP2420_MCBSP_PDATA_SZ         ARRAY_SIZE(omap2420_mcbsp_pdata)
  45 #define OMAP2420_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
  46 #else
  47 #define omap2420_mcbsp_pdata            NULL
  48 #define OMAP2420_MCBSP_PDATA_SZ         0
  49 #define OMAP2420_MCBSP_REG_NUM          0
  50 #endif
  51
  52 #ifdef CONFIG_ARCH_OMAP2430
  53 static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
  54         {
  55                 .phys_base      = OMAP24XX_MCBSP1_BASE,
  56                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
  57                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
  58                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
  59                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
  60         },
  61         {
  62                 .phys_base      = OMAP24XX_MCBSP2_BASE,
  63                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
  64                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
  65                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
  66                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
  67         },
  68         {
  69                 .phys_base      = OMAP2430_MCBSP3_BASE,
  70                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP3_RX,
  71                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP3_TX,
  72                 .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
  73                 .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
  74         },
  75         {
  76                 .phys_base      = OMAP2430_MCBSP4_BASE,
  77                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP4_RX,
  78                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP4_TX,
  79                 .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
  80                 .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
  81         },
  82         {
  83                 .phys_base      = OMAP2430_MCBSP5_BASE,
  84                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP5_RX,
  85                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP5_TX,
  86                 .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
  87                 .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
  88         },
  89 };
  90 #define OMAP2430_MCBSP_PDATA_SZ         ARRAY_SIZE(omap2430_mcbsp_pdata)
  91 #define OMAP2430_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
  92 #else
  93 #define omap2430_mcbsp_pdata            NULL
  94 #define OMAP2430_MCBSP_PDATA_SZ         0
  95 #define OMAP2430_MCBSP_REG_NUM          0
  96 #endif
  97
  98 #ifdef CONFIG_ARCH_OMAP3
  99 static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
 100         {
 101                 .phys_base      = OMAP34XX_MCBSP1_BASE,
 102                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
 103                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
 104                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
 105                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
 106                 .buffer_size    = 0x80, /* The FIFO has 128 locations */
 107         },
 108         {
 109                 .phys_base      = OMAP34XX_MCBSP2_BASE,
 110                 .phys_base_st   = OMAP34XX_MCBSP2_ST_BASE,
 111                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
 112                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
 113                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
 114                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
 115                 .buffer_size    = 0x500, /* The FIFO has 1024 + 256 locations */
 116         },
 117         {
 118                 .phys_base      = OMAP34XX_MCBSP3_BASE,
 119                 .phys_base_st   = OMAP34XX_MCBSP3_ST_BASE,
 120                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP3_RX,
 121                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP3_TX,
 122                 .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
 123                 .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
 124                 .buffer_size    = 0x80, /* The FIFO has 128 locations */
 125         },
 126         {
 127                 .phys_base      = OMAP34XX_MCBSP4_BASE,
 128                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP4_RX,
 129                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP4_TX,
 130                 .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
 131                 .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
 132                 .buffer_size    = 0x80, /* The FIFO has 128 locations */
 133         },
 134         {
 135                 .phys_base      = OMAP34XX_MCBSP5_BASE,
 136                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP5_RX,
 137                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP5_TX,
 138                 .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
 139                 .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
 140                 .buffer_size    = 0x80, /* The FIFO has 128 locations */
 141         },
 142 };
 143 #define OMAP34XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap34xx_mcbsp_pdata)
 144 #define OMAP34XX_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
 145 #else
 146 #define omap34xx_mcbsp_pdata            NULL
 147 #define OMAP34XX_MCBSP_PDATA_SZ         0
 148 #define OMAP34XX_MCBSP_REG_NUM          0
 149 #endif
 150
 151 static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
 152         {
 153                 .phys_base      = OMAP44XX_MCBSP1_BASE,
 154                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP1_RX,
 155                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP1_TX,
 156                 .tx_irq         = OMAP44XX_IRQ_MCBSP1,
 157         },
 158         {
 159                 .phys_base      = OMAP44XX_MCBSP2_BASE,
 160                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP2_RX,
 161                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP2_TX,
 162                 .tx_irq         = OMAP44XX_IRQ_MCBSP2,
 163         },
 164         {
 165                 .phys_base      = OMAP44XX_MCBSP3_BASE,
 166                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP3_RX,
 167                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP3_TX,
 168                 .tx_irq         = OMAP44XX_IRQ_MCBSP3,
 169         },
 170         {
 171                 .phys_base      = OMAP44XX_MCBSP4_BASE,
 172                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP4_RX,
 173                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP4_TX,
 174                 .tx_irq         = OMAP44XX_IRQ_MCBSP4,
 175         },
 176 };
 177 #define OMAP44XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap44xx_mcbsp_pdata)
 178 #define OMAP44XX_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
 179
 180 static int __init omap2_mcbsp_init(void)
 181 {
 182         if (cpu_is_omap2420()) {
 183                 omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
 184                 omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16);
 185         } else if (cpu_is_omap2430()) {
 186                 omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
 187                 omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32);
 188         } else if (cpu_is_omap34xx()) {
 189                 omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
 190                 omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
 191         } else if (cpu_is_omap44xx()) {
 192                 omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
 193                 omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
 194         }
 195
 196         mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
 197                                                                 GFP_KERNEL);
 198         if (!mcbsp_ptr)
 199                 return -ENOMEM;
 200
 201         if (cpu_is_omap2420())
 202                 omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
 203                                                 OMAP2420_MCBSP_PDATA_SZ);
 204         if (cpu_is_omap2430())
 205                 omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
 206                                                 OMAP2430_MCBSP_PDATA_SZ);
 207         if (cpu_is_omap34xx())
 208                 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
 209                                                 OMAP34XX_MCBSP_PDATA_SZ);
 210         if (cpu_is_omap44xx())
 211                 omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
 212                                                 OMAP44XX_MCBSP_PDATA_SZ);
 213
 214         return omap_mcbsp_init();
 215 }
 216 arch_initcall(omap2_mcbsp_init);