arch/arm/mach-omap2/io.c

   1 /*
   2  * linux/arch/arm/mach-omap2/io.c
   3  *
   4  * OMAP2 I/O mapping code
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Copyright (C) 2007-2009 Texas Instruments
   8  *
   9  * Author:
  10  *      Juha Yrjola <juha.yrjola@nokia.com>
  11  *      Syed Khasim <x0khasim@ti.com>
  12  *
  13  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23 #include <linux/clk.h>
  24 #include <linux/omapfb.h>
  25
  26 #include <asm/tlb.h>
  27
  28 #include <asm/mach/map.h>
  29
  30 #include <plat/sram.h>
  31 #include <plat/sdrc.h>
  32 #include <plat/serial.h>
  33
  34 #include "clock2xxx.h"
  35 #include "clock3xxx.h"
  36 #include "clock44xx.h"
  37 #include "io.h"
  38
  39 #include <plat/omap-pm.h>
  40 #include "voltage.h"
  41 #include "powerdomain.h"
  42
  43 #include "clockdomain.h"
  44 #include <plat/omap_hwmod.h>
  45 #include <plat/multi.h>
  46
  47 /*
  48  * The machine specific code may provide the extra mapping besides the
  49  * default mapping provided here.
  50  */
  51
  52 #ifdef CONFIG_ARCH_OMAP2
  53 static struct map_desc omap24xx_io_desc[] __initdata = {
  54         {
  55                 .virtual        = L3_24XX_VIRT,
  56                 .pfn            = __phys_to_pfn(L3_24XX_PHYS),
  57                 .length         = L3_24XX_SIZE,
  58                 .type           = MT_DEVICE
  59         },
  60         {
  61                 .virtual        = L4_24XX_VIRT,
  62                 .pfn            = __phys_to_pfn(L4_24XX_PHYS),
  63                 .length         = L4_24XX_SIZE,
  64                 .type           = MT_DEVICE
  65         },
  66 };
  67
  68 #ifdef CONFIG_SOC_OMAP2420
  69 static struct map_desc omap242x_io_desc[] __initdata = {
  70         {
  71                 .virtual        = DSP_MEM_2420_VIRT,
  72                 .pfn            = __phys_to_pfn(DSP_MEM_2420_PHYS),
  73                 .length         = DSP_MEM_2420_SIZE,
  74                 .type           = MT_DEVICE
  75         },
  76         {
  77                 .virtual        = DSP_IPI_2420_VIRT,
  78                 .pfn            = __phys_to_pfn(DSP_IPI_2420_PHYS),
  79                 .length         = DSP_IPI_2420_SIZE,
  80                 .type           = MT_DEVICE
  81         },
  82         {
  83                 .virtual        = DSP_MMU_2420_VIRT,
  84                 .pfn            = __phys_to_pfn(DSP_MMU_2420_PHYS),
  85                 .length         = DSP_MMU_2420_SIZE,
  86                 .type           = MT_DEVICE
  87         },
  88 };
  89
  90 #endif
  91
  92 #ifdef CONFIG_SOC_OMAP2430
  93 static struct map_desc omap243x_io_desc[] __initdata = {
  94         {
  95                 .virtual        = L4_WK_243X_VIRT,
  96                 .pfn            = __phys_to_pfn(L4_WK_243X_PHYS),
  97                 .length         = L4_WK_243X_SIZE,
  98                 .type           = MT_DEVICE
  99         },
 100         {
 101                 .virtual        = OMAP243X_GPMC_VIRT,
 102                 .pfn            = __phys_to_pfn(OMAP243X_GPMC_PHYS),
 103                 .length         = OMAP243X_GPMC_SIZE,
 104                 .type           = MT_DEVICE
 105         },
 106         {
 107                 .virtual        = OMAP243X_SDRC_VIRT,
 108                 .pfn            = __phys_to_pfn(OMAP243X_SDRC_PHYS),
 109                 .length         = OMAP243X_SDRC_SIZE,
 110                 .type           = MT_DEVICE
 111         },
 112         {
 113                 .virtual        = OMAP243X_SMS_VIRT,
 114                 .pfn            = __phys_to_pfn(OMAP243X_SMS_PHYS),
 115                 .length         = OMAP243X_SMS_SIZE,
 116                 .type           = MT_DEVICE
 117         },
 118 };
 119 #endif
 120 #endif
 121
 122 #ifdef  CONFIG_ARCH_OMAP3
 123 static struct map_desc omap34xx_io_desc[] __initdata = {
 124         {
 125                 .virtual        = L3_34XX_VIRT,
 126                 .pfn            = __phys_to_pfn(L3_34XX_PHYS),
 127                 .length         = L3_34XX_SIZE,
 128                 .type           = MT_DEVICE
 129         },
 130         {
 131                 .virtual        = L4_34XX_VIRT,
 132                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 133                 .length         = L4_34XX_SIZE,
 134                 .type           = MT_DEVICE
 135         },
 136         {
 137                 .virtual        = OMAP34XX_GPMC_VIRT,
 138                 .pfn            = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
 139                 .length         = OMAP34XX_GPMC_SIZE,
 140                 .type           = MT_DEVICE
 141         },
 142         {
 143                 .virtual        = OMAP343X_SMS_VIRT,
 144                 .pfn            = __phys_to_pfn(OMAP343X_SMS_PHYS),
 145                 .length         = OMAP343X_SMS_SIZE,
 146                 .type           = MT_DEVICE
 147         },
 148         {
 149                 .virtual        = OMAP343X_SDRC_VIRT,
 150                 .pfn            = __phys_to_pfn(OMAP343X_SDRC_PHYS),
 151                 .length         = OMAP343X_SDRC_SIZE,
 152                 .type           = MT_DEVICE
 153         },
 154         {
 155                 .virtual        = L4_PER_34XX_VIRT,
 156                 .pfn            = __phys_to_pfn(L4_PER_34XX_PHYS),
 157                 .length         = L4_PER_34XX_SIZE,
 158                 .type           = MT_DEVICE
 159         },
 160         {
 161                 .virtual        = L4_EMU_34XX_VIRT,
 162                 .pfn            = __phys_to_pfn(L4_EMU_34XX_PHYS),
 163                 .length         = L4_EMU_34XX_SIZE,
 164                 .type           = MT_DEVICE
 165         },
 166 #if defined(CONFIG_DEBUG_LL) &&                                                 \
 167         (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
 168         {
 169                 .virtual        = ZOOM_UART_VIRT,
 170                 .pfn            = __phys_to_pfn(ZOOM_UART_BASE),
 171                 .length         = SZ_1M,
 172                 .type           = MT_DEVICE
 173         },
 174 #endif
 175 };
 176 #endif
 177
 178 #ifdef CONFIG_SOC_OMAPTI816X
 179 static struct map_desc omapti816x_io_desc[] __initdata = {
 180         {
 181                 .virtual        = L4_34XX_VIRT,
 182                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 183                 .length         = L4_34XX_SIZE,
 184                 .type           = MT_DEVICE
 185         },
 186 };
 187 #endif
 188
 189 #ifdef  CONFIG_ARCH_OMAP4
 190 static struct map_desc omap44xx_io_desc[] __initdata = {
 191         {
 192                 .virtual        = L3_44XX_VIRT,
 193                 .pfn            = __phys_to_pfn(L3_44XX_PHYS),
 194                 .length         = L3_44XX_SIZE,
 195                 .type           = MT_DEVICE,
 196         },
 197         {
 198                 .virtual        = L4_44XX_VIRT,
 199                 .pfn            = __phys_to_pfn(L4_44XX_PHYS),
 200                 .length         = L4_44XX_SIZE,
 201                 .type           = MT_DEVICE,
 202         },
 203         {
 204                 .virtual        = OMAP44XX_GPMC_VIRT,
 205                 .pfn            = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
 206                 .length         = OMAP44XX_GPMC_SIZE,
 207                 .type           = MT_DEVICE,
 208         },
 209         {
 210                 .virtual        = OMAP44XX_EMIF1_VIRT,
 211                 .pfn            = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
 212                 .length         = OMAP44XX_EMIF1_SIZE,
 213                 .type           = MT_DEVICE,
 214         },
 215         {
 216                 .virtual        = OMAP44XX_EMIF2_VIRT,
 217                 .pfn            = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
 218                 .length         = OMAP44XX_EMIF2_SIZE,
 219                 .type           = MT_DEVICE,
 220         },
 221         {
 222                 .virtual        = OMAP44XX_DMM_VIRT,
 223                 .pfn            = __phys_to_pfn(OMAP44XX_DMM_PHYS),
 224                 .length         = OMAP44XX_DMM_SIZE,
 225                 .type           = MT_DEVICE,
 226         },
 227         {
 228                 .virtual        = L4_PER_44XX_VIRT,
 229                 .pfn            = __phys_to_pfn(L4_PER_44XX_PHYS),
 230                 .length         = L4_PER_44XX_SIZE,
 231                 .type           = MT_DEVICE,
 232         },
 233         {
 234                 .virtual        = L4_EMU_44XX_VIRT,
 235                 .pfn            = __phys_to_pfn(L4_EMU_44XX_PHYS),
 236                 .length         = L4_EMU_44XX_SIZE,
 237                 .type           = MT_DEVICE,
 238         },
 239 };
 240 #endif
 241
 242 static void __init _omap2_map_common_io(void)
 243 {
 244         /* Normally devicemaps_init() would flush caches and tlb after
 245          * mdesc->map_io(), but we must also do it here because of the CPU
 246          * revision check below.
 247          */
 248         local_flush_tlb_all();
 249         flush_cache_all();
 250
 251         omap2_check_revision();
 252         omap_sram_init();
 253         omap_init_consistent_dma_size();
 254 }
 255
 256 #ifdef CONFIG_SOC_OMAP2420
 257 void __init omap242x_map_common_io(void)
 258 {
 259         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
 260         iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
 261         _omap2_map_common_io();
 262 }
 263 #endif
 264
 265 #ifdef CONFIG_SOC_OMAP2430
 266 void __init omap243x_map_common_io(void)
 267 {
 268         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
 269         iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
 270         _omap2_map_common_io();
 271 }
 272 #endif
 273
 274 #ifdef CONFIG_ARCH_OMAP3
 275 void __init omap34xx_map_common_io(void)
 276 {
 277         iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
 278         _omap2_map_common_io();
 279 }
 280 #endif
 281
 282 #ifdef CONFIG_SOC_OMAPTI816X
 283 void __init omapti816x_map_common_io(void)
 284 {
 285         iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
 286         _omap2_map_common_io();
 287 }
 288 #endif
 289
 290 #ifdef CONFIG_ARCH_OMAP4
 291 void __init omap44xx_map_common_io(void)
 292 {
 293         iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
 294         _omap2_map_common_io();
 295 }
 296 #endif
 297
 298 /*
 299  * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
 300  *
 301  * Sets the CORE DPLL3 M2 divider to the same value that it's at
 302  * currently.  This has the effect of setting the SDRC SDRAM AC timing
 303  * registers to the values currently defined by the kernel.  Currently
 304  * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
 305  * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
 306  * or passes along the return value of clk_set_rate().
 307  */
 308 static int __init _omap2_init_reprogram_sdrc(void)
 309 {
 310         struct clk *dpll3_m2_ck;
 311         int v = -EINVAL;
 312         long rate;
 313
 314         if (!cpu_is_omap34xx())
 315                 return 0;
 316
 317         dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
 318         if (IS_ERR(dpll3_m2_ck))
 319                 return -EINVAL;
 320
 321         rate = clk_get_rate(dpll3_m2_ck);
 322         pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
 323         v = clk_set_rate(dpll3_m2_ck, rate);
 324         if (v)
 325                 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
 326
 327         clk_put(dpll3_m2_ck);
 328
 329         return v;
 330 }
 331
 332 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
 333 {
 334         return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
 335 }
 336
 337 /* See irq.c, omap4-common.c and entry-macro.S */
 338 void __iomem *omap_irq_base;
 339
 340 void __init omap2_init_common_infrastructure(void)
 341 {
 342         u8 postsetup_state;
 343
 344         if (cpu_is_omap242x()) {
 345                 omap2xxx_voltagedomains_init();
 346                 omap242x_powerdomains_init();
 347                 omap242x_clockdomains_init();
 348                 omap2420_hwmod_init();
 349         } else if (cpu_is_omap243x()) {
 350                 omap2xxx_voltagedomains_init();
 351                 omap243x_powerdomains_init();
 352                 omap243x_clockdomains_init();
 353                 omap2430_hwmod_init();
 354         } else if (cpu_is_omap34xx()) {
 355                 omap3xxx_voltagedomains_init();
 356                 omap3xxx_powerdomains_init();
 357                 omap3xxx_clockdomains_init();
 358                 omap3xxx_hwmod_init();
 359         } else if (cpu_is_omap44xx()) {
 360                 omap44xx_voltagedomains_init();
 361                 omap44xx_powerdomains_init();
 362                 omap44xx_clockdomains_init();
 363                 omap44xx_hwmod_init();
 364         } else {
 365                 pr_err("Could not init hwmod data - unknown SoC\n");
 366         }
 367
 368         /* Set the default postsetup state for all hwmods */
 369 #ifdef CONFIG_PM_RUNTIME
 370         postsetup_state = _HWMOD_STATE_IDLE;
 371 #else
 372         postsetup_state = _HWMOD_STATE_ENABLED;
 373 #endif
 374         omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
 375
 376         /*
 377          * Set the default postsetup state for unusual modules (like
 378          * MPU WDT).
 379          *
 380          * The postsetup_state is not actually used until
 381          * omap_hwmod_late_init(), so boards that desire full watchdog
 382          * coverage of kernel initialization can reprogram the
 383          * postsetup_state between the calls to
 384          * omap2_init_common_infra() and omap_sdrc_init().
 385          *
 386          * XXX ideally we could detect whether the MPU WDT was currently
 387          * enabled here and make this conditional
 388          */
 389         postsetup_state = _HWMOD_STATE_DISABLED;
 390         omap_hwmod_for_each_by_class("wd_timer",
 391                                      _set_hwmod_postsetup_state,
 392                                      &postsetup_state);
 393
 394         omap_pm_if_early_init();
 395
 396         if (cpu_is_omap2420())
 397                 omap2420_clk_init();
 398         else if (cpu_is_omap2430())
 399                 omap2430_clk_init();
 400         else if (cpu_is_omap34xx())
 401                 omap3xxx_clk_init();
 402         else if (cpu_is_omap44xx())
 403                 omap4xxx_clk_init();
 404         else
 405                 pr_err("Could not init clock framework - unknown SoC\n");
 406 }
 407
 408 void __init omap2420_init_early(void)
 409 {
 410         omap2_init_common_infrastructure();
 411 }
 412
 413 void __init omap2430_init_early(void)
 414 {
 415         omap2_init_common_infrastructure();
 416 }
 417
 418 void __init omap3430_init_early(void)
 419 {
 420         omap2_init_common_infrastructure();
 421 }
 422
 423 void __init omap35xx_init_early(void)
 424 {
 425         omap2_init_common_infrastructure();
 426 }
 427
 428 void __init omap3630_init_early(void)
 429 {
 430         omap2_init_common_infrastructure();
 431 }
 432
 433 void __init am35xx_init_early(void)
 434 {
 435         omap2_init_common_infrastructure();
 436 }
 437
 438 void __init ti816x_init_early(void)
 439 {
 440         omap2_init_common_infrastructure();
 441 }
 442
 443 void __init omap4430_init_early(void)
 444 {
 445         omap2_init_common_infrastructure();
 446 }
 447
 448 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 449                                       struct omap_sdrc_params *sdrc_cs1)
 450 {
 451         if (cpu_is_omap24xx() || omap3_has_sdrc()) {
 452                 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
 453                 _omap2_init_reprogram_sdrc();
 454         }
 455
 456 }
 457
 458 /*
 459  * NOTE: Please use ioremap + __raw_read/write where possible instead of these
 460  */
 461
 462 u8 omap_readb(u32 pa)
 463 {
 464         return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
 465 }
 466 EXPORT_SYMBOL(omap_readb);
 467
 468 u16 omap_readw(u32 pa)
 469 {
 470         return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
 471 }
 472 EXPORT_SYMBOL(omap_readw);
 473
 474 u32 omap_readl(u32 pa)
 475 {
 476         return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
 477 }
 478 EXPORT_SYMBOL(omap_readl);
 479
 480 void omap_writeb(u8 v, u32 pa)
 481 {
 482         __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
 483 }
 484 EXPORT_SYMBOL(omap_writeb);
 485
 486 void omap_writew(u16 v, u32 pa)
 487 {
 488         __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
 489 }
 490 EXPORT_SYMBOL(omap_writew);
 491
 492 void omap_writel(u32 v, u32 pa)
 493 {
 494         __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
 495 }
 496 EXPORT_SYMBOL(omap_writel);