arch/arm/mach-omap2/hsmmc.c

   1 /*
   2  * linux/arch/arm/mach-omap2/hsmmc.c
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Author: Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/slab.h>
  14 #include <linux/string.h>
  15 #include <linux/delay.h>
  16 #include <mach/hardware.h>
  17 #include <plat/mmc.h>
  18 #include <plat/omap-pm.h>
  19 #include <plat/mux.h>
  20
  21 #include "mux.h"
  22 #include "hsmmc.h"
  23 #include "control.h"
  24
  25 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  26
  27 static u16 control_pbias_offset;
  28 static u16 control_devconf1_offset;
  29 static u16 control_mmc1;
  30
  31 #define HSMMC_NAME_LEN  9
  32
  33 static struct hsmmc_controller {
  34         char                            name[HSMMC_NAME_LEN + 1];
  35 } hsmmc[OMAP34XX_NR_MMC];
  36
  37 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  38
  39 static int hsmmc_get_context_loss(struct device *dev)
  40 {
  41         return omap_pm_get_dev_context_loss_count(dev);
  42 }
  43
  44 #else
  45 #define hsmmc_get_context_loss NULL
  46 #endif
  47
  48 static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
  49                                   int power_on, int vdd)
  50 {
  51         u32 reg, prog_io;
  52         struct omap_mmc_platform_data *mmc = dev->platform_data;
  53
  54         if (mmc->slots[0].remux)
  55                 mmc->slots[0].remux(dev, slot, power_on);
  56
  57         /*
  58          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
  59          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
  60          * 1.8V and 3.0V modes, controlled by the PBIAS register.
  61          *
  62          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
  63          * is most naturally TWL VSIM; those pins also use PBIAS.
  64          *
  65          * FIXME handle VMMC1A as needed ...
  66          */
  67         if (power_on) {
  68                 if (cpu_is_omap2430()) {
  69                         reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
  70                         if ((1 << vdd) >= MMC_VDD_30_31)
  71                                 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
  72                         else
  73                                 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
  74                         omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
  75                 }
  76
  77                 if (mmc->slots[0].internal_clock) {
  78                         reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  79                         reg |= OMAP2_MMCSDIO1ADPCLKISEL;
  80                         omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
  81                 }
  82
  83                 reg = omap_ctrl_readl(control_pbias_offset);
  84                 if (cpu_is_omap3630()) {
  85                         /* Set MMC I/O to 52Mhz */
  86                         prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
  87                         prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
  88                         omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
  89                 } else {
  90                         reg |= OMAP2_PBIASSPEEDCTRL0;
  91                 }
  92                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  93                 omap_ctrl_writel(reg, control_pbias_offset);
  94         } else {
  95                 reg = omap_ctrl_readl(control_pbias_offset);
  96                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  97                 omap_ctrl_writel(reg, control_pbias_offset);
  98         }
  99 }
 100
 101 static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
 102                                  int power_on, int vdd)
 103 {
 104         u32 reg;
 105
 106         /* 100ms delay required for PBIAS configuration */
 107         msleep(100);
 108
 109         if (power_on) {
 110                 reg = omap_ctrl_readl(control_pbias_offset);
 111                 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
 112                 if ((1 << vdd) <= MMC_VDD_165_195)
 113                         reg &= ~OMAP2_PBIASLITEVMODE0;
 114                 else
 115                         reg |= OMAP2_PBIASLITEVMODE0;
 116                 omap_ctrl_writel(reg, control_pbias_offset);
 117         } else {
 118                 reg = omap_ctrl_readl(control_pbias_offset);
 119                 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
 120                         OMAP2_PBIASLITEVMODE0);
 121                 omap_ctrl_writel(reg, control_pbias_offset);
 122         }
 123 }
 124
 125 static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
 126                                   int power_on, int vdd)
 127 {
 128         u32 reg;
 129
 130         /*
 131          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
 132          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
 133          * 1.8V and 3.0V modes, controlled by the PBIAS register.
 134          *
 135          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
 136          * is most naturally TWL VSIM; those pins also use PBIAS.
 137          *
 138          * FIXME handle VMMC1A as needed ...
 139          */
 140         reg = omap4_ctrl_pad_readl(control_pbias_offset);
 141         reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 142                 OMAP4_MMC1_PWRDNZ_MASK |
 143                 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 144         omap4_ctrl_pad_writel(reg, control_pbias_offset);
 145 }
 146
 147 static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
 148                                  int power_on, int vdd)
 149 {
 150         u32 reg;
 151
 152         if (power_on) {
 153                 reg = omap4_ctrl_pad_readl(control_pbias_offset);
 154                 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
 155                 if ((1 << vdd) <= MMC_VDD_165_195)
 156                         reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
 157                 else
 158                         reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
 159                 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 160                         OMAP4_MMC1_PWRDNZ_MASK |
 161                         OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 162                 omap4_ctrl_pad_writel(reg, control_pbias_offset);
 163                 /* 4 microsec delay for comparator to generate an error*/
 164                 udelay(4);
 165                 reg = omap4_ctrl_pad_readl(control_pbias_offset);
 166                 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
 167                         pr_err("Pbias Voltage is not same as LDO\n");
 168                         /* Caution : On VMODE_ERROR Power Down MMC IO */
 169                         reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
 170                                 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 171                         omap4_ctrl_pad_writel(reg, control_pbias_offset);
 172                 }
 173         } else {
 174                 reg = omap4_ctrl_pad_readl(control_pbias_offset);
 175                 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 176                         OMAP4_MMC1_PWRDNZ_MASK |
 177                         OMAP4_MMC1_PBIASLITE_VMODE_MASK |
 178                         OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 179                 omap4_ctrl_pad_writel(reg, control_pbias_offset);
 180         }
 181 }
 182
 183 static void hsmmc23_before_set_reg(struct device *dev, int slot,
 184                                    int power_on, int vdd)
 185 {
 186         struct omap_mmc_platform_data *mmc = dev->platform_data;
 187
 188         if (mmc->slots[0].remux)
 189                 mmc->slots[0].remux(dev, slot, power_on);
 190
 191         if (power_on) {
 192                 /* Only MMC2 supports a CLKIN */
 193                 if (mmc->slots[0].internal_clock) {
 194                         u32 reg;
 195
 196                         reg = omap_ctrl_readl(control_devconf1_offset);
 197                         reg |= OMAP2_MMCSDIO2ADPCLKISEL;
 198                         omap_ctrl_writel(reg, control_devconf1_offset);
 199                 }
 200         }
 201 }
 202
 203 static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
 204                                                         int vdd)
 205 {
 206         return 0;
 207 }
 208
 209 static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
 210                         int controller_nr)
 211 {
 212         if ((mmc_controller->slots[0].switch_pin > 0) && \
 213                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
 214                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
 215                                         OMAP_PIN_INPUT_PULLUP);
 216         if ((mmc_controller->slots[0].gpio_wp > 0) && \
 217                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
 218                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
 219                                         OMAP_PIN_INPUT_PULLUP);
 220         if (cpu_is_omap34xx()) {
 221                 if (controller_nr == 0) {
 222                         omap_mux_init_signal("sdmmc1_clk",
 223                                 OMAP_PIN_INPUT_PULLUP);
 224                         omap_mux_init_signal("sdmmc1_cmd",
 225                                 OMAP_PIN_INPUT_PULLUP);
 226                         omap_mux_init_signal("sdmmc1_dat0",
 227                                 OMAP_PIN_INPUT_PULLUP);
 228                         if (mmc_controller->slots[0].caps &
 229                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 230                                 omap_mux_init_signal("sdmmc1_dat1",
 231                                         OMAP_PIN_INPUT_PULLUP);
 232                                 omap_mux_init_signal("sdmmc1_dat2",
 233                                         OMAP_PIN_INPUT_PULLUP);
 234                                 omap_mux_init_signal("sdmmc1_dat3",
 235                                         OMAP_PIN_INPUT_PULLUP);
 236                         }
 237                         if (mmc_controller->slots[0].caps &
 238                                                 MMC_CAP_8_BIT_DATA) {
 239                                 omap_mux_init_signal("sdmmc1_dat4",
 240                                         OMAP_PIN_INPUT_PULLUP);
 241                                 omap_mux_init_signal("sdmmc1_dat5",
 242                                         OMAP_PIN_INPUT_PULLUP);
 243                                 omap_mux_init_signal("sdmmc1_dat6",
 244                                         OMAP_PIN_INPUT_PULLUP);
 245                                 omap_mux_init_signal("sdmmc1_dat7",
 246                                         OMAP_PIN_INPUT_PULLUP);
 247                         }
 248                 }
 249                 if (controller_nr == 1) {
 250                         /* MMC2 */
 251                         omap_mux_init_signal("sdmmc2_clk",
 252                                 OMAP_PIN_INPUT_PULLUP);
 253                         omap_mux_init_signal("sdmmc2_cmd",
 254                                 OMAP_PIN_INPUT_PULLUP);
 255                         omap_mux_init_signal("sdmmc2_dat0",
 256                                 OMAP_PIN_INPUT_PULLUP);
 257
 258                         /*
 259                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7
 260                          * need to be muxed in the board-*.c files
 261                          */
 262                         if (mmc_controller->slots[0].caps &
 263                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 264                                 omap_mux_init_signal("sdmmc2_dat1",
 265                                         OMAP_PIN_INPUT_PULLUP);
 266                                 omap_mux_init_signal("sdmmc2_dat2",
 267                                         OMAP_PIN_INPUT_PULLUP);
 268                                 omap_mux_init_signal("sdmmc2_dat3",
 269                                         OMAP_PIN_INPUT_PULLUP);
 270                         }
 271                         if (mmc_controller->slots[0].caps &
 272                                                         MMC_CAP_8_BIT_DATA) {
 273                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
 274                                         OMAP_PIN_INPUT_PULLUP);
 275                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
 276                                         OMAP_PIN_INPUT_PULLUP);
 277                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
 278                                         OMAP_PIN_INPUT_PULLUP);
 279                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
 280                                         OMAP_PIN_INPUT_PULLUP);
 281                         }
 282                 }
 283
 284                 /*
 285                  * For MMC3 the pins need to be muxed in the board-*.c files
 286                  */
 287         }
 288 }
 289
 290 static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
 291
 292 void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
 293 {
 294         struct omap2_hsmmc_info *c;
 295         int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
 296         int i;
 297         u32 reg;
 298
 299         if (!cpu_is_omap44xx()) {
 300                 if (cpu_is_omap2430()) {
 301                         control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
 302                         control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
 303                 } else {
 304                         control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
 305                         control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
 306                 }
 307         } else {
 308                 control_pbias_offset =
 309                         OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
 310                 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
 311                 reg = omap4_ctrl_pad_readl(control_mmc1);
 312                 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
 313                         OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
 314                 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
 315                         OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
 316                 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
 317                         OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
 318                         OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
 319                 omap4_ctrl_pad_writel(reg, control_mmc1);
 320         }
 321
 322         for (c = controllers; c->mmc; c++) {
 323                 struct hsmmc_controller *hc = hsmmc + c->mmc - 1;
 324                 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
 325
 326                 if (!c->mmc || c->mmc > nr_hsmmc) {
 327                         pr_debug("MMC%d: no such controller\n", c->mmc);
 328                         continue;
 329                 }
 330                 if (mmc) {
 331                         pr_debug("MMC%d: already configured\n", c->mmc);
 332                         continue;
 333                 }
 334
 335                 mmc = kzalloc(sizeof(struct omap_mmc_platform_data),
 336                               GFP_KERNEL);
 337                 if (!mmc) {
 338                         pr_err("Cannot allocate memory for mmc device!\n");
 339                         goto done;
 340                 }
 341
 342                 if (c->name)
 343                         strncpy(hc->name, c->name, HSMMC_NAME_LEN);
 344                 else
 345                         snprintf(hc->name, ARRAY_SIZE(hc->name),
 346                                 "mmc%islot%i", c->mmc, 1);
 347                 mmc->slots[0].name = hc->name;
 348                 mmc->nr_slots = 1;
 349                 mmc->slots[0].caps = c->caps;
 350                 mmc->slots[0].internal_clock = !c->ext_clock;
 351                 mmc->dma_mask = 0xffffffff;
 352                 if (cpu_is_omap44xx())
 353                         mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
 354                 else
 355                         mmc->reg_offset = 0;
 356
 357                 mmc->get_context_loss_count = hsmmc_get_context_loss;
 358
 359                 mmc->slots[0].switch_pin = c->gpio_cd;
 360                 mmc->slots[0].gpio_wp = c->gpio_wp;
 361
 362                 mmc->slots[0].remux = c->remux;
 363                 mmc->slots[0].init_card = c->init_card;
 364
 365                 if (c->cover_only)
 366                         mmc->slots[0].cover = 1;
 367
 368                 if (c->nonremovable)
 369                         mmc->slots[0].nonremovable = 1;
 370
 371                 if (c->power_saving)
 372                         mmc->slots[0].power_saving = 1;
 373
 374                 if (c->no_off)
 375                         mmc->slots[0].no_off = 1;
 376
 377                 if (c->vcc_aux_disable_is_sleep)
 378                         mmc->slots[0].vcc_aux_disable_is_sleep = 1;
 379
 380                 /* NOTE:  MMC slots should have a Vcc regulator set up.
 381                  * This may be from a TWL4030-family chip, another
 382                  * controllable regulator, or a fixed supply.
 383                  *
 384                  * temporary HACK: ocr_mask instead of fixed supply
 385                  */
 386                 mmc->slots[0].ocr_mask = c->ocr_mask;
 387
 388                 if (cpu_is_omap3517() || cpu_is_omap3505())
 389                         mmc->slots[0].set_power = nop_mmc_set_power;
 390                 else
 391                         mmc->slots[0].features |= HSMMC_HAS_PBIAS;
 392
 393                 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
 394                         mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
 395
 396                 switch (c->mmc) {
 397                 case 1:
 398                         if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 399                                 /* on-chip level shifting via PBIAS0/PBIAS1 */
 400                                 if (cpu_is_omap44xx()) {
 401                                         mmc->slots[0].before_set_reg =
 402                                                 omap4_hsmmc1_before_set_reg;
 403                                         mmc->slots[0].after_set_reg =
 404                                                 omap4_hsmmc1_after_set_reg;
 405                                 } else {
 406                                         mmc->slots[0].before_set_reg =
 407                                                 omap_hsmmc1_before_set_reg;
 408                                         mmc->slots[0].after_set_reg =
 409                                                 omap_hsmmc1_after_set_reg;
 410                                 }
 411                         }
 412
 413                         /* Omap3630 HSMMC1 supports only 4-bit */
 414                         if (cpu_is_omap3630() &&
 415                                         (c->caps & MMC_CAP_8_BIT_DATA)) {
 416                                 c->caps &= ~MMC_CAP_8_BIT_DATA;
 417                                 c->caps |= MMC_CAP_4_BIT_DATA;
 418                                 mmc->slots[0].caps = c->caps;
 419                         }
 420                         break;
 421                 case 2:
 422                         if (c->ext_clock)
 423                                 c->transceiver = 1;
 424                         if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
 425                                 c->caps &= ~MMC_CAP_8_BIT_DATA;
 426                                 c->caps |= MMC_CAP_4_BIT_DATA;
 427                         }
 428                         /* FALLTHROUGH */
 429                 case 3:
 430                         if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 431                                 /* off-chip level shifting, or none */
 432                                 mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
 433                                 mmc->slots[0].after_set_reg = NULL;
 434                         }
 435                         break;
 436                 case 4:
 437                 case 5:
 438                         mmc->slots[0].before_set_reg = NULL;
 439                         mmc->slots[0].after_set_reg = NULL;
 440                         break;
 441                 default:
 442                         pr_err("MMC%d configuration not supported!\n", c->mmc);
 443                         kfree(mmc);
 444                         continue;
 445                 }
 446                 hsmmc_data[c->mmc - 1] = mmc;
 447                 omap_hsmmc_mux(hsmmc_data[c->mmc - 1], (c->mmc - 1));
 448         }
 449
 450         omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
 451
 452         /* pass the device nodes back to board setup code */
 453         for (c = controllers; c->mmc; c++) {
 454                 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
 455
 456                 if (!c->mmc || c->mmc > nr_hsmmc)
 457                         continue;
 458                 c->dev = mmc->dev;
 459         }
 460
 461 done:
 462         for (i = 0; i < nr_hsmmc; i++)
 463                 kfree(hsmmc_data[i]);
 464 }
 465
 466 #endif