arch/arm/mach-omap2/hsmmc.c

   1 /*
   2  * linux/arch/arm/mach-omap2/hsmmc.c
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Author: Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/slab.h>
  14 #include <linux/string.h>
  15 #include <linux/delay.h>
  16 #include <linux/gpio.h>
  17 #include <mach/hardware.h>
  18 #include <plat/mmc.h>
  19 #include <plat/omap-pm.h>
  20 #include <plat/mux.h>
  21 #include <plat/omap_device.h>
  22 #include <asm/mach-types.h>
  23
  24 #include "mux.h"
  25 #include "hsmmc.h"
  26 #include "control.h"
  27
  28 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  29
  30 static u16 control_pbias_offset;
  31 static u16 control_devconf1_offset;
  32 static u16 control_mmc1;
  33
  34 #define HSMMC_NAME_LEN  9
  35
  36 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  37
  38 static int hsmmc_get_context_loss(struct device *dev)
  39 {
  40         return omap_pm_get_dev_context_loss_count(dev);
  41 }
  42
  43 #else
  44 #define hsmmc_get_context_loss NULL
  45 #endif
  46
  47 static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
  48                                   int power_on, int vdd)
  49 {
  50         u32 reg, prog_io;
  51         struct omap_mmc_platform_data *mmc = dev->platform_data;
  52
  53         if (mmc->slots[0].remux)
  54                 mmc->slots[0].remux(dev, slot, power_on);
  55
  56         /*
  57          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
  58          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
  59          * 1.8V and 3.0V modes, controlled by the PBIAS register.
  60          *
  61          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
  62          * is most naturally TWL VSIM; those pins also use PBIAS.
  63          *
  64          * FIXME handle VMMC1A as needed ...
  65          */
  66         if (power_on) {
  67                 if (cpu_is_omap2430()) {
  68                         reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
  69                         if ((1 << vdd) >= MMC_VDD_30_31)
  70                                 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
  71                         else
  72                                 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
  73                         omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
  74                 }
  75
  76                 if (mmc->slots[0].internal_clock) {
  77                         reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  78                         reg |= OMAP2_MMCSDIO1ADPCLKISEL;
  79                         omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
  80                 }
  81
  82                 reg = omap_ctrl_readl(control_pbias_offset);
  83                 if (cpu_is_omap3630()) {
  84                         /* Set MMC I/O to 52Mhz */
  85                         prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
  86                         prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
  87                         omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
  88                 } else {
  89                         reg |= OMAP2_PBIASSPEEDCTRL0;
  90                 }
  91                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  92                 omap_ctrl_writel(reg, control_pbias_offset);
  93         } else {
  94                 reg = omap_ctrl_readl(control_pbias_offset);
  95                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  96                 omap_ctrl_writel(reg, control_pbias_offset);
  97         }
  98 }
  99
 100 static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
 101                                  int power_on, int vdd)
 102 {
 103         u32 reg;
 104
 105         /* 100ms delay required for PBIAS configuration */
 106         msleep(100);
 107
 108         if (power_on) {
 109                 reg = omap_ctrl_readl(control_pbias_offset);
 110                 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
 111                 if ((1 << vdd) <= MMC_VDD_165_195)
 112                         reg &= ~OMAP2_PBIASLITEVMODE0;
 113                 else
 114                         reg |= OMAP2_PBIASLITEVMODE0;
 115                 omap_ctrl_writel(reg, control_pbias_offset);
 116         } else {
 117                 reg = omap_ctrl_readl(control_pbias_offset);
 118                 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
 119                         OMAP2_PBIASLITEVMODE0);
 120                 omap_ctrl_writel(reg, control_pbias_offset);
 121         }
 122 }
 123
 124 static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
 125                                   int power_on, int vdd)
 126 {
 127         u32 reg;
 128
 129         /*
 130          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
 131          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
 132          * 1.8V and 3.0V modes, controlled by the PBIAS register.
 133          */
 134         reg = omap4_ctrl_pad_readl(control_pbias_offset);
 135         reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 136                 OMAP4_MMC1_PWRDNZ_MASK |
 137                 OMAP4_MMC1_PBIASLITE_VMODE_MASK);
 138         omap4_ctrl_pad_writel(reg, control_pbias_offset);
 139 }
 140
 141 static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
 142                                  int power_on, int vdd)
 143 {
 144         u32 reg;
 145         unsigned long timeout;
 146
 147         if (power_on) {
 148                 reg = omap4_ctrl_pad_readl(control_pbias_offset);
 149                 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
 150                 if ((1 << vdd) <= MMC_VDD_165_195)
 151                         reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
 152                 else
 153                         reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
 154                 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 155                         OMAP4_MMC1_PWRDNZ_MASK);
 156                 omap4_ctrl_pad_writel(reg, control_pbias_offset);
 157
 158                 timeout = jiffies + msecs_to_jiffies(5);
 159                 do {
 160                         reg = omap4_ctrl_pad_readl(control_pbias_offset);
 161                         if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
 162                                 break;
 163                         usleep_range(100, 200);
 164                 } while (!time_after(jiffies, timeout));
 165
 166                 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
 167                         pr_err("Pbias Voltage is not same as LDO\n");
 168                         /* Caution : On VMODE_ERROR Power Down MMC IO */
 169                         reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
 170                         omap4_ctrl_pad_writel(reg, control_pbias_offset);
 171                 }
 172         }
 173 }
 174
 175 static void hsmmc2_before_set_reg(struct device *dev, int slot,
 176                                    int power_on, int vdd)
 177 {
 178         struct omap_mmc_platform_data *mmc = dev->platform_data;
 179
 180         if (mmc->slots[0].remux)
 181                 mmc->slots[0].remux(dev, slot, power_on);
 182
 183         if (power_on) {
 184                 u32 reg;
 185
 186                 reg = omap_ctrl_readl(control_devconf1_offset);
 187                 if (mmc->slots[0].internal_clock)
 188                         reg |= OMAP2_MMCSDIO2ADPCLKISEL;
 189                 else
 190                         reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
 191                 omap_ctrl_writel(reg, control_devconf1_offset);
 192         }
 193 }
 194
 195 static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
 196                                                         int vdd)
 197 {
 198         return 0;
 199 }
 200
 201 static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
 202                         int controller_nr)
 203 {
 204         if (gpio_is_valid(mmc_controller->slots[0].switch_pin))
 205                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
 206                                         OMAP_PIN_INPUT_PULLUP);
 207         if (gpio_is_valid(mmc_controller->slots[0].gpio_wp))
 208                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
 209                                         OMAP_PIN_INPUT_PULLUP);
 210         if (cpu_is_omap34xx()) {
 211                 if (controller_nr == 0) {
 212                         omap_mux_init_signal("sdmmc1_clk",
 213                                 OMAP_PIN_INPUT_PULLUP);
 214                         omap_mux_init_signal("sdmmc1_cmd",
 215                                 OMAP_PIN_INPUT_PULLUP);
 216                         omap_mux_init_signal("sdmmc1_dat0",
 217                                 OMAP_PIN_INPUT_PULLUP);
 218                         if (mmc_controller->slots[0].caps &
 219                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 220                                 omap_mux_init_signal("sdmmc1_dat1",
 221                                         OMAP_PIN_INPUT_PULLUP);
 222                                 omap_mux_init_signal("sdmmc1_dat2",
 223                                         OMAP_PIN_INPUT_PULLUP);
 224                                 omap_mux_init_signal("sdmmc1_dat3",
 225                                         OMAP_PIN_INPUT_PULLUP);
 226                         }
 227                         if (mmc_controller->slots[0].caps &
 228                                                 MMC_CAP_8_BIT_DATA) {
 229                                 omap_mux_init_signal("sdmmc1_dat4",
 230                                         OMAP_PIN_INPUT_PULLUP);
 231                                 omap_mux_init_signal("sdmmc1_dat5",
 232                                         OMAP_PIN_INPUT_PULLUP);
 233                                 omap_mux_init_signal("sdmmc1_dat6",
 234                                         OMAP_PIN_INPUT_PULLUP);
 235                                 omap_mux_init_signal("sdmmc1_dat7",
 236                                         OMAP_PIN_INPUT_PULLUP);
 237                         }
 238                 }
 239                 if (controller_nr == 1) {
 240                         /* MMC2 */
 241                         omap_mux_init_signal("sdmmc2_clk",
 242                                 OMAP_PIN_INPUT_PULLUP);
 243                         omap_mux_init_signal("sdmmc2_cmd",
 244                                 OMAP_PIN_INPUT_PULLUP);
 245                         omap_mux_init_signal("sdmmc2_dat0",
 246                                 OMAP_PIN_INPUT_PULLUP);
 247
 248                         /*
 249                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7
 250                          * need to be muxed in the board-*.c files
 251                          */
 252                         if (mmc_controller->slots[0].caps &
 253                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 254                                 omap_mux_init_signal("sdmmc2_dat1",
 255                                         OMAP_PIN_INPUT_PULLUP);
 256                                 omap_mux_init_signal("sdmmc2_dat2",
 257                                         OMAP_PIN_INPUT_PULLUP);
 258                                 omap_mux_init_signal("sdmmc2_dat3",
 259                                         OMAP_PIN_INPUT_PULLUP);
 260                         }
 261                         if (mmc_controller->slots[0].caps &
 262                                                         MMC_CAP_8_BIT_DATA) {
 263                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
 264                                         OMAP_PIN_INPUT_PULLUP);
 265                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
 266                                         OMAP_PIN_INPUT_PULLUP);
 267                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
 268                                         OMAP_PIN_INPUT_PULLUP);
 269                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
 270                                         OMAP_PIN_INPUT_PULLUP);
 271                         }
 272                 }
 273
 274                 /*
 275                  * For MMC3 the pins need to be muxed in the board-*.c files
 276                  */
 277         }
 278 }
 279
 280 static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 281                                         struct omap_mmc_platform_data *mmc)
 282 {
 283         char *hc_name;
 284
 285         hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
 286         if (!hc_name) {
 287                 pr_err("Cannot allocate memory for controller slot name\n");
 288                 kfree(hc_name);
 289                 return -ENOMEM;
 290         }
 291
 292         if (c->name)
 293                 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
 294         else
 295                 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
 296                                                                 c->mmc, 1);
 297         mmc->slots[0].name = hc_name;
 298         mmc->nr_slots = 1;
 299         mmc->slots[0].caps = c->caps;
 300         mmc->slots[0].internal_clock = !c->ext_clock;
 301         mmc->dma_mask = 0xffffffff;
 302         if (cpu_is_omap44xx())
 303                 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
 304         else
 305                 mmc->reg_offset = 0;
 306
 307         mmc->get_context_loss_count = hsmmc_get_context_loss;
 308
 309         mmc->slots[0].switch_pin = c->gpio_cd;
 310         mmc->slots[0].gpio_wp = c->gpio_wp;
 311
 312         mmc->slots[0].remux = c->remux;
 313         mmc->slots[0].init_card = c->init_card;
 314
 315         if (c->cover_only)
 316                 mmc->slots[0].cover = 1;
 317
 318         if (c->nonremovable)
 319                 mmc->slots[0].nonremovable = 1;
 320
 321         if (c->power_saving)
 322                 mmc->slots[0].power_saving = 1;
 323
 324         if (c->no_off)
 325                 mmc->slots[0].no_off = 1;
 326
 327         if (c->no_off_init)
 328                 mmc->slots[0].no_regulator_off_init = c->no_off_init;
 329
 330         if (c->vcc_aux_disable_is_sleep)
 331                 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
 332
 333         /*
 334          * NOTE:  MMC slots should have a Vcc regulator set up.
 335          * This may be from a TWL4030-family chip, another
 336          * controllable regulator, or a fixed supply.
 337          *
 338          * temporary HACK: ocr_mask instead of fixed supply
 339          */
 340         mmc->slots[0].ocr_mask = c->ocr_mask;
 341
 342         if (cpu_is_omap3517() || cpu_is_omap3505())
 343                 mmc->slots[0].set_power = nop_mmc_set_power;
 344         else
 345                 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
 346
 347         if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
 348                 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
 349
 350         switch (c->mmc) {
 351         case 1:
 352                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 353                         /* on-chip level shifting via PBIAS0/PBIAS1 */
 354                         if (cpu_is_omap44xx()) {
 355                                 mmc->slots[0].before_set_reg =
 356                                                 omap4_hsmmc1_before_set_reg;
 357                                 mmc->slots[0].after_set_reg =
 358                                                 omap4_hsmmc1_after_set_reg;
 359                         } else {
 360                                 mmc->slots[0].before_set_reg =
 361                                                 omap_hsmmc1_before_set_reg;
 362                                 mmc->slots[0].after_set_reg =
 363                                                 omap_hsmmc1_after_set_reg;
 364                         }
 365                 }
 366
 367                 /* OMAP3630 HSMMC1 supports only 4-bit */
 368                 if (cpu_is_omap3630() &&
 369                                 (c->caps & MMC_CAP_8_BIT_DATA)) {
 370                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 371                         c->caps |= MMC_CAP_4_BIT_DATA;
 372                         mmc->slots[0].caps = c->caps;
 373                 }
 374                 break;
 375         case 2:
 376                 if (c->ext_clock)
 377                         c->transceiver = 1;
 378                 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
 379                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 380                         c->caps |= MMC_CAP_4_BIT_DATA;
 381                 }
 382                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 383                         /* off-chip level shifting, or none */
 384                         mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
 385                         mmc->slots[0].after_set_reg = NULL;
 386                 }
 387                 break;
 388         case 3:
 389         case 4:
 390         case 5:
 391                 mmc->slots[0].before_set_reg = NULL;
 392                 mmc->slots[0].after_set_reg = NULL;
 393                 break;
 394         default:
 395                 pr_err("MMC%d configuration not supported!\n", c->mmc);
 396                 kfree(hc_name);
 397                 return -ENODEV;
 398         }
 399         return 0;
 400 }
 401
 402 #define MAX_OMAP_MMC_HWMOD_NAME_LEN             16
 403
 404 void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
 405 {
 406         struct omap_hwmod *oh;
 407         struct platform_device *pdev;
 408         char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
 409         struct omap_mmc_platform_data *mmc_data;
 410         struct omap_mmc_dev_attr *mmc_dev_attr;
 411         char *name;
 412         int l;
 413
 414         mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
 415         if (!mmc_data) {
 416                 pr_err("Cannot allocate memory for mmc device!\n");
 417                 goto done;
 418         }
 419
 420         if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
 421                 pr_err("%s fails!\n", __func__);
 422                 goto done;
 423         }
 424         omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
 425
 426         name = "omap_hsmmc";
 427
 428         l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
 429                      "mmc%d", ctrl_nr);
 430         WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
 431              "String buffer overflow in MMC%d device setup\n", ctrl_nr);
 432         oh = omap_hwmod_lookup(oh_name);
 433         if (!oh) {
 434                 pr_err("Could not look up %s\n", oh_name);
 435                 kfree(mmc_data->slots[0].name);
 436                 goto done;
 437         }
 438
 439         if (oh->dev_attr != NULL) {
 440                 mmc_dev_attr = oh->dev_attr;
 441                 mmc_data->controller_flags = mmc_dev_attr->flags;
 442                 /*
 443                  * erratum 2.1.1.128 doesn't apply if board has
 444                  * a transceiver is attached
 445                  */
 446                 if (hsmmcinfo->transceiver)
 447                         mmc_data->controller_flags &=
 448                                 ~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;
 449         }
 450
 451         pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
 452                 sizeof(struct omap_mmc_platform_data), NULL, 0, false);
 453         if (IS_ERR(pdev)) {
 454                 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
 455                 kfree(mmc_data->slots[0].name);
 456                 goto done;
 457         }
 458         /*
 459          * return device handle to board setup code
 460          * required to populate for regulator framework structure
 461          */
 462         hsmmcinfo->dev = &pdev->dev;
 463
 464 done:
 465         kfree(mmc_data);
 466 }
 467
 468 void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
 469 {
 470         u32 reg;
 471
 472         if (!cpu_is_omap44xx()) {
 473                 if (cpu_is_omap2430()) {
 474                         control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
 475                         control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
 476                 } else {
 477                         control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
 478                         control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
 479                 }
 480
 481                 if (machine_is_omap3_pandora()) {
 482                         /* needed for gpio_126 - gpio_129 to work correctly */
 483                         reg = omap_ctrl_readl(control_pbias_offset);
 484                         reg &= ~OMAP343X_PBIASLITEVMODE1;
 485                         omap_ctrl_writel(reg, control_pbias_offset);
 486                 }
 487         } else {
 488                 control_pbias_offset =
 489                         OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
 490                 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
 491                 reg = omap4_ctrl_pad_readl(control_mmc1);
 492                 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
 493                         OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
 494                 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
 495                         OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
 496                 reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
 497                         OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
 498                         OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
 499                 omap4_ctrl_pad_writel(reg, control_mmc1);
 500         }
 501
 502         for (; controllers->mmc; controllers++)
 503                 omap_init_hsmmc(controllers, controllers->mmc);
 504
 505 }
 506
 507 #endif