arch/arm/mach-omap2/hsmmc.c

   1 /*
   2  * linux/arch/arm/mach-omap2/board-sdp-hsmmc.c
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Author: Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/delay.h>
  18 #include <linux/gpio.h>
  19 #include <linux/i2c/twl4030.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/mmc.h>
  23 #include <mach/board.h>
  24 #include <asm/mach-types.h>
  25
  26 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  27
  28 #define VMMC1_DEV_GRP           0x27
  29 #define P1_DEV_GRP              0x20
  30 #define VMMC1_DEDICATED         0x2A
  31 #define VSEL_3V                 0x02
  32 #define VSEL_3V15               0x03
  33 #define VSEL_18V                0x00
  34 #define TWL_GPIO_IMR1A          0x1C
  35 #define TWL_GPIO_ISR1A          0x19
  36 #define LDO_CLR                 0x00
  37 #define VSEL_S2_CLR             0x40
  38 #define GPIO_0_BIT_POS          (1 << 0)
  39
  40 #define OMAP2_CONTROL_DEVCONF0  0x48002274
  41 #if defined(CONFIG_ARCH_OMAP2430)
  42 #define OMAP2_CONTROL_DEVCONF1  0x490022E8
  43 #else
  44 #define OMAP2_CONTROL_DEVCONF1  0x480022D8
  45 #endif
  46
  47 #define OMAP2_MMCSDIO2ADPCLKISEL        (1 << 6)
  48 #define OMAP2_CONTROL_DEVCONF0_LBCLK    (1 << 24)
  49 #define OMAP2_CONTROL_DEVCONF1_ACTOV    (1 << 31)
  50
  51 #define OMAP2_CONTROL_PBIAS_VMODE       (1 << 0)
  52 #define OMAP2_CONTROL_PBIAS_PWRDNZ      (1 << 1)
  53 #define OMAP2_CONTROL_PBIAS_SCTRL       (1 << 2)
  54
  55
  56 static const int mmc1_cd_gpio = OMAP_MAX_GPIO_LINES;            /* HACK!! */
  57
  58 static int hsmmc_card_detect(int irq)
  59 {
  60         return gpio_get_value_cansleep(mmc1_cd_gpio);
  61 }
  62
  63 /*
  64  * MMC Slot Initialization.
  65  */
  66 static int hsmmc_late_init(struct device *dev)
  67 {
  68         int ret = 0;
  69
  70         /*
  71          * Configure TWL4030 GPIO parameters for MMC hotplug irq
  72          */
  73         ret = gpio_request(mmc1_cd_gpio, "mmc0_cd");
  74         if (ret)
  75                 goto err;
  76
  77         ret = twl4030_set_gpio_debounce(0, true);
  78         if (ret)
  79                 goto err;
  80
  81         return ret;
  82
  83 err:
  84         dev_err(dev, "Failed to configure TWL4030 GPIO IRQ\n");
  85         return ret;
  86 }
  87
  88 static void hsmmc_cleanup(struct device *dev)
  89 {
  90         gpio_free(mmc1_cd_gpio);
  91 }
  92
  93 #ifdef CONFIG_PM
  94
  95 /*
  96  * To mask and unmask MMC Card Detect Interrupt
  97  * mask : 1
  98  * unmask : 0
  99  */
 100 static int mask_cd_interrupt(int mask)
 101 {
 102         u8 reg = 0, ret = 0;
 103
 104         ret = twl4030_i2c_read_u8(TWL4030_MODULE_GPIO, &reg, TWL_GPIO_IMR1A);
 105         if (ret)
 106                 goto err;
 107
 108         reg = (mask == 1) ? (reg | GPIO_0_BIT_POS) : (reg & ~GPIO_0_BIT_POS);
 109
 110         ret = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, reg, TWL_GPIO_IMR1A);
 111         if (ret)
 112                 goto err;
 113
 114         ret = twl4030_i2c_read_u8(TWL4030_MODULE_GPIO, &reg, TWL_GPIO_ISR1A);
 115         if (ret)
 116                 goto err;
 117
 118         reg = (mask == 1) ? (reg | GPIO_0_BIT_POS) : (reg & ~GPIO_0_BIT_POS);
 119
 120         ret = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, reg, TWL_GPIO_ISR1A);
 121         if (ret)
 122                 goto err;
 123
 124 err:
 125         return ret;
 126 }
 127
 128 static int hsmmc_suspend(struct device *dev, int slot)
 129 {
 130         int ret = 0;
 131
 132         disable_irq(TWL4030_GPIO_IRQ_NO(0));
 133         ret = mask_cd_interrupt(1);
 134
 135         return ret;
 136 }
 137
 138 static int hsmmc_resume(struct device *dev, int slot)
 139 {
 140         int ret = 0;
 141
 142         enable_irq(TWL4030_GPIO_IRQ_NO(0));
 143         ret = mask_cd_interrupt(0);
 144
 145         return ret;
 146 }
 147
 148 #endif
 149
 150 static int hsmmc_set_power(struct device *dev, int slot, int power_on,
 151                                 int vdd)
 152 {
 153         u32 vdd_sel = 0, devconf = 0, reg = 0;
 154         int ret = 0;
 155
 156         dev_dbg(dev, "power %s, vdd %i\n", power_on ? "on" : "off", vdd);
 157
 158         /* REVISIT: Using address directly till the control.h defines
 159          * are settled.
 160          */
 161 #if defined(CONFIG_ARCH_OMAP2430)
 162         #define OMAP2_CONTROL_PBIAS 0x490024A0
 163 #else
 164         #define OMAP2_CONTROL_PBIAS 0x48002520
 165 #endif
 166
 167         if (power_on) {
 168                 if (cpu_is_omap24xx())
 169                         devconf = omap_readl(OMAP2_CONTROL_DEVCONF1);
 170                 else
 171                         devconf = omap_readl(OMAP2_CONTROL_DEVCONF0);
 172
 173                 switch (1 << vdd) {
 174                 case MMC_VDD_33_34:
 175                 case MMC_VDD_32_33:
 176                         vdd_sel = VSEL_3V15;
 177                         if (cpu_is_omap24xx())
 178                                 devconf |= OMAP2_CONTROL_DEVCONF1_ACTOV;
 179                         break;
 180                 case MMC_VDD_165_195:
 181                         vdd_sel = VSEL_18V;
 182                         if (cpu_is_omap24xx())
 183                                 devconf &= ~OMAP2_CONTROL_DEVCONF1_ACTOV;
 184                 }
 185
 186                 if (cpu_is_omap24xx())
 187                         omap_writel(devconf, OMAP2_CONTROL_DEVCONF1);
 188                 else
 189                         omap_writel(devconf | OMAP2_CONTROL_DEVCONF0_LBCLK,
 190                                     OMAP2_CONTROL_DEVCONF0);
 191
 192                 reg = omap_readl(OMAP2_CONTROL_PBIAS);
 193                 reg |= OMAP2_CONTROL_PBIAS_SCTRL;
 194                 omap_writel(reg, OMAP2_CONTROL_PBIAS);
 195
 196                 reg = omap_readl(OMAP2_CONTROL_PBIAS);
 197                 reg &= ~OMAP2_CONTROL_PBIAS_PWRDNZ;
 198                 omap_writel(reg, OMAP2_CONTROL_PBIAS);
 199
 200                 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 201                                                 P1_DEV_GRP, VMMC1_DEV_GRP);
 202                 if (ret)
 203                         goto err;
 204
 205                 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 206                                                 vdd_sel, VMMC1_DEDICATED);
 207                 if (ret)
 208                         goto err;
 209
 210                 msleep(100);
 211                 reg = omap_readl(OMAP2_CONTROL_PBIAS);
 212                 reg |= (OMAP2_CONTROL_PBIAS_SCTRL |
 213                         OMAP2_CONTROL_PBIAS_PWRDNZ);
 214                 if (vdd_sel == VSEL_18V)
 215                         reg &= ~OMAP2_CONTROL_PBIAS_VMODE;
 216                 else
 217                         reg |= OMAP2_CONTROL_PBIAS_VMODE;
 218                 omap_writel(reg, OMAP2_CONTROL_PBIAS);
 219
 220                 return ret;
 221
 222         } else {
 223                 /* Power OFF */
 224
 225                 /* For MMC1, Toggle PBIAS before every power up sequence */
 226                 reg = omap_readl(OMAP2_CONTROL_PBIAS);
 227                 reg &= ~OMAP2_CONTROL_PBIAS_PWRDNZ;
 228                 omap_writel(reg, OMAP2_CONTROL_PBIAS);
 229
 230                 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 231                                                 LDO_CLR, VMMC1_DEV_GRP);
 232                 if (ret)
 233                         goto err;
 234
 235                 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 236                                                 VSEL_S2_CLR, VMMC1_DEDICATED);
 237                 if (ret)
 238                         goto err;
 239
 240                 /* 100ms delay required for PBIAS configuration */
 241                 msleep(100);
 242                 reg = omap_readl(OMAP2_CONTROL_PBIAS);
 243                 reg |= (OMAP2_CONTROL_PBIAS_VMODE |
 244                         OMAP2_CONTROL_PBIAS_PWRDNZ |
 245                         OMAP2_CONTROL_PBIAS_SCTRL);
 246                 omap_writel(reg, OMAP2_CONTROL_PBIAS);
 247         }
 248
 249         return 0;
 250
 251 err:
 252         return 1;
 253 }
 254
 255 static struct omap_mmc_platform_data mmc1_data = {
 256         .nr_slots                       = 1,
 257         .init                           = hsmmc_late_init,
 258         .cleanup                        = hsmmc_cleanup,
 259 #ifdef CONFIG_PM
 260         .suspend                        = hsmmc_suspend,
 261         .resume                         = hsmmc_resume,
 262 #endif
 263         .dma_mask                       = 0xffffffff,
 264         .slots[0] = {
 265                 .wire4                  = 1,
 266                 .set_power              = hsmmc_set_power,
 267                 .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34 |
 268                                                 MMC_VDD_165_195,
 269                 .name                   = "first slot",
 270
 271                 .card_detect_irq        = TWL4030_GPIO_IRQ_NO(0),
 272                 .card_detect            = hsmmc_card_detect,
 273         },
 274 };
 275
 276 /* ************************************************************************* */
 277
 278 #define VMMC2_DEV_GRP           0x2B
 279 #define VMMC2_DEDICATED         0x2E
 280
 281 #define mmc2_cd_gpio (mmc1_cd_gpio + 1)
 282
 283 static int hsmmc2_card_detect(int irq)
 284 {
 285         return gpio_get_value_cansleep(mmc2_cd_gpio);
 286 }
 287
 288 static int hsmmc2_late_init(struct device *dev)
 289 {
 290         int ret = 0;
 291
 292         ret = gpio_request(mmc2_cd_gpio, "mmc1_cd");
 293         if (ret)
 294                 goto err;
 295
 296         ret = twl4030_set_gpio_debounce(1, true);
 297         if (ret)
 298                 goto err;
 299
 300         return ret;
 301
 302 err:
 303         dev_err(dev, "Failed to configure TWL4030 GPIO IRQ for MMC2\n");
 304         return ret;
 305 }
 306
 307 static void hsmmc2_cleanup(struct device *dev)
 308 {
 309         gpio_free(mmc2_cd_gpio);
 310 }
 311
 312 static int hsmmc2_set_power(struct device *dev, int slot, int power_on,
 313                                 int vdd)
 314 {
 315         u32 vdd_sel = 0, ret = 0;
 316
 317         dev_dbg(dev, "power %s, vdd %i\n", power_on ? "on" : "off", vdd);
 318
 319         if (power_on) {
 320                 if (machine_is_omap3_pandora()) {
 321                         u32 devconf = omap_readl(OMAP2_CONTROL_DEVCONF1);
 322                         devconf &= ~OMAP2_MMCSDIO2ADPCLKISEL;
 323                         omap_writel(devconf, OMAP2_CONTROL_DEVCONF1);
 324                 }
 325
 326                 switch (1 << vdd) {
 327                 case MMC_VDD_33_34:
 328                 case MMC_VDD_32_33:
 329                         vdd_sel = 0x0c;
 330                         break;
 331                 case MMC_VDD_165_195:
 332                         vdd_sel = 0x05;
 333                         break;
 334                 default:
 335                         dev_err(dev, "Bad vdd request %i for MMC2\n", vdd);
 336                         goto err;
 337                 }
 338
 339                 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 340                                                 P1_DEV_GRP, VMMC2_DEV_GRP);
 341                 if (ret)
 342                         goto err;
 343
 344                 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 345                                                 vdd_sel, VMMC2_DEDICATED);
 346                 if (ret)
 347                         goto err;
 348
 349                 msleep(100);
 350         } else {
 351                 /* Power OFF */
 352                 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 353                                                 LDO_CLR, VMMC2_DEV_GRP);
 354                 if (ret)
 355                         goto err;
 356
 357                 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 358                                                 VSEL_S2_CLR, VMMC2_DEDICATED);
 359                 if (ret)
 360                         goto err;
 361         }
 362
 363         return 0;
 364
 365 err:
 366         return ret;
 367 }
 368
 369 static struct omap_mmc_platform_data mmc2_data = {
 370         .nr_slots                       = 1,
 371         .init                           = hsmmc2_late_init,
 372         .cleanup                        = hsmmc2_cleanup,
 373         /* TODO: .suspend, .resume */
 374         .dma_mask                       = 0xffffffff,
 375         .slots[0] = {
 376                 .wire4                  = 1,
 377                 .set_power              = hsmmc2_set_power,
 378                 .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34 |
 379                                                 MMC_VDD_165_195,
 380                 .name                   = "second slot",
 381
 382                 .card_detect_irq        = TWL4030_GPIO_IRQ_NO(1),
 383                 .card_detect            = hsmmc2_card_detect,
 384         },
 385 };
 386
 387 /* ************************************************************************* */
 388
 389 static int hsmmc3_set_power(struct device *dev, int slot, int power_on,
 390                 int vdd)
 391 {
 392         /* nothing to do for MMC3 */
 393         return 0;
 394 }
 395
 396 /*
 397  * Hack: Hardcoded WL1251 embedded data for Pandora
 398  * - passed up via a dirty hack to the MMC platform data.
 399  */
 400
 401 #include <linux/mmc/host.h>
 402 #include <linux/mmc/card.h>
 403 #include <linux/mmc/sdio_func.h>
 404 #include <linux/mmc/sdio_ids.h>
 405
 406 static struct sdio_embedded_func wifi_func = {
 407         .f_class        = SDIO_CLASS_WLAN,
 408         .f_maxblksize   = 512,
 409 };
 410
 411 static struct embedded_sdio_data pandora_wifi_emb_data = {
 412         .cis    = {
 413                 .vendor         = 0x104c,
 414                 .device         = 0x9066,
 415                 .blksize        = 512,
 416                 .max_dtr        = 20000000,
 417         },
 418         .cccr   = {
 419                 .multi_block    = 0,
 420                 .low_speed      = 0,
 421                 .wide_bus       = 1,
 422                 .high_power     = 0,
 423                 .high_speed     = 0,
 424         },
 425         .funcs  = &wifi_func,
 426         .num_funcs = 1,
 427 };
 428
 429 static struct omap_mmc_platform_data mmc3_data = {
 430         .nr_slots                       = 1,
 431         .dma_mask                       = 0xffffffff,
 432         .embedded_sdio                  = &pandora_wifi_emb_data,
 433         .slots[0] = {
 434                 .wire4                  = 1,
 435                 .set_power              = hsmmc3_set_power,
 436                 .ocr_mask               = MMC_VDD_165_195 | MMC_VDD_20_21,
 437                 .name                   = "third slot",
 438         },
 439 };
 440
 441 /* ************************************************************************* */
 442
 443 static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC];
 444
 445 void __init hsmmc_init(void)
 446 {
 447         hsmmc_data[0] = &mmc1_data;
 448         hsmmc_data[1] = &mmc2_data;
 449         hsmmc_data[2] = &mmc3_data;
 450         omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
 451 }
 452
 453 #else
 454
 455 void __init hsmmc_init(void)
 456 {
 457
 458 }
 459
 460 #endif