arch/arm/mach-omap2/display.c

   1 /*
   2  * OMAP2plus display device setup / initialization.
   3  *
   4  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   5  *      Senthilvadivu Guruswamy
   6  *      Sumit Semwal
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/string.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/io.h>
  23 #include <linux/clk.h>
  24 #include <linux/err.h>
  25 #include <linux/delay.h>
  26
  27 #include <video/omapdss.h>
  28 #include <plat/omap_hwmod.h>
  29 #include <plat/omap_device.h>
  30 #include <plat/omap-pm.h>
  31 #include "common.h"
  32
  33 #include "iomap.h"
  34 #include "mux.h"
  35 #include "control.h"
  36 #include "display.h"
  37
  38 #define DISPC_CONTROL           0x0040
  39 #define DISPC_CONTROL2          0x0238
  40 #define DISPC_IRQSTATUS         0x0018
  41
  42 #define DSS_SYSCONFIG           0x10
  43 #define DSS_SYSSTATUS           0x14
  44 #define DSS_CONTROL             0x40
  45 #define DSS_SDI_CONTROL         0x44
  46 #define DSS_PLL_CONTROL         0x48
  47
  48 #define LCD_EN_MASK             (0x1 << 0)
  49 #define DIGIT_EN_MASK           (0x1 << 1)
  50
  51 #define FRAMEDONE_IRQ_SHIFT     0
  52 #define EVSYNC_EVEN_IRQ_SHIFT   2
  53 #define EVSYNC_ODD_IRQ_SHIFT    3
  54 #define FRAMEDONE2_IRQ_SHIFT    22
  55 #define FRAMEDONETV_IRQ_SHIFT   24
  56
  57 /*
  58  * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
  59  *     reset before deciding that something has gone wrong
  60  */
  61 #define FRAMEDONE_IRQ_TIMEOUT           100
  62
  63 static struct platform_device omap_display_device = {
  64         .name          = "omapdss",
  65         .id            = -1,
  66         .dev            = {
  67                 .platform_data = NULL,
  68         },
  69 };
  70
  71 struct omap_dss_hwmod_data {
  72         const char *oh_name;
  73         const char *dev_name;
  74         const int id;
  75 };
  76
  77 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
  78         { "dss_core", "omapdss_dss", -1 },
  79         { "dss_dispc", "omapdss_dispc", -1 },
  80         { "dss_rfbi", "omapdss_rfbi", -1 },
  81         { "dss_venc", "omapdss_venc", -1 },
  82 };
  83
  84 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
  85         { "dss_core", "omapdss_dss", -1 },
  86         { "dss_dispc", "omapdss_dispc", -1 },
  87         { "dss_rfbi", "omapdss_rfbi", -1 },
  88         { "dss_venc", "omapdss_venc", -1 },
  89         { "dss_dsi1", "omapdss_dsi", 0 },
  90 };
  91
  92 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
  93         { "dss_core", "omapdss_dss", -1 },
  94         { "dss_dispc", "omapdss_dispc", -1 },
  95         { "dss_rfbi", "omapdss_rfbi", -1 },
  96         { "dss_venc", "omapdss_venc", -1 },
  97         { "dss_dsi1", "omapdss_dsi", 0 },
  98         { "dss_dsi2", "omapdss_dsi", 1 },
  99         { "dss_hdmi", "omapdss_hdmi", -1 },
 100 };
 101
 102 static void omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
 103 {
 104         u32 reg;
 105         u16 control_i2c_1;
 106
 107         omap_mux_init_signal("hdmi_cec",
 108                         OMAP_PIN_INPUT_PULLUP);
 109         omap_mux_init_signal("hdmi_ddc_scl",
 110                         OMAP_PIN_INPUT_PULLUP);
 111         omap_mux_init_signal("hdmi_ddc_sda",
 112                         OMAP_PIN_INPUT_PULLUP);
 113
 114         /*
 115          * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
 116          * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
 117          * internal pull up resistor.
 118          */
 119         if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
 120                 control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
 121                 reg = omap4_ctrl_pad_readl(control_i2c_1);
 122                 reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
 123                         OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
 124                         omap4_ctrl_pad_writel(reg, control_i2c_1);
 125         }
 126 }
 127
 128 static int __init omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
 129 {
 130         u32 enable_mask, enable_shift;
 131         u32 pipd_mask, pipd_shift;
 132         u32 reg;
 133
 134         if (dsi_id == 0) {
 135                 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
 136                 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
 137                 pipd_mask = OMAP4_DSI1_PIPD_MASK;
 138                 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
 139         } else if (dsi_id == 1) {
 140                 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
 141                 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
 142                 pipd_mask = OMAP4_DSI2_PIPD_MASK;
 143                 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
 144         } else {
 145                 return -ENODEV;
 146         }
 147
 148         reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
 149
 150         reg &= ~enable_mask;
 151         reg &= ~pipd_mask;
 152
 153         reg |= (lanes << enable_shift) & enable_mask;
 154         reg |= (lanes << pipd_shift) & pipd_mask;
 155
 156         omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
 157
 158         return 0;
 159 }
 160
 161 int __init omap_hdmi_init(enum omap_hdmi_flags flags)
 162 {
 163         if (cpu_is_omap44xx())
 164                 omap4_hdmi_mux_pads(flags);
 165
 166         return 0;
 167 }
 168
 169 static int __init omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
 170 {
 171         if (cpu_is_omap44xx())
 172                 return omap4_dsi_mux_pads(dsi_id, lane_mask);
 173
 174         return 0;
 175 }
 176
 177 static void __init omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
 178 {
 179         if (cpu_is_omap44xx())
 180                 omap4_dsi_mux_pads(dsi_id, 0);
 181 }
 182
 183 int __init omap_display_init(struct omap_dss_board_info *board_data)
 184 {
 185         int r = 0;
 186         struct omap_hwmod *oh;
 187         struct platform_device *pdev;
 188         int i, oh_count;
 189         struct omap_display_platform_data pdata;
 190         const struct omap_dss_hwmod_data *curr_dss_hwmod;
 191
 192         memset(&pdata, 0, sizeof(pdata));
 193
 194         if (cpu_is_omap24xx()) {
 195                 curr_dss_hwmod = omap2_dss_hwmod_data;
 196                 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
 197         } else if (cpu_is_omap34xx()) {
 198                 curr_dss_hwmod = omap3_dss_hwmod_data;
 199                 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
 200         } else {
 201                 curr_dss_hwmod = omap4_dss_hwmod_data;
 202                 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
 203         }
 204
 205         if (board_data->dsi_enable_pads == NULL)
 206                 board_data->dsi_enable_pads = omap_dsi_enable_pads;
 207         if (board_data->dsi_disable_pads == NULL)
 208                 board_data->dsi_disable_pads = omap_dsi_disable_pads;
 209
 210         pdata.board_data = board_data;
 211         pdata.board_data->get_context_loss_count =
 212                 omap_pm_get_dev_context_loss_count;
 213
 214         for (i = 0; i < oh_count; i++) {
 215                 oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name);
 216                 if (!oh) {
 217                         pr_err("Could not look up %s\n",
 218                                 curr_dss_hwmod[i].oh_name);
 219                         return -ENODEV;
 220                 }
 221
 222                 pdev = omap_device_build(curr_dss_hwmod[i].dev_name,
 223                                 curr_dss_hwmod[i].id, oh, &pdata,
 224                                 sizeof(struct omap_display_platform_data),
 225                                 NULL, 0, 0);
 226
 227                 if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n",
 228                                 curr_dss_hwmod[i].oh_name))
 229                         return -ENODEV;
 230         }
 231         omap_display_device.dev.platform_data = board_data;
 232
 233         r = platform_device_register(&omap_display_device);
 234         if (r < 0)
 235                 printk(KERN_ERR "Unable to register OMAP-Display device\n");
 236
 237         return r;
 238 }
 239
 240 static void dispc_disable_outputs(void)
 241 {
 242         u32 v, irq_mask = 0;
 243         bool lcd_en, digit_en, lcd2_en = false;
 244         int i;
 245         struct omap_dss_dispc_dev_attr *da;
 246         struct omap_hwmod *oh;
 247
 248         oh = omap_hwmod_lookup("dss_dispc");
 249         if (!oh) {
 250                 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
 251                 return;
 252         }
 253
 254         if (!oh->dev_attr) {
 255                 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
 256                 return;
 257         }
 258
 259         da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
 260
 261         /* store value of LCDENABLE and DIGITENABLE bits */
 262         v = omap_hwmod_read(oh, DISPC_CONTROL);
 263         lcd_en = v & LCD_EN_MASK;
 264         digit_en = v & DIGIT_EN_MASK;
 265
 266         /* store value of LCDENABLE for LCD2 */
 267         if (da->manager_count > 2) {
 268                 v = omap_hwmod_read(oh, DISPC_CONTROL2);
 269                 lcd2_en = v & LCD_EN_MASK;
 270         }
 271
 272         if (!(lcd_en | digit_en | lcd2_en))
 273                 return; /* no managers currently enabled */
 274
 275         /*
 276          * If any manager was enabled, we need to disable it before
 277          * DSS clocks are disabled or DISPC module is reset
 278          */
 279         if (lcd_en)
 280                 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
 281
 282         if (digit_en) {
 283                 if (da->has_framedonetv_irq) {
 284                         irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
 285                 } else {
 286                         irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
 287                                 1 << EVSYNC_ODD_IRQ_SHIFT;
 288                 }
 289         }
 290
 291         if (lcd2_en)
 292                 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
 293
 294         /*
 295          * clear any previous FRAMEDONE, FRAMEDONETV,
 296          * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
 297          */
 298         omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
 299
 300         /* disable LCD and TV managers */
 301         v = omap_hwmod_read(oh, DISPC_CONTROL);
 302         v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
 303         omap_hwmod_write(v, oh, DISPC_CONTROL);
 304
 305         /* disable LCD2 manager */
 306         if (da->manager_count > 2) {
 307                 v = omap_hwmod_read(oh, DISPC_CONTROL2);
 308                 v &= ~LCD_EN_MASK;
 309                 omap_hwmod_write(v, oh, DISPC_CONTROL2);
 310         }
 311
 312         i = 0;
 313         while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
 314                irq_mask) {
 315                 i++;
 316                 if (i > FRAMEDONE_IRQ_TIMEOUT) {
 317                         pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
 318                         break;
 319                 }
 320                 mdelay(1);
 321         }
 322 }
 323
 324 #define MAX_MODULE_SOFTRESET_WAIT       10000
 325 int omap_dss_reset(struct omap_hwmod *oh)
 326 {
 327         struct omap_hwmod_opt_clk *oc;
 328         int c = 0;
 329         int i, r;
 330
 331         if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
 332                 pr_err("dss_core: hwmod data doesn't contain reset data\n");
 333                 return -EINVAL;
 334         }
 335
 336         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 337                 if (oc->_clk)
 338                         clk_enable(oc->_clk);
 339
 340         dispc_disable_outputs();
 341
 342         /* clear SDI registers */
 343         if (cpu_is_omap3430()) {
 344                 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
 345                 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
 346         }
 347
 348         /*
 349          * clear DSS_CONTROL register to switch DSS clock sources to
 350          * PRCM clock, if any
 351          */
 352         omap_hwmod_write(0x0, oh, DSS_CONTROL);
 353
 354         omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
 355                                 & SYSS_RESETDONE_MASK),
 356                         MAX_MODULE_SOFTRESET_WAIT, c);
 357
 358         if (c == MAX_MODULE_SOFTRESET_WAIT)
 359                 pr_warning("dss_core: waiting for reset to finish failed\n");
 360         else
 361                 pr_debug("dss_core: softreset done\n");
 362
 363         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 364                 if (oc->_clk)
 365                         clk_disable(oc->_clk);
 366
 367         r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
 368
 369         return r;
 370 }