arch/arm/mach-omap2/devices.c

   1 /*
   2  * linux/arch/arm/mach-omap2/devices.c
   3  *
   4  * OMAP2 platform device setup/initialization
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/io.h>
  17 #include <linux/clk.h>
  18
  19 #include <mach/hardware.h>
  20 #include <asm/mach-types.h>
  21 #include <asm/mach/map.h>
  22
  23 #include <mach/control.h>
  24 #include <mach/tc.h>
  25 #include <mach/board.h>
  26 #include <mach/mux.h>
  27 #include <mach/gpio.h>
  28 #include <mach/mmc.h>
  29
  30 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
  31
  32 static struct resource cam_resources[] = {
  33         {
  34                 .start          = OMAP24XX_CAMERA_BASE,
  35                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
  36                 .flags          = IORESOURCE_MEM,
  37         },
  38         {
  39                 .start          = INT_24XX_CAM_IRQ,
  40                 .flags          = IORESOURCE_IRQ,
  41         }
  42 };
  43
  44 static struct platform_device omap_cam_device = {
  45         .name           = "omap24xxcam",
  46         .id             = -1,
  47         .num_resources  = ARRAY_SIZE(cam_resources),
  48         .resource       = cam_resources,
  49 };
  50
  51 static inline void omap_init_camera(void)
  52 {
  53         platform_device_register(&omap_cam_device);
  54 }
  55
  56 #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
  57
  58 static struct resource omap3isp_resources[] = {
  59         {
  60                 .start          = OMAP3430_ISP_BASE,
  61                 .end            = OMAP3430_ISP_END,
  62                 .flags          = IORESOURCE_MEM,
  63         },
  64         {
  65                 .start          = OMAP3430_ISP_CBUFF_BASE,
  66                 .end            = OMAP3430_ISP_CBUFF_END,
  67                 .flags          = IORESOURCE_MEM,
  68         },
  69         {
  70                 .start          = OMAP3430_ISP_CCP2_BASE,
  71                 .end            = OMAP3430_ISP_CCP2_END,
  72                 .flags          = IORESOURCE_MEM,
  73         },
  74         {
  75                 .start          = OMAP3430_ISP_CCDC_BASE,
  76                 .end            = OMAP3430_ISP_CCDC_END,
  77                 .flags          = IORESOURCE_MEM,
  78         },
  79         {
  80                 .start          = OMAP3430_ISP_HIST_BASE,
  81                 .end            = OMAP3430_ISP_HIST_END,
  82                 .flags          = IORESOURCE_MEM,
  83         },
  84         {
  85                 .start          = OMAP3430_ISP_H3A_BASE,
  86                 .end            = OMAP3430_ISP_H3A_END,
  87                 .flags          = IORESOURCE_MEM,
  88         },
  89         {
  90                 .start          = OMAP3430_ISP_PREV_BASE,
  91                 .end            = OMAP3430_ISP_PREV_END,
  92                 .flags          = IORESOURCE_MEM,
  93         },
  94         {
  95                 .start          = OMAP3430_ISP_RESZ_BASE,
  96                 .end            = OMAP3430_ISP_RESZ_END,
  97                 .flags          = IORESOURCE_MEM,
  98         },
  99         {
 100                 .start          = OMAP3430_ISP_SBL_BASE,
 101                 .end            = OMAP3430_ISP_SBL_END,
 102                 .flags          = IORESOURCE_MEM,
 103         },
 104         {
 105                 .start          = OMAP3430_ISP_CSI2A_BASE,
 106                 .end            = OMAP3430_ISP_CSI2A_END,
 107                 .flags          = IORESOURCE_MEM,
 108         },
 109         {
 110                 .start          = OMAP3430_ISP_CSI2PHY_BASE,
 111                 .end            = OMAP3430_ISP_CSI2PHY_END,
 112                 .flags          = IORESOURCE_MEM,
 113         },
 114         {
 115                 .start          = INT_34XX_CAM_IRQ,
 116                 .flags          = IORESOURCE_IRQ,
 117         }
 118 };
 119
 120 static struct platform_device omap3isp_device = {
 121         .name           = "omap3isp",
 122         .id             = -1,
 123         .num_resources  = ARRAY_SIZE(omap3isp_resources),
 124         .resource       = omap3isp_resources,
 125 };
 126
 127 static inline void omap_init_camera(void)
 128 {
 129         platform_device_register(&omap3isp_device);
 130 }
 131 #else
 132 static inline void omap_init_camera(void)
 133 {
 134 }
 135 #endif
 136
 137 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
 138
 139 #define MBOX_REG_SIZE   0x120
 140
 141 static struct resource omap2_mbox_resources[] = {
 142         {
 143                 .start          = OMAP24XX_MAILBOX_BASE,
 144                 .end            = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
 145                 .flags          = IORESOURCE_MEM,
 146         },
 147         {
 148                 .start          = INT_24XX_MAIL_U0_MPU,
 149                 .flags          = IORESOURCE_IRQ,
 150         },
 151         {
 152                 .start          = INT_24XX_MAIL_U3_MPU,
 153                 .flags          = IORESOURCE_IRQ,
 154         },
 155 };
 156
 157 static struct resource omap3_mbox_resources[] = {
 158         {
 159                 .start          = OMAP34XX_MAILBOX_BASE,
 160                 .end            = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
 161                 .flags          = IORESOURCE_MEM,
 162         },
 163         {
 164                 .start          = INT_24XX_MAIL_U0_MPU,
 165                 .flags          = IORESOURCE_IRQ,
 166         },
 167 };
 168
 169 static struct platform_device mbox_device = {
 170         .name           = "omap2-mailbox",
 171         .id             = -1,
 172 };
 173
 174 static inline void omap_init_mbox(void)
 175 {
 176         if (cpu_is_omap2420()) {
 177                 mbox_device.num_resources = ARRAY_SIZE(omap2_mbox_resources);
 178                 mbox_device.resource = omap2_mbox_resources;
 179         } else if (cpu_is_omap3430()) {
 180                 mbox_device.num_resources = ARRAY_SIZE(omap3_mbox_resources);
 181                 mbox_device.resource = omap3_mbox_resources;
 182         } else {
 183                 pr_err("%s: platform not supported\n", __func__);
 184                 return;
 185         }
 186         platform_device_register(&mbox_device);
 187 }
 188 #else
 189 static inline void omap_init_mbox(void) { }
 190 #endif /* CONFIG_OMAP_MBOX_FWK */
 191
 192 #if defined(CONFIG_OMAP_STI)
 193
 194 #if defined(CONFIG_ARCH_OMAP2)
 195
 196 #define OMAP2_STI_BASE          0x48068000
 197 #define OMAP2_STI_CHANNEL_BASE  0x54000000
 198 #define OMAP2_STI_IRQ           4
 199
 200 static struct resource sti_resources[] = {
 201         {
 202                 .start          = OMAP2_STI_BASE,
 203                 .end            = OMAP2_STI_BASE + 0x7ff,
 204                 .flags          = IORESOURCE_MEM,
 205         },
 206         {
 207                 .start          = OMAP2_STI_CHANNEL_BASE,
 208                 .end            = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1,
 209                 .flags          = IORESOURCE_MEM,
 210         },
 211         {
 212                 .start          = OMAP2_STI_IRQ,
 213                 .flags          = IORESOURCE_IRQ,
 214         }
 215 };
 216 #elif defined(CONFIG_ARCH_OMAP3)
 217
 218 #define OMAP3_SDTI_BASE         0x54500000
 219 #define OMAP3_SDTI_CHANNEL_BASE 0x54600000
 220
 221 static struct resource sti_resources[] = {
 222         {
 223                 .start          = OMAP3_SDTI_BASE,
 224                 .end            = OMAP3_SDTI_BASE + 0xFFF,
 225                 .flags          = IORESOURCE_MEM,
 226         },
 227         {
 228                 .start          = OMAP3_SDTI_CHANNEL_BASE,
 229                 .end            = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
 230                 .flags          = IORESOURCE_MEM,
 231         }
 232 };
 233
 234 #endif
 235
 236 static struct platform_device sti_device = {
 237         .name           = "sti",
 238         .id             = -1,
 239         .num_resources  = ARRAY_SIZE(sti_resources),
 240         .resource       = sti_resources,
 241 };
 242
 243 static inline void omap_init_sti(void)
 244 {
 245         platform_device_register(&sti_device);
 246 }
 247 #else
 248 static inline void omap_init_sti(void) {}
 249 #endif
 250
 251 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 252
 253 #include <mach/mcspi.h>
 254
 255 #define OMAP2_MCSPI1_BASE               0x48098000
 256 #define OMAP2_MCSPI2_BASE               0x4809a000
 257 #define OMAP2_MCSPI3_BASE               0x480b8000
 258 #define OMAP2_MCSPI4_BASE               0x480ba000
 259
 260 #define OMAP4_MCSPI1_BASE               0x48098100
 261 #define OMAP4_MCSPI2_BASE               0x4809a100
 262 #define OMAP4_MCSPI3_BASE               0x480b8100
 263 #define OMAP4_MCSPI4_BASE               0x480ba100
 264
 265 static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
 266         .num_cs         = 4,
 267 };
 268
 269 static struct resource omap2_mcspi1_resources[] = {
 270         {
 271                 .start          = OMAP2_MCSPI1_BASE,
 272                 .end            = OMAP2_MCSPI1_BASE + 0xff,
 273                 .flags          = IORESOURCE_MEM,
 274         },
 275 };
 276
 277 static struct platform_device omap2_mcspi1 = {
 278         .name           = "omap2_mcspi",
 279         .id             = 1,
 280         .num_resources  = ARRAY_SIZE(omap2_mcspi1_resources),
 281         .resource       = omap2_mcspi1_resources,
 282         .dev            = {
 283                 .platform_data = &omap2_mcspi1_config,
 284         },
 285 };
 286
 287 static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
 288         .num_cs         = 2,
 289 };
 290
 291 static struct resource omap2_mcspi2_resources[] = {
 292         {
 293                 .start          = OMAP2_MCSPI2_BASE,
 294                 .end            = OMAP2_MCSPI2_BASE + 0xff,
 295                 .flags          = IORESOURCE_MEM,
 296         },
 297 };
 298
 299 static struct platform_device omap2_mcspi2 = {
 300         .name           = "omap2_mcspi",
 301         .id             = 2,
 302         .num_resources  = ARRAY_SIZE(omap2_mcspi2_resources),
 303         .resource       = omap2_mcspi2_resources,
 304         .dev            = {
 305                 .platform_data = &omap2_mcspi2_config,
 306         },
 307 };
 308
 309 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
 310         defined(CONFIG_ARCH_OMAP4)
 311 static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
 312         .num_cs         = 2,
 313 };
 314
 315 static struct resource omap2_mcspi3_resources[] = {
 316         {
 317         .start          = OMAP2_MCSPI3_BASE,
 318         .end            = OMAP2_MCSPI3_BASE + 0xff,
 319         .flags          = IORESOURCE_MEM,
 320         },
 321 };
 322
 323 static struct platform_device omap2_mcspi3 = {
 324         .name           = "omap2_mcspi",
 325         .id             = 3,
 326         .num_resources  = ARRAY_SIZE(omap2_mcspi3_resources),
 327         .resource       = omap2_mcspi3_resources,
 328         .dev            = {
 329                 .platform_data = &omap2_mcspi3_config,
 330         },
 331 };
 332 #endif
 333
 334 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 335 static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
 336         .num_cs         = 1,
 337 };
 338
 339 static struct resource omap2_mcspi4_resources[] = {
 340         {
 341                 .start          = OMAP2_MCSPI4_BASE,
 342                 .end            = OMAP2_MCSPI4_BASE + 0xff,
 343                 .flags          = IORESOURCE_MEM,
 344         },
 345 };
 346
 347 static struct platform_device omap2_mcspi4 = {
 348         .name           = "omap2_mcspi",
 349         .id             = 4,
 350         .num_resources  = ARRAY_SIZE(omap2_mcspi4_resources),
 351         .resource       = omap2_mcspi4_resources,
 352         .dev            = {
 353                 .platform_data = &omap2_mcspi4_config,
 354         },
 355 };
 356 #endif
 357
 358 static void omap_init_mcspi(void)
 359 {
 360         if (cpu_is_omap44xx()) {
 361                 omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
 362                 omap2_mcspi1_resources[0].end   = OMAP4_MCSPI1_BASE + 0xff;
 363                 omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
 364                 omap2_mcspi2_resources[0].end   = OMAP4_MCSPI2_BASE + 0xff;
 365                 omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
 366                 omap2_mcspi3_resources[0].end   = OMAP4_MCSPI3_BASE + 0xff;
 367                 omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
 368                 omap2_mcspi4_resources[0].end   = OMAP4_MCSPI4_BASE + 0xff;
 369         }
 370         platform_device_register(&omap2_mcspi1);
 371         platform_device_register(&omap2_mcspi2);
 372 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
 373         defined(CONFIG_ARCH_OMAP4)
 374         if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
 375                 platform_device_register(&omap2_mcspi3);
 376 #endif
 377 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 378         if (cpu_is_omap343x() || cpu_is_omap44xx())
 379                 platform_device_register(&omap2_mcspi4);
 380 #endif
 381 }
 382
 383 #else
 384 static inline void omap_init_mcspi(void) {}
 385 #endif
 386
 387 #ifdef CONFIG_OMAP_SHA1_MD5
 388 static struct resource sha1_md5_resources[] = {
 389         {
 390                 .start  = OMAP24XX_SEC_SHA1MD5_BASE,
 391                 .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
 392                 .flags  = IORESOURCE_MEM,
 393         },
 394         {
 395                 .start  = INT_24XX_SHA1MD5,
 396                 .flags  = IORESOURCE_IRQ,
 397         }
 398 };
 399
 400 static struct platform_device sha1_md5_device = {
 401         .name           = "OMAP SHA1/MD5",
 402         .id             = -1,
 403         .num_resources  = ARRAY_SIZE(sha1_md5_resources),
 404         .resource       = sha1_md5_resources,
 405 };
 406
 407 static void omap_init_sha1_md5(void)
 408 {
 409         platform_device_register(&sha1_md5_device);
 410 }
 411 #else
 412 static inline void omap_init_sha1_md5(void) { }
 413 #endif
 414
 415 /*-------------------------------------------------------------------------*/
 416
 417 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 418
 419 #define MMCHS_SYSCONFIG                 0x0010
 420 #define MMCHS_SYSCONFIG_SWRESET         (1 << 1)
 421 #define MMCHS_SYSSTATUS                 0x0014
 422 #define MMCHS_SYSSTATUS_RESETDONE       (1 << 0)
 423
 424 static struct platform_device dummy_pdev = {
 425         .dev = {
 426                 .bus = &platform_bus_type,
 427         },
 428 };
 429
 430 /**
 431  * omap_hsmmc_reset() - Full reset of each HS-MMC controller
 432  *
 433  * Ensure that each MMC controller is fully reset.  Controllers
 434  * left in an unknown state (by bootloader) may prevent retention
 435  * or OFF-mode.  This is especially important in cases where the
 436  * MMC driver is not enabled, _or_ built as a module.
 437  *
 438  * In order for reset to work, interface, functional and debounce
 439  * clocks must be enabled.  The debounce clock comes from func_32k_clk
 440  * and is not under SW control, so we only enable i- and f-clocks.
 441  **/
 442 static void __init omap_hsmmc_reset(void)
 443 {
 444         u32 i, nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
 445                 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
 446
 447         for (i = 0; i < nr_controllers; i++) {
 448                 u32 v, base = 0;
 449                 struct clk *iclk, *fclk;
 450                 struct device *dev = &dummy_pdev.dev;
 451
 452                 switch (i) {
 453                 case 0:
 454                         base = OMAP2_MMC1_BASE;
 455                         break;
 456                 case 1:
 457                         base = OMAP2_MMC2_BASE;
 458                         break;
 459                 case 2:
 460                         base = OMAP3_MMC3_BASE;
 461                         break;
 462                 case 3:
 463                         if (!cpu_is_omap44xx())
 464                                 return;
 465                         base = OMAP4_MMC4_BASE;
 466                         break;
 467                 case 4:
 468                         if (!cpu_is_omap44xx())
 469                                 return;
 470                         base = OMAP4_MMC5_BASE;
 471                         break;
 472                 }
 473
 474                 if (cpu_is_omap44xx())
 475                         base += OMAP4_MMC_REG_OFFSET;
 476
 477                 dummy_pdev.id = i;
 478                 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
 479                 iclk = clk_get(dev, "ick");
 480                 if (iclk && clk_enable(iclk))
 481                         iclk = NULL;
 482
 483                 fclk = clk_get(dev, "fck");
 484                 if (fclk && clk_enable(fclk))
 485                         fclk = NULL;
 486
 487                 if (!iclk || !fclk) {
 488                         printk(KERN_WARNING
 489                                "%s: Unable to enable clocks for MMC%d, "
 490                                "cannot reset.\n",  __func__, i);
 491                         break;
 492                 }
 493
 494                 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
 495                 v = omap_readl(base + MMCHS_SYSSTATUS);
 496                 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
 497                          MMCHS_SYSSTATUS_RESETDONE))
 498                         cpu_relax();
 499
 500                 if (fclk) {
 501                         clk_disable(fclk);
 502                         clk_put(fclk);
 503                 }
 504                 if (iclk) {
 505                         clk_disable(iclk);
 506                         clk_put(iclk);
 507                 }
 508         }
 509 }
 510 #else
 511 static inline void omap_hsmmc_reset(void) {}
 512 #endif
 513
 514 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
 515         defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 516
 517 static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
 518                         int controller_nr)
 519 {
 520         if (cpu_is_omap2420() && controller_nr == 0) {
 521                 omap_cfg_reg(H18_24XX_MMC_CMD);
 522                 omap_cfg_reg(H15_24XX_MMC_CLKI);
 523                 omap_cfg_reg(G19_24XX_MMC_CLKO);
 524                 omap_cfg_reg(F20_24XX_MMC_DAT0);
 525                 omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
 526                 omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
 527                 if (mmc_controller->slots[0].wires == 4) {
 528                         omap_cfg_reg(H14_24XX_MMC_DAT1);
 529                         omap_cfg_reg(E19_24XX_MMC_DAT2);
 530                         omap_cfg_reg(D19_24XX_MMC_DAT3);
 531                         omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
 532                         omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
 533                         omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
 534                 }
 535
 536                 /*
 537                  * Use internal loop-back in MMC/SDIO Module Input Clock
 538                  * selection
 539                  */
 540                 if (mmc_controller->slots[0].internal_clock) {
 541                         u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 542                         v |= (1 << 24);
 543                         omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
 544                 }
 545         }
 546
 547         if (cpu_is_omap3430()) {
 548                 if (controller_nr == 0) {
 549                         omap_cfg_reg(N28_3430_MMC1_CLK);
 550                         omap_cfg_reg(M27_3430_MMC1_CMD);
 551                         omap_cfg_reg(N27_3430_MMC1_DAT0);
 552                         if (mmc_controller->slots[0].wires == 4 ||
 553                                 mmc_controller->slots[0].wires == 8) {
 554                                 omap_cfg_reg(N26_3430_MMC1_DAT1);
 555                                 omap_cfg_reg(N25_3430_MMC1_DAT2);
 556                                 omap_cfg_reg(P28_3430_MMC1_DAT3);
 557                         }
 558                         if (mmc_controller->slots[0].wires == 8) {
 559                                 omap_cfg_reg(P27_3430_MMC1_DAT4);
 560                                 omap_cfg_reg(P26_3430_MMC1_DAT5);
 561                                 omap_cfg_reg(R27_3430_MMC1_DAT6);
 562                                 omap_cfg_reg(R25_3430_MMC1_DAT7);
 563                         }
 564                 }
 565                 if (controller_nr == 1) {
 566                         /* MMC2 */
 567                         omap_cfg_reg(AE2_3430_MMC2_CLK);
 568                         omap_cfg_reg(AG5_3430_MMC2_CMD);
 569                         omap_cfg_reg(AH5_3430_MMC2_DAT0);
 570
 571                         /*
 572                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
 573                          * in the board-*.c files
 574                          */
 575                         if (mmc_controller->slots[0].wires == 4 ||
 576                                 mmc_controller->slots[0].wires == 8) {
 577                                 omap_cfg_reg(AH4_3430_MMC2_DAT1);
 578                                 omap_cfg_reg(AG4_3430_MMC2_DAT2);
 579                                 omap_cfg_reg(AF4_3430_MMC2_DAT3);
 580                         }
 581                 }
 582
 583                 /*
 584                  * For MMC3 the pins need to be muxed in the board-*.c files
 585                  */
 586         }
 587 }
 588
 589 void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
 590                         int nr_controllers)
 591 {
 592         int i;
 593         char *name;
 594
 595         for (i = 0; i < nr_controllers; i++) {
 596                 unsigned long base, size;
 597                 unsigned int irq = 0;
 598
 599                 if (!mmc_data[i])
 600                         continue;
 601
 602                 omap2_mmc_mux(mmc_data[i], i);
 603
 604                 switch (i) {
 605                 case 0:
 606                         base = OMAP2_MMC1_BASE;
 607                         irq = INT_24XX_MMC_IRQ;
 608                         break;
 609                 case 1:
 610                         base = OMAP2_MMC2_BASE;
 611                         irq = INT_24XX_MMC2_IRQ;
 612                         break;
 613                 case 2:
 614                         if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
 615                                 return;
 616                         base = OMAP3_MMC3_BASE;
 617                         irq = INT_34XX_MMC3_IRQ;
 618                         break;
 619                 case 3:
 620                         if (!cpu_is_omap44xx())
 621                                 return;
 622                         base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
 623                         irq = INT_44XX_MMC4_IRQ;
 624                         break;
 625                 case 4:
 626                         if (!cpu_is_omap44xx())
 627                                 return;
 628                         base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
 629                         irq = INT_44XX_MMC5_IRQ;
 630                         break;
 631                 default:
 632                         continue;
 633                 }
 634
 635                 if (cpu_is_omap2420()) {
 636                         size = OMAP2420_MMC_SIZE;
 637                         name = "mmci-omap";
 638                 } else if (cpu_is_omap44xx()) {
 639                         if (i < 3) {
 640                                 base += OMAP4_MMC_REG_OFFSET;
 641                                 irq += IRQ_GIC_START;
 642                         }
 643                         size = OMAP4_HSMMC_SIZE;
 644                         name = "mmci-omap-hs";
 645                 } else {
 646                         size = OMAP3_HSMMC_SIZE;
 647                         name = "mmci-omap-hs";
 648                 }
 649                 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
 650         };
 651 }
 652
 653 #endif
 654
 655 /*-------------------------------------------------------------------------*/
 656
 657 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
 658 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
 659 #define OMAP_HDQ_BASE   0x480B2000
 660 #endif
 661 static struct resource omap_hdq_resources[] = {
 662         {
 663                 .start          = OMAP_HDQ_BASE,
 664                 .end            = OMAP_HDQ_BASE + 0x1C,
 665                 .flags          = IORESOURCE_MEM,
 666         },
 667         {
 668                 .start          = INT_24XX_HDQ_IRQ,
 669                 .flags          = IORESOURCE_IRQ,
 670         },
 671 };
 672 static struct platform_device omap_hdq_dev = {
 673         .name = "omap_hdq",
 674         .id = 0,
 675         .dev = {
 676                 .platform_data = NULL,
 677         },
 678         .num_resources  = ARRAY_SIZE(omap_hdq_resources),
 679         .resource       = omap_hdq_resources,
 680 };
 681 static inline void omap_hdq_init(void)
 682 {
 683         (void) platform_device_register(&omap_hdq_dev);
 684 }
 685 #else
 686 static inline void omap_hdq_init(void) {}
 687 #endif
 688
 689 /*-------------------------------------------------------------------------*/
 690
 691 static int __init omap2_init_devices(void)
 692 {
 693         /* please keep these calls, and their implementations above,
 694          * in alphabetical order so they're easier to sort through.
 695          */
 696         omap_hsmmc_reset();
 697         omap_init_camera();
 698         omap_init_mbox();
 699         omap_init_mcspi();
 700         omap_hdq_init();
 701         omap_init_sti();
 702         omap_init_sha1_md5();
 703
 704         return 0;
 705 }
 706 arch_initcall(omap2_init_devices);