arch/arm/mach-omap2/devices.c

   1 /*
   2  * linux/arch/arm/mach-omap2/devices.c
   3  *
   4  * OMAP2 platform device setup/initialization
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/io.h>
  17 #include <linux/clk.h>
  18
  19 #include <mach/hardware.h>
  20 #include <asm/mach-types.h>
  21 #include <asm/mach/map.h>
  22
  23 #include <plat/control.h>
  24 #include <plat/tc.h>
  25 #include <plat/board.h>
  26 #include <plat/mux.h>
  27 #include <mach/gpio.h>
  28 #include <plat/mmc.h>
  29 #include <plat/dma.h>
  30
  31 #include "mux.h"
  32
  33 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
  34
  35 static struct resource cam_resources[] = {
  36         {
  37                 .start          = OMAP24XX_CAMERA_BASE,
  38                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
  39                 .flags          = IORESOURCE_MEM,
  40         },
  41         {
  42                 .start          = INT_24XX_CAM_IRQ,
  43                 .flags          = IORESOURCE_IRQ,
  44         }
  45 };
  46
  47 static struct platform_device omap_cam_device = {
  48         .name           = "omap24xxcam",
  49         .id             = -1,
  50         .num_resources  = ARRAY_SIZE(cam_resources),
  51         .resource       = cam_resources,
  52 };
  53
  54 static inline void omap_init_camera(void)
  55 {
  56         platform_device_register(&omap_cam_device);
  57 }
  58
  59 #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
  60
  61 static struct resource omap3isp_resources[] = {
  62         {
  63                 .start          = OMAP3430_ISP_BASE,
  64                 .end            = OMAP3430_ISP_END,
  65                 .flags          = IORESOURCE_MEM,
  66         },
  67         {
  68                 .start          = OMAP3430_ISP_CBUFF_BASE,
  69                 .end            = OMAP3430_ISP_CBUFF_END,
  70                 .flags          = IORESOURCE_MEM,
  71         },
  72         {
  73                 .start          = OMAP3430_ISP_CCP2_BASE,
  74                 .end            = OMAP3430_ISP_CCP2_END,
  75                 .flags          = IORESOURCE_MEM,
  76         },
  77         {
  78                 .start          = OMAP3430_ISP_CCDC_BASE,
  79                 .end            = OMAP3430_ISP_CCDC_END,
  80                 .flags          = IORESOURCE_MEM,
  81         },
  82         {
  83                 .start          = OMAP3430_ISP_HIST_BASE,
  84                 .end            = OMAP3430_ISP_HIST_END,
  85                 .flags          = IORESOURCE_MEM,
  86         },
  87         {
  88                 .start          = OMAP3430_ISP_H3A_BASE,
  89                 .end            = OMAP3430_ISP_H3A_END,
  90                 .flags          = IORESOURCE_MEM,
  91         },
  92         {
  93                 .start          = OMAP3430_ISP_PREV_BASE,
  94                 .end            = OMAP3430_ISP_PREV_END,
  95                 .flags          = IORESOURCE_MEM,
  96         },
  97         {
  98                 .start          = OMAP3430_ISP_RESZ_BASE,
  99                 .end            = OMAP3430_ISP_RESZ_END,
 100                 .flags          = IORESOURCE_MEM,
 101         },
 102         {
 103                 .start          = OMAP3430_ISP_SBL_BASE,
 104                 .end            = OMAP3430_ISP_SBL_END,
 105                 .flags          = IORESOURCE_MEM,
 106         },
 107         {
 108                 .start          = OMAP3430_ISP_CSI2A_BASE,
 109                 .end            = OMAP3430_ISP_CSI2A_END,
 110                 .flags          = IORESOURCE_MEM,
 111         },
 112         {
 113                 .start          = OMAP3430_ISP_CSI2PHY_BASE,
 114                 .end            = OMAP3430_ISP_CSI2PHY_END,
 115                 .flags          = IORESOURCE_MEM,
 116         },
 117         {
 118                 .start          = INT_34XX_CAM_IRQ,
 119                 .flags          = IORESOURCE_IRQ,
 120         }
 121 };
 122
 123 static struct platform_device omap3isp_device = {
 124         .name           = "omap3isp",
 125         .id             = -1,
 126         .num_resources  = ARRAY_SIZE(omap3isp_resources),
 127         .resource       = omap3isp_resources,
 128 };
 129
 130 static inline void omap_init_camera(void)
 131 {
 132         platform_device_register(&omap3isp_device);
 133 }
 134 #else
 135 static inline void omap_init_camera(void)
 136 {
 137 }
 138 #endif
 139
 140 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
 141
 142 #define MBOX_REG_SIZE   0x120
 143
 144 #ifdef CONFIG_ARCH_OMAP2
 145 static struct resource omap2_mbox_resources[] = {
 146         {
 147                 .start          = OMAP24XX_MAILBOX_BASE,
 148                 .end            = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
 149                 .flags          = IORESOURCE_MEM,
 150         },
 151         {
 152                 .start          = INT_24XX_MAIL_U0_MPU,
 153                 .flags          = IORESOURCE_IRQ,
 154         },
 155         {
 156                 .start          = INT_24XX_MAIL_U3_MPU,
 157                 .flags          = IORESOURCE_IRQ,
 158         },
 159 };
 160 static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
 161 #else
 162 #define omap2_mbox_resources            NULL
 163 #define omap2_mbox_resources_sz         0
 164 #endif
 165
 166 #ifdef CONFIG_ARCH_OMAP3
 167 static struct resource omap3_mbox_resources[] = {
 168         {
 169                 .start          = OMAP34XX_MAILBOX_BASE,
 170                 .end            = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
 171                 .flags          = IORESOURCE_MEM,
 172         },
 173         {
 174                 .start          = INT_24XX_MAIL_U0_MPU,
 175                 .flags          = IORESOURCE_IRQ,
 176         },
 177 };
 178 static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
 179 #else
 180 #define omap3_mbox_resources            NULL
 181 #define omap3_mbox_resources_sz         0
 182 #endif
 183
 184 #ifdef CONFIG_ARCH_OMAP4
 185
 186 #define OMAP4_MBOX_REG_SIZE     0x130
 187 static struct resource omap4_mbox_resources[] = {
 188         {
 189                 .start          = OMAP44XX_MAILBOX_BASE,
 190                 .end            = OMAP44XX_MAILBOX_BASE +
 191                                         OMAP4_MBOX_REG_SIZE - 1,
 192                 .flags          = IORESOURCE_MEM,
 193         },
 194         {
 195                 .start          = OMAP44XX_IRQ_MAIL_U0,
 196                 .flags          = IORESOURCE_IRQ,
 197         },
 198 };
 199 static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
 200 #else
 201 #define omap4_mbox_resources            NULL
 202 #define omap4_mbox_resources_sz         0
 203 #endif
 204
 205 static struct platform_device mbox_device = {
 206         .name           = "omap2-mailbox",
 207         .id             = -1,
 208 };
 209
 210 static inline void omap_init_mbox(void)
 211 {
 212         if (cpu_is_omap24xx()) {
 213                 mbox_device.resource = omap2_mbox_resources;
 214                 mbox_device.num_resources = omap2_mbox_resources_sz;
 215         } else if (cpu_is_omap34xx()) {
 216                 mbox_device.resource = omap3_mbox_resources;
 217                 mbox_device.num_resources = omap3_mbox_resources_sz;
 218         } else if (cpu_is_omap44xx()) {
 219                 mbox_device.resource = omap4_mbox_resources;
 220                 mbox_device.num_resources = omap4_mbox_resources_sz;
 221         } else {
 222                 pr_err("%s: platform not supported\n", __func__);
 223                 return;
 224         }
 225         platform_device_register(&mbox_device);
 226 }
 227 #else
 228 static inline void omap_init_mbox(void) { }
 229 #endif /* CONFIG_OMAP_MBOX_FWK */
 230
 231 #if defined(CONFIG_OMAP_STI)
 232
 233 #if defined(CONFIG_ARCH_OMAP2)
 234
 235 #define OMAP2_STI_BASE          0x48068000
 236 #define OMAP2_STI_CHANNEL_BASE  0x54000000
 237 #define OMAP2_STI_IRQ           4
 238
 239 static struct resource sti_resources[] = {
 240         {
 241                 .start          = OMAP2_STI_BASE,
 242                 .end            = OMAP2_STI_BASE + 0x7ff,
 243                 .flags          = IORESOURCE_MEM,
 244         },
 245         {
 246                 .start          = OMAP2_STI_CHANNEL_BASE,
 247                 .end            = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1,
 248                 .flags          = IORESOURCE_MEM,
 249         },
 250         {
 251                 .start          = OMAP2_STI_IRQ,
 252                 .flags          = IORESOURCE_IRQ,
 253         }
 254 };
 255 #elif defined(CONFIG_ARCH_OMAP3)
 256
 257 #define OMAP3_SDTI_BASE         0x54500000
 258 #define OMAP3_SDTI_CHANNEL_BASE 0x54600000
 259
 260 static struct resource sti_resources[] = {
 261         {
 262                 .start          = OMAP3_SDTI_BASE,
 263                 .end            = OMAP3_SDTI_BASE + 0xFFF,
 264                 .flags          = IORESOURCE_MEM,
 265         },
 266         {
 267                 .start          = OMAP3_SDTI_CHANNEL_BASE,
 268                 .end            = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
 269                 .flags          = IORESOURCE_MEM,
 270         }
 271 };
 272
 273 #endif
 274
 275 static struct platform_device sti_device = {
 276         .name           = "sti",
 277         .id             = -1,
 278         .num_resources  = ARRAY_SIZE(sti_resources),
 279         .resource       = sti_resources,
 280 };
 281
 282 static inline void omap_init_sti(void)
 283 {
 284         platform_device_register(&sti_device);
 285 }
 286 #else
 287 static inline void omap_init_sti(void) {}
 288 #endif
 289
 290 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 291
 292 #include <plat/mcspi.h>
 293
 294 #define OMAP2_MCSPI1_BASE               0x48098000
 295 #define OMAP2_MCSPI2_BASE               0x4809a000
 296 #define OMAP2_MCSPI3_BASE               0x480b8000
 297 #define OMAP2_MCSPI4_BASE               0x480ba000
 298
 299 #define OMAP4_MCSPI1_BASE               0x48098100
 300 #define OMAP4_MCSPI2_BASE               0x4809a100
 301 #define OMAP4_MCSPI3_BASE               0x480b8100
 302 #define OMAP4_MCSPI4_BASE               0x480ba100
 303
 304 static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
 305         .num_cs         = 4,
 306 };
 307
 308 static struct resource omap2_mcspi1_resources[] = {
 309         {
 310                 .start          = OMAP2_MCSPI1_BASE,
 311                 .end            = OMAP2_MCSPI1_BASE + 0xff,
 312                 .flags          = IORESOURCE_MEM,
 313         },
 314 };
 315
 316 static struct platform_device omap2_mcspi1 = {
 317         .name           = "omap2_mcspi",
 318         .id             = 1,
 319         .num_resources  = ARRAY_SIZE(omap2_mcspi1_resources),
 320         .resource       = omap2_mcspi1_resources,
 321         .dev            = {
 322                 .platform_data = &omap2_mcspi1_config,
 323         },
 324 };
 325
 326 static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
 327         .num_cs         = 2,
 328 };
 329
 330 static struct resource omap2_mcspi2_resources[] = {
 331         {
 332                 .start          = OMAP2_MCSPI2_BASE,
 333                 .end            = OMAP2_MCSPI2_BASE + 0xff,
 334                 .flags          = IORESOURCE_MEM,
 335         },
 336 };
 337
 338 static struct platform_device omap2_mcspi2 = {
 339         .name           = "omap2_mcspi",
 340         .id             = 2,
 341         .num_resources  = ARRAY_SIZE(omap2_mcspi2_resources),
 342         .resource       = omap2_mcspi2_resources,
 343         .dev            = {
 344                 .platform_data = &omap2_mcspi2_config,
 345         },
 346 };
 347
 348 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
 349         defined(CONFIG_ARCH_OMAP4)
 350 static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
 351         .num_cs         = 2,
 352 };
 353
 354 static struct resource omap2_mcspi3_resources[] = {
 355         {
 356         .start          = OMAP2_MCSPI3_BASE,
 357         .end            = OMAP2_MCSPI3_BASE + 0xff,
 358         .flags          = IORESOURCE_MEM,
 359         },
 360 };
 361
 362 static struct platform_device omap2_mcspi3 = {
 363         .name           = "omap2_mcspi",
 364         .id             = 3,
 365         .num_resources  = ARRAY_SIZE(omap2_mcspi3_resources),
 366         .resource       = omap2_mcspi3_resources,
 367         .dev            = {
 368                 .platform_data = &omap2_mcspi3_config,
 369         },
 370 };
 371 #endif
 372
 373 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 374 static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
 375         .num_cs         = 1,
 376 };
 377
 378 static struct resource omap2_mcspi4_resources[] = {
 379         {
 380                 .start          = OMAP2_MCSPI4_BASE,
 381                 .end            = OMAP2_MCSPI4_BASE + 0xff,
 382                 .flags          = IORESOURCE_MEM,
 383         },
 384 };
 385
 386 static struct platform_device omap2_mcspi4 = {
 387         .name           = "omap2_mcspi",
 388         .id             = 4,
 389         .num_resources  = ARRAY_SIZE(omap2_mcspi4_resources),
 390         .resource       = omap2_mcspi4_resources,
 391         .dev            = {
 392                 .platform_data = &omap2_mcspi4_config,
 393         },
 394 };
 395 #endif
 396
 397 #ifdef CONFIG_ARCH_OMAP4
 398 static inline void omap4_mcspi_fixup(void)
 399 {
 400         omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
 401         omap2_mcspi1_resources[0].end   = OMAP4_MCSPI1_BASE + 0xff;
 402         omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
 403         omap2_mcspi2_resources[0].end   = OMAP4_MCSPI2_BASE + 0xff;
 404         omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
 405         omap2_mcspi3_resources[0].end   = OMAP4_MCSPI3_BASE + 0xff;
 406         omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
 407         omap2_mcspi4_resources[0].end   = OMAP4_MCSPI4_BASE + 0xff;
 408 }
 409 #else
 410 static inline void omap4_mcspi_fixup(void)
 411 {
 412 }
 413 #endif
 414
 415 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
 416         defined(CONFIG_ARCH_OMAP4)
 417 static inline void omap2_mcspi3_init(void)
 418 {
 419         platform_device_register(&omap2_mcspi3);
 420 }
 421 #else
 422 static inline void omap2_mcspi3_init(void)
 423 {
 424 }
 425 #endif
 426
 427 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 428 static inline void omap2_mcspi4_init(void)
 429 {
 430         platform_device_register(&omap2_mcspi4);
 431 }
 432 #else
 433 static inline void omap2_mcspi4_init(void)
 434 {
 435 }
 436 #endif
 437
 438 static void omap_init_mcspi(void)
 439 {
 440         if (cpu_is_omap44xx())
 441                 omap4_mcspi_fixup();
 442
 443         platform_device_register(&omap2_mcspi1);
 444         platform_device_register(&omap2_mcspi2);
 445
 446         if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
 447                 omap2_mcspi3_init();
 448
 449         if (cpu_is_omap343x() || cpu_is_omap44xx())
 450                 omap2_mcspi4_init();
 451 }
 452
 453 #else
 454 static inline void omap_init_mcspi(void) {}
 455 #endif
 456
 457 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
 458
 459 #ifdef CONFIG_ARCH_OMAP2
 460 static struct resource omap2_sham_resources[] = {
 461         {
 462                 .start  = OMAP24XX_SEC_SHA1MD5_BASE,
 463                 .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
 464                 .flags  = IORESOURCE_MEM,
 465         },
 466         {
 467                 .start  = INT_24XX_SHA1MD5,
 468                 .flags  = IORESOURCE_IRQ,
 469         }
 470 };
 471 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
 472 #else
 473 #define omap2_sham_resources            NULL
 474 #define omap2_sham_resources_sz         0
 475 #endif
 476
 477 #ifdef CONFIG_ARCH_OMAP3
 478 static struct resource omap3_sham_resources[] = {
 479         {
 480                 .start  = OMAP34XX_SEC_SHA1MD5_BASE,
 481                 .end    = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
 482                 .flags  = IORESOURCE_MEM,
 483         },
 484         {
 485                 .start  = INT_34XX_SHA1MD52_IRQ,
 486                 .flags  = IORESOURCE_IRQ,
 487         },
 488         {
 489                 .start  = OMAP34XX_DMA_SHA1MD5_RX,
 490                 .flags  = IORESOURCE_DMA,
 491         }
 492 };
 493 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
 494 #else
 495 #define omap3_sham_resources            NULL
 496 #define omap3_sham_resources_sz         0
 497 #endif
 498
 499 static struct platform_device sham_device = {
 500         .name           = "omap-sham",
 501         .id             = -1,
 502 };
 503
 504 static void omap_init_sham(void)
 505 {
 506         if (cpu_is_omap24xx()) {
 507                 sham_device.resource = omap2_sham_resources;
 508                 sham_device.num_resources = omap2_sham_resources_sz;
 509         } else if (cpu_is_omap34xx()) {
 510                 sham_device.resource = omap3_sham_resources;
 511                 sham_device.num_resources = omap3_sham_resources_sz;
 512         } else {
 513                 pr_err("%s: platform not supported\n", __func__);
 514                 return;
 515         }
 516         platform_device_register(&sham_device);
 517 }
 518 #else
 519 static inline void omap_init_sham(void) { }
 520 #endif
 521
 522 /*-------------------------------------------------------------------------*/
 523
 524 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 525
 526 #define MMCHS_SYSCONFIG                 0x0010
 527 #define MMCHS_SYSCONFIG_SWRESET         (1 << 1)
 528 #define MMCHS_SYSSTATUS                 0x0014
 529 #define MMCHS_SYSSTATUS_RESETDONE       (1 << 0)
 530
 531 static struct platform_device dummy_pdev = {
 532         .dev = {
 533                 .bus = &platform_bus_type,
 534         },
 535 };
 536
 537 /**
 538  * omap_hsmmc_reset() - Full reset of each HS-MMC controller
 539  *
 540  * Ensure that each MMC controller is fully reset.  Controllers
 541  * left in an unknown state (by bootloader) may prevent retention
 542  * or OFF-mode.  This is especially important in cases where the
 543  * MMC driver is not enabled, _or_ built as a module.
 544  *
 545  * In order for reset to work, interface, functional and debounce
 546  * clocks must be enabled.  The debounce clock comes from func_32k_clk
 547  * and is not under SW control, so we only enable i- and f-clocks.
 548  **/
 549 static void __init omap_hsmmc_reset(void)
 550 {
 551         u32 i, nr_controllers;
 552
 553         if (cpu_is_omap242x())
 554                 return;
 555
 556         nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
 557                 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
 558
 559         for (i = 0; i < nr_controllers; i++) {
 560                 u32 v, base = 0;
 561                 struct clk *iclk, *fclk;
 562                 struct device *dev = &dummy_pdev.dev;
 563
 564                 switch (i) {
 565                 case 0:
 566                         base = OMAP2_MMC1_BASE;
 567                         break;
 568                 case 1:
 569                         base = OMAP2_MMC2_BASE;
 570                         break;
 571                 case 2:
 572                         base = OMAP3_MMC3_BASE;
 573                         break;
 574                 case 3:
 575                         if (!cpu_is_omap44xx())
 576                                 return;
 577                         base = OMAP4_MMC4_BASE;
 578                         break;
 579                 case 4:
 580                         if (!cpu_is_omap44xx())
 581                                 return;
 582                         base = OMAP4_MMC5_BASE;
 583                         break;
 584                 }
 585
 586                 if (cpu_is_omap44xx())
 587                         base += OMAP4_MMC_REG_OFFSET;
 588
 589                 dummy_pdev.id = i;
 590                 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
 591                 iclk = clk_get(dev, "ick");
 592                 if (iclk && clk_enable(iclk))
 593                         iclk = NULL;
 594
 595                 fclk = clk_get(dev, "fck");
 596                 if (fclk && clk_enable(fclk))
 597                         fclk = NULL;
 598
 599                 if (!iclk || !fclk) {
 600                         printk(KERN_WARNING
 601                                "%s: Unable to enable clocks for MMC%d, "
 602                                "cannot reset.\n",  __func__, i);
 603                         break;
 604                 }
 605
 606                 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
 607                 v = omap_readl(base + MMCHS_SYSSTATUS);
 608                 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
 609                          MMCHS_SYSSTATUS_RESETDONE))
 610                         cpu_relax();
 611
 612                 if (fclk) {
 613                         clk_disable(fclk);
 614                         clk_put(fclk);
 615                 }
 616                 if (iclk) {
 617                         clk_disable(iclk);
 618                         clk_put(iclk);
 619                 }
 620         }
 621 }
 622 #else
 623 static inline void omap_hsmmc_reset(void) {}
 624 #endif
 625
 626 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
 627         defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 628
 629 static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
 630                         int controller_nr)
 631 {
 632         if (cpu_is_omap2420() && controller_nr == 0) {
 633                 omap_cfg_reg(H18_24XX_MMC_CMD);
 634                 omap_cfg_reg(H15_24XX_MMC_CLKI);
 635                 omap_cfg_reg(G19_24XX_MMC_CLKO);
 636                 omap_cfg_reg(F20_24XX_MMC_DAT0);
 637                 omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
 638                 omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
 639                 if (mmc_controller->slots[0].wires == 4) {
 640                         omap_cfg_reg(H14_24XX_MMC_DAT1);
 641                         omap_cfg_reg(E19_24XX_MMC_DAT2);
 642                         omap_cfg_reg(D19_24XX_MMC_DAT3);
 643                         omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
 644                         omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
 645                         omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
 646                 }
 647
 648                 /*
 649                  * Use internal loop-back in MMC/SDIO Module Input Clock
 650                  * selection
 651                  */
 652                 if (mmc_controller->slots[0].internal_clock) {
 653                         u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 654                         v |= (1 << 24);
 655                         omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
 656                 }
 657         }
 658
 659         if (cpu_is_omap34xx()) {
 660                 if (controller_nr == 0) {
 661                         omap_mux_init_signal("sdmmc1_clk",
 662                                 OMAP_PIN_INPUT_PULLUP);
 663                         omap_mux_init_signal("sdmmc1_cmd",
 664                                 OMAP_PIN_INPUT_PULLUP);
 665                         omap_mux_init_signal("sdmmc1_dat0",
 666                                 OMAP_PIN_INPUT_PULLUP);
 667                         if (mmc_controller->slots[0].wires == 4 ||
 668                                 mmc_controller->slots[0].wires == 8) {
 669                                 omap_mux_init_signal("sdmmc1_dat1",
 670                                         OMAP_PIN_INPUT_PULLUP);
 671                                 omap_mux_init_signal("sdmmc1_dat2",
 672                                         OMAP_PIN_INPUT_PULLUP);
 673                                 omap_mux_init_signal("sdmmc1_dat3",
 674                                         OMAP_PIN_INPUT_PULLUP);
 675                         }
 676                         if (mmc_controller->slots[0].wires == 8) {
 677                                 omap_mux_init_signal("sdmmc1_dat4",
 678                                         OMAP_PIN_INPUT_PULLUP);
 679                                 omap_mux_init_signal("sdmmc1_dat5",
 680                                         OMAP_PIN_INPUT_PULLUP);
 681                                 omap_mux_init_signal("sdmmc1_dat6",
 682                                         OMAP_PIN_INPUT_PULLUP);
 683                                 omap_mux_init_signal("sdmmc1_dat7",
 684                                         OMAP_PIN_INPUT_PULLUP);
 685                         }
 686                 }
 687                 if (controller_nr == 1) {
 688                         /* MMC2 */
 689                         omap_mux_init_signal("sdmmc2_clk",
 690                                 OMAP_PIN_INPUT_PULLUP);
 691                         omap_mux_init_signal("sdmmc2_cmd",
 692                                 OMAP_PIN_INPUT_PULLUP);
 693                         omap_mux_init_signal("sdmmc2_dat0",
 694                                 OMAP_PIN_INPUT_PULLUP);
 695
 696                         /*
 697                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
 698                          * in the board-*.c files
 699                          */
 700                         if (mmc_controller->slots[0].wires == 4 ||
 701                                 mmc_controller->slots[0].wires == 8) {
 702                                 omap_mux_init_signal("sdmmc2_dat1",
 703                                         OMAP_PIN_INPUT_PULLUP);
 704                                 omap_mux_init_signal("sdmmc2_dat2",
 705                                         OMAP_PIN_INPUT_PULLUP);
 706                                 omap_mux_init_signal("sdmmc2_dat3",
 707                                         OMAP_PIN_INPUT_PULLUP);
 708                         }
 709                         if (mmc_controller->slots[0].wires == 8) {
 710                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
 711                                         OMAP_PIN_INPUT_PULLUP);
 712                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
 713                                         OMAP_PIN_INPUT_PULLUP);
 714                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
 715                                         OMAP_PIN_INPUT_PULLUP);
 716                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
 717                                         OMAP_PIN_INPUT_PULLUP);
 718                         }
 719                 }
 720
 721                 /*
 722                  * For MMC3 the pins need to be muxed in the board-*.c files
 723                  */
 724         }
 725 }
 726
 727 void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
 728                         int nr_controllers)
 729 {
 730         int i;
 731         char *name;
 732
 733         for (i = 0; i < nr_controllers; i++) {
 734                 unsigned long base, size;
 735                 unsigned int irq = 0;
 736
 737                 if (!mmc_data[i])
 738                         continue;
 739
 740                 omap2_mmc_mux(mmc_data[i], i);
 741
 742                 switch (i) {
 743                 case 0:
 744                         base = OMAP2_MMC1_BASE;
 745                         irq = INT_24XX_MMC_IRQ;
 746                         break;
 747                 case 1:
 748                         base = OMAP2_MMC2_BASE;
 749                         irq = INT_24XX_MMC2_IRQ;
 750                         break;
 751                 case 2:
 752                         if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
 753                                 return;
 754                         base = OMAP3_MMC3_BASE;
 755                         irq = INT_34XX_MMC3_IRQ;
 756                         break;
 757                 case 3:
 758                         if (!cpu_is_omap44xx())
 759                                 return;
 760                         base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
 761                         irq = OMAP44XX_IRQ_MMC4;
 762                         break;
 763                 case 4:
 764                         if (!cpu_is_omap44xx())
 765                                 return;
 766                         base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
 767                         irq = OMAP44XX_IRQ_MMC5;
 768                         break;
 769                 default:
 770                         continue;
 771                 }
 772
 773                 if (cpu_is_omap2420()) {
 774                         size = OMAP2420_MMC_SIZE;
 775                         name = "mmci-omap";
 776                 } else if (cpu_is_omap44xx()) {
 777                         if (i < 3) {
 778                                 base += OMAP4_MMC_REG_OFFSET;
 779                                 irq += OMAP44XX_IRQ_GIC_START;
 780                         }
 781                         size = OMAP4_HSMMC_SIZE;
 782                         name = "mmci-omap-hs";
 783                 } else {
 784                         size = OMAP3_HSMMC_SIZE;
 785                         name = "mmci-omap-hs";
 786                 }
 787                 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
 788         };
 789 }
 790
 791 #endif
 792
 793 /*-------------------------------------------------------------------------*/
 794
 795 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
 796 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
 797 #define OMAP_HDQ_BASE   0x480B2000
 798 #endif
 799 static struct resource omap_hdq_resources[] = {
 800         {
 801                 .start          = OMAP_HDQ_BASE,
 802                 .end            = OMAP_HDQ_BASE + 0x1C,
 803                 .flags          = IORESOURCE_MEM,
 804         },
 805         {
 806                 .start          = INT_24XX_HDQ_IRQ,
 807                 .flags          = IORESOURCE_IRQ,
 808         },
 809 };
 810 static struct platform_device omap_hdq_dev = {
 811         .name = "omap_hdq",
 812         .id = 0,
 813         .dev = {
 814                 .platform_data = NULL,
 815         },
 816         .num_resources  = ARRAY_SIZE(omap_hdq_resources),
 817         .resource       = omap_hdq_resources,
 818 };
 819 static inline void omap_hdq_init(void)
 820 {
 821         (void) platform_device_register(&omap_hdq_dev);
 822 }
 823 #else
 824 static inline void omap_hdq_init(void) {}
 825 #endif
 826
 827 /*-------------------------------------------------------------------------*/
 828
 829 static int __init omap2_init_devices(void)
 830 {
 831         /* please keep these calls, and their implementations above,
 832          * in alphabetical order so they're easier to sort through.
 833          */
 834         omap_hsmmc_reset();
 835         omap_init_camera();
 836         omap_init_mbox();
 837         omap_init_mcspi();
 838         omap_hdq_init();
 839         omap_init_sti();
 840         omap_init_sham();
 841
 842         return 0;
 843 }
 844 arch_initcall(omap2_init_devices);