2 * linux/arch/arm/mach-omap2/cpuidle34xx.c
4 * OMAP3 CPU IDLE Routines
6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Rajendra Nayak <rnayak@ti.com>
9 * Copyright (C) 2007 Texas Instruments, Inc.
10 * Karthik Dasu <karthik-dp@ti.com>
12 * Copyright (C) 2006 Nokia Corporation
13 * Tony Lindgren <tony@atomide.com>
15 * Copyright (C) 2005 Texas Instruments, Inc.
16 * Richard Woodruff <r-woodruff2@ti.com>
18 * Based on pm.c for omap2
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License version 2 as
22 * published by the Free Software Foundation.
25 #include <linux/sched.h>
26 #include <linux/cpuidle.h>
28 #include <plat/prcm.h>
29 #include <plat/irqs.h>
30 #include "powerdomain.h"
31 #include "clockdomain.h"
32 #include <plat/serial.h>
37 #ifdef CONFIG_CPU_IDLE
40 * The latencies/thresholds for various C states have
41 * to be configured from the respective board files.
42 * These are some default values (which might not provide
43 * the best power savings) used on boards which do not
44 * pass these details from the board file.
46 static struct cpuidle_params cpuidle_params_table[] = {
54 {1500 + 1800, 4000, 1},
56 {2500 + 7500, 12000, 1},
58 {3000 + 8500, 15000, 1},
60 {10000 + 30000, 300000, 1},
62 #define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
64 /* Mach specific information to be recorded in the C-state driver_data */
65 struct omap3_idle_statedata {
70 struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
72 struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
74 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
75 struct clockdomain *clkdm)
77 clkdm_allow_idle(clkdm);
81 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
82 struct clockdomain *clkdm)
84 clkdm_deny_idle(clkdm);
89 * omap3_enter_idle - Programs OMAP3 to enter the specified state
90 * @dev: cpuidle device
91 * @index: the index of state to be entered
93 * Called from the CPUidle framework to program the device to the
94 * specified target state selected by the governor.
96 static int omap3_enter_idle(struct cpuidle_device *dev,
99 struct omap3_idle_statedata *cx =
100 cpuidle_get_statedata(&dev->states[index]);
101 struct timespec ts_preidle, ts_postidle, ts_idle;
102 u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
105 /* Used to keep track of the total time in idle */
106 getnstimeofday(&ts_preidle);
111 pwrdm_set_next_pwrst(mpu_pd, mpu_state);
112 pwrdm_set_next_pwrst(core_pd, core_state);
114 if (omap_irq_pending() || need_resched())
115 goto return_sleep_time;
117 /* Deny idle for C1 */
119 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
120 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
123 /* Execute ARM wfi */
126 /* Re-allow idle for C1 */
128 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
129 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
133 getnstimeofday(&ts_postidle);
134 ts_idle = timespec_sub(ts_postidle, ts_preidle);
139 idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
142 /* Update cpuidle counters */
143 dev->last_residency = idle_time;
149 * next_valid_state - Find next valid C-state
150 * @dev: cpuidle device
151 * @index: Index of currently selected c-state
153 * If the state corresponding to index is valid, index is returned back
154 * to the caller. Else, this function searches for a lower c-state which is
155 * still valid (as defined in omap3_power_states[]) and returns its index.
157 * A state is valid if the 'valid' field is enabled and
158 * if it satisfies the enable_off_mode condition.
160 static int next_valid_state(struct cpuidle_device *dev,
163 struct cpuidle_state *curr = &dev->states[index];
164 struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr);
165 u32 mpu_deepest_state = PWRDM_POWER_RET;
166 u32 core_deepest_state = PWRDM_POWER_RET;
169 if (enable_off_mode) {
170 mpu_deepest_state = PWRDM_POWER_OFF;
172 * Erratum i583: valable for ES rev < Es1.2 on 3630.
173 * CORE OFF mode is not supported in a stable form, restrict
174 * instead the CORE state to RET.
176 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
177 core_deepest_state = PWRDM_POWER_OFF;
180 /* Check if current state is valid */
182 (cx->mpu_state >= mpu_deepest_state) &&
183 (cx->core_state >= core_deepest_state)) {
186 int idx = OMAP3_NUM_STATES - 1;
188 /* Reach the current state starting at highest C-state */
189 for (; idx >= 0; idx--) {
190 if (&dev->states[idx] == curr) {
196 /* Should never hit this condition */
197 WARN_ON(next_index == -1);
200 * Drop to next valid state.
201 * Start search from the next (lower) state.
204 for (; idx >= 0; idx--) {
205 cx = cpuidle_get_statedata(&dev->states[idx]);
207 (cx->mpu_state >= mpu_deepest_state) &&
208 (cx->core_state >= core_deepest_state)) {
214 * C1 is always valid.
215 * So, no need to check for 'next_index == -1' outside
224 * omap3_enter_idle_bm - Checks for any bus activity
225 * @dev: cpuidle device
226 * @index: array index of target state to be programmed
228 * This function checks for any pending activity and then programs
229 * the device to the specified or a safer state.
231 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
234 struct cpuidle_state *state = &dev->states[index];
236 u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
237 struct omap3_idle_statedata *cx;
240 if (!omap3_can_sleep()) {
241 new_state_idx = dev->safe_state_index;
246 * Prevent idle completely if CAM is active.
247 * CAM does not have wakeup capability in OMAP3.
249 cam_state = pwrdm_read_pwrst(cam_pd);
250 if (cam_state == PWRDM_POWER_ON) {
251 new_state_idx = dev->safe_state_index;
256 * FIXME: we currently manage device-specific idle states
257 * for PER and CORE in combination with CPU-specific
258 * idle states. This is wrong, and device-specific
259 * idle management needs to be separated out into
264 * Prevent PER off if CORE is not in retention or off as this
265 * would disable PER wakeups completely.
267 cx = cpuidle_get_statedata(state);
268 core_next_state = cx->core_state;
269 per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
270 if ((per_next_state == PWRDM_POWER_OFF) &&
271 (core_next_state > PWRDM_POWER_RET))
272 per_next_state = PWRDM_POWER_RET;
274 /* Are we changing PER target state? */
275 if (per_next_state != per_saved_state)
276 pwrdm_set_next_pwrst(per_pd, per_next_state);
278 new_state_idx = next_valid_state(dev, index);
281 ret = omap3_enter_idle(dev, new_state_idx);
283 /* Restore original PER state if it was modified */
284 if (per_next_state != per_saved_state)
285 pwrdm_set_next_pwrst(per_pd, per_saved_state);
290 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
292 void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
296 if (!cpuidle_board_params)
299 for (i = 0; i < OMAP3_NUM_STATES; i++) {
300 cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
301 cpuidle_params_table[i].exit_latency =
302 cpuidle_board_params[i].exit_latency;
303 cpuidle_params_table[i].target_residency =
304 cpuidle_board_params[i].target_residency;
309 struct cpuidle_driver omap3_idle_driver = {
310 .name = "omap3_idle",
311 .owner = THIS_MODULE,
314 /* Helper to fill the C-state common data and register the driver_data */
315 static inline struct omap3_idle_statedata *_fill_cstate(
316 struct cpuidle_device *dev,
317 int idx, const char *descr)
319 struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
320 struct cpuidle_state *state = &dev->states[idx];
322 state->exit_latency = cpuidle_params_table[idx].exit_latency;
323 state->target_residency = cpuidle_params_table[idx].target_residency;
324 state->flags = CPUIDLE_FLAG_TIME_VALID;
325 state->enter = omap3_enter_idle_bm;
326 cx->valid = cpuidle_params_table[idx].valid;
327 sprintf(state->name, "C%d", idx + 1);
328 strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
329 cpuidle_set_statedata(state, cx);
335 * omap3_idle_init - Init routine for OMAP3 idle
337 * Registers the OMAP3 specific cpuidle driver to the cpuidle
338 * framework with the valid set of states.
340 int __init omap3_idle_init(void)
342 struct cpuidle_device *dev;
343 struct omap3_idle_statedata *cx;
345 mpu_pd = pwrdm_lookup("mpu_pwrdm");
346 core_pd = pwrdm_lookup("core_pwrdm");
347 per_pd = pwrdm_lookup("per_pwrdm");
348 cam_pd = pwrdm_lookup("cam_pwrdm");
350 cpuidle_register_driver(&omap3_idle_driver);
351 dev = &per_cpu(omap3_idle_dev, smp_processor_id());
352 dev->safe_state_index = -1;
354 /* C1 . MPU WFI + Core active */
355 cx = _fill_cstate(dev, 0, "MPU ON + CORE ON");
356 (&dev->states[0])->enter = omap3_enter_idle;
357 dev->safe_state_index = 0;
358 cx->valid = 1; /* C1 is always valid */
359 cx->mpu_state = PWRDM_POWER_ON;
360 cx->core_state = PWRDM_POWER_ON;
362 /* C2 . MPU WFI + Core inactive */
363 cx = _fill_cstate(dev, 1, "MPU ON + CORE ON");
364 cx->mpu_state = PWRDM_POWER_ON;
365 cx->core_state = PWRDM_POWER_ON;
367 /* C3 . MPU CSWR + Core inactive */
368 cx = _fill_cstate(dev, 2, "MPU RET + CORE ON");
369 cx->mpu_state = PWRDM_POWER_RET;
370 cx->core_state = PWRDM_POWER_ON;
372 /* C4 . MPU OFF + Core inactive */
373 cx = _fill_cstate(dev, 3, "MPU OFF + CORE ON");
374 cx->mpu_state = PWRDM_POWER_OFF;
375 cx->core_state = PWRDM_POWER_ON;
377 /* C5 . MPU RET + Core RET */
378 cx = _fill_cstate(dev, 4, "MPU RET + CORE RET");
379 cx->mpu_state = PWRDM_POWER_RET;
380 cx->core_state = PWRDM_POWER_RET;
382 /* C6 . MPU OFF + Core RET */
383 cx = _fill_cstate(dev, 5, "MPU OFF + CORE RET");
384 cx->mpu_state = PWRDM_POWER_OFF;
385 cx->core_state = PWRDM_POWER_RET;
387 /* C7 . MPU OFF + Core OFF */
388 cx = _fill_cstate(dev, 6, "MPU OFF + CORE OFF");
390 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
391 * enable OFF mode in a stable form for previous revisions.
392 * We disable C7 state as a result.
394 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
396 pr_warn("%s: core off state C7 disabled due to i583\n",
399 cx->mpu_state = PWRDM_POWER_OFF;
400 cx->core_state = PWRDM_POWER_OFF;
402 dev->state_count = OMAP3_NUM_STATES;
403 if (cpuidle_register_device(dev)) {
404 printk(KERN_ERR "%s: CPUidle register device failed\n",
412 int __init omap3_idle_init(void)
416 #endif /* CONFIG_CPU_IDLE */