2 * linux/arch/arm/mach-omap2/cpuidle34xx.c
4 * OMAP3 CPU IDLE Routines
6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Rajendra Nayak <rnayak@ti.com>
9 * Copyright (C) 2007 Texas Instruments, Inc.
10 * Karthik Dasu <karthik-dp@ti.com>
12 * Copyright (C) 2006 Nokia Corporation
13 * Tony Lindgren <tony@atomide.com>
15 * Copyright (C) 2005 Texas Instruments, Inc.
16 * Richard Woodruff <r-woodruff2@ti.com>
18 * Based on pm.c for omap2
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License version 2 as
22 * published by the Free Software Foundation.
25 #include <linux/sched.h>
26 #include <linux/cpuidle.h>
28 #include <plat/prcm.h>
29 #include <plat/irqs.h>
30 #include <plat/powerdomain.h>
31 #include <plat/clockdomain.h>
32 #include <plat/control.h>
33 #include <plat/serial.h>
37 #ifdef CONFIG_CPU_IDLE
39 #define OMAP3_MAX_STATES 7
40 #define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
41 #define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
42 #define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
43 #define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
44 #define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
45 #define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
46 #define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
48 #define OMAP3_STATE_MAX OMAP3_STATE_C7
50 struct omap3_processor_cx {
61 struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
62 struct omap3_processor_cx current_cx_state;
63 struct powerdomain *mpu_pd, *core_pd, *per_pd;
64 struct powerdomain *cam_pd;
67 * The latencies/thresholds for various C states have
68 * to be configured from the respective board files.
69 * These are some default values (which might not provide
70 * the best power savings) used on boards which do not
71 * pass these details from the board file.
73 static struct cpuidle_params cpuidle_params_table[] = {
81 {1, 1500, 1800, 4000},
83 {1, 2500, 7500, 12000},
85 {1, 3000, 8500, 15000},
87 {1, 10000, 30000, 300000},
90 static int omap3_idle_bm_check(void)
92 if (!omap3_can_sleep())
97 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
98 struct clockdomain *clkdm)
100 omap2_clkdm_allow_idle(clkdm);
104 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
105 struct clockdomain *clkdm)
107 omap2_clkdm_deny_idle(clkdm);
112 * omap3_enter_idle - Programs OMAP3 to enter the specified state
113 * @dev: cpuidle device
114 * @state: The target state to be programmed
116 * Called from the CPUidle framework to program the device to the
117 * specified target state selected by the governor.
119 static int omap3_enter_idle(struct cpuidle_device *dev,
120 struct cpuidle_state *state)
122 struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
123 struct timespec ts_preidle, ts_postidle, ts_idle;
124 u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
126 current_cx_state = *cx;
128 /* Used to keep track of the total time in idle */
129 getnstimeofday(&ts_preidle);
134 pwrdm_set_next_pwrst(mpu_pd, mpu_state);
135 pwrdm_set_next_pwrst(core_pd, core_state);
137 if (omap_irq_pending() || need_resched())
138 goto return_sleep_time;
140 if (cx->type == OMAP3_STATE_C1) {
141 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
142 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
145 /* Execute ARM wfi */
148 if (cx->type == OMAP3_STATE_C1) {
149 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
150 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
154 getnstimeofday(&ts_postidle);
155 ts_idle = timespec_sub(ts_postidle, ts_preidle);
160 return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
164 * next_valid_state - Find next valid c-state
165 * @dev: cpuidle device
166 * @state: Currently selected c-state
168 * If the current state is valid, it is returned back to the caller.
169 * Else, this function searches for a lower c-state which is still
170 * valid (as defined in omap3_power_states[]).
172 static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev,
173 struct cpuidle_state *curr)
175 struct cpuidle_state *next = NULL;
176 struct omap3_processor_cx *cx;
178 cx = (struct omap3_processor_cx *)cpuidle_get_statedata(curr);
180 /* Check if current state is valid */
184 u8 idx = OMAP3_STATE_MAX;
187 * Reach the current state starting at highest C-state
189 for (; idx >= OMAP3_STATE_C1; idx--) {
190 if (&dev->states[idx] == curr) {
191 next = &dev->states[idx];
197 * Should never hit this condition.
199 WARN_ON(next == NULL);
202 * Drop to next valid state.
203 * Start search from the next (lower) state.
206 for (; idx >= OMAP3_STATE_C1; idx--) {
207 struct omap3_processor_cx *cx;
209 cx = cpuidle_get_statedata(&dev->states[idx]);
211 next = &dev->states[idx];
216 * C1 and C2 are always valid.
217 * So, no need to check for 'next==NULL' outside this loop.
225 * omap3_enter_idle_bm - Checks for any bus activity
226 * @dev: cpuidle device
227 * @state: The target state to be programmed
229 * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
230 * function checks for any pending activity and then programs the
231 * device to the specified or a safer state.
233 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
234 struct cpuidle_state *state)
236 struct cpuidle_state *new_state = next_valid_state(dev, state);
237 u32 core_next_state, per_next_state = 0, per_saved_state = 0;
239 struct omap3_processor_cx *cx;
242 if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
243 BUG_ON(!dev->safe_state);
244 new_state = dev->safe_state;
248 cx = cpuidle_get_statedata(state);
249 core_next_state = cx->core_state;
252 * FIXME: we currently manage device-specific idle states
253 * for PER and CORE in combination with CPU-specific
254 * idle states. This is wrong, and device-specific
255 * idle managment needs to be separated out into
260 * Prevent idle completely if CAM is active.
261 * CAM does not have wakeup capability in OMAP3.
263 cam_state = pwrdm_read_pwrst(cam_pd);
264 if (cam_state == PWRDM_POWER_ON) {
265 new_state = dev->safe_state;
270 * Prevent PER off if CORE is not in retention or off as this
271 * would disable PER wakeups completely.
273 per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
274 if ((per_next_state == PWRDM_POWER_OFF) &&
275 (core_next_state > PWRDM_POWER_RET)) {
276 per_next_state = PWRDM_POWER_RET;
277 pwrdm_set_next_pwrst(per_pd, per_next_state);
280 /* Are we changing PER target state? */
281 if (per_next_state != per_saved_state)
282 pwrdm_set_next_pwrst(per_pd, per_next_state);
285 dev->last_state = new_state;
286 ret = omap3_enter_idle(dev, new_state);
288 /* Restore original PER state if it was modified */
289 if (per_next_state != per_saved_state)
290 pwrdm_set_next_pwrst(per_pd, per_saved_state);
295 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
298 * omap3_cpuidle_update_states - Update the cpuidle states.
300 * Currently, this function toggles the validity of idle states based upon
301 * the flag 'enable_off_mode'. When the flag is set all states are valid.
302 * Else, states leading to OFF state set to be invalid.
304 void omap3_cpuidle_update_states(void)
308 for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
309 struct omap3_processor_cx *cx = &omap3_power_states[i];
311 if (enable_off_mode) {
314 if ((cx->mpu_state == PWRDM_POWER_OFF) ||
315 (cx->core_state == PWRDM_POWER_OFF))
321 void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
325 if (!cpuidle_board_params)
328 for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
329 cpuidle_params_table[i].valid =
330 cpuidle_board_params[i].valid;
331 cpuidle_params_table[i].sleep_latency =
332 cpuidle_board_params[i].sleep_latency;
333 cpuidle_params_table[i].wake_latency =
334 cpuidle_board_params[i].wake_latency;
335 cpuidle_params_table[i].threshold =
336 cpuidle_board_params[i].threshold;
341 /* omap3_init_power_states - Initialises the OMAP3 specific C states.
343 * Below is the desciption of each C state.
344 * C1 . MPU WFI + Core active
345 * C2 . MPU WFI + Core inactive
346 * C3 . MPU CSWR + Core inactive
347 * C4 . MPU OFF + Core inactive
348 * C5 . MPU CSWR + Core CSWR
349 * C6 . MPU OFF + Core CSWR
350 * C7 . MPU OFF + Core OFF
352 void omap_init_power_states(void)
354 /* C1 . MPU WFI + Core active */
355 omap3_power_states[OMAP3_STATE_C1].valid =
356 cpuidle_params_table[OMAP3_STATE_C1].valid;
357 omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
358 omap3_power_states[OMAP3_STATE_C1].sleep_latency =
359 cpuidle_params_table[OMAP3_STATE_C1].sleep_latency;
360 omap3_power_states[OMAP3_STATE_C1].wakeup_latency =
361 cpuidle_params_table[OMAP3_STATE_C1].wake_latency;
362 omap3_power_states[OMAP3_STATE_C1].threshold =
363 cpuidle_params_table[OMAP3_STATE_C1].threshold;
364 omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
365 omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
366 omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
368 /* C2 . MPU WFI + Core inactive */
369 omap3_power_states[OMAP3_STATE_C2].valid =
370 cpuidle_params_table[OMAP3_STATE_C2].valid;
371 omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
372 omap3_power_states[OMAP3_STATE_C2].sleep_latency =
373 cpuidle_params_table[OMAP3_STATE_C2].sleep_latency;
374 omap3_power_states[OMAP3_STATE_C2].wakeup_latency =
375 cpuidle_params_table[OMAP3_STATE_C2].wake_latency;
376 omap3_power_states[OMAP3_STATE_C2].threshold =
377 cpuidle_params_table[OMAP3_STATE_C2].threshold;
378 omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
379 omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
380 omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
381 CPUIDLE_FLAG_CHECK_BM;
383 /* C3 . MPU CSWR + Core inactive */
384 omap3_power_states[OMAP3_STATE_C3].valid =
385 cpuidle_params_table[OMAP3_STATE_C3].valid;
386 omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
387 omap3_power_states[OMAP3_STATE_C3].sleep_latency =
388 cpuidle_params_table[OMAP3_STATE_C3].sleep_latency;
389 omap3_power_states[OMAP3_STATE_C3].wakeup_latency =
390 cpuidle_params_table[OMAP3_STATE_C3].wake_latency;
391 omap3_power_states[OMAP3_STATE_C3].threshold =
392 cpuidle_params_table[OMAP3_STATE_C3].threshold;
393 omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
394 omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
395 omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
396 CPUIDLE_FLAG_CHECK_BM;
398 /* C4 . MPU OFF + Core inactive */
399 omap3_power_states[OMAP3_STATE_C4].valid =
400 cpuidle_params_table[OMAP3_STATE_C4].valid;
401 omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
402 omap3_power_states[OMAP3_STATE_C4].sleep_latency =
403 cpuidle_params_table[OMAP3_STATE_C4].sleep_latency;
404 omap3_power_states[OMAP3_STATE_C4].wakeup_latency =
405 cpuidle_params_table[OMAP3_STATE_C4].wake_latency;
406 omap3_power_states[OMAP3_STATE_C4].threshold =
407 cpuidle_params_table[OMAP3_STATE_C4].threshold;
408 omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
409 omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
410 omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
411 CPUIDLE_FLAG_CHECK_BM;
413 /* C5 . MPU CSWR + Core CSWR*/
414 omap3_power_states[OMAP3_STATE_C5].valid =
415 cpuidle_params_table[OMAP3_STATE_C5].valid;
416 omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
417 omap3_power_states[OMAP3_STATE_C5].sleep_latency =
418 cpuidle_params_table[OMAP3_STATE_C5].sleep_latency;
419 omap3_power_states[OMAP3_STATE_C5].wakeup_latency =
420 cpuidle_params_table[OMAP3_STATE_C5].wake_latency;
421 omap3_power_states[OMAP3_STATE_C5].threshold =
422 cpuidle_params_table[OMAP3_STATE_C5].threshold;
423 omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
424 omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
425 omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
426 CPUIDLE_FLAG_CHECK_BM;
428 /* C6 . MPU OFF + Core CSWR */
429 omap3_power_states[OMAP3_STATE_C6].valid =
430 cpuidle_params_table[OMAP3_STATE_C6].valid;
431 omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
432 omap3_power_states[OMAP3_STATE_C6].sleep_latency =
433 cpuidle_params_table[OMAP3_STATE_C6].sleep_latency;
434 omap3_power_states[OMAP3_STATE_C6].wakeup_latency =
435 cpuidle_params_table[OMAP3_STATE_C6].wake_latency;
436 omap3_power_states[OMAP3_STATE_C6].threshold =
437 cpuidle_params_table[OMAP3_STATE_C6].threshold;
438 omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
439 omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
440 omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
441 CPUIDLE_FLAG_CHECK_BM;
443 /* C7 . MPU OFF + Core OFF */
444 omap3_power_states[OMAP3_STATE_C7].valid =
445 cpuidle_params_table[OMAP3_STATE_C7].valid;
446 omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
447 omap3_power_states[OMAP3_STATE_C7].sleep_latency =
448 cpuidle_params_table[OMAP3_STATE_C7].sleep_latency;
449 omap3_power_states[OMAP3_STATE_C7].wakeup_latency =
450 cpuidle_params_table[OMAP3_STATE_C7].wake_latency;
451 omap3_power_states[OMAP3_STATE_C7].threshold =
452 cpuidle_params_table[OMAP3_STATE_C7].threshold;
453 omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
454 omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
455 omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
456 CPUIDLE_FLAG_CHECK_BM;
459 struct cpuidle_driver omap3_idle_driver = {
460 .name = "omap3_idle",
461 .owner = THIS_MODULE,
465 * omap3_idle_init - Init routine for OMAP3 idle
467 * Registers the OMAP3 specific cpuidle driver with the cpuidle
468 * framework with the valid set of states.
470 int __init omap3_idle_init(void)
473 struct omap3_processor_cx *cx;
474 struct cpuidle_state *state;
475 struct cpuidle_device *dev;
477 mpu_pd = pwrdm_lookup("mpu_pwrdm");
478 core_pd = pwrdm_lookup("core_pwrdm");
479 per_pd = pwrdm_lookup("per_pwrdm");
480 cam_pd = pwrdm_lookup("cam_pwrdm");
482 omap_init_power_states();
483 cpuidle_register_driver(&omap3_idle_driver);
485 dev = &per_cpu(omap3_idle_dev, smp_processor_id());
487 for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
488 cx = &omap3_power_states[i];
489 state = &dev->states[count];
493 cpuidle_set_statedata(state, cx);
494 state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
495 state->target_residency = cx->threshold;
496 state->flags = cx->flags;
497 state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
498 omap3_enter_idle_bm : omap3_enter_idle;
499 if (cx->type == OMAP3_STATE_C1)
500 dev->safe_state = state;
501 sprintf(state->name, "C%d", count+1);
507 dev->state_count = count;
509 omap3_cpuidle_update_states();
511 if (cpuidle_register_device(dev)) {
512 printk(KERN_ERR "%s: CPUidle register device failed\n",
520 int __init omap3_idle_init(void)
524 #endif /* CONFIG_CPU_IDLE */