arch/arm/mach-omap2/control.c

   1 /*
   2  * OMAP2/3 System Control Module register access
   3  *
   4  * Copyright (C) 2007 Texas Instruments, Inc.
   5  * Copyright (C) 2007 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #undef DEBUG
  14
  15 #include <linux/kernel.h>
  16 #include <linux/io.h>
  17
  18 #include <plat/common.h>
  19 #include <plat/control.h>
  20 #include <plat/sdrc.h>
  21 #include "cm-regbits-34xx.h"
  22 #include "prm-regbits-34xx.h"
  23 #include "cm.h"
  24 #include "prm.h"
  25 #include "sdrc.h"
  26 #include "pm.h"
  27
  28 static void __iomem *omap2_ctrl_base;
  29 static void __iomem *omap4_ctrl_pad_base;
  30
  31 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  32 struct omap3_scratchpad {
  33         u32 boot_config_ptr;
  34         u32 public_restore_ptr;
  35         u32 secure_ram_restore_ptr;
  36         u32 sdrc_module_semaphore;
  37         u32 prcm_block_offset;
  38         u32 sdrc_block_offset;
  39 };
  40
  41 struct omap3_scratchpad_prcm_block {
  42         u32 prm_clksrc_ctrl;
  43         u32 prm_clksel;
  44         u32 cm_clksel_core;
  45         u32 cm_clksel_wkup;
  46         u32 cm_clken_pll;
  47         u32 cm_autoidle_pll;
  48         u32 cm_clksel1_pll;
  49         u32 cm_clksel2_pll;
  50         u32 cm_clksel3_pll;
  51         u32 cm_clken_pll_mpu;
  52         u32 cm_autoidle_pll_mpu;
  53         u32 cm_clksel1_pll_mpu;
  54         u32 cm_clksel2_pll_mpu;
  55         u32 prcm_block_size;
  56 };
  57
  58 struct omap3_scratchpad_sdrc_block {
  59         u16 sysconfig;
  60         u16 cs_cfg;
  61         u16 sharing;
  62         u16 err_type;
  63         u32 dll_a_ctrl;
  64         u32 dll_b_ctrl;
  65         u32 power;
  66         u32 cs_0;
  67         u32 mcfg_0;
  68         u16 mr_0;
  69         u16 emr_1_0;
  70         u16 emr_2_0;
  71         u16 emr_3_0;
  72         u32 actim_ctrla_0;
  73         u32 actim_ctrlb_0;
  74         u32 rfr_ctrl_0;
  75         u32 cs_1;
  76         u32 mcfg_1;
  77         u16 mr_1;
  78         u16 emr_1_1;
  79         u16 emr_2_1;
  80         u16 emr_3_1;
  81         u32 actim_ctrla_1;
  82         u32 actim_ctrlb_1;
  83         u32 rfr_ctrl_1;
  84         u16 dcdl_1_ctrl;
  85         u16 dcdl_2_ctrl;
  86         u32 flags;
  87         u32 block_size;
  88 };
  89
  90 void *omap3_secure_ram_storage;
  91
  92 /*
  93  * This is used to store ARM registers in SDRAM before attempting
  94  * an MPU OFF. The save and restore happens from the SRAM sleep code.
  95  * The address is stored in scratchpad, so that it can be used
  96  * during the restore path.
  97  */
  98 u32 omap3_arm_context[128];
  99
 100 struct omap3_control_regs {
 101         u32 sysconfig;
 102         u32 devconf0;
 103         u32 mem_dftrw0;
 104         u32 mem_dftrw1;
 105         u32 msuspendmux_0;
 106         u32 msuspendmux_1;
 107         u32 msuspendmux_2;
 108         u32 msuspendmux_3;
 109         u32 msuspendmux_4;
 110         u32 msuspendmux_5;
 111         u32 sec_ctrl;
 112         u32 devconf1;
 113         u32 csirxfe;
 114         u32 iva2_bootaddr;
 115         u32 iva2_bootmod;
 116         u32 debobs_0;
 117         u32 debobs_1;
 118         u32 debobs_2;
 119         u32 debobs_3;
 120         u32 debobs_4;
 121         u32 debobs_5;
 122         u32 debobs_6;
 123         u32 debobs_7;
 124         u32 debobs_8;
 125         u32 prog_io0;
 126         u32 prog_io1;
 127         u32 dss_dpll_spreading;
 128         u32 core_dpll_spreading;
 129         u32 per_dpll_spreading;
 130         u32 usbhost_dpll_spreading;
 131         u32 pbias_lite;
 132         u32 temp_sensor;
 133         u32 sramldo4;
 134         u32 sramldo5;
 135         u32 csi;
 136 };
 137
 138 static struct omap3_control_regs control_context;
 139 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 140
 141 #define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
 142 #define OMAP4_CTRL_PAD_REGADDR(reg)     (omap4_ctrl_pad_base + (reg))
 143
 144 void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
 145 {
 146         /* Static mapping, never released */
 147         if (omap2_globals->ctrl) {
 148                 omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
 149                 WARN_ON(!omap2_ctrl_base);
 150         }
 151
 152         /* Static mapping, never released */
 153         if (omap2_globals->ctrl_pad) {
 154                 omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K);
 155                 WARN_ON(!omap4_ctrl_pad_base);
 156         }
 157 }
 158
 159 void __iomem *omap_ctrl_base_get(void)
 160 {
 161         return omap2_ctrl_base;
 162 }
 163
 164 u8 omap_ctrl_readb(u16 offset)
 165 {
 166         return __raw_readb(OMAP_CTRL_REGADDR(offset));
 167 }
 168
 169 u16 omap_ctrl_readw(u16 offset)
 170 {
 171         return __raw_readw(OMAP_CTRL_REGADDR(offset));
 172 }
 173
 174 u32 omap_ctrl_readl(u16 offset)
 175 {
 176         return __raw_readl(OMAP_CTRL_REGADDR(offset));
 177 }
 178
 179 void omap_ctrl_writeb(u8 val, u16 offset)
 180 {
 181         __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
 182 }
 183
 184 void omap_ctrl_writew(u16 val, u16 offset)
 185 {
 186         __raw_writew(val, OMAP_CTRL_REGADDR(offset));
 187 }
 188
 189 void omap_ctrl_writel(u32 val, u16 offset)
 190 {
 191         __raw_writel(val, OMAP_CTRL_REGADDR(offset));
 192 }
 193
 194 /*
 195  * On OMAP4 control pad are not addressable from control
 196  * core base. So the common omap_ctrl_read/write APIs breaks
 197  * Hence export separate APIs to manage the omap4 pad control
 198  * registers. This APIs will work only for OMAP4
 199  */
 200
 201 u32 omap4_ctrl_pad_readl(u16 offset)
 202 {
 203         return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
 204 }
 205
 206 void omap4_ctrl_pad_writel(u32 val, u16 offset)
 207 {
 208         __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
 209 }
 210
 211 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 212 /*
 213  * Clears the scratchpad contents in case of cold boot-
 214  * called during bootup
 215  */
 216 void omap3_clear_scratchpad_contents(void)
 217 {
 218         u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
 219         void __iomem *v_addr;
 220         u32 offset = 0;
 221         v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
 222         if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
 223             OMAP3430_GLOBAL_COLD_RST_MASK) {
 224                 for ( ; offset <= max_offset; offset += 0x4)
 225                         __raw_writel(0x0, (v_addr + offset));
 226                 prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
 227                                      OMAP3430_GR_MOD,
 228                                      OMAP3_PRM_RSTST_OFFSET);
 229         }
 230 }
 231
 232 /* Populate the scratchpad structure with restore structure */
 233 void omap3_save_scratchpad_contents(void)
 234 {
 235         void  __iomem *scratchpad_address;
 236         u32 arm_context_addr;
 237         struct omap3_scratchpad scratchpad_contents;
 238         struct omap3_scratchpad_prcm_block prcm_block_contents;
 239         struct omap3_scratchpad_sdrc_block sdrc_block_contents;
 240
 241         /* Populate the Scratchpad contents */
 242         scratchpad_contents.boot_config_ptr = 0x0;
 243         if (omap_rev() != OMAP3430_REV_ES3_0 &&
 244                                         omap_rev() != OMAP3430_REV_ES3_1)
 245                 scratchpad_contents.public_restore_ptr =
 246                         virt_to_phys(get_restore_pointer());
 247         else
 248                 scratchpad_contents.public_restore_ptr =
 249                         virt_to_phys(get_es3_restore_pointer());
 250         if (omap_type() == OMAP2_DEVICE_TYPE_GP)
 251                 scratchpad_contents.secure_ram_restore_ptr = 0x0;
 252         else
 253                 scratchpad_contents.secure_ram_restore_ptr =
 254                         (u32) __pa(omap3_secure_ram_storage);
 255         scratchpad_contents.sdrc_module_semaphore = 0x0;
 256         scratchpad_contents.prcm_block_offset = 0x2C;
 257         scratchpad_contents.sdrc_block_offset = 0x64;
 258
 259         /* Populate the PRCM block contents */
 260         prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
 261                         OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 262         prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
 263                         OMAP3_PRM_CLKSEL_OFFSET);
 264         prcm_block_contents.cm_clksel_core =
 265                         cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
 266         prcm_block_contents.cm_clksel_wkup =
 267                         cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
 268         prcm_block_contents.cm_clken_pll =
 269                         cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 270         prcm_block_contents.cm_autoidle_pll =
 271                         cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
 272         prcm_block_contents.cm_clksel1_pll =
 273                         cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
 274         prcm_block_contents.cm_clksel2_pll =
 275                         cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
 276         prcm_block_contents.cm_clksel3_pll =
 277                         cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
 278         prcm_block_contents.cm_clken_pll_mpu =
 279                         cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
 280         prcm_block_contents.cm_autoidle_pll_mpu =
 281                         cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
 282         prcm_block_contents.cm_clksel1_pll_mpu =
 283                         cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
 284         prcm_block_contents.cm_clksel2_pll_mpu =
 285                         cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
 286         prcm_block_contents.prcm_block_size = 0x0;
 287
 288         /* Populate the SDRC block contents */
 289         sdrc_block_contents.sysconfig =
 290                         (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
 291         sdrc_block_contents.cs_cfg =
 292                         (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
 293         sdrc_block_contents.sharing =
 294                         (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
 295         sdrc_block_contents.err_type =
 296                         (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
 297         sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
 298         sdrc_block_contents.dll_b_ctrl = 0x0;
 299         /*
 300          * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
 301          * be programed to issue automatic self refresh on timeout
 302          * of AUTO_CNT = 1 prior to any transition to OFF mode.
 303          */
 304         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
 305                         && (omap_rev() >= OMAP3430_REV_ES3_0))
 306                 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
 307                                 ~(SDRC_POWER_AUTOCOUNT_MASK|
 308                                 SDRC_POWER_CLKCTRL_MASK)) |
 309                                 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
 310                                 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
 311         else
 312                 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
 313
 314         sdrc_block_contents.cs_0 = 0x0;
 315         sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
 316         sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
 317         sdrc_block_contents.emr_1_0 = 0x0;
 318         sdrc_block_contents.emr_2_0 = 0x0;
 319         sdrc_block_contents.emr_3_0 = 0x0;
 320         sdrc_block_contents.actim_ctrla_0 =
 321                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
 322         sdrc_block_contents.actim_ctrlb_0 =
 323                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
 324         sdrc_block_contents.rfr_ctrl_0 =
 325                         sdrc_read_reg(SDRC_RFR_CTRL_0);
 326         sdrc_block_contents.cs_1 = 0x0;
 327         sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
 328         sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
 329         sdrc_block_contents.emr_1_1 = 0x0;
 330         sdrc_block_contents.emr_2_1 = 0x0;
 331         sdrc_block_contents.emr_3_1 = 0x0;
 332         sdrc_block_contents.actim_ctrla_1 =
 333                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
 334         sdrc_block_contents.actim_ctrlb_1 =
 335                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
 336         sdrc_block_contents.rfr_ctrl_1 =
 337                         sdrc_read_reg(SDRC_RFR_CTRL_1);
 338         sdrc_block_contents.dcdl_1_ctrl = 0x0;
 339         sdrc_block_contents.dcdl_2_ctrl = 0x0;
 340         sdrc_block_contents.flags = 0x0;
 341         sdrc_block_contents.block_size = 0x0;
 342
 343         arm_context_addr = virt_to_phys(omap3_arm_context);
 344
 345         /* Copy all the contents to the scratchpad location */
 346         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 347         memcpy_toio(scratchpad_address, &scratchpad_contents,
 348                  sizeof(scratchpad_contents));
 349         /* Scratchpad contents being 32 bits, a divide by 4 done here */
 350         memcpy_toio(scratchpad_address +
 351                 scratchpad_contents.prcm_block_offset,
 352                 &prcm_block_contents, sizeof(prcm_block_contents));
 353         memcpy_toio(scratchpad_address +
 354                 scratchpad_contents.sdrc_block_offset,
 355                 &sdrc_block_contents, sizeof(sdrc_block_contents));
 356         /*
 357          * Copies the address of the location in SDRAM where ARM
 358          * registers get saved during a MPU OFF transition.
 359          */
 360         memcpy_toio(scratchpad_address +
 361                 scratchpad_contents.sdrc_block_offset +
 362                 sizeof(sdrc_block_contents), &arm_context_addr, 4);
 363 }
 364
 365 void omap3_control_save_context(void)
 366 {
 367         control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
 368         control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 369         control_context.mem_dftrw0 =
 370                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
 371         control_context.mem_dftrw1 =
 372                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
 373         control_context.msuspendmux_0 =
 374                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
 375         control_context.msuspendmux_1 =
 376                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
 377         control_context.msuspendmux_2 =
 378                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
 379         control_context.msuspendmux_3 =
 380                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
 381         control_context.msuspendmux_4 =
 382                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
 383         control_context.msuspendmux_5 =
 384                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
 385         control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
 386         control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
 387         control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
 388         control_context.iva2_bootaddr =
 389                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
 390         control_context.iva2_bootmod =
 391                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
 392         control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
 393         control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
 394         control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
 395         control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
 396         control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
 397         control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
 398         control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
 399         control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
 400         control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
 401         control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
 402         control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
 403         control_context.dss_dpll_spreading =
 404                         omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 405         control_context.core_dpll_spreading =
 406                         omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 407         control_context.per_dpll_spreading =
 408                         omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
 409         control_context.usbhost_dpll_spreading =
 410                 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 411         control_context.pbias_lite =
 412                         omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
 413         control_context.temp_sensor =
 414                         omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
 415         control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
 416         control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
 417         control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
 418         return;
 419 }
 420
 421 void omap3_control_restore_context(void)
 422 {
 423         omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
 424         omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
 425         omap_ctrl_writel(control_context.mem_dftrw0,
 426                                         OMAP343X_CONTROL_MEM_DFTRW0);
 427         omap_ctrl_writel(control_context.mem_dftrw1,
 428                                         OMAP343X_CONTROL_MEM_DFTRW1);
 429         omap_ctrl_writel(control_context.msuspendmux_0,
 430                                         OMAP2_CONTROL_MSUSPENDMUX_0);
 431         omap_ctrl_writel(control_context.msuspendmux_1,
 432                                         OMAP2_CONTROL_MSUSPENDMUX_1);
 433         omap_ctrl_writel(control_context.msuspendmux_2,
 434                                         OMAP2_CONTROL_MSUSPENDMUX_2);
 435         omap_ctrl_writel(control_context.msuspendmux_3,
 436                                         OMAP2_CONTROL_MSUSPENDMUX_3);
 437         omap_ctrl_writel(control_context.msuspendmux_4,
 438                                         OMAP2_CONTROL_MSUSPENDMUX_4);
 439         omap_ctrl_writel(control_context.msuspendmux_5,
 440                                         OMAP2_CONTROL_MSUSPENDMUX_5);
 441         omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
 442         omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
 443         omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
 444         omap_ctrl_writel(control_context.iva2_bootaddr,
 445                                         OMAP343X_CONTROL_IVA2_BOOTADDR);
 446         omap_ctrl_writel(control_context.iva2_bootmod,
 447                                         OMAP343X_CONTROL_IVA2_BOOTMOD);
 448         omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
 449         omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
 450         omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
 451         omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
 452         omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
 453         omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
 454         omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
 455         omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
 456         omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
 457         omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
 458         omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
 459         omap_ctrl_writel(control_context.dss_dpll_spreading,
 460                                         OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 461         omap_ctrl_writel(control_context.core_dpll_spreading,
 462                                         OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 463         omap_ctrl_writel(control_context.per_dpll_spreading,
 464                                         OMAP343X_CONTROL_PER_DPLL_SPREADING);
 465         omap_ctrl_writel(control_context.usbhost_dpll_spreading,
 466                                 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 467         omap_ctrl_writel(control_context.pbias_lite,
 468                                         OMAP343X_CONTROL_PBIAS_LITE);
 469         omap_ctrl_writel(control_context.temp_sensor,
 470                                         OMAP343X_CONTROL_TEMP_SENSOR);
 471         omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
 472         omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
 473         omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
 474         return;
 475 }
 476 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */