2 * OMAP2/3 System Control Module register access
4 * Copyright (C) 2007 Texas Instruments, Inc.
5 * Copyright (C) 2007 Nokia Corporation
7 * Written by Paul Walmsley
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
18 #include <plat/common.h>
19 #include <plat/control.h>
20 #include <plat/sdrc.h>
21 #include "cm-regbits-34xx.h"
22 #include "prm-regbits-34xx.h"
27 static void __iomem *omap2_ctrl_base;
28 static void __iomem *omap4_ctrl_pad_base;
30 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
31 struct omap3_scratchpad {
33 u32 public_restore_ptr;
34 u32 secure_ram_restore_ptr;
35 u32 sdrc_module_semaphore;
36 u32 prcm_block_offset;
37 u32 sdrc_block_offset;
40 struct omap3_scratchpad_prcm_block {
51 u32 cm_autoidle_pll_mpu;
52 u32 cm_clksel1_pll_mpu;
53 u32 cm_clksel2_pll_mpu;
57 struct omap3_scratchpad_sdrc_block {
89 void *omap3_secure_ram_storage;
92 * This is used to store ARM registers in SDRAM before attempting
93 * an MPU OFF. The save and restore happens from the SRAM sleep code.
94 * The address is stored in scratchpad, so that it can be used
95 * during the restore path.
97 u32 omap3_arm_context[128];
99 struct omap3_control_regs {
126 u32 dss_dpll_spreading;
127 u32 core_dpll_spreading;
128 u32 per_dpll_spreading;
129 u32 usbhost_dpll_spreading;
137 static struct omap3_control_regs control_context;
138 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
140 #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
141 #define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg))
143 void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
145 /* Static mapping, never released */
146 if (omap2_globals->ctrl) {
147 omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
148 WARN_ON(!omap2_ctrl_base);
151 /* Static mapping, never released */
152 if (omap2_globals->ctrl_pad) {
153 omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K);
154 WARN_ON(!omap4_ctrl_pad_base);
158 void __iomem *omap_ctrl_base_get(void)
160 return omap2_ctrl_base;
163 u8 omap_ctrl_readb(u16 offset)
165 return __raw_readb(OMAP_CTRL_REGADDR(offset));
168 u16 omap_ctrl_readw(u16 offset)
170 return __raw_readw(OMAP_CTRL_REGADDR(offset));
173 u32 omap_ctrl_readl(u16 offset)
175 return __raw_readl(OMAP_CTRL_REGADDR(offset));
178 void omap_ctrl_writeb(u8 val, u16 offset)
180 __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
183 void omap_ctrl_writew(u16 val, u16 offset)
185 __raw_writew(val, OMAP_CTRL_REGADDR(offset));
188 void omap_ctrl_writel(u32 val, u16 offset)
190 __raw_writel(val, OMAP_CTRL_REGADDR(offset));
194 * On OMAP4 control pad are not addressable from control
195 * core base. So the common omap_ctrl_read/write APIs breaks
196 * Hence export separate APIs to manage the omap4 pad control
197 * registers. This APIs will work only for OMAP4
200 u32 omap4_ctrl_pad_readl(u16 offset)
202 return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
205 void omap4_ctrl_pad_writel(u32 val, u16 offset)
207 __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
210 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
212 * Clears the scratchpad contents in case of cold boot-
213 * called during bootup
215 void omap3_clear_scratchpad_contents(void)
217 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
218 void __iomem *v_addr;
220 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
221 if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
222 OMAP3430_GLOBAL_COLD_RST_MASK) {
223 for ( ; offset <= max_offset; offset += 0x4)
224 __raw_writel(0x0, (v_addr + offset));
225 prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
227 OMAP3_PRM_RSTST_OFFSET);
231 /* Populate the scratchpad structure with restore structure */
232 void omap3_save_scratchpad_contents(void)
234 void __iomem *scratchpad_address;
235 u32 arm_context_addr;
236 struct omap3_scratchpad scratchpad_contents;
237 struct omap3_scratchpad_prcm_block prcm_block_contents;
238 struct omap3_scratchpad_sdrc_block sdrc_block_contents;
240 /* Populate the Scratchpad contents */
241 scratchpad_contents.boot_config_ptr = 0x0;
242 if (omap_rev() != OMAP3430_REV_ES3_0 &&
243 omap_rev() != OMAP3430_REV_ES3_1)
244 scratchpad_contents.public_restore_ptr =
245 virt_to_phys(get_restore_pointer());
247 scratchpad_contents.public_restore_ptr =
248 virt_to_phys(get_es3_restore_pointer());
249 if (omap_type() == OMAP2_DEVICE_TYPE_GP)
250 scratchpad_contents.secure_ram_restore_ptr = 0x0;
252 scratchpad_contents.secure_ram_restore_ptr =
253 (u32) __pa(omap3_secure_ram_storage);
254 scratchpad_contents.sdrc_module_semaphore = 0x0;
255 scratchpad_contents.prcm_block_offset = 0x2C;
256 scratchpad_contents.sdrc_block_offset = 0x64;
258 /* Populate the PRCM block contents */
259 prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
260 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
261 prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
262 OMAP3_PRM_CLKSEL_OFFSET);
263 prcm_block_contents.cm_clksel_core =
264 cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
265 prcm_block_contents.cm_clksel_wkup =
266 cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
267 prcm_block_contents.cm_clken_pll =
268 cm_read_mod_reg(PLL_MOD, CM_CLKEN);
269 prcm_block_contents.cm_autoidle_pll =
270 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
271 prcm_block_contents.cm_clksel1_pll =
272 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
273 prcm_block_contents.cm_clksel2_pll =
274 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
275 prcm_block_contents.cm_clksel3_pll =
276 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
277 prcm_block_contents.cm_clken_pll_mpu =
278 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
279 prcm_block_contents.cm_autoidle_pll_mpu =
280 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
281 prcm_block_contents.cm_clksel1_pll_mpu =
282 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
283 prcm_block_contents.cm_clksel2_pll_mpu =
284 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
285 prcm_block_contents.prcm_block_size = 0x0;
287 /* Populate the SDRC block contents */
288 sdrc_block_contents.sysconfig =
289 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
290 sdrc_block_contents.cs_cfg =
291 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
292 sdrc_block_contents.sharing =
293 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
294 sdrc_block_contents.err_type =
295 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
296 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
297 sdrc_block_contents.dll_b_ctrl = 0x0;
299 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
300 * be programed to issue automatic self refresh on timeout
301 * of AUTO_CNT = 1 prior to any transition to OFF mode.
303 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
304 && (omap_rev() >= OMAP3430_REV_ES3_0))
305 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
306 ~(SDRC_POWER_AUTOCOUNT_MASK|
307 SDRC_POWER_CLKCTRL_MASK)) |
308 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
309 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
311 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
313 sdrc_block_contents.cs_0 = 0x0;
314 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
315 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
316 sdrc_block_contents.emr_1_0 = 0x0;
317 sdrc_block_contents.emr_2_0 = 0x0;
318 sdrc_block_contents.emr_3_0 = 0x0;
319 sdrc_block_contents.actim_ctrla_0 =
320 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
321 sdrc_block_contents.actim_ctrlb_0 =
322 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
323 sdrc_block_contents.rfr_ctrl_0 =
324 sdrc_read_reg(SDRC_RFR_CTRL_0);
325 sdrc_block_contents.cs_1 = 0x0;
326 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
327 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
328 sdrc_block_contents.emr_1_1 = 0x0;
329 sdrc_block_contents.emr_2_1 = 0x0;
330 sdrc_block_contents.emr_3_1 = 0x0;
331 sdrc_block_contents.actim_ctrla_1 =
332 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
333 sdrc_block_contents.actim_ctrlb_1 =
334 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
335 sdrc_block_contents.rfr_ctrl_1 =
336 sdrc_read_reg(SDRC_RFR_CTRL_1);
337 sdrc_block_contents.dcdl_1_ctrl = 0x0;
338 sdrc_block_contents.dcdl_2_ctrl = 0x0;
339 sdrc_block_contents.flags = 0x0;
340 sdrc_block_contents.block_size = 0x0;
342 arm_context_addr = virt_to_phys(omap3_arm_context);
344 /* Copy all the contents to the scratchpad location */
345 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
346 memcpy_toio(scratchpad_address, &scratchpad_contents,
347 sizeof(scratchpad_contents));
348 /* Scratchpad contents being 32 bits, a divide by 4 done here */
349 memcpy_toio(scratchpad_address +
350 scratchpad_contents.prcm_block_offset,
351 &prcm_block_contents, sizeof(prcm_block_contents));
352 memcpy_toio(scratchpad_address +
353 scratchpad_contents.sdrc_block_offset,
354 &sdrc_block_contents, sizeof(sdrc_block_contents));
356 * Copies the address of the location in SDRAM where ARM
357 * registers get saved during a MPU OFF transition.
359 memcpy_toio(scratchpad_address +
360 scratchpad_contents.sdrc_block_offset +
361 sizeof(sdrc_block_contents), &arm_context_addr, 4);
364 void omap3_control_save_context(void)
366 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
367 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
368 control_context.mem_dftrw0 =
369 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
370 control_context.mem_dftrw1 =
371 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
372 control_context.msuspendmux_0 =
373 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
374 control_context.msuspendmux_1 =
375 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
376 control_context.msuspendmux_2 =
377 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
378 control_context.msuspendmux_3 =
379 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
380 control_context.msuspendmux_4 =
381 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
382 control_context.msuspendmux_5 =
383 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
384 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
385 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
386 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
387 control_context.iva2_bootaddr =
388 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
389 control_context.iva2_bootmod =
390 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
391 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
392 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
393 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
394 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
395 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
396 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
397 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
398 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
399 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
400 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
401 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
402 control_context.dss_dpll_spreading =
403 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
404 control_context.core_dpll_spreading =
405 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
406 control_context.per_dpll_spreading =
407 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
408 control_context.usbhost_dpll_spreading =
409 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
410 control_context.pbias_lite =
411 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
412 control_context.temp_sensor =
413 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
414 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
415 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
416 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
420 void omap3_control_restore_context(void)
422 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
423 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
424 omap_ctrl_writel(control_context.mem_dftrw0,
425 OMAP343X_CONTROL_MEM_DFTRW0);
426 omap_ctrl_writel(control_context.mem_dftrw1,
427 OMAP343X_CONTROL_MEM_DFTRW1);
428 omap_ctrl_writel(control_context.msuspendmux_0,
429 OMAP2_CONTROL_MSUSPENDMUX_0);
430 omap_ctrl_writel(control_context.msuspendmux_1,
431 OMAP2_CONTROL_MSUSPENDMUX_1);
432 omap_ctrl_writel(control_context.msuspendmux_2,
433 OMAP2_CONTROL_MSUSPENDMUX_2);
434 omap_ctrl_writel(control_context.msuspendmux_3,
435 OMAP2_CONTROL_MSUSPENDMUX_3);
436 omap_ctrl_writel(control_context.msuspendmux_4,
437 OMAP2_CONTROL_MSUSPENDMUX_4);
438 omap_ctrl_writel(control_context.msuspendmux_5,
439 OMAP2_CONTROL_MSUSPENDMUX_5);
440 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
441 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
442 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
443 omap_ctrl_writel(control_context.iva2_bootaddr,
444 OMAP343X_CONTROL_IVA2_BOOTADDR);
445 omap_ctrl_writel(control_context.iva2_bootmod,
446 OMAP343X_CONTROL_IVA2_BOOTMOD);
447 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
448 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
449 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
450 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
451 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
452 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
453 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
454 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
455 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
456 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
457 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
458 omap_ctrl_writel(control_context.dss_dpll_spreading,
459 OMAP343X_CONTROL_DSS_DPLL_SPREADING);
460 omap_ctrl_writel(control_context.core_dpll_spreading,
461 OMAP343X_CONTROL_CORE_DPLL_SPREADING);
462 omap_ctrl_writel(control_context.per_dpll_spreading,
463 OMAP343X_CONTROL_PER_DPLL_SPREADING);
464 omap_ctrl_writel(control_context.usbhost_dpll_spreading,
465 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
466 omap_ctrl_writel(control_context.pbias_lite,
467 OMAP343X_CONTROL_PBIAS_LITE);
468 omap_ctrl_writel(control_context.temp_sensor,
469 OMAP343X_CONTROL_TEMP_SENSOR);
470 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
471 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
472 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
475 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */