arch/arm/mach-omap2/clock44xx_data.c

   1 /*
   2  * OMAP4 Clock data
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  *
  21  * XXX Some of the ES1 clocks have been removed/changed; once support
  22  * is added for discriminating clocks by ES level, these should be added back
  23  * in.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30
  31 #include <plat/hardware.h>
  32 #include <plat/clkdev_omap.h>
  33
  34 #include "iomap.h"
  35 #include "clock.h"
  36 #include "clock44xx.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "cm-regbits-44xx.h"
  40 #include "prm44xx.h"
  41 #include "prm-regbits-44xx.h"
  42 #include "control.h"
  43 #include "scrm44xx.h"
  44
  45 /* OMAP4 modulemode control */
  46 #define OMAP4430_MODULEMODE_HWCTRL                      0
  47 #define OMAP4430_MODULEMODE_SWCTRL                      1
  48
  49 /* Root clocks */
  50
  51 static struct clk extalt_clkin_ck = {
  52         .name           = "extalt_clkin_ck",
  53         .rate           = 59000000,
  54         .ops            = &clkops_null,
  55 };
  56
  57 static struct clk pad_clks_ck = {
  58         .name           = "pad_clks_ck",
  59         .rate           = 12000000,
  60         .ops            = &clkops_omap2_dflt,
  61         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  62         .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
  63 };
  64
  65 static struct clk pad_slimbus_core_clks_ck = {
  66         .name           = "pad_slimbus_core_clks_ck",
  67         .rate           = 12000000,
  68         .ops            = &clkops_null,
  69 };
  70
  71 static struct clk secure_32k_clk_src_ck = {
  72         .name           = "secure_32k_clk_src_ck",
  73         .rate           = 32768,
  74         .ops            = &clkops_null,
  75 };
  76
  77 static struct clk slimbus_clk = {
  78         .name           = "slimbus_clk",
  79         .rate           = 12000000,
  80         .ops            = &clkops_omap2_dflt,
  81         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  82         .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
  83 };
  84
  85 static struct clk sys_32k_ck = {
  86         .name           = "sys_32k_ck",
  87         .rate           = 32768,
  88         .ops            = &clkops_null,
  89 };
  90
  91 static struct clk virt_12000000_ck = {
  92         .name           = "virt_12000000_ck",
  93         .ops            = &clkops_null,
  94         .rate           = 12000000,
  95 };
  96
  97 static struct clk virt_13000000_ck = {
  98         .name           = "virt_13000000_ck",
  99         .ops            = &clkops_null,
 100         .rate           = 13000000,
 101 };
 102
 103 static struct clk virt_16800000_ck = {
 104         .name           = "virt_16800000_ck",
 105         .ops            = &clkops_null,
 106         .rate           = 16800000,
 107 };
 108
 109 static struct clk virt_19200000_ck = {
 110         .name           = "virt_19200000_ck",
 111         .ops            = &clkops_null,
 112         .rate           = 19200000,
 113 };
 114
 115 static struct clk virt_26000000_ck = {
 116         .name           = "virt_26000000_ck",
 117         .ops            = &clkops_null,
 118         .rate           = 26000000,
 119 };
 120
 121 static struct clk virt_27000000_ck = {
 122         .name           = "virt_27000000_ck",
 123         .ops            = &clkops_null,
 124         .rate           = 27000000,
 125 };
 126
 127 static struct clk virt_38400000_ck = {
 128         .name           = "virt_38400000_ck",
 129         .ops            = &clkops_null,
 130         .rate           = 38400000,
 131 };
 132
 133 static const struct clksel_rate div_1_0_rates[] = {
 134         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 135         { .div = 0 },
 136 };
 137
 138 static const struct clksel_rate div_1_1_rates[] = {
 139         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 140         { .div = 0 },
 141 };
 142
 143 static const struct clksel_rate div_1_2_rates[] = {
 144         { .div = 1, .val = 2, .flags = RATE_IN_4430 },
 145         { .div = 0 },
 146 };
 147
 148 static const struct clksel_rate div_1_3_rates[] = {
 149         { .div = 1, .val = 3, .flags = RATE_IN_4430 },
 150         { .div = 0 },
 151 };
 152
 153 static const struct clksel_rate div_1_4_rates[] = {
 154         { .div = 1, .val = 4, .flags = RATE_IN_4430 },
 155         { .div = 0 },
 156 };
 157
 158 static const struct clksel_rate div_1_5_rates[] = {
 159         { .div = 1, .val = 5, .flags = RATE_IN_4430 },
 160         { .div = 0 },
 161 };
 162
 163 static const struct clksel_rate div_1_6_rates[] = {
 164         { .div = 1, .val = 6, .flags = RATE_IN_4430 },
 165         { .div = 0 },
 166 };
 167
 168 static const struct clksel_rate div_1_7_rates[] = {
 169         { .div = 1, .val = 7, .flags = RATE_IN_4430 },
 170         { .div = 0 },
 171 };
 172
 173 static const struct clksel sys_clkin_sel[] = {
 174         { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
 175         { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
 176         { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
 177         { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
 178         { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
 179         { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
 180         { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
 181         { .parent = NULL },
 182 };
 183
 184 static struct clk sys_clkin_ck = {
 185         .name           = "sys_clkin_ck",
 186         .rate           = 38400000,
 187         .clksel         = sys_clkin_sel,
 188         .init           = &omap2_init_clksel_parent,
 189         .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
 190         .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
 191         .ops            = &clkops_null,
 192         .recalc         = &omap2_clksel_recalc,
 193 };
 194
 195 static struct clk tie_low_clock_ck = {
 196         .name           = "tie_low_clock_ck",
 197         .rate           = 0,
 198         .ops            = &clkops_null,
 199 };
 200
 201 static struct clk utmi_phy_clkout_ck = {
 202         .name           = "utmi_phy_clkout_ck",
 203         .rate           = 60000000,
 204         .ops            = &clkops_null,
 205 };
 206
 207 static struct clk xclk60mhsp1_ck = {
 208         .name           = "xclk60mhsp1_ck",
 209         .rate           = 60000000,
 210         .ops            = &clkops_null,
 211 };
 212
 213 static struct clk xclk60mhsp2_ck = {
 214         .name           = "xclk60mhsp2_ck",
 215         .rate           = 60000000,
 216         .ops            = &clkops_null,
 217 };
 218
 219 static struct clk xclk60motg_ck = {
 220         .name           = "xclk60motg_ck",
 221         .rate           = 60000000,
 222         .ops            = &clkops_null,
 223 };
 224
 225 /* Module clocks and DPLL outputs */
 226
 227 static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
 228         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 229         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
 230         { .parent = NULL },
 231 };
 232
 233 static struct clk abe_dpll_bypass_clk_mux_ck = {
 234         .name           = "abe_dpll_bypass_clk_mux_ck",
 235         .parent         = &sys_clkin_ck,
 236         .ops            = &clkops_null,
 237         .recalc         = &followparent_recalc,
 238 };
 239
 240 static struct clk abe_dpll_refclk_mux_ck = {
 241         .name           = "abe_dpll_refclk_mux_ck",
 242         .parent         = &sys_clkin_ck,
 243         .clksel         = abe_dpll_bypass_clk_mux_sel,
 244         .init           = &omap2_init_clksel_parent,
 245         .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
 246         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
 247         .ops            = &clkops_null,
 248         .recalc         = &omap2_clksel_recalc,
 249 };
 250
 251 /* DPLL_ABE */
 252 static struct dpll_data dpll_abe_dd = {
 253         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
 254         .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
 255         .clk_ref        = &abe_dpll_refclk_mux_ck,
 256         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
 257         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 258         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
 259         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
 260         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 261         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 262         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 263         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 264         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 265         .max_multiplier = 2047,
 266         .max_divider    = 128,
 267         .min_divider    = 1,
 268 };
 269
 270
 271 static struct clk dpll_abe_ck = {
 272         .name           = "dpll_abe_ck",
 273         .parent         = &abe_dpll_refclk_mux_ck,
 274         .dpll_data      = &dpll_abe_dd,
 275         .init           = &omap2_init_dpll_parent,
 276         .ops            = &clkops_omap3_noncore_dpll_ops,
 277         .recalc         = &omap4_dpll_regm4xen_recalc,
 278         .round_rate     = &omap4_dpll_regm4xen_round_rate,
 279         .set_rate       = &omap3_noncore_dpll_set_rate,
 280 };
 281
 282 static struct clk dpll_abe_x2_ck = {
 283         .name           = "dpll_abe_x2_ck",
 284         .parent         = &dpll_abe_ck,
 285         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 286         .flags          = CLOCK_CLKOUTX2,
 287         .ops            = &clkops_omap4_dpllmx_ops,
 288         .recalc         = &omap3_clkoutx2_recalc,
 289 };
 290
 291 static const struct clksel_rate div31_1to31_rates[] = {
 292         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 293         { .div = 2, .val = 2, .flags = RATE_IN_4430 },
 294         { .div = 3, .val = 3, .flags = RATE_IN_4430 },
 295         { .div = 4, .val = 4, .flags = RATE_IN_4430 },
 296         { .div = 5, .val = 5, .flags = RATE_IN_4430 },
 297         { .div = 6, .val = 6, .flags = RATE_IN_4430 },
 298         { .div = 7, .val = 7, .flags = RATE_IN_4430 },
 299         { .div = 8, .val = 8, .flags = RATE_IN_4430 },
 300         { .div = 9, .val = 9, .flags = RATE_IN_4430 },
 301         { .div = 10, .val = 10, .flags = RATE_IN_4430 },
 302         { .div = 11, .val = 11, .flags = RATE_IN_4430 },
 303         { .div = 12, .val = 12, .flags = RATE_IN_4430 },
 304         { .div = 13, .val = 13, .flags = RATE_IN_4430 },
 305         { .div = 14, .val = 14, .flags = RATE_IN_4430 },
 306         { .div = 15, .val = 15, .flags = RATE_IN_4430 },
 307         { .div = 16, .val = 16, .flags = RATE_IN_4430 },
 308         { .div = 17, .val = 17, .flags = RATE_IN_4430 },
 309         { .div = 18, .val = 18, .flags = RATE_IN_4430 },
 310         { .div = 19, .val = 19, .flags = RATE_IN_4430 },
 311         { .div = 20, .val = 20, .flags = RATE_IN_4430 },
 312         { .div = 21, .val = 21, .flags = RATE_IN_4430 },
 313         { .div = 22, .val = 22, .flags = RATE_IN_4430 },
 314         { .div = 23, .val = 23, .flags = RATE_IN_4430 },
 315         { .div = 24, .val = 24, .flags = RATE_IN_4430 },
 316         { .div = 25, .val = 25, .flags = RATE_IN_4430 },
 317         { .div = 26, .val = 26, .flags = RATE_IN_4430 },
 318         { .div = 27, .val = 27, .flags = RATE_IN_4430 },
 319         { .div = 28, .val = 28, .flags = RATE_IN_4430 },
 320         { .div = 29, .val = 29, .flags = RATE_IN_4430 },
 321         { .div = 30, .val = 30, .flags = RATE_IN_4430 },
 322         { .div = 31, .val = 31, .flags = RATE_IN_4430 },
 323         { .div = 0 },
 324 };
 325
 326 static const struct clksel dpll_abe_m2x2_div[] = {
 327         { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
 328         { .parent = NULL },
 329 };
 330
 331 static struct clk dpll_abe_m2x2_ck = {
 332         .name           = "dpll_abe_m2x2_ck",
 333         .parent         = &dpll_abe_x2_ck,
 334         .clksel         = dpll_abe_m2x2_div,
 335         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 336         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 337         .ops            = &clkops_omap4_dpllmx_ops,
 338         .recalc         = &omap2_clksel_recalc,
 339         .round_rate     = &omap2_clksel_round_rate,
 340         .set_rate       = &omap2_clksel_set_rate,
 341 };
 342
 343 static struct clk abe_24m_fclk = {
 344         .name           = "abe_24m_fclk",
 345         .parent         = &dpll_abe_m2x2_ck,
 346         .ops            = &clkops_null,
 347         .fixed_div      = 8,
 348         .recalc         = &omap_fixed_divisor_recalc,
 349 };
 350
 351 static const struct clksel_rate div3_1to4_rates[] = {
 352         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 353         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 354         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 355         { .div = 0 },
 356 };
 357
 358 static const struct clksel abe_clk_div[] = {
 359         { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
 360         { .parent = NULL },
 361 };
 362
 363 static struct clk abe_clk = {
 364         .name           = "abe_clk",
 365         .parent         = &dpll_abe_m2x2_ck,
 366         .clksel         = abe_clk_div,
 367         .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
 368         .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
 369         .ops            = &clkops_null,
 370         .recalc         = &omap2_clksel_recalc,
 371         .round_rate     = &omap2_clksel_round_rate,
 372         .set_rate       = &omap2_clksel_set_rate,
 373 };
 374
 375 static const struct clksel_rate div2_1to2_rates[] = {
 376         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 377         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 378         { .div = 0 },
 379 };
 380
 381 static const struct clksel aess_fclk_div[] = {
 382         { .parent = &abe_clk, .rates = div2_1to2_rates },
 383         { .parent = NULL },
 384 };
 385
 386 static struct clk aess_fclk = {
 387         .name           = "aess_fclk",
 388         .parent         = &abe_clk,
 389         .clksel         = aess_fclk_div,
 390         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 391         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
 392         .ops            = &clkops_null,
 393         .recalc         = &omap2_clksel_recalc,
 394         .round_rate     = &omap2_clksel_round_rate,
 395         .set_rate       = &omap2_clksel_set_rate,
 396 };
 397
 398 static struct clk dpll_abe_m3x2_ck = {
 399         .name           = "dpll_abe_m3x2_ck",
 400         .parent         = &dpll_abe_x2_ck,
 401         .clksel         = dpll_abe_m2x2_div,
 402         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
 403         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 404         .ops            = &clkops_omap4_dpllmx_ops,
 405         .recalc         = &omap2_clksel_recalc,
 406         .round_rate     = &omap2_clksel_round_rate,
 407         .set_rate       = &omap2_clksel_set_rate,
 408 };
 409
 410 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
 411         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 412         { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
 413         { .parent = NULL },
 414 };
 415
 416 static struct clk core_hsd_byp_clk_mux_ck = {
 417         .name           = "core_hsd_byp_clk_mux_ck",
 418         .parent         = &sys_clkin_ck,
 419         .clksel         = core_hsd_byp_clk_mux_sel,
 420         .init           = &omap2_init_clksel_parent,
 421         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
 422         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 423         .ops            = &clkops_null,
 424         .recalc         = &omap2_clksel_recalc,
 425 };
 426
 427 /* DPLL_CORE */
 428 static struct dpll_data dpll_core_dd = {
 429         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
 430         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
 431         .clk_ref        = &sys_clkin_ck,
 432         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
 433         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 434         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
 435         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
 436         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 437         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 438         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 439         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 440         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 441         .max_multiplier = 2047,
 442         .max_divider    = 128,
 443         .min_divider    = 1,
 444 };
 445
 446
 447 static struct clk dpll_core_ck = {
 448         .name           = "dpll_core_ck",
 449         .parent         = &sys_clkin_ck,
 450         .dpll_data      = &dpll_core_dd,
 451         .init           = &omap2_init_dpll_parent,
 452         .ops            = &clkops_omap3_core_dpll_ops,
 453         .recalc         = &omap3_dpll_recalc,
 454 };
 455
 456 static struct clk dpll_core_x2_ck = {
 457         .name           = "dpll_core_x2_ck",
 458         .parent         = &dpll_core_ck,
 459         .flags          = CLOCK_CLKOUTX2,
 460         .ops            = &clkops_null,
 461         .recalc         = &omap3_clkoutx2_recalc,
 462 };
 463
 464 static const struct clksel dpll_core_m6x2_div[] = {
 465         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
 466         { .parent = NULL },
 467 };
 468
 469 static struct clk dpll_core_m6x2_ck = {
 470         .name           = "dpll_core_m6x2_ck",
 471         .parent         = &dpll_core_x2_ck,
 472         .clksel         = dpll_core_m6x2_div,
 473         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
 474         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 475         .ops            = &clkops_omap4_dpllmx_ops,
 476         .recalc         = &omap2_clksel_recalc,
 477         .round_rate     = &omap2_clksel_round_rate,
 478         .set_rate       = &omap2_clksel_set_rate,
 479 };
 480
 481 static const struct clksel dbgclk_mux_sel[] = {
 482         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 483         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
 484         { .parent = NULL },
 485 };
 486
 487 static struct clk dbgclk_mux_ck = {
 488         .name           = "dbgclk_mux_ck",
 489         .parent         = &sys_clkin_ck,
 490         .ops            = &clkops_null,
 491         .recalc         = &followparent_recalc,
 492 };
 493
 494 static const struct clksel dpll_core_m2_div[] = {
 495         { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
 496         { .parent = NULL },
 497 };
 498
 499 static struct clk dpll_core_m2_ck = {
 500         .name           = "dpll_core_m2_ck",
 501         .parent         = &dpll_core_ck,
 502         .clksel         = dpll_core_m2_div,
 503         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
 504         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 505         .ops            = &clkops_omap4_dpllmx_ops,
 506         .recalc         = &omap2_clksel_recalc,
 507         .round_rate     = &omap2_clksel_round_rate,
 508         .set_rate       = &omap2_clksel_set_rate,
 509 };
 510
 511 static struct clk ddrphy_ck = {
 512         .name           = "ddrphy_ck",
 513         .parent         = &dpll_core_m2_ck,
 514         .ops            = &clkops_null,
 515         .fixed_div      = 2,
 516         .recalc         = &omap_fixed_divisor_recalc,
 517 };
 518
 519 static struct clk dpll_core_m5x2_ck = {
 520         .name           = "dpll_core_m5x2_ck",
 521         .parent         = &dpll_core_x2_ck,
 522         .clksel         = dpll_core_m6x2_div,
 523         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
 524         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 525         .ops            = &clkops_omap4_dpllmx_ops,
 526         .recalc         = &omap2_clksel_recalc,
 527         .round_rate     = &omap2_clksel_round_rate,
 528         .set_rate       = &omap2_clksel_set_rate,
 529 };
 530
 531 static const struct clksel div_core_div[] = {
 532         { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
 533         { .parent = NULL },
 534 };
 535
 536 static struct clk div_core_ck = {
 537         .name           = "div_core_ck",
 538         .parent         = &dpll_core_m5x2_ck,
 539         .clksel         = div_core_div,
 540         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
 541         .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
 542         .ops            = &clkops_null,
 543         .recalc         = &omap2_clksel_recalc,
 544         .round_rate     = &omap2_clksel_round_rate,
 545         .set_rate       = &omap2_clksel_set_rate,
 546 };
 547
 548 static const struct clksel_rate div4_1to8_rates[] = {
 549         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 550         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 551         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 552         { .div = 8, .val = 3, .flags = RATE_IN_4430 },
 553         { .div = 0 },
 554 };
 555
 556 static const struct clksel div_iva_hs_clk_div[] = {
 557         { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
 558         { .parent = NULL },
 559 };
 560
 561 static struct clk div_iva_hs_clk = {
 562         .name           = "div_iva_hs_clk",
 563         .parent         = &dpll_core_m5x2_ck,
 564         .clksel         = div_iva_hs_clk_div,
 565         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
 566         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 567         .ops            = &clkops_null,
 568         .recalc         = &omap2_clksel_recalc,
 569         .round_rate     = &omap2_clksel_round_rate,
 570         .set_rate       = &omap2_clksel_set_rate,
 571 };
 572
 573 static struct clk div_mpu_hs_clk = {
 574         .name           = "div_mpu_hs_clk",
 575         .parent         = &dpll_core_m5x2_ck,
 576         .clksel         = div_iva_hs_clk_div,
 577         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
 578         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 579         .ops            = &clkops_null,
 580         .recalc         = &omap2_clksel_recalc,
 581         .round_rate     = &omap2_clksel_round_rate,
 582         .set_rate       = &omap2_clksel_set_rate,
 583 };
 584
 585 static struct clk dpll_core_m4x2_ck = {
 586         .name           = "dpll_core_m4x2_ck",
 587         .parent         = &dpll_core_x2_ck,
 588         .clksel         = dpll_core_m6x2_div,
 589         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
 590         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 591         .ops            = &clkops_omap4_dpllmx_ops,
 592         .recalc         = &omap2_clksel_recalc,
 593         .round_rate     = &omap2_clksel_round_rate,
 594         .set_rate       = &omap2_clksel_set_rate,
 595 };
 596
 597 static struct clk dll_clk_div_ck = {
 598         .name           = "dll_clk_div_ck",
 599         .parent         = &dpll_core_m4x2_ck,
 600         .ops            = &clkops_null,
 601         .fixed_div      = 2,
 602         .recalc         = &omap_fixed_divisor_recalc,
 603 };
 604
 605 static const struct clksel dpll_abe_m2_div[] = {
 606         { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
 607         { .parent = NULL },
 608 };
 609
 610 static struct clk dpll_abe_m2_ck = {
 611         .name           = "dpll_abe_m2_ck",
 612         .parent         = &dpll_abe_ck,
 613         .clksel         = dpll_abe_m2_div,
 614         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 615         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 616         .ops            = &clkops_omap4_dpllmx_ops,
 617         .recalc         = &omap2_clksel_recalc,
 618         .round_rate     = &omap2_clksel_round_rate,
 619         .set_rate       = &omap2_clksel_set_rate,
 620 };
 621
 622 static struct clk dpll_core_m3x2_ck = {
 623         .name           = "dpll_core_m3x2_ck",
 624         .parent         = &dpll_core_x2_ck,
 625         .clksel         = dpll_core_m6x2_div,
 626         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 627         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 628         .ops            = &clkops_omap2_dflt,
 629         .recalc         = &omap2_clksel_recalc,
 630         .round_rate     = &omap2_clksel_round_rate,
 631         .set_rate       = &omap2_clksel_set_rate,
 632         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 633         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 634 };
 635
 636 static struct clk dpll_core_m7x2_ck = {
 637         .name           = "dpll_core_m7x2_ck",
 638         .parent         = &dpll_core_x2_ck,
 639         .clksel         = dpll_core_m6x2_div,
 640         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
 641         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 642         .ops            = &clkops_omap4_dpllmx_ops,
 643         .recalc         = &omap2_clksel_recalc,
 644         .round_rate     = &omap2_clksel_round_rate,
 645         .set_rate       = &omap2_clksel_set_rate,
 646 };
 647
 648 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
 649         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 650         { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
 651         { .parent = NULL },
 652 };
 653
 654 static struct clk iva_hsd_byp_clk_mux_ck = {
 655         .name           = "iva_hsd_byp_clk_mux_ck",
 656         .parent         = &sys_clkin_ck,
 657         .clksel         = iva_hsd_byp_clk_mux_sel,
 658         .init           = &omap2_init_clksel_parent,
 659         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_IVA,
 660         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 661         .ops            = &clkops_null,
 662         .recalc         = &omap2_clksel_recalc,
 663 };
 664
 665 /* DPLL_IVA */
 666 static struct dpll_data dpll_iva_dd = {
 667         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
 668         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
 669         .clk_ref        = &sys_clkin_ck,
 670         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
 671         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 672         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
 673         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
 674         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 675         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 676         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 677         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 678         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 679         .max_multiplier = 2047,
 680         .max_divider    = 128,
 681         .min_divider    = 1,
 682 };
 683
 684
 685 static struct clk dpll_iva_ck = {
 686         .name           = "dpll_iva_ck",
 687         .parent         = &sys_clkin_ck,
 688         .dpll_data      = &dpll_iva_dd,
 689         .init           = &omap2_init_dpll_parent,
 690         .ops            = &clkops_omap3_noncore_dpll_ops,
 691         .recalc         = &omap3_dpll_recalc,
 692         .round_rate     = &omap2_dpll_round_rate,
 693         .set_rate       = &omap3_noncore_dpll_set_rate,
 694 };
 695
 696 static struct clk dpll_iva_x2_ck = {
 697         .name           = "dpll_iva_x2_ck",
 698         .parent         = &dpll_iva_ck,
 699         .flags          = CLOCK_CLKOUTX2,
 700         .ops            = &clkops_null,
 701         .recalc         = &omap3_clkoutx2_recalc,
 702 };
 703
 704 static const struct clksel dpll_iva_m4x2_div[] = {
 705         { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
 706         { .parent = NULL },
 707 };
 708
 709 static struct clk dpll_iva_m4x2_ck = {
 710         .name           = "dpll_iva_m4x2_ck",
 711         .parent         = &dpll_iva_x2_ck,
 712         .clksel         = dpll_iva_m4x2_div,
 713         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
 714         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 715         .ops            = &clkops_omap4_dpllmx_ops,
 716         .recalc         = &omap2_clksel_recalc,
 717         .round_rate     = &omap2_clksel_round_rate,
 718         .set_rate       = &omap2_clksel_set_rate,
 719 };
 720
 721 static struct clk dpll_iva_m5x2_ck = {
 722         .name           = "dpll_iva_m5x2_ck",
 723         .parent         = &dpll_iva_x2_ck,
 724         .clksel         = dpll_iva_m4x2_div,
 725         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
 726         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 727         .ops            = &clkops_omap4_dpllmx_ops,
 728         .recalc         = &omap2_clksel_recalc,
 729         .round_rate     = &omap2_clksel_round_rate,
 730         .set_rate       = &omap2_clksel_set_rate,
 731 };
 732
 733 /* DPLL_MPU */
 734 static struct dpll_data dpll_mpu_dd = {
 735         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
 736         .clk_bypass     = &div_mpu_hs_clk,
 737         .clk_ref        = &sys_clkin_ck,
 738         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
 739         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 740         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
 741         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
 742         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 743         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 744         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 745         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 746         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 747         .max_multiplier = 2047,
 748         .max_divider    = 128,
 749         .min_divider    = 1,
 750 };
 751
 752
 753 static struct clk dpll_mpu_ck = {
 754         .name           = "dpll_mpu_ck",
 755         .parent         = &sys_clkin_ck,
 756         .dpll_data      = &dpll_mpu_dd,
 757         .init           = &omap2_init_dpll_parent,
 758         .ops            = &clkops_omap3_noncore_dpll_ops,
 759         .recalc         = &omap3_dpll_recalc,
 760         .round_rate     = &omap2_dpll_round_rate,
 761         .set_rate       = &omap3_noncore_dpll_set_rate,
 762 };
 763
 764 static const struct clksel dpll_mpu_m2_div[] = {
 765         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
 766         { .parent = NULL },
 767 };
 768
 769 static struct clk dpll_mpu_m2_ck = {
 770         .name           = "dpll_mpu_m2_ck",
 771         .parent         = &dpll_mpu_ck,
 772         .clksel         = dpll_mpu_m2_div,
 773         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
 774         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 775         .ops            = &clkops_omap4_dpllmx_ops,
 776         .recalc         = &omap2_clksel_recalc,
 777         .round_rate     = &omap2_clksel_round_rate,
 778         .set_rate       = &omap2_clksel_set_rate,
 779 };
 780
 781 static struct clk per_hs_clk_div_ck = {
 782         .name           = "per_hs_clk_div_ck",
 783         .parent         = &dpll_abe_m3x2_ck,
 784         .ops            = &clkops_null,
 785         .fixed_div      = 2,
 786         .recalc         = &omap_fixed_divisor_recalc,
 787 };
 788
 789 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
 790         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 791         { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
 792         { .parent = NULL },
 793 };
 794
 795 static struct clk per_hsd_byp_clk_mux_ck = {
 796         .name           = "per_hsd_byp_clk_mux_ck",
 797         .parent         = &sys_clkin_ck,
 798         .clksel         = per_hsd_byp_clk_mux_sel,
 799         .init           = &omap2_init_clksel_parent,
 800         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
 801         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 802         .ops            = &clkops_null,
 803         .recalc         = &omap2_clksel_recalc,
 804 };
 805
 806 /* DPLL_PER */
 807 static struct dpll_data dpll_per_dd = {
 808         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
 809         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
 810         .clk_ref        = &sys_clkin_ck,
 811         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
 812         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 813         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
 814         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
 815         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 816         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 817         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 818         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 819         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 820         .max_multiplier = 2047,
 821         .max_divider    = 128,
 822         .min_divider    = 1,
 823 };
 824
 825
 826 static struct clk dpll_per_ck = {
 827         .name           = "dpll_per_ck",
 828         .parent         = &sys_clkin_ck,
 829         .dpll_data      = &dpll_per_dd,
 830         .init           = &omap2_init_dpll_parent,
 831         .ops            = &clkops_omap3_noncore_dpll_ops,
 832         .recalc         = &omap3_dpll_recalc,
 833         .round_rate     = &omap2_dpll_round_rate,
 834         .set_rate       = &omap3_noncore_dpll_set_rate,
 835 };
 836
 837 static const struct clksel dpll_per_m2_div[] = {
 838         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
 839         { .parent = NULL },
 840 };
 841
 842 static struct clk dpll_per_m2_ck = {
 843         .name           = "dpll_per_m2_ck",
 844         .parent         = &dpll_per_ck,
 845         .clksel         = dpll_per_m2_div,
 846         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 847         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 848         .ops            = &clkops_omap4_dpllmx_ops,
 849         .recalc         = &omap2_clksel_recalc,
 850         .round_rate     = &omap2_clksel_round_rate,
 851         .set_rate       = &omap2_clksel_set_rate,
 852 };
 853
 854 static struct clk dpll_per_x2_ck = {
 855         .name           = "dpll_per_x2_ck",
 856         .parent         = &dpll_per_ck,
 857         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 858         .flags          = CLOCK_CLKOUTX2,
 859         .ops            = &clkops_omap4_dpllmx_ops,
 860         .recalc         = &omap3_clkoutx2_recalc,
 861 };
 862
 863 static const struct clksel dpll_per_m2x2_div[] = {
 864         { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
 865         { .parent = NULL },
 866 };
 867
 868 static struct clk dpll_per_m2x2_ck = {
 869         .name           = "dpll_per_m2x2_ck",
 870         .parent         = &dpll_per_x2_ck,
 871         .clksel         = dpll_per_m2x2_div,
 872         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 873         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 874         .ops            = &clkops_omap4_dpllmx_ops,
 875         .recalc         = &omap2_clksel_recalc,
 876         .round_rate     = &omap2_clksel_round_rate,
 877         .set_rate       = &omap2_clksel_set_rate,
 878 };
 879
 880 static struct clk dpll_per_m3x2_ck = {
 881         .name           = "dpll_per_m3x2_ck",
 882         .parent         = &dpll_per_x2_ck,
 883         .clksel         = dpll_per_m2x2_div,
 884         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 885         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 886         .ops            = &clkops_omap2_dflt,
 887         .recalc         = &omap2_clksel_recalc,
 888         .round_rate     = &omap2_clksel_round_rate,
 889         .set_rate       = &omap2_clksel_set_rate,
 890         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 891         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 892 };
 893
 894 static struct clk dpll_per_m4x2_ck = {
 895         .name           = "dpll_per_m4x2_ck",
 896         .parent         = &dpll_per_x2_ck,
 897         .clksel         = dpll_per_m2x2_div,
 898         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
 899         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 900         .ops            = &clkops_omap4_dpllmx_ops,
 901         .recalc         = &omap2_clksel_recalc,
 902         .round_rate     = &omap2_clksel_round_rate,
 903         .set_rate       = &omap2_clksel_set_rate,
 904 };
 905
 906 static struct clk dpll_per_m5x2_ck = {
 907         .name           = "dpll_per_m5x2_ck",
 908         .parent         = &dpll_per_x2_ck,
 909         .clksel         = dpll_per_m2x2_div,
 910         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
 911         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 912         .ops            = &clkops_omap4_dpllmx_ops,
 913         .recalc         = &omap2_clksel_recalc,
 914         .round_rate     = &omap2_clksel_round_rate,
 915         .set_rate       = &omap2_clksel_set_rate,
 916 };
 917
 918 static struct clk dpll_per_m6x2_ck = {
 919         .name           = "dpll_per_m6x2_ck",
 920         .parent         = &dpll_per_x2_ck,
 921         .clksel         = dpll_per_m2x2_div,
 922         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
 923         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 924         .ops            = &clkops_omap4_dpllmx_ops,
 925         .recalc         = &omap2_clksel_recalc,
 926         .round_rate     = &omap2_clksel_round_rate,
 927         .set_rate       = &omap2_clksel_set_rate,
 928 };
 929
 930 static struct clk dpll_per_m7x2_ck = {
 931         .name           = "dpll_per_m7x2_ck",
 932         .parent         = &dpll_per_x2_ck,
 933         .clksel         = dpll_per_m2x2_div,
 934         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
 935         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 936         .ops            = &clkops_omap4_dpllmx_ops,
 937         .recalc         = &omap2_clksel_recalc,
 938         .round_rate     = &omap2_clksel_round_rate,
 939         .set_rate       = &omap2_clksel_set_rate,
 940 };
 941
 942 static struct clk usb_hs_clk_div_ck = {
 943         .name           = "usb_hs_clk_div_ck",
 944         .parent         = &dpll_abe_m3x2_ck,
 945         .ops            = &clkops_null,
 946         .fixed_div      = 3,
 947         .recalc         = &omap_fixed_divisor_recalc,
 948 };
 949
 950 /* DPLL_USB */
 951 static struct dpll_data dpll_usb_dd = {
 952         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
 953         .clk_bypass     = &usb_hs_clk_div_ck,
 954         .flags          = DPLL_J_TYPE,
 955         .clk_ref        = &sys_clkin_ck,
 956         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
 957         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 958         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
 959         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
 960         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 961         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 962         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 963         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 964         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 965         .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
 966         .max_multiplier = 4095,
 967         .max_divider    = 256,
 968         .min_divider    = 1,
 969 };
 970
 971
 972 static struct clk dpll_usb_ck = {
 973         .name           = "dpll_usb_ck",
 974         .parent         = &sys_clkin_ck,
 975         .dpll_data      = &dpll_usb_dd,
 976         .init           = &omap2_init_dpll_parent,
 977         .ops            = &clkops_omap3_noncore_dpll_ops,
 978         .recalc         = &omap3_dpll_recalc,
 979         .round_rate     = &omap2_dpll_round_rate,
 980         .set_rate       = &omap3_noncore_dpll_set_rate,
 981 };
 982
 983 static struct clk dpll_usb_clkdcoldo_ck = {
 984         .name           = "dpll_usb_clkdcoldo_ck",
 985         .parent         = &dpll_usb_ck,
 986         .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
 987         .ops            = &clkops_omap4_dpllmx_ops,
 988         .recalc         = &followparent_recalc,
 989 };
 990
 991 static const struct clksel dpll_usb_m2_div[] = {
 992         { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
 993         { .parent = NULL },
 994 };
 995
 996 static struct clk dpll_usb_m2_ck = {
 997         .name           = "dpll_usb_m2_ck",
 998         .parent         = &dpll_usb_ck,
 999         .clksel         = dpll_usb_m2_div,
1000         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
1001         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
1002         .ops            = &clkops_omap4_dpllmx_ops,
1003         .recalc         = &omap2_clksel_recalc,
1004         .round_rate     = &omap2_clksel_round_rate,
1005         .set_rate       = &omap2_clksel_set_rate,
1006 };
1007
1008 static const struct clksel ducati_clk_mux_sel[] = {
1009         { .parent = &div_core_ck, .rates = div_1_0_rates },
1010         { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
1011         { .parent = NULL },
1012 };
1013
1014 static struct clk ducati_clk_mux_ck = {
1015         .name           = "ducati_clk_mux_ck",
1016         .parent         = &div_core_ck,
1017         .clksel         = ducati_clk_mux_sel,
1018         .init           = &omap2_init_clksel_parent,
1019         .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1020         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1021         .ops            = &clkops_null,
1022         .recalc         = &omap2_clksel_recalc,
1023 };
1024
1025 static struct clk func_12m_fclk = {
1026         .name           = "func_12m_fclk",
1027         .parent         = &dpll_per_m2x2_ck,
1028         .ops            = &clkops_null,
1029         .fixed_div      = 16,
1030         .recalc         = &omap_fixed_divisor_recalc,
1031 };
1032
1033 static struct clk func_24m_clk = {
1034         .name           = "func_24m_clk",
1035         .parent         = &dpll_per_m2_ck,
1036         .ops            = &clkops_null,
1037         .fixed_div      = 4,
1038         .recalc         = &omap_fixed_divisor_recalc,
1039 };
1040
1041 static struct clk func_24mc_fclk = {
1042         .name           = "func_24mc_fclk",
1043         .parent         = &dpll_per_m2x2_ck,
1044         .ops            = &clkops_null,
1045         .fixed_div      = 8,
1046         .recalc         = &omap_fixed_divisor_recalc,
1047 };
1048
1049 static const struct clksel_rate div2_4to8_rates[] = {
1050         { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1051         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1052         { .div = 0 },
1053 };
1054
1055 static const struct clksel func_48m_fclk_div[] = {
1056         { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1057         { .parent = NULL },
1058 };
1059
1060 static struct clk func_48m_fclk = {
1061         .name           = "func_48m_fclk",
1062         .parent         = &dpll_per_m2x2_ck,
1063         .clksel         = func_48m_fclk_div,
1064         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1065         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1066         .ops            = &clkops_null,
1067         .recalc         = &omap2_clksel_recalc,
1068         .round_rate     = &omap2_clksel_round_rate,
1069         .set_rate       = &omap2_clksel_set_rate,
1070 };
1071
1072 static struct clk func_48mc_fclk = {
1073         .name           = "func_48mc_fclk",
1074         .parent         = &dpll_per_m2x2_ck,
1075         .ops            = &clkops_null,
1076         .fixed_div      = 4,
1077         .recalc         = &omap_fixed_divisor_recalc,
1078 };
1079
1080 static const struct clksel_rate div2_2to4_rates[] = {
1081         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1082         { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1083         { .div = 0 },
1084 };
1085
1086 static const struct clksel func_64m_fclk_div[] = {
1087         { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1088         { .parent = NULL },
1089 };
1090
1091 static struct clk func_64m_fclk = {
1092         .name           = "func_64m_fclk",
1093         .parent         = &dpll_per_m4x2_ck,
1094         .clksel         = func_64m_fclk_div,
1095         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1096         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1097         .ops            = &clkops_null,
1098         .recalc         = &omap2_clksel_recalc,
1099         .round_rate     = &omap2_clksel_round_rate,
1100         .set_rate       = &omap2_clksel_set_rate,
1101 };
1102
1103 static const struct clksel func_96m_fclk_div[] = {
1104         { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1105         { .parent = NULL },
1106 };
1107
1108 static struct clk func_96m_fclk = {
1109         .name           = "func_96m_fclk",
1110         .parent         = &dpll_per_m2x2_ck,
1111         .clksel         = func_96m_fclk_div,
1112         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1113         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1114         .ops            = &clkops_null,
1115         .recalc         = &omap2_clksel_recalc,
1116         .round_rate     = &omap2_clksel_round_rate,
1117         .set_rate       = &omap2_clksel_set_rate,
1118 };
1119
1120 static const struct clksel_rate div2_1to8_rates[] = {
1121         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1122         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1123         { .div = 0 },
1124 };
1125
1126 static const struct clksel init_60m_fclk_div[] = {
1127         { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1128         { .parent = NULL },
1129 };
1130
1131 static struct clk init_60m_fclk = {
1132         .name           = "init_60m_fclk",
1133         .parent         = &dpll_usb_m2_ck,
1134         .clksel         = init_60m_fclk_div,
1135         .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
1136         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1137         .ops            = &clkops_null,
1138         .recalc         = &omap2_clksel_recalc,
1139         .round_rate     = &omap2_clksel_round_rate,
1140         .set_rate       = &omap2_clksel_set_rate,
1141 };
1142
1143 static const struct clksel l3_div_div[] = {
1144         { .parent = &div_core_ck, .rates = div2_1to2_rates },
1145         { .parent = NULL },
1146 };
1147
1148 static struct clk l3_div_ck = {
1149         .name           = "l3_div_ck",
1150         .parent         = &div_core_ck,
1151         .clksel         = l3_div_div,
1152         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1153         .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
1154         .ops            = &clkops_null,
1155         .recalc         = &omap2_clksel_recalc,
1156         .round_rate     = &omap2_clksel_round_rate,
1157         .set_rate       = &omap2_clksel_set_rate,
1158 };
1159
1160 static const struct clksel l4_div_div[] = {
1161         { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1162         { .parent = NULL },
1163 };
1164
1165 static struct clk l4_div_ck = {
1166         .name           = "l4_div_ck",
1167         .parent         = &l3_div_ck,
1168         .clksel         = l4_div_div,
1169         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1170         .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
1171         .ops            = &clkops_null,
1172         .recalc         = &omap2_clksel_recalc,
1173         .round_rate     = &omap2_clksel_round_rate,
1174         .set_rate       = &omap2_clksel_set_rate,
1175 };
1176
1177 static struct clk lp_clk_div_ck = {
1178         .name           = "lp_clk_div_ck",
1179         .parent         = &dpll_abe_m2x2_ck,
1180         .ops            = &clkops_null,
1181         .fixed_div      = 16,
1182         .recalc         = &omap_fixed_divisor_recalc,
1183 };
1184
1185 static const struct clksel l4_wkup_clk_mux_sel[] = {
1186         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1187         { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1188         { .parent = NULL },
1189 };
1190
1191 static struct clk l4_wkup_clk_mux_ck = {
1192         .name           = "l4_wkup_clk_mux_ck",
1193         .parent         = &sys_clkin_ck,
1194         .clksel         = l4_wkup_clk_mux_sel,
1195         .init           = &omap2_init_clksel_parent,
1196         .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
1197         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1198         .ops            = &clkops_null,
1199         .recalc         = &omap2_clksel_recalc,
1200 };
1201
1202 static const struct clksel_rate div2_2to1_rates[] = {
1203         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
1204         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1205         { .div = 0 },
1206 };
1207
1208 static const struct clksel ocp_abe_iclk_div[] = {
1209         { .parent = &aess_fclk, .rates = div2_2to1_rates },
1210         { .parent = NULL },
1211 };
1212
1213 static struct clk mpu_periphclk = {
1214         .name           = "mpu_periphclk",
1215         .parent         = &dpll_mpu_ck,
1216         .ops            = &clkops_null,
1217         .fixed_div      = 2,
1218         .recalc         = &omap_fixed_divisor_recalc,
1219 };
1220
1221 static struct clk ocp_abe_iclk = {
1222         .name           = "ocp_abe_iclk",
1223         .parent         = &aess_fclk,
1224         .clksel         = ocp_abe_iclk_div,
1225         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1226         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
1227         .ops            = &clkops_null,
1228         .recalc         = &omap2_clksel_recalc,
1229 };
1230
1231 static struct clk per_abe_24m_fclk = {
1232         .name           = "per_abe_24m_fclk",
1233         .parent         = &dpll_abe_m2_ck,
1234         .ops            = &clkops_null,
1235         .fixed_div      = 4,
1236         .recalc         = &omap_fixed_divisor_recalc,
1237 };
1238
1239 static const struct clksel per_abe_nc_fclk_div[] = {
1240         { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1241         { .parent = NULL },
1242 };
1243
1244 static struct clk per_abe_nc_fclk = {
1245         .name           = "per_abe_nc_fclk",
1246         .parent         = &dpll_abe_m2_ck,
1247         .clksel         = per_abe_nc_fclk_div,
1248         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1249         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1250         .ops            = &clkops_null,
1251         .recalc         = &omap2_clksel_recalc,
1252         .round_rate     = &omap2_clksel_round_rate,
1253         .set_rate       = &omap2_clksel_set_rate,
1254 };
1255
1256 static const struct clksel pmd_stm_clock_mux_sel[] = {
1257         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1258         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1259         { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1260         { .parent = NULL },
1261 };
1262
1263 static struct clk pmd_stm_clock_mux_ck = {
1264         .name           = "pmd_stm_clock_mux_ck",
1265         .parent         = &sys_clkin_ck,
1266         .ops            = &clkops_null,
1267         .recalc         = &followparent_recalc,
1268 };
1269
1270 static struct clk pmd_trace_clk_mux_ck = {
1271         .name           = "pmd_trace_clk_mux_ck",
1272         .parent         = &sys_clkin_ck,
1273         .ops            = &clkops_null,
1274         .recalc         = &followparent_recalc,
1275 };
1276
1277 static const struct clksel syc_clk_div_div[] = {
1278         { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1279         { .parent = NULL },
1280 };
1281
1282 static struct clk syc_clk_div_ck = {
1283         .name           = "syc_clk_div_ck",
1284         .parent         = &sys_clkin_ck,
1285         .clksel         = syc_clk_div_div,
1286         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1287         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1288         .ops            = &clkops_null,
1289         .recalc         = &omap2_clksel_recalc,
1290         .round_rate     = &omap2_clksel_round_rate,
1291         .set_rate       = &omap2_clksel_set_rate,
1292 };
1293
1294 /* Leaf clocks controlled by modules */
1295
1296 static struct clk aes1_fck = {
1297         .name           = "aes1_fck",
1298         .ops            = &clkops_omap2_dflt,
1299         .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1300         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1301         .clkdm_name     = "l4_secure_clkdm",
1302         .parent         = &l3_div_ck,
1303         .recalc         = &followparent_recalc,
1304 };
1305
1306 static struct clk aes2_fck = {
1307         .name           = "aes2_fck",
1308         .ops            = &clkops_omap2_dflt,
1309         .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1310         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1311         .clkdm_name     = "l4_secure_clkdm",
1312         .parent         = &l3_div_ck,
1313         .recalc         = &followparent_recalc,
1314 };
1315
1316 static struct clk aess_fck = {
1317         .name           = "aess_fck",
1318         .ops            = &clkops_omap2_dflt,
1319         .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1320         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1321         .clkdm_name     = "abe_clkdm",
1322         .parent         = &aess_fclk,
1323         .recalc         = &followparent_recalc,
1324 };
1325
1326 static struct clk bandgap_fclk = {
1327         .name           = "bandgap_fclk",
1328         .ops            = &clkops_omap2_dflt,
1329         .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1330         .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1331         .clkdm_name     = "l4_wkup_clkdm",
1332         .parent         = &sys_32k_ck,
1333         .recalc         = &followparent_recalc,
1334 };
1335
1336 static struct clk des3des_fck = {
1337         .name           = "des3des_fck",
1338         .ops            = &clkops_omap2_dflt,
1339         .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1340         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1341         .clkdm_name     = "l4_secure_clkdm",
1342         .parent         = &l4_div_ck,
1343         .recalc         = &followparent_recalc,
1344 };
1345
1346 static const struct clksel dmic_sync_mux_sel[] = {
1347         { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1348         { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1349         { .parent = &func_24m_clk, .rates = div_1_2_rates },
1350         { .parent = NULL },
1351 };
1352
1353 static struct clk dmic_sync_mux_ck = {
1354         .name           = "dmic_sync_mux_ck",
1355         .parent         = &abe_24m_fclk,
1356         .clksel         = dmic_sync_mux_sel,
1357         .init           = &omap2_init_clksel_parent,
1358         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1359         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1360         .ops            = &clkops_null,
1361         .recalc         = &omap2_clksel_recalc,
1362 };
1363
1364 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1365         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1366         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1367         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1368         { .parent = NULL },
1369 };
1370
1371 /* Merged func_dmic_abe_gfclk into dmic */
1372 static struct clk dmic_fck = {
1373         .name           = "dmic_fck",
1374         .parent         = &dmic_sync_mux_ck,
1375         .clksel         = func_dmic_abe_gfclk_sel,
1376         .init           = &omap2_init_clksel_parent,
1377         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1378         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1379         .ops            = &clkops_omap2_dflt,
1380         .recalc         = &omap2_clksel_recalc,
1381         .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1382         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1383         .clkdm_name     = "abe_clkdm",
1384 };
1385
1386 static struct clk dsp_fck = {
1387         .name           = "dsp_fck",
1388         .ops            = &clkops_omap2_dflt,
1389         .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1390         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1391         .clkdm_name     = "tesla_clkdm",
1392         .parent         = &dpll_iva_m4x2_ck,
1393         .recalc         = &followparent_recalc,
1394 };
1395
1396 static struct clk dss_sys_clk = {
1397         .name           = "dss_sys_clk",
1398         .ops            = &clkops_omap2_dflt,
1399         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1400         .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1401         .clkdm_name     = "l3_dss_clkdm",
1402         .parent         = &syc_clk_div_ck,
1403         .recalc         = &followparent_recalc,
1404 };
1405
1406 static struct clk dss_tv_clk = {
1407         .name           = "dss_tv_clk",
1408         .ops            = &clkops_omap2_dflt,
1409         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1410         .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1411         .clkdm_name     = "l3_dss_clkdm",
1412         .parent         = &extalt_clkin_ck,
1413         .recalc         = &followparent_recalc,
1414 };
1415
1416 static struct clk dss_dss_clk = {
1417         .name           = "dss_dss_clk",
1418         .ops            = &clkops_omap2_dflt,
1419         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1420         .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1421         .clkdm_name     = "l3_dss_clkdm",
1422         .parent         = &dpll_per_m5x2_ck,
1423         .recalc         = &followparent_recalc,
1424 };
1425
1426 static const struct clksel_rate div3_8to32_rates[] = {
1427         { .div = 8, .val = 0, .flags = RATE_IN_4460 },
1428         { .div = 16, .val = 1, .flags = RATE_IN_4460 },
1429         { .div = 32, .val = 2, .flags = RATE_IN_4460 },
1430         { .div = 0 },
1431 };
1432
1433 static const struct clksel div_ts_div[] = {
1434         { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
1435         { .parent = NULL },
1436 };
1437
1438 static struct clk div_ts_ck = {
1439         .name           = "div_ts_ck",
1440         .parent         = &l4_wkup_clk_mux_ck,
1441         .clksel         = div_ts_div,
1442         .clksel_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1443         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1444         .ops            = &clkops_null,
1445         .recalc         = &omap2_clksel_recalc,
1446         .round_rate     = &omap2_clksel_round_rate,
1447         .set_rate       = &omap2_clksel_set_rate,
1448 };
1449
1450 static struct clk bandgap_ts_fclk = {
1451         .name           = "bandgap_ts_fclk",
1452         .ops            = &clkops_omap2_dflt,
1453         .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1454         .enable_bit     = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
1455         .clkdm_name     = "l4_wkup_clkdm",
1456         .parent         = &div_ts_ck,
1457         .recalc         = &followparent_recalc,
1458 };
1459
1460 static struct clk dss_48mhz_clk = {
1461         .name           = "dss_48mhz_clk",
1462         .ops            = &clkops_omap2_dflt,
1463         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1464         .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1465         .clkdm_name     = "l3_dss_clkdm",
1466         .parent         = &func_48mc_fclk,
1467         .recalc         = &followparent_recalc,
1468 };
1469
1470 static struct clk dss_fck = {
1471         .name           = "dss_fck",
1472         .ops            = &clkops_omap2_dflt,
1473         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1474         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1475         .clkdm_name     = "l3_dss_clkdm",
1476         .parent         = &l3_div_ck,
1477         .recalc         = &followparent_recalc,
1478 };
1479
1480 static struct clk efuse_ctrl_cust_fck = {
1481         .name           = "efuse_ctrl_cust_fck",
1482         .ops            = &clkops_omap2_dflt,
1483         .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1484         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1485         .clkdm_name     = "l4_cefuse_clkdm",
1486         .parent         = &sys_clkin_ck,
1487         .recalc         = &followparent_recalc,
1488 };
1489
1490 static struct clk emif1_fck = {
1491         .name           = "emif1_fck",
1492         .ops            = &clkops_omap2_dflt,
1493         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1494         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1495         .flags          = ENABLE_ON_INIT,
1496         .clkdm_name     = "l3_emif_clkdm",
1497         .parent         = &ddrphy_ck,
1498         .recalc         = &followparent_recalc,
1499 };
1500
1501 static struct clk emif2_fck = {
1502         .name           = "emif2_fck",
1503         .ops            = &clkops_omap2_dflt,
1504         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1505         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1506         .flags          = ENABLE_ON_INIT,
1507         .clkdm_name     = "l3_emif_clkdm",
1508         .parent         = &ddrphy_ck,
1509         .recalc         = &followparent_recalc,
1510 };
1511
1512 static const struct clksel fdif_fclk_div[] = {
1513         { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1514         { .parent = NULL },
1515 };
1516
1517 /* Merged fdif_fclk into fdif */
1518 static struct clk fdif_fck = {
1519         .name           = "fdif_fck",
1520         .parent         = &dpll_per_m4x2_ck,
1521         .clksel         = fdif_fclk_div,
1522         .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1523         .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
1524         .ops            = &clkops_omap2_dflt,
1525         .recalc         = &omap2_clksel_recalc,
1526         .round_rate     = &omap2_clksel_round_rate,
1527         .set_rate       = &omap2_clksel_set_rate,
1528         .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1529         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1530         .clkdm_name     = "iss_clkdm",
1531 };
1532
1533 static struct clk fpka_fck = {
1534         .name           = "fpka_fck",
1535         .ops            = &clkops_omap2_dflt,
1536         .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1537         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1538         .clkdm_name     = "l4_secure_clkdm",
1539         .parent         = &l4_div_ck,
1540         .recalc         = &followparent_recalc,
1541 };
1542
1543 static struct clk gpio1_dbclk = {
1544         .name           = "gpio1_dbclk",
1545         .ops            = &clkops_omap2_dflt,
1546         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1547         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1548         .clkdm_name     = "l4_wkup_clkdm",
1549         .parent         = &sys_32k_ck,
1550         .recalc         = &followparent_recalc,
1551 };
1552
1553 static struct clk gpio1_ick = {
1554         .name           = "gpio1_ick",
1555         .ops            = &clkops_omap2_dflt,
1556         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1557         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1558         .clkdm_name     = "l4_wkup_clkdm",
1559         .parent         = &l4_wkup_clk_mux_ck,
1560         .recalc         = &followparent_recalc,
1561 };
1562
1563 static struct clk gpio2_dbclk = {
1564         .name           = "gpio2_dbclk",
1565         .ops            = &clkops_omap2_dflt,
1566         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1567         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1568         .clkdm_name     = "l4_per_clkdm",
1569         .parent         = &sys_32k_ck,
1570         .recalc         = &followparent_recalc,
1571 };
1572
1573 static struct clk gpio2_ick = {
1574         .name           = "gpio2_ick",
1575         .ops            = &clkops_omap2_dflt,
1576         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1577         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1578         .clkdm_name     = "l4_per_clkdm",
1579         .parent         = &l4_div_ck,
1580         .recalc         = &followparent_recalc,
1581 };
1582
1583 static struct clk gpio3_dbclk = {
1584         .name           = "gpio3_dbclk",
1585         .ops            = &clkops_omap2_dflt,
1586         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1587         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1588         .clkdm_name     = "l4_per_clkdm",
1589         .parent         = &sys_32k_ck,
1590         .recalc         = &followparent_recalc,
1591 };
1592
1593 static struct clk gpio3_ick = {
1594         .name           = "gpio3_ick",
1595         .ops            = &clkops_omap2_dflt,
1596         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1597         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1598         .clkdm_name     = "l4_per_clkdm",
1599         .parent         = &l4_div_ck,
1600         .recalc         = &followparent_recalc,
1601 };
1602
1603 static struct clk gpio4_dbclk = {
1604         .name           = "gpio4_dbclk",
1605         .ops            = &clkops_omap2_dflt,
1606         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1607         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1608         .clkdm_name     = "l4_per_clkdm",
1609         .parent         = &sys_32k_ck,
1610         .recalc         = &followparent_recalc,
1611 };
1612
1613 static struct clk gpio4_ick = {
1614         .name           = "gpio4_ick",
1615         .ops            = &clkops_omap2_dflt,
1616         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1617         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1618         .clkdm_name     = "l4_per_clkdm",
1619         .parent         = &l4_div_ck,
1620         .recalc         = &followparent_recalc,
1621 };
1622
1623 static struct clk gpio5_dbclk = {
1624         .name           = "gpio5_dbclk",
1625         .ops            = &clkops_omap2_dflt,
1626         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1627         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1628         .clkdm_name     = "l4_per_clkdm",
1629         .parent         = &sys_32k_ck,
1630         .recalc         = &followparent_recalc,
1631 };
1632
1633 static struct clk gpio5_ick = {
1634         .name           = "gpio5_ick",
1635         .ops            = &clkops_omap2_dflt,
1636         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1637         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1638         .clkdm_name     = "l4_per_clkdm",
1639         .parent         = &l4_div_ck,
1640         .recalc         = &followparent_recalc,
1641 };
1642
1643 static struct clk gpio6_dbclk = {
1644         .name           = "gpio6_dbclk",
1645         .ops            = &clkops_omap2_dflt,
1646         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1647         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1648         .clkdm_name     = "l4_per_clkdm",
1649         .parent         = &sys_32k_ck,
1650         .recalc         = &followparent_recalc,
1651 };
1652
1653 static struct clk gpio6_ick = {
1654         .name           = "gpio6_ick",
1655         .ops            = &clkops_omap2_dflt,
1656         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1657         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1658         .clkdm_name     = "l4_per_clkdm",
1659         .parent         = &l4_div_ck,
1660         .recalc         = &followparent_recalc,
1661 };
1662
1663 static struct clk gpmc_ick = {
1664         .name           = "gpmc_ick",
1665         .ops            = &clkops_omap2_dflt,
1666         .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1667         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1668         .flags          = ENABLE_ON_INIT,
1669         .clkdm_name     = "l3_2_clkdm",
1670         .parent         = &l3_div_ck,
1671         .recalc         = &followparent_recalc,
1672 };
1673
1674 static const struct clksel sgx_clk_mux_sel[] = {
1675         { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1676         { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1677         { .parent = NULL },
1678 };
1679
1680 /* Merged sgx_clk_mux into gpu */
1681 static struct clk gpu_fck = {
1682         .name           = "gpu_fck",
1683         .parent         = &dpll_core_m7x2_ck,
1684         .clksel         = sgx_clk_mux_sel,
1685         .init           = &omap2_init_clksel_parent,
1686         .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1687         .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1688         .ops            = &clkops_omap2_dflt,
1689         .recalc         = &omap2_clksel_recalc,
1690         .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1691         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1692         .clkdm_name     = "l3_gfx_clkdm",
1693 };
1694
1695 static struct clk hdq1w_fck = {
1696         .name           = "hdq1w_fck",
1697         .ops            = &clkops_omap2_dflt,
1698         .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1699         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1700         .clkdm_name     = "l4_per_clkdm",
1701         .parent         = &func_12m_fclk,
1702         .recalc         = &followparent_recalc,
1703 };
1704
1705 static const struct clksel hsi_fclk_div[] = {
1706         { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1707         { .parent = NULL },
1708 };
1709
1710 /* Merged hsi_fclk into hsi */
1711 static struct clk hsi_fck = {
1712         .name           = "hsi_fck",
1713         .parent         = &dpll_per_m2x2_ck,
1714         .clksel         = hsi_fclk_div,
1715         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1716         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1717         .ops            = &clkops_omap2_dflt,
1718         .recalc         = &omap2_clksel_recalc,
1719         .round_rate     = &omap2_clksel_round_rate,
1720         .set_rate       = &omap2_clksel_set_rate,
1721         .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1722         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1723         .clkdm_name     = "l3_init_clkdm",
1724 };
1725
1726 static struct clk i2c1_fck = {
1727         .name           = "i2c1_fck",
1728         .ops            = &clkops_omap2_dflt,
1729         .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1730         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1731         .clkdm_name     = "l4_per_clkdm",
1732         .parent         = &func_96m_fclk,
1733         .recalc         = &followparent_recalc,
1734 };
1735
1736 static struct clk i2c2_fck = {
1737         .name           = "i2c2_fck",
1738         .ops            = &clkops_omap2_dflt,
1739         .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1740         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1741         .clkdm_name     = "l4_per_clkdm",
1742         .parent         = &func_96m_fclk,
1743         .recalc         = &followparent_recalc,
1744 };
1745
1746 static struct clk i2c3_fck = {
1747         .name           = "i2c3_fck",
1748         .ops            = &clkops_omap2_dflt,
1749         .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1750         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1751         .clkdm_name     = "l4_per_clkdm",
1752         .parent         = &func_96m_fclk,
1753         .recalc         = &followparent_recalc,
1754 };
1755
1756 static struct clk i2c4_fck = {
1757         .name           = "i2c4_fck",
1758         .ops            = &clkops_omap2_dflt,
1759         .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1760         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1761         .clkdm_name     = "l4_per_clkdm",
1762         .parent         = &func_96m_fclk,
1763         .recalc         = &followparent_recalc,
1764 };
1765
1766 static struct clk ipu_fck = {
1767         .name           = "ipu_fck",
1768         .ops            = &clkops_omap2_dflt,
1769         .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1770         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1771         .clkdm_name     = "ducati_clkdm",
1772         .parent         = &ducati_clk_mux_ck,
1773         .recalc         = &followparent_recalc,
1774 };
1775
1776 static struct clk iss_ctrlclk = {
1777         .name           = "iss_ctrlclk",
1778         .ops            = &clkops_omap2_dflt,
1779         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1780         .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1781         .clkdm_name     = "iss_clkdm",
1782         .parent         = &func_96m_fclk,
1783         .recalc         = &followparent_recalc,
1784 };
1785
1786 static struct clk iss_fck = {
1787         .name           = "iss_fck",
1788         .ops            = &clkops_omap2_dflt,
1789         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1790         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1791         .clkdm_name     = "iss_clkdm",
1792         .parent         = &ducati_clk_mux_ck,
1793         .recalc         = &followparent_recalc,
1794 };
1795
1796 static struct clk iva_fck = {
1797         .name           = "iva_fck",
1798         .ops            = &clkops_omap2_dflt,
1799         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1800         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1801         .clkdm_name     = "ivahd_clkdm",
1802         .parent         = &dpll_iva_m5x2_ck,
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk kbd_fck = {
1807         .name           = "kbd_fck",
1808         .ops            = &clkops_omap2_dflt,
1809         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1810         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1811         .clkdm_name     = "l4_wkup_clkdm",
1812         .parent         = &sys_32k_ck,
1813         .recalc         = &followparent_recalc,
1814 };
1815
1816 static struct clk l3_instr_ick = {
1817         .name           = "l3_instr_ick",
1818         .ops            = &clkops_omap2_dflt,
1819         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1820         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1821         .flags          = ENABLE_ON_INIT,
1822         .clkdm_name     = "l3_instr_clkdm",
1823         .parent         = &l3_div_ck,
1824         .recalc         = &followparent_recalc,
1825 };
1826
1827 static struct clk l3_main_3_ick = {
1828         .name           = "l3_main_3_ick",
1829         .ops            = &clkops_omap2_dflt,
1830         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1831         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1832         .flags          = ENABLE_ON_INIT,
1833         .clkdm_name     = "l3_instr_clkdm",
1834         .parent         = &l3_div_ck,
1835         .recalc         = &followparent_recalc,
1836 };
1837
1838 static struct clk mcasp_sync_mux_ck = {
1839         .name           = "mcasp_sync_mux_ck",
1840         .parent         = &abe_24m_fclk,
1841         .clksel         = dmic_sync_mux_sel,
1842         .init           = &omap2_init_clksel_parent,
1843         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1844         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1845         .ops            = &clkops_null,
1846         .recalc         = &omap2_clksel_recalc,
1847 };
1848
1849 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1850         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1851         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1852         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1853         { .parent = NULL },
1854 };
1855
1856 /* Merged func_mcasp_abe_gfclk into mcasp */
1857 static struct clk mcasp_fck = {
1858         .name           = "mcasp_fck",
1859         .parent         = &mcasp_sync_mux_ck,
1860         .clksel         = func_mcasp_abe_gfclk_sel,
1861         .init           = &omap2_init_clksel_parent,
1862         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1863         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1864         .ops            = &clkops_omap2_dflt,
1865         .recalc         = &omap2_clksel_recalc,
1866         .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1867         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1868         .clkdm_name     = "abe_clkdm",
1869 };
1870
1871 static struct clk mcbsp1_sync_mux_ck = {
1872         .name           = "mcbsp1_sync_mux_ck",
1873         .parent         = &abe_24m_fclk,
1874         .clksel         = dmic_sync_mux_sel,
1875         .init           = &omap2_init_clksel_parent,
1876         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1877         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1878         .ops            = &clkops_null,
1879         .recalc         = &omap2_clksel_recalc,
1880 };
1881
1882 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1883         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1884         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1885         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1886         { .parent = NULL },
1887 };
1888
1889 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1890 static struct clk mcbsp1_fck = {
1891         .name           = "mcbsp1_fck",
1892         .parent         = &mcbsp1_sync_mux_ck,
1893         .clksel         = func_mcbsp1_gfclk_sel,
1894         .init           = &omap2_init_clksel_parent,
1895         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1896         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1897         .ops            = &clkops_omap2_dflt,
1898         .recalc         = &omap2_clksel_recalc,
1899         .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1900         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1901         .clkdm_name     = "abe_clkdm",
1902 };
1903
1904 static struct clk mcbsp2_sync_mux_ck = {
1905         .name           = "mcbsp2_sync_mux_ck",
1906         .parent         = &abe_24m_fclk,
1907         .clksel         = dmic_sync_mux_sel,
1908         .init           = &omap2_init_clksel_parent,
1909         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1910         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1911         .ops            = &clkops_null,
1912         .recalc         = &omap2_clksel_recalc,
1913 };
1914
1915 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1916         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1917         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1918         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1919         { .parent = NULL },
1920 };
1921
1922 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1923 static struct clk mcbsp2_fck = {
1924         .name           = "mcbsp2_fck",
1925         .parent         = &mcbsp2_sync_mux_ck,
1926         .clksel         = func_mcbsp2_gfclk_sel,
1927         .init           = &omap2_init_clksel_parent,
1928         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1929         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1930         .ops            = &clkops_omap2_dflt,
1931         .recalc         = &omap2_clksel_recalc,
1932         .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1933         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1934         .clkdm_name     = "abe_clkdm",
1935 };
1936
1937 static struct clk mcbsp3_sync_mux_ck = {
1938         .name           = "mcbsp3_sync_mux_ck",
1939         .parent         = &abe_24m_fclk,
1940         .clksel         = dmic_sync_mux_sel,
1941         .init           = &omap2_init_clksel_parent,
1942         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1943         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1944         .ops            = &clkops_null,
1945         .recalc         = &omap2_clksel_recalc,
1946 };
1947
1948 static const struct clksel func_mcbsp3_gfclk_sel[] = {
1949         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1950         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1951         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1952         { .parent = NULL },
1953 };
1954
1955 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1956 static struct clk mcbsp3_fck = {
1957         .name           = "mcbsp3_fck",
1958         .parent         = &mcbsp3_sync_mux_ck,
1959         .clksel         = func_mcbsp3_gfclk_sel,
1960         .init           = &omap2_init_clksel_parent,
1961         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1962         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1963         .ops            = &clkops_omap2_dflt,
1964         .recalc         = &omap2_clksel_recalc,
1965         .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1966         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1967         .clkdm_name     = "abe_clkdm",
1968 };
1969
1970 static const struct clksel mcbsp4_sync_mux_sel[] = {
1971         { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1972         { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1973         { .parent = NULL },
1974 };
1975
1976 static struct clk mcbsp4_sync_mux_ck = {
1977         .name           = "mcbsp4_sync_mux_ck",
1978         .parent         = &func_96m_fclk,
1979         .clksel         = mcbsp4_sync_mux_sel,
1980         .init           = &omap2_init_clksel_parent,
1981         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1982         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1983         .ops            = &clkops_null,
1984         .recalc         = &omap2_clksel_recalc,
1985 };
1986
1987 static const struct clksel per_mcbsp4_gfclk_sel[] = {
1988         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1989         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1990         { .parent = NULL },
1991 };
1992
1993 /* Merged per_mcbsp4_gfclk into mcbsp4 */
1994 static struct clk mcbsp4_fck = {
1995         .name           = "mcbsp4_fck",
1996         .parent         = &mcbsp4_sync_mux_ck,
1997         .clksel         = per_mcbsp4_gfclk_sel,
1998         .init           = &omap2_init_clksel_parent,
1999         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2000         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
2001         .ops            = &clkops_omap2_dflt,
2002         .recalc         = &omap2_clksel_recalc,
2003         .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2004         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2005         .clkdm_name     = "l4_per_clkdm",
2006 };
2007
2008 static struct clk mcpdm_fck = {
2009         .name           = "mcpdm_fck",
2010         .ops            = &clkops_omap2_dflt,
2011         .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2012         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2013         .clkdm_name     = "abe_clkdm",
2014         .parent         = &pad_clks_ck,
2015         .recalc         = &followparent_recalc,
2016 };
2017
2018 static struct clk mcspi1_fck = {
2019         .name           = "mcspi1_fck",
2020         .ops            = &clkops_omap2_dflt,
2021         .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2022         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2023         .clkdm_name     = "l4_per_clkdm",
2024         .parent         = &func_48m_fclk,
2025         .recalc         = &followparent_recalc,
2026 };
2027
2028 static struct clk mcspi2_fck = {
2029         .name           = "mcspi2_fck",
2030         .ops            = &clkops_omap2_dflt,
2031         .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2032         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2033         .clkdm_name     = "l4_per_clkdm",
2034         .parent         = &func_48m_fclk,
2035         .recalc         = &followparent_recalc,
2036 };
2037
2038 static struct clk mcspi3_fck = {
2039         .name           = "mcspi3_fck",
2040         .ops            = &clkops_omap2_dflt,
2041         .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2042         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2043         .clkdm_name     = "l4_per_clkdm",
2044         .parent         = &func_48m_fclk,
2045         .recalc         = &followparent_recalc,
2046 };
2047
2048 static struct clk mcspi4_fck = {
2049         .name           = "mcspi4_fck",
2050         .ops            = &clkops_omap2_dflt,
2051         .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2052         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2053         .clkdm_name     = "l4_per_clkdm",
2054         .parent         = &func_48m_fclk,
2055         .recalc         = &followparent_recalc,
2056 };
2057
2058 static const struct clksel hsmmc1_fclk_sel[] = {
2059         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
2060         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
2061         { .parent = NULL },
2062 };
2063
2064 /* Merged hsmmc1_fclk into mmc1 */
2065 static struct clk mmc1_fck = {
2066         .name           = "mmc1_fck",
2067         .parent         = &func_64m_fclk,
2068         .clksel         = hsmmc1_fclk_sel,
2069         .init           = &omap2_init_clksel_parent,
2070         .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2071         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2072         .ops            = &clkops_omap2_dflt,
2073         .recalc         = &omap2_clksel_recalc,
2074         .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2075         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2076         .clkdm_name     = "l3_init_clkdm",
2077 };
2078
2079 /* Merged hsmmc2_fclk into mmc2 */
2080 static struct clk mmc2_fck = {
2081         .name           = "mmc2_fck",
2082         .parent         = &func_64m_fclk,
2083         .clksel         = hsmmc1_fclk_sel,
2084         .init           = &omap2_init_clksel_parent,
2085         .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2086         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2087         .ops            = &clkops_omap2_dflt,
2088         .recalc         = &omap2_clksel_recalc,
2089         .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2090         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2091         .clkdm_name     = "l3_init_clkdm",
2092 };
2093
2094 static struct clk mmc3_fck = {
2095         .name           = "mmc3_fck",
2096         .ops            = &clkops_omap2_dflt,
2097         .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2098         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2099         .clkdm_name     = "l4_per_clkdm",
2100         .parent         = &func_48m_fclk,
2101         .recalc         = &followparent_recalc,
2102 };
2103
2104 static struct clk mmc4_fck = {
2105         .name           = "mmc4_fck",
2106         .ops            = &clkops_omap2_dflt,
2107         .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2108         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2109         .clkdm_name     = "l4_per_clkdm",
2110         .parent         = &func_48m_fclk,
2111         .recalc         = &followparent_recalc,
2112 };
2113
2114 static struct clk mmc5_fck = {
2115         .name           = "mmc5_fck",
2116         .ops            = &clkops_omap2_dflt,
2117         .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2118         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2119         .clkdm_name     = "l4_per_clkdm",
2120         .parent         = &func_48m_fclk,
2121         .recalc         = &followparent_recalc,
2122 };
2123
2124 static struct clk ocp2scp_usb_phy_phy_48m = {
2125         .name           = "ocp2scp_usb_phy_phy_48m",
2126         .ops            = &clkops_omap2_dflt,
2127         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2128         .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2129         .clkdm_name     = "l3_init_clkdm",
2130         .parent         = &func_48m_fclk,
2131         .recalc         = &followparent_recalc,
2132 };
2133
2134 static struct clk ocp2scp_usb_phy_ick = {
2135         .name           = "ocp2scp_usb_phy_ick",
2136         .ops            = &clkops_omap2_dflt,
2137         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2138         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2139         .clkdm_name     = "l3_init_clkdm",
2140         .parent         = &l4_div_ck,
2141         .recalc         = &followparent_recalc,
2142 };
2143
2144 static struct clk ocp_wp_noc_ick = {
2145         .name           = "ocp_wp_noc_ick",
2146         .ops            = &clkops_omap2_dflt,
2147         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2148         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2149         .flags          = ENABLE_ON_INIT,
2150         .clkdm_name     = "l3_instr_clkdm",
2151         .parent         = &l3_div_ck,
2152         .recalc         = &followparent_recalc,
2153 };
2154
2155 static struct clk rng_ick = {
2156         .name           = "rng_ick",
2157         .ops            = &clkops_omap2_dflt,
2158         .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2159         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2160         .clkdm_name     = "l4_secure_clkdm",
2161         .parent         = &l4_div_ck,
2162         .recalc         = &followparent_recalc,
2163 };
2164
2165 static struct clk sha2md5_fck = {
2166         .name           = "sha2md5_fck",
2167         .ops            = &clkops_omap2_dflt,
2168         .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2169         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2170         .clkdm_name     = "l4_secure_clkdm",
2171         .parent         = &l3_div_ck,
2172         .recalc         = &followparent_recalc,
2173 };
2174
2175 static struct clk sl2if_ick = {
2176         .name           = "sl2if_ick",
2177         .ops            = &clkops_omap2_dflt,
2178         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2179         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2180         .clkdm_name     = "ivahd_clkdm",
2181         .parent         = &dpll_iva_m5x2_ck,
2182         .recalc         = &followparent_recalc,
2183 };
2184
2185 static struct clk slimbus1_fclk_1 = {
2186         .name           = "slimbus1_fclk_1",
2187         .ops            = &clkops_omap2_dflt,
2188         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2189         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2190         .clkdm_name     = "abe_clkdm",
2191         .parent         = &func_24m_clk,
2192         .recalc         = &followparent_recalc,
2193 };
2194
2195 static struct clk slimbus1_fclk_0 = {
2196         .name           = "slimbus1_fclk_0",
2197         .ops            = &clkops_omap2_dflt,
2198         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2199         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2200         .clkdm_name     = "abe_clkdm",
2201         .parent         = &abe_24m_fclk,
2202         .recalc         = &followparent_recalc,
2203 };
2204
2205 static struct clk slimbus1_fclk_2 = {
2206         .name           = "slimbus1_fclk_2",
2207         .ops            = &clkops_omap2_dflt,
2208         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2209         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2210         .clkdm_name     = "abe_clkdm",
2211         .parent         = &pad_clks_ck,
2212         .recalc         = &followparent_recalc,
2213 };
2214
2215 static struct clk slimbus1_slimbus_clk = {
2216         .name           = "slimbus1_slimbus_clk",
2217         .ops            = &clkops_omap2_dflt,
2218         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2219         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2220         .clkdm_name     = "abe_clkdm",
2221         .parent         = &slimbus_clk,
2222         .recalc         = &followparent_recalc,
2223 };
2224
2225 static struct clk slimbus1_fck = {
2226         .name           = "slimbus1_fck",
2227         .ops            = &clkops_omap2_dflt,
2228         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2229         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2230         .clkdm_name     = "abe_clkdm",
2231         .parent         = &ocp_abe_iclk,
2232         .recalc         = &followparent_recalc,
2233 };
2234
2235 static struct clk slimbus2_fclk_1 = {
2236         .name           = "slimbus2_fclk_1",
2237         .ops            = &clkops_omap2_dflt,
2238         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2239         .enable_bit     = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2240         .clkdm_name     = "l4_per_clkdm",
2241         .parent         = &per_abe_24m_fclk,
2242         .recalc         = &followparent_recalc,
2243 };
2244
2245 static struct clk slimbus2_fclk_0 = {
2246         .name           = "slimbus2_fclk_0",
2247         .ops            = &clkops_omap2_dflt,
2248         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2249         .enable_bit     = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2250         .clkdm_name     = "l4_per_clkdm",
2251         .parent         = &func_24mc_fclk,
2252         .recalc         = &followparent_recalc,
2253 };
2254
2255 static struct clk slimbus2_slimbus_clk = {
2256         .name           = "slimbus2_slimbus_clk",
2257         .ops            = &clkops_omap2_dflt,
2258         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2259         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2260         .clkdm_name     = "l4_per_clkdm",
2261         .parent         = &pad_slimbus_core_clks_ck,
2262         .recalc         = &followparent_recalc,
2263 };
2264
2265 static struct clk slimbus2_fck = {
2266         .name           = "slimbus2_fck",
2267         .ops            = &clkops_omap2_dflt,
2268         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2269         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2270         .clkdm_name     = "l4_per_clkdm",
2271         .parent         = &l4_div_ck,
2272         .recalc         = &followparent_recalc,
2273 };
2274
2275 static struct clk smartreflex_core_fck = {
2276         .name           = "smartreflex_core_fck",
2277         .ops            = &clkops_omap2_dflt,
2278         .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2279         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2280         .clkdm_name     = "l4_ao_clkdm",
2281         .parent         = &l4_wkup_clk_mux_ck,
2282         .recalc         = &followparent_recalc,
2283 };
2284
2285 static struct clk smartreflex_iva_fck = {
2286         .name           = "smartreflex_iva_fck",
2287         .ops            = &clkops_omap2_dflt,
2288         .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2289         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2290         .clkdm_name     = "l4_ao_clkdm",
2291         .parent         = &l4_wkup_clk_mux_ck,
2292         .recalc         = &followparent_recalc,
2293 };
2294
2295 static struct clk smartreflex_mpu_fck = {
2296         .name           = "smartreflex_mpu_fck",
2297         .ops            = &clkops_omap2_dflt,
2298         .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2299         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2300         .clkdm_name     = "l4_ao_clkdm",
2301         .parent         = &l4_wkup_clk_mux_ck,
2302         .recalc         = &followparent_recalc,
2303 };
2304
2305 /* Merged dmt1_clk_mux into timer1 */
2306 static struct clk timer1_fck = {
2307         .name           = "timer1_fck",
2308         .parent         = &sys_clkin_ck,
2309         .clksel         = abe_dpll_bypass_clk_mux_sel,
2310         .init           = &omap2_init_clksel_parent,
2311         .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2312         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2313         .ops            = &clkops_omap2_dflt,
2314         .recalc         = &omap2_clksel_recalc,
2315         .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2316         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2317         .clkdm_name     = "l4_wkup_clkdm",
2318 };
2319
2320 /* Merged cm2_dm10_mux into timer10 */
2321 static struct clk timer10_fck = {
2322         .name           = "timer10_fck",
2323         .parent         = &sys_clkin_ck,
2324         .clksel         = abe_dpll_bypass_clk_mux_sel,
2325         .init           = &omap2_init_clksel_parent,
2326         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2327         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2328         .ops            = &clkops_omap2_dflt,
2329         .recalc         = &omap2_clksel_recalc,
2330         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2331         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2332         .clkdm_name     = "l4_per_clkdm",
2333 };
2334
2335 /* Merged cm2_dm11_mux into timer11 */
2336 static struct clk timer11_fck = {
2337         .name           = "timer11_fck",
2338         .parent         = &sys_clkin_ck,
2339         .clksel         = abe_dpll_bypass_clk_mux_sel,
2340         .init           = &omap2_init_clksel_parent,
2341         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2342         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2343         .ops            = &clkops_omap2_dflt,
2344         .recalc         = &omap2_clksel_recalc,
2345         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2346         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2347         .clkdm_name     = "l4_per_clkdm",
2348 };
2349
2350 /* Merged cm2_dm2_mux into timer2 */
2351 static struct clk timer2_fck = {
2352         .name           = "timer2_fck",
2353         .parent         = &sys_clkin_ck,
2354         .clksel         = abe_dpll_bypass_clk_mux_sel,
2355         .init           = &omap2_init_clksel_parent,
2356         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2357         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2358         .ops            = &clkops_omap2_dflt,
2359         .recalc         = &omap2_clksel_recalc,
2360         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2361         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2362         .clkdm_name     = "l4_per_clkdm",
2363 };
2364
2365 /* Merged cm2_dm3_mux into timer3 */
2366 static struct clk timer3_fck = {
2367         .name           = "timer3_fck",
2368         .parent         = &sys_clkin_ck,
2369         .clksel         = abe_dpll_bypass_clk_mux_sel,
2370         .init           = &omap2_init_clksel_parent,
2371         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2372         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2373         .ops            = &clkops_omap2_dflt,
2374         .recalc         = &omap2_clksel_recalc,
2375         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2376         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2377         .clkdm_name     = "l4_per_clkdm",
2378 };
2379
2380 /* Merged cm2_dm4_mux into timer4 */
2381 static struct clk timer4_fck = {
2382         .name           = "timer4_fck",
2383         .parent         = &sys_clkin_ck,
2384         .clksel         = abe_dpll_bypass_clk_mux_sel,
2385         .init           = &omap2_init_clksel_parent,
2386         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2387         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2388         .ops            = &clkops_omap2_dflt,
2389         .recalc         = &omap2_clksel_recalc,
2390         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2391         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2392         .clkdm_name     = "l4_per_clkdm",
2393 };
2394
2395 static const struct clksel timer5_sync_mux_sel[] = {
2396         { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2397         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2398         { .parent = NULL },
2399 };
2400
2401 /* Merged timer5_sync_mux into timer5 */
2402 static struct clk timer5_fck = {
2403         .name           = "timer5_fck",
2404         .parent         = &syc_clk_div_ck,
2405         .clksel         = timer5_sync_mux_sel,
2406         .init           = &omap2_init_clksel_parent,
2407         .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2408         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2409         .ops            = &clkops_omap2_dflt,
2410         .recalc         = &omap2_clksel_recalc,
2411         .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2412         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2413         .clkdm_name     = "abe_clkdm",
2414 };
2415
2416 /* Merged timer6_sync_mux into timer6 */
2417 static struct clk timer6_fck = {
2418         .name           = "timer6_fck",
2419         .parent         = &syc_clk_div_ck,
2420         .clksel         = timer5_sync_mux_sel,
2421         .init           = &omap2_init_clksel_parent,
2422         .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2423         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2424         .ops            = &clkops_omap2_dflt,
2425         .recalc         = &omap2_clksel_recalc,
2426         .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2427         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2428         .clkdm_name     = "abe_clkdm",
2429 };
2430
2431 /* Merged timer7_sync_mux into timer7 */
2432 static struct clk timer7_fck = {
2433         .name           = "timer7_fck",
2434         .parent         = &syc_clk_div_ck,
2435         .clksel         = timer5_sync_mux_sel,
2436         .init           = &omap2_init_clksel_parent,
2437         .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2438         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2439         .ops            = &clkops_omap2_dflt,
2440         .recalc         = &omap2_clksel_recalc,
2441         .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2442         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2443         .clkdm_name     = "abe_clkdm",
2444 };
2445
2446 /* Merged timer8_sync_mux into timer8 */
2447 static struct clk timer8_fck = {
2448         .name           = "timer8_fck",
2449         .parent         = &syc_clk_div_ck,
2450         .clksel         = timer5_sync_mux_sel,
2451         .init           = &omap2_init_clksel_parent,
2452         .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2453         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2454         .ops            = &clkops_omap2_dflt,
2455         .recalc         = &omap2_clksel_recalc,
2456         .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2457         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2458         .clkdm_name     = "abe_clkdm",
2459 };
2460
2461 /* Merged cm2_dm9_mux into timer9 */
2462 static struct clk timer9_fck = {
2463         .name           = "timer9_fck",
2464         .parent         = &sys_clkin_ck,
2465         .clksel         = abe_dpll_bypass_clk_mux_sel,
2466         .init           = &omap2_init_clksel_parent,
2467         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2468         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2469         .ops            = &clkops_omap2_dflt,
2470         .recalc         = &omap2_clksel_recalc,
2471         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2472         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2473         .clkdm_name     = "l4_per_clkdm",
2474 };
2475
2476 static struct clk uart1_fck = {
2477         .name           = "uart1_fck",
2478         .ops            = &clkops_omap2_dflt,
2479         .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2480         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2481         .clkdm_name     = "l4_per_clkdm",
2482         .parent         = &func_48m_fclk,
2483         .recalc         = &followparent_recalc,
2484 };
2485
2486 static struct clk uart2_fck = {
2487         .name           = "uart2_fck",
2488         .ops            = &clkops_omap2_dflt,
2489         .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2490         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2491         .clkdm_name     = "l4_per_clkdm",
2492         .parent         = &func_48m_fclk,
2493         .recalc         = &followparent_recalc,
2494 };
2495
2496 static struct clk uart3_fck = {
2497         .name           = "uart3_fck",
2498         .ops            = &clkops_omap2_dflt,
2499         .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2500         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2501         .clkdm_name     = "l4_per_clkdm",
2502         .parent         = &func_48m_fclk,
2503         .recalc         = &followparent_recalc,
2504 };
2505
2506 static struct clk uart4_fck = {
2507         .name           = "uart4_fck",
2508         .ops            = &clkops_omap2_dflt,
2509         .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2510         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2511         .clkdm_name     = "l4_per_clkdm",
2512         .parent         = &func_48m_fclk,
2513         .recalc         = &followparent_recalc,
2514 };
2515
2516 static struct clk usb_host_fs_fck = {
2517         .name           = "usb_host_fs_fck",
2518         .ops            = &clkops_omap2_dflt,
2519         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2520         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2521         .clkdm_name     = "l3_init_clkdm",
2522         .parent         = &func_48mc_fclk,
2523         .recalc         = &followparent_recalc,
2524 };
2525
2526 static const struct clksel utmi_p1_gfclk_sel[] = {
2527         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2528         { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2529         { .parent = NULL },
2530 };
2531
2532 static struct clk utmi_p1_gfclk = {
2533         .name           = "utmi_p1_gfclk",
2534         .parent         = &init_60m_fclk,
2535         .clksel         = utmi_p1_gfclk_sel,
2536         .init           = &omap2_init_clksel_parent,
2537         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2538         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
2539         .ops            = &clkops_null,
2540         .recalc         = &omap2_clksel_recalc,
2541 };
2542
2543 static struct clk usb_host_hs_utmi_p1_clk = {
2544         .name           = "usb_host_hs_utmi_p1_clk",
2545         .ops            = &clkops_omap2_dflt,
2546         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2547         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2548         .clkdm_name     = "l3_init_clkdm",
2549         .parent         = &utmi_p1_gfclk,
2550         .recalc         = &followparent_recalc,
2551 };
2552
2553 static const struct clksel utmi_p2_gfclk_sel[] = {
2554         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2555         { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2556         { .parent = NULL },
2557 };
2558
2559 static struct clk utmi_p2_gfclk = {
2560         .name           = "utmi_p2_gfclk",
2561         .parent         = &init_60m_fclk,
2562         .clksel         = utmi_p2_gfclk_sel,
2563         .init           = &omap2_init_clksel_parent,
2564         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2565         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
2566         .ops            = &clkops_null,
2567         .recalc         = &omap2_clksel_recalc,
2568 };
2569
2570 static struct clk usb_host_hs_utmi_p2_clk = {
2571         .name           = "usb_host_hs_utmi_p2_clk",
2572         .ops            = &clkops_omap2_dflt,
2573         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2574         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2575         .clkdm_name     = "l3_init_clkdm",
2576         .parent         = &utmi_p2_gfclk,
2577         .recalc         = &followparent_recalc,
2578 };
2579
2580 static struct clk usb_host_hs_utmi_p3_clk = {
2581         .name           = "usb_host_hs_utmi_p3_clk",
2582         .ops            = &clkops_omap2_dflt,
2583         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2584         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2585         .clkdm_name     = "l3_init_clkdm",
2586         .parent         = &init_60m_fclk,
2587         .recalc         = &followparent_recalc,
2588 };
2589
2590 static struct clk usb_host_hs_hsic480m_p1_clk = {
2591         .name           = "usb_host_hs_hsic480m_p1_clk",
2592         .ops            = &clkops_omap2_dflt,
2593         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2594         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2595         .clkdm_name     = "l3_init_clkdm",
2596         .parent         = &dpll_usb_m2_ck,
2597         .recalc         = &followparent_recalc,
2598 };
2599
2600 static struct clk usb_host_hs_hsic60m_p1_clk = {
2601         .name           = "usb_host_hs_hsic60m_p1_clk",
2602         .ops            = &clkops_omap2_dflt,
2603         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2604         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2605         .clkdm_name     = "l3_init_clkdm",
2606         .parent         = &init_60m_fclk,
2607         .recalc         = &followparent_recalc,
2608 };
2609
2610 static struct clk usb_host_hs_hsic60m_p2_clk = {
2611         .name           = "usb_host_hs_hsic60m_p2_clk",
2612         .ops            = &clkops_omap2_dflt,
2613         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2614         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2615         .clkdm_name     = "l3_init_clkdm",
2616         .parent         = &init_60m_fclk,
2617         .recalc         = &followparent_recalc,
2618 };
2619
2620 static struct clk usb_host_hs_hsic480m_p2_clk = {
2621         .name           = "usb_host_hs_hsic480m_p2_clk",
2622         .ops            = &clkops_omap2_dflt,
2623         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2624         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2625         .clkdm_name     = "l3_init_clkdm",
2626         .parent         = &dpll_usb_m2_ck,
2627         .recalc         = &followparent_recalc,
2628 };
2629
2630 static struct clk usb_host_hs_func48mclk = {
2631         .name           = "usb_host_hs_func48mclk",
2632         .ops            = &clkops_omap2_dflt,
2633         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2634         .enable_bit     = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2635         .clkdm_name     = "l3_init_clkdm",
2636         .parent         = &func_48mc_fclk,
2637         .recalc         = &followparent_recalc,
2638 };
2639
2640 static struct clk usb_host_hs_fck = {
2641         .name           = "usb_host_hs_fck",
2642         .ops            = &clkops_omap2_dflt,
2643         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2644         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2645         .clkdm_name     = "l3_init_clkdm",
2646         .parent         = &init_60m_fclk,
2647         .recalc         = &followparent_recalc,
2648 };
2649
2650 static const struct clksel otg_60m_gfclk_sel[] = {
2651         { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2652         { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2653         { .parent = NULL },
2654 };
2655
2656 static struct clk otg_60m_gfclk = {
2657         .name           = "otg_60m_gfclk",
2658         .parent         = &utmi_phy_clkout_ck,
2659         .clksel         = otg_60m_gfclk_sel,
2660         .init           = &omap2_init_clksel_parent,
2661         .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2662         .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
2663         .ops            = &clkops_null,
2664         .recalc         = &omap2_clksel_recalc,
2665 };
2666
2667 static struct clk usb_otg_hs_xclk = {
2668         .name           = "usb_otg_hs_xclk",
2669         .ops            = &clkops_omap2_dflt,
2670         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2671         .enable_bit     = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2672         .clkdm_name     = "l3_init_clkdm",
2673         .parent         = &otg_60m_gfclk,
2674         .recalc         = &followparent_recalc,
2675 };
2676
2677 static struct clk usb_otg_hs_ick = {
2678         .name           = "usb_otg_hs_ick",
2679         .ops            = &clkops_omap2_dflt,
2680         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2681         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2682         .clkdm_name     = "l3_init_clkdm",
2683         .parent         = &l3_div_ck,
2684         .recalc         = &followparent_recalc,
2685 };
2686
2687 static struct clk usb_phy_cm_clk32k = {
2688         .name           = "usb_phy_cm_clk32k",
2689         .ops            = &clkops_omap2_dflt,
2690         .enable_reg     = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2691         .enable_bit     = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2692         .clkdm_name     = "l4_ao_clkdm",
2693         .parent         = &sys_32k_ck,
2694         .recalc         = &followparent_recalc,
2695 };
2696
2697 static struct clk usb_tll_hs_usb_ch2_clk = {
2698         .name           = "usb_tll_hs_usb_ch2_clk",
2699         .ops            = &clkops_omap2_dflt,
2700         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2701         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2702         .clkdm_name     = "l3_init_clkdm",
2703         .parent         = &init_60m_fclk,
2704         .recalc         = &followparent_recalc,
2705 };
2706
2707 static struct clk usb_tll_hs_usb_ch0_clk = {
2708         .name           = "usb_tll_hs_usb_ch0_clk",
2709         .ops            = &clkops_omap2_dflt,
2710         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2711         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2712         .clkdm_name     = "l3_init_clkdm",
2713         .parent         = &init_60m_fclk,
2714         .recalc         = &followparent_recalc,
2715 };
2716
2717 static struct clk usb_tll_hs_usb_ch1_clk = {
2718         .name           = "usb_tll_hs_usb_ch1_clk",
2719         .ops            = &clkops_omap2_dflt,
2720         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2721         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2722         .clkdm_name     = "l3_init_clkdm",
2723         .parent         = &init_60m_fclk,
2724         .recalc         = &followparent_recalc,
2725 };
2726
2727 static struct clk usb_tll_hs_ick = {
2728         .name           = "usb_tll_hs_ick",
2729         .ops            = &clkops_omap2_dflt,
2730         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2731         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2732         .clkdm_name     = "l3_init_clkdm",
2733         .parent         = &l4_div_ck,
2734         .recalc         = &followparent_recalc,
2735 };
2736
2737 static const struct clksel_rate div2_14to18_rates[] = {
2738         { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2739         { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2740         { .div = 0 },
2741 };
2742
2743 static const struct clksel usim_fclk_div[] = {
2744         { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2745         { .parent = NULL },
2746 };
2747
2748 static struct clk usim_ck = {
2749         .name           = "usim_ck",
2750         .parent         = &dpll_per_m4x2_ck,
2751         .clksel         = usim_fclk_div,
2752         .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2753         .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
2754         .ops            = &clkops_null,
2755         .recalc         = &omap2_clksel_recalc,
2756         .round_rate     = &omap2_clksel_round_rate,
2757         .set_rate       = &omap2_clksel_set_rate,
2758 };
2759
2760 static struct clk usim_fclk = {
2761         .name           = "usim_fclk",
2762         .ops            = &clkops_omap2_dflt,
2763         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2764         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2765         .clkdm_name     = "l4_wkup_clkdm",
2766         .parent         = &usim_ck,
2767         .recalc         = &followparent_recalc,
2768 };
2769
2770 static struct clk usim_fck = {
2771         .name           = "usim_fck",
2772         .ops            = &clkops_omap2_dflt,
2773         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2774         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2775         .clkdm_name     = "l4_wkup_clkdm",
2776         .parent         = &sys_32k_ck,
2777         .recalc         = &followparent_recalc,
2778 };
2779
2780 static struct clk wd_timer2_fck = {
2781         .name           = "wd_timer2_fck",
2782         .ops            = &clkops_omap2_dflt,
2783         .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2784         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2785         .clkdm_name     = "l4_wkup_clkdm",
2786         .parent         = &sys_32k_ck,
2787         .recalc         = &followparent_recalc,
2788 };
2789
2790 static struct clk wd_timer3_fck = {
2791         .name           = "wd_timer3_fck",
2792         .ops            = &clkops_omap2_dflt,
2793         .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2794         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2795         .clkdm_name     = "abe_clkdm",
2796         .parent         = &sys_32k_ck,
2797         .recalc         = &followparent_recalc,
2798 };
2799
2800 /* Remaining optional clocks */
2801 static const struct clksel stm_clk_div_div[] = {
2802         { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2803         { .parent = NULL },
2804 };
2805
2806 static struct clk stm_clk_div_ck = {
2807         .name           = "stm_clk_div_ck",
2808         .parent         = &pmd_stm_clock_mux_ck,
2809         .clksel         = stm_clk_div_div,
2810         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2811         .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2812         .ops            = &clkops_null,
2813         .recalc         = &omap2_clksel_recalc,
2814         .round_rate     = &omap2_clksel_round_rate,
2815         .set_rate       = &omap2_clksel_set_rate,
2816 };
2817
2818 static const struct clksel trace_clk_div_div[] = {
2819         { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2820         { .parent = NULL },
2821 };
2822
2823 static struct clk trace_clk_div_ck = {
2824         .name           = "trace_clk_div_ck",
2825         .parent         = &pmd_trace_clk_mux_ck,
2826         .clksel         = trace_clk_div_div,
2827         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2828         .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2829         .ops            = &clkops_null,
2830         .recalc         = &omap2_clksel_recalc,
2831         .round_rate     = &omap2_clksel_round_rate,
2832         .set_rate       = &omap2_clksel_set_rate,
2833 };
2834
2835 /* SCRM aux clk nodes */
2836
2837 static const struct clksel auxclk_src_sel[] = {
2838         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2839         { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2840         { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2841         { .parent = NULL },
2842 };
2843
2844 static const struct clksel_rate div16_1to16_rates[] = {
2845         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
2846         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
2847         { .div = 3, .val = 2, .flags = RATE_IN_4430 },
2848         { .div = 4, .val = 3, .flags = RATE_IN_4430 },
2849         { .div = 5, .val = 4, .flags = RATE_IN_4430 },
2850         { .div = 6, .val = 5, .flags = RATE_IN_4430 },
2851         { .div = 7, .val = 6, .flags = RATE_IN_4430 },
2852         { .div = 8, .val = 7, .flags = RATE_IN_4430 },
2853         { .div = 9, .val = 8, .flags = RATE_IN_4430 },
2854         { .div = 10, .val = 9, .flags = RATE_IN_4430 },
2855         { .div = 11, .val = 10, .flags = RATE_IN_4430 },
2856         { .div = 12, .val = 11, .flags = RATE_IN_4430 },
2857         { .div = 13, .val = 12, .flags = RATE_IN_4430 },
2858         { .div = 14, .val = 13, .flags = RATE_IN_4430 },
2859         { .div = 15, .val = 14, .flags = RATE_IN_4430 },
2860         { .div = 16, .val = 15, .flags = RATE_IN_4430 },
2861         { .div = 0 },
2862 };
2863
2864 static struct clk auxclk0_src_ck = {
2865         .name           = "auxclk0_src_ck",
2866         .parent         = &sys_clkin_ck,
2867         .init           = &omap2_init_clksel_parent,
2868         .ops            = &clkops_omap2_dflt,
2869         .clksel         = auxclk_src_sel,
2870         .clksel_reg     = OMAP4_SCRM_AUXCLK0,
2871         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2872         .recalc         = &omap2_clksel_recalc,
2873         .enable_reg     = OMAP4_SCRM_AUXCLK0,
2874         .enable_bit     = OMAP4_ENABLE_SHIFT,
2875 };
2876
2877 static const struct clksel auxclk0_sel[] = {
2878         { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
2879         { .parent = NULL },
2880 };
2881
2882 static struct clk auxclk0_ck = {
2883         .name           = "auxclk0_ck",
2884         .parent         = &auxclk0_src_ck,
2885         .clksel         = auxclk0_sel,
2886         .clksel_reg     = OMAP4_SCRM_AUXCLK0,
2887         .clksel_mask    = OMAP4_CLKDIV_MASK,
2888         .ops            = &clkops_null,
2889         .recalc         = &omap2_clksel_recalc,
2890         .round_rate     = &omap2_clksel_round_rate,
2891         .set_rate       = &omap2_clksel_set_rate,
2892 };
2893
2894 static struct clk auxclk1_src_ck = {
2895         .name           = "auxclk1_src_ck",
2896         .parent         = &sys_clkin_ck,
2897         .init           = &omap2_init_clksel_parent,
2898         .ops            = &clkops_omap2_dflt,
2899         .clksel         = auxclk_src_sel,
2900         .clksel_reg     = OMAP4_SCRM_AUXCLK1,
2901         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2902         .recalc         = &omap2_clksel_recalc,
2903         .enable_reg     = OMAP4_SCRM_AUXCLK1,
2904         .enable_bit     = OMAP4_ENABLE_SHIFT,
2905 };
2906
2907 static const struct clksel auxclk1_sel[] = {
2908         { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
2909         { .parent = NULL },
2910 };
2911
2912 static struct clk auxclk1_ck = {
2913         .name           = "auxclk1_ck",
2914         .parent         = &auxclk1_src_ck,
2915         .clksel         = auxclk1_sel,
2916         .clksel_reg     = OMAP4_SCRM_AUXCLK1,
2917         .clksel_mask    = OMAP4_CLKDIV_MASK,
2918         .ops            = &clkops_null,
2919         .recalc         = &omap2_clksel_recalc,
2920         .round_rate     = &omap2_clksel_round_rate,
2921         .set_rate       = &omap2_clksel_set_rate,
2922 };
2923
2924 static struct clk auxclk2_src_ck = {
2925         .name           = "auxclk2_src_ck",
2926         .parent         = &sys_clkin_ck,
2927         .init           = &omap2_init_clksel_parent,
2928         .ops            = &clkops_omap2_dflt,
2929         .clksel         = auxclk_src_sel,
2930         .clksel_reg     = OMAP4_SCRM_AUXCLK2,
2931         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2932         .recalc         = &omap2_clksel_recalc,
2933         .enable_reg     = OMAP4_SCRM_AUXCLK2,
2934         .enable_bit     = OMAP4_ENABLE_SHIFT,
2935 };
2936
2937 static const struct clksel auxclk2_sel[] = {
2938         { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
2939         { .parent = NULL },
2940 };
2941
2942 static struct clk auxclk2_ck = {
2943         .name           = "auxclk2_ck",
2944         .parent         = &auxclk2_src_ck,
2945         .clksel         = auxclk2_sel,
2946         .clksel_reg     = OMAP4_SCRM_AUXCLK2,
2947         .clksel_mask    = OMAP4_CLKDIV_MASK,
2948         .ops            = &clkops_null,
2949         .recalc         = &omap2_clksel_recalc,
2950         .round_rate     = &omap2_clksel_round_rate,
2951         .set_rate       = &omap2_clksel_set_rate,
2952 };
2953
2954 static struct clk auxclk3_src_ck = {
2955         .name           = "auxclk3_src_ck",
2956         .parent         = &sys_clkin_ck,
2957         .init           = &omap2_init_clksel_parent,
2958         .ops            = &clkops_omap2_dflt,
2959         .clksel         = auxclk_src_sel,
2960         .clksel_reg     = OMAP4_SCRM_AUXCLK3,
2961         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2962         .recalc         = &omap2_clksel_recalc,
2963         .enable_reg     = OMAP4_SCRM_AUXCLK3,
2964         .enable_bit     = OMAP4_ENABLE_SHIFT,
2965 };
2966
2967 static const struct clksel auxclk3_sel[] = {
2968         { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
2969         { .parent = NULL },
2970 };
2971
2972 static struct clk auxclk3_ck = {
2973         .name           = "auxclk3_ck",
2974         .parent         = &auxclk3_src_ck,
2975         .clksel         = auxclk3_sel,
2976         .clksel_reg     = OMAP4_SCRM_AUXCLK3,
2977         .clksel_mask    = OMAP4_CLKDIV_MASK,
2978         .ops            = &clkops_null,
2979         .recalc         = &omap2_clksel_recalc,
2980         .round_rate     = &omap2_clksel_round_rate,
2981         .set_rate       = &omap2_clksel_set_rate,
2982 };
2983
2984 static struct clk auxclk4_src_ck = {
2985         .name           = "auxclk4_src_ck",
2986         .parent         = &sys_clkin_ck,
2987         .init           = &omap2_init_clksel_parent,
2988         .ops            = &clkops_omap2_dflt,
2989         .clksel         = auxclk_src_sel,
2990         .clksel_reg     = OMAP4_SCRM_AUXCLK4,
2991         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2992         .recalc         = &omap2_clksel_recalc,
2993         .enable_reg     = OMAP4_SCRM_AUXCLK4,
2994         .enable_bit     = OMAP4_ENABLE_SHIFT,
2995 };
2996
2997 static const struct clksel auxclk4_sel[] = {
2998         { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
2999         { .parent = NULL },
3000 };
3001
3002 static struct clk auxclk4_ck = {
3003         .name           = "auxclk4_ck",
3004         .parent         = &auxclk4_src_ck,
3005         .clksel         = auxclk4_sel,
3006         .clksel_reg     = OMAP4_SCRM_AUXCLK4,
3007         .clksel_mask    = OMAP4_CLKDIV_MASK,
3008         .ops            = &clkops_null,
3009         .recalc         = &omap2_clksel_recalc,
3010         .round_rate     = &omap2_clksel_round_rate,
3011         .set_rate       = &omap2_clksel_set_rate,
3012 };
3013
3014 static struct clk auxclk5_src_ck = {
3015         .name           = "auxclk5_src_ck",
3016         .parent         = &sys_clkin_ck,
3017         .init           = &omap2_init_clksel_parent,
3018         .ops            = &clkops_omap2_dflt,
3019         .clksel         = auxclk_src_sel,
3020         .clksel_reg     = OMAP4_SCRM_AUXCLK5,
3021         .clksel_mask    = OMAP4_SRCSELECT_MASK,
3022         .recalc         = &omap2_clksel_recalc,
3023         .enable_reg     = OMAP4_SCRM_AUXCLK5,
3024         .enable_bit     = OMAP4_ENABLE_SHIFT,
3025 };
3026
3027 static const struct clksel auxclk5_sel[] = {
3028         { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
3029         { .parent = NULL },
3030 };
3031
3032 static struct clk auxclk5_ck = {
3033         .name           = "auxclk5_ck",
3034         .parent         = &auxclk5_src_ck,
3035         .clksel         = auxclk5_sel,
3036         .clksel_reg     = OMAP4_SCRM_AUXCLK5,
3037         .clksel_mask    = OMAP4_CLKDIV_MASK,
3038         .ops            = &clkops_null,
3039         .recalc         = &omap2_clksel_recalc,
3040         .round_rate     = &omap2_clksel_round_rate,
3041         .set_rate       = &omap2_clksel_set_rate,
3042 };
3043
3044 static const struct clksel auxclkreq_sel[] = {
3045         { .parent = &auxclk0_ck, .rates = div_1_0_rates },
3046         { .parent = &auxclk1_ck, .rates = div_1_1_rates },
3047         { .parent = &auxclk2_ck, .rates = div_1_2_rates },
3048         { .parent = &auxclk3_ck, .rates = div_1_3_rates },
3049         { .parent = &auxclk4_ck, .rates = div_1_4_rates },
3050         { .parent = &auxclk5_ck, .rates = div_1_5_rates },
3051         { .parent = NULL },
3052 };
3053
3054 static struct clk auxclkreq0_ck = {
3055         .name           = "auxclkreq0_ck",
3056         .parent         = &auxclk0_ck,
3057         .init           = &omap2_init_clksel_parent,
3058         .ops            = &clkops_null,
3059         .clksel         = auxclkreq_sel,
3060         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ0,
3061         .clksel_mask    = OMAP4_MAPPING_MASK,
3062         .recalc         = &omap2_clksel_recalc,
3063 };
3064
3065 static struct clk auxclkreq1_ck = {
3066         .name           = "auxclkreq1_ck",
3067         .parent         = &auxclk1_ck,
3068         .init           = &omap2_init_clksel_parent,
3069         .ops            = &clkops_null,
3070         .clksel         = auxclkreq_sel,
3071         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ1,
3072         .clksel_mask    = OMAP4_MAPPING_MASK,
3073         .recalc         = &omap2_clksel_recalc,
3074 };
3075
3076 static struct clk auxclkreq2_ck = {
3077         .name           = "auxclkreq2_ck",
3078         .parent         = &auxclk2_ck,
3079         .init           = &omap2_init_clksel_parent,
3080         .ops            = &clkops_null,
3081         .clksel         = auxclkreq_sel,
3082         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ2,
3083         .clksel_mask    = OMAP4_MAPPING_MASK,
3084         .recalc         = &omap2_clksel_recalc,
3085 };
3086
3087 static struct clk auxclkreq3_ck = {
3088         .name           = "auxclkreq3_ck",
3089         .parent         = &auxclk3_ck,
3090         .init           = &omap2_init_clksel_parent,
3091         .ops            = &clkops_null,
3092         .clksel         = auxclkreq_sel,
3093         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ3,
3094         .clksel_mask    = OMAP4_MAPPING_MASK,
3095         .recalc         = &omap2_clksel_recalc,
3096 };
3097
3098 static struct clk auxclkreq4_ck = {
3099         .name           = "auxclkreq4_ck",
3100         .parent         = &auxclk4_ck,
3101         .init           = &omap2_init_clksel_parent,
3102         .ops            = &clkops_null,
3103         .clksel         = auxclkreq_sel,
3104         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ4,
3105         .clksel_mask    = OMAP4_MAPPING_MASK,
3106         .recalc         = &omap2_clksel_recalc,
3107 };
3108
3109 static struct clk auxclkreq5_ck = {
3110         .name           = "auxclkreq5_ck",
3111         .parent         = &auxclk5_ck,
3112         .init           = &omap2_init_clksel_parent,
3113         .ops            = &clkops_null,
3114         .clksel         = auxclkreq_sel,
3115         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ5,
3116         .clksel_mask    = OMAP4_MAPPING_MASK,
3117         .recalc         = &omap2_clksel_recalc,
3118 };
3119
3120 /*
3121  * clkdev
3122  */
3123
3124 static struct omap_clk omap44xx_clks[] = {
3125         CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
3126         CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
3127         CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
3128         CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
3129         CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
3130         CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
3131         CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
3132         CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
3133         CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
3134         CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
3135         CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
3136         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
3137         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
3138         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
3139         CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
3140         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
3141         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
3142         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
3143         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
3144         CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
3145         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
3146         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
3147         CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
3148         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
3149         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
3150         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
3151         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
3152         CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
3153         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
3154         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
3155         CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
3156         CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
3157         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
3158         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
3159         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
3160         CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
3161         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
3162         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
3163         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
3164         CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
3165         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
3166         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
3167         CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
3168         CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
3169         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
3170         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
3171         CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
3172         CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
3173         CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
3174         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
3175         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
3176         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
3177         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
3178         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
3179         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
3180         CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
3181         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
3182         CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
3183         CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
3184         CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
3185         CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
3186         CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
3187         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
3188         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
3189         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
3190         CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
3191         CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
3192         CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
3193         CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
3194         CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
3195         CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
3196         CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
3197         CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
3198         CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
3199         CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
3200         CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
3201         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
3202         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
3203         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
3204         CLK("smp_twd",  NULL,                           &mpu_periphclk, CK_443X),
3205         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
3206         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
3207         CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
3208         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
3209         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
3210         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
3211         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
3212         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
3213         CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
3214         CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
3215         CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
3216         CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
3217         CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
3218         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
3219         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
3220         CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
3221         CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
3222         CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
3223         CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
3224         CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
3225         CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
3226         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
3227         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
3228         CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
3229         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
3230         CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
3231         CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
3232         CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
3233         CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
3234         CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
3235         CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
3236         CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
3237         CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
3238         CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
3239         CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
3240         CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
3241         CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
3242         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
3243         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
3244         CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
3245         CLK(NULL,       "hdq1w_fck",                    &hdq1w_fck,     CK_443X),
3246         CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
3247         CLK(NULL,       "i2c1_fck",                     &i2c1_fck,      CK_443X),
3248         CLK(NULL,       "i2c2_fck",                     &i2c2_fck,      CK_443X),
3249         CLK(NULL,       "i2c3_fck",                     &i2c3_fck,      CK_443X),
3250         CLK(NULL,       "i2c4_fck",                     &i2c4_fck,      CK_443X),
3251         CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
3252         CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
3253         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
3254         CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
3255         CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
3256         CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
3257         CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
3258         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
3259         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
3260         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
3261         CLK(NULL,       "mcbsp1_fck",                   &mcbsp1_fck,    CK_443X),
3262         CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
3263         CLK(NULL,       "mcbsp2_fck",                   &mcbsp2_fck,    CK_443X),
3264         CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
3265         CLK(NULL,       "mcbsp3_fck",                   &mcbsp3_fck,    CK_443X),
3266         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
3267         CLK(NULL,       "mcbsp4_fck",                   &mcbsp4_fck,    CK_443X),
3268         CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
3269         CLK(NULL,       "mcspi1_fck",                   &mcspi1_fck,    CK_443X),
3270         CLK(NULL,       "mcspi2_fck",                   &mcspi2_fck,    CK_443X),
3271         CLK(NULL,       "mcspi3_fck",                   &mcspi3_fck,    CK_443X),
3272         CLK(NULL,       "mcspi4_fck",                   &mcspi4_fck,    CK_443X),
3273         CLK(NULL,       "mmc1_fck",                     &mmc1_fck,      CK_443X),
3274         CLK(NULL,       "mmc2_fck",                     &mmc2_fck,      CK_443X),
3275         CLK(NULL,       "mmc3_fck",                     &mmc3_fck,      CK_443X),
3276         CLK(NULL,       "mmc4_fck",                     &mmc4_fck,      CK_443X),
3277         CLK(NULL,       "mmc5_fck",                     &mmc5_fck,      CK_443X),
3278         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
3279         CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
3280         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
3281         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
3282         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
3283         CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
3284         CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
3285         CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
3286         CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
3287         CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
3288         CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
3289         CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
3290         CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
3291         CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
3292         CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
3293         CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
3294         CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
3295         CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
3296         CLK(NULL,       "gpt1_fck",                     &timer1_fck,    CK_443X),
3297         CLK(NULL,       "gpt10_fck",                    &timer10_fck,   CK_443X),
3298         CLK(NULL,       "gpt11_fck",                    &timer11_fck,   CK_443X),
3299         CLK(NULL,       "gpt2_fck",                     &timer2_fck,    CK_443X),
3300         CLK(NULL,       "gpt3_fck",                     &timer3_fck,    CK_443X),
3301         CLK(NULL,       "gpt4_fck",                     &timer4_fck,    CK_443X),
3302         CLK(NULL,       "gpt5_fck",                     &timer5_fck,    CK_443X),
3303         CLK(NULL,       "gpt6_fck",                     &timer6_fck,    CK_443X),
3304         CLK(NULL,       "gpt7_fck",                     &timer7_fck,    CK_443X),
3305         CLK(NULL,       "gpt8_fck",                     &timer8_fck,    CK_443X),
3306         CLK(NULL,       "gpt9_fck",                     &timer9_fck,    CK_443X),
3307         CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
3308         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
3309         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
3310         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
3311         CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
3312         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
3313         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
3314         CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
3315         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
3316         CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
3317         CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
3318         CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
3319         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
3320         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
3321         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
3322         CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck,       CK_443X),
3323         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
3324         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
3325         CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
3326         CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
3327         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
3328         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
3329         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
3330         CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
3331         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
3332         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
3333         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
3334         CLK(NULL,       "wd_timer2_fck",                &wd_timer2_fck, CK_443X),
3335         CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
3336         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
3337         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
3338         CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck,        CK_443X),
3339         CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
3340         CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
3341         CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck,        CK_443X),
3342         CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
3343         CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
3344         CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck,        CK_443X),
3345         CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
3346         CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
3347         CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck,        CK_443X),
3348         CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
3349         CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
3350         CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck,        CK_443X),
3351         CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
3352         CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
3353         CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck,        CK_443X),
3354         CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
3355         CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
3356         CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
3357         CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
3358         CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
3359         CLK(NULL,       "gpt3_ick",                     &dummy_ck,      CK_443X),
3360         CLK(NULL,       "gpt4_ick",                     &dummy_ck,      CK_443X),
3361         CLK(NULL,       "gpt5_ick",                     &dummy_ck,      CK_443X),
3362         CLK(NULL,       "gpt6_ick",                     &dummy_ck,      CK_443X),
3363         CLK(NULL,       "gpt7_ick",                     &dummy_ck,      CK_443X),
3364         CLK(NULL,       "gpt8_ick",                     &dummy_ck,      CK_443X),
3365         CLK(NULL,       "gpt9_ick",                     &dummy_ck,      CK_443X),
3366         CLK(NULL,       "gpt10_ick",                    &dummy_ck,      CK_443X),
3367         CLK(NULL,       "gpt11_ick",                    &dummy_ck,      CK_443X),
3368         CLK("omap_i2c.1",       "ick",                          &dummy_ck,      CK_443X),
3369         CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
3370         CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
3371         CLK("omap_i2c.4",       "ick",                          &dummy_ck,      CK_443X),
3372         CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
3373         CLK("omap_hsmmc.0",     "ick",                          &dummy_ck,      CK_443X),
3374         CLK("omap_hsmmc.1",     "ick",                          &dummy_ck,      CK_443X),
3375         CLK("omap_hsmmc.2",     "ick",                          &dummy_ck,      CK_443X),
3376         CLK("omap_hsmmc.3",     "ick",                          &dummy_ck,      CK_443X),
3377         CLK("omap_hsmmc.4",     "ick",                          &dummy_ck,      CK_443X),
3378         CLK("omap-mcbsp.1",     "ick",                          &dummy_ck,      CK_443X),
3379         CLK("omap-mcbsp.2",     "ick",                          &dummy_ck,      CK_443X),
3380         CLK("omap-mcbsp.3",     "ick",                          &dummy_ck,      CK_443X),
3381         CLK("omap-mcbsp.4",     "ick",                          &dummy_ck,      CK_443X),
3382         CLK("omap2_mcspi.1",    "ick",                          &dummy_ck,      CK_443X),
3383         CLK("omap2_mcspi.2",    "ick",                          &dummy_ck,      CK_443X),
3384         CLK("omap2_mcspi.3",    "ick",                          &dummy_ck,      CK_443X),
3385         CLK("omap2_mcspi.4",    "ick",                          &dummy_ck,      CK_443X),
3386         CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
3387         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
3388         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
3389         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
3390         CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
3391         CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
3392         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
3393         CLK("omap_timer.1",     "32k_ck",       &sys_32k_ck,    CK_443X),
3394         CLK("omap_timer.2",     "32k_ck",       &sys_32k_ck,    CK_443X),
3395         CLK("omap_timer.3",     "32k_ck",       &sys_32k_ck,    CK_443X),
3396         CLK("omap_timer.4",     "32k_ck",       &sys_32k_ck,    CK_443X),
3397         CLK("omap_timer.5",     "32k_ck",       &sys_32k_ck,    CK_443X),
3398         CLK("omap_timer.6",     "32k_ck",       &sys_32k_ck,    CK_443X),
3399         CLK("omap_timer.7",     "32k_ck",       &sys_32k_ck,    CK_443X),
3400         CLK("omap_timer.8",     "32k_ck",       &sys_32k_ck,    CK_443X),
3401         CLK("omap_timer.9",     "32k_ck",       &sys_32k_ck,    CK_443X),
3402         CLK("omap_timer.10",    "32k_ck",       &sys_32k_ck,    CK_443X),
3403         CLK("omap_timer.11",    "32k_ck",       &sys_32k_ck,    CK_443X),
3404         CLK("omap_timer.1",     "sys_ck",       &sys_clkin_ck,  CK_443X),
3405         CLK("omap_timer.2",     "sys_ck",       &sys_clkin_ck,  CK_443X),
3406         CLK("omap_timer.3",     "sys_ck",       &sys_clkin_ck,  CK_443X),
3407         CLK("omap_timer.4",     "sys_ck",       &sys_clkin_ck,  CK_443X),
3408         CLK("omap_timer.9",     "sys_ck",       &sys_clkin_ck,  CK_443X),
3409         CLK("omap_timer.10",    "sys_ck",       &sys_clkin_ck,  CK_443X),
3410         CLK("omap_timer.11",    "sys_ck",       &sys_clkin_ck,  CK_443X),
3411         CLK("omap_timer.5",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
3412         CLK("omap_timer.6",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
3413         CLK("omap_timer.7",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
3414         CLK("omap_timer.8",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
3415 };
3416
3417 int __init omap4xxx_clk_init(void)
3418 {
3419         struct omap_clk *c;
3420         u32 cpu_clkflg;
3421
3422         if (cpu_is_omap443x()) {
3423                 cpu_mask = RATE_IN_4430;
3424                 cpu_clkflg = CK_443X;
3425         } else if (cpu_is_omap446x()) {
3426                 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
3427                 cpu_clkflg = CK_446X | CK_443X;
3428         } else {
3429                 return 0;
3430         }
3431
3432         clk_init(&omap2_clk_functions);
3433
3434         /*
3435          * Must stay commented until all OMAP SoC drivers are
3436          * converted to runtime PM, or drivers may start crashing
3437          *
3438          * omap2_clk_disable_clkdm_control();
3439          */
3440
3441         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3442                                                                           c++)
3443                 clk_preinit(c->lk.clk);
3444
3445         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3446                                                                           c++)
3447                 if (c->cpu & cpu_clkflg) {
3448                         clkdev_add(&c->lk);
3449                         clk_register(c->lk.clk);
3450                         omap2_init_clk_clkdm(c->lk.clk);
3451                 }
3452
3453         /* Disable autoidle on all clocks; let the PM code enable it later */
3454         omap_clk_disable_autoidle_all();
3455
3456         recalculate_root_clocks();
3457
3458         /*
3459          * Only enable those clocks we will need, let the drivers
3460          * enable other clocks as necessary
3461          */
3462         clk_enable_init_clocks();
3463
3464         return 0;
3465 }