arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  39
  40 /* Maximum DPLL multiplier, divider values for OMAP3 */
  41 #define OMAP3_MAX_DPLL_MULT             2048
  42 #define OMAP3_MAX_DPLL_DIV              128
  43
  44 /*
  45  * DPLL1 supplies clock to the MPU.
  46  * DPLL2 supplies clock to the IVA2.
  47  * DPLL3 supplies CORE domain clocks.
  48  * DPLL4 supplies peripheral clocks.
  49  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  50  */
  51
  52 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  53 #define DPLL_LOW_POWER_STOP             0x1
  54 #define DPLL_LOW_POWER_BYPASS           0x5
  55 #define DPLL_LOCKED                     0x7
  56
  57 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
  58         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
  59
  60 #define OMAP3430_PRM_CLKSRC_CTRL                                        \
  61         _OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET)
  62
  63 #define OMAP3430_PRM_CLKSEL                                             \
  64         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
  65
  66 #define OMAP3430_PRM_CLKOUT_CTRL                                        \
  67         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
  68
  69 /* PRM CLOCKS */
  70
  71 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  72 static struct clk omap_32k_fck = {
  73         .name           = "omap_32k_fck",
  74         .rate           = 32768,
  75         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  76                                 ALWAYS_ENABLED,
  77         .clkdm          = { .name = "prm_clkdm" },
  78         .recalc         = &propagate_rate,
  79 };
  80
  81 static struct clk secure_32k_fck = {
  82         .name           = "secure_32k_fck",
  83         .rate           = 32768,
  84         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  85                                 ALWAYS_ENABLED,
  86         .clkdm          = { .name = "prm_clkdm" },
  87         .recalc         = &propagate_rate,
  88 };
  89
  90 /* Virtual source clocks for osc_sys_ck */
  91 static struct clk virt_12m_ck = {
  92         .name           = "virt_12m_ck",
  93         .rate           = 12000000,
  94         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  95                                 ALWAYS_ENABLED,
  96         .clkdm          = { .name = "prm_clkdm" },
  97         .recalc         = &propagate_rate,
  98 };
  99
 100 static struct clk virt_13m_ck = {
 101         .name           = "virt_13m_ck",
 102         .rate           = 13000000,
 103         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 104                                 ALWAYS_ENABLED,
 105         .clkdm          = { .name = "prm_clkdm" },
 106         .recalc         = &propagate_rate,
 107 };
 108
 109 static struct clk virt_16_8m_ck = {
 110         .name           = "virt_16_8m_ck",
 111         .rate           = 16800000,
 112         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
 113                                 ALWAYS_ENABLED,
 114         .clkdm          = { .name = "prm_clkdm" },
 115         .recalc         = &propagate_rate,
 116 };
 117
 118 static struct clk virt_19_2m_ck = {
 119         .name           = "virt_19_2m_ck",
 120         .rate           = 19200000,
 121         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 122                                 ALWAYS_ENABLED,
 123         .clkdm          = { .name = "prm_clkdm" },
 124         .recalc         = &propagate_rate,
 125 };
 126
 127 static struct clk virt_26m_ck = {
 128         .name           = "virt_26m_ck",
 129         .rate           = 26000000,
 130         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 131                                 ALWAYS_ENABLED,
 132         .clkdm          = { .name = "prm_clkdm" },
 133         .recalc         = &propagate_rate,
 134 };
 135
 136 static struct clk virt_38_4m_ck = {
 137         .name           = "virt_38_4m_ck",
 138         .rate           = 38400000,
 139         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 140                                 ALWAYS_ENABLED,
 141         .clkdm          = { .name = "prm_clkdm" },
 142         .recalc         = &propagate_rate,
 143 };
 144
 145 static const struct clksel_rate osc_sys_12m_rates[] = {
 146         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 147         { .div = 0 }
 148 };
 149
 150 static const struct clksel_rate osc_sys_13m_rates[] = {
 151         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 152         { .div = 0 }
 153 };
 154
 155 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 156         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 157         { .div = 0 }
 158 };
 159
 160 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 161         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 162         { .div = 0 }
 163 };
 164
 165 static const struct clksel_rate osc_sys_26m_rates[] = {
 166         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 167         { .div = 0 }
 168 };
 169
 170 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 171         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 172         { .div = 0 }
 173 };
 174
 175 static const struct clksel osc_sys_clksel[] = {
 176         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 177         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 178         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 179         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 180         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 181         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 182         { .parent = NULL },
 183 };
 184
 185 /* Oscillator clock */
 186 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 187 static struct clk osc_sys_ck = {
 188         .name           = "osc_sys_ck",
 189         .init           = &omap2_init_clksel_parent,
 190         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSEL,
 191         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 192         .clksel         = osc_sys_clksel,
 193         /* REVISIT: deal with autoextclkmode? */
 194         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 195                                 ALWAYS_ENABLED,
 196         .clkdm          = { .name = "prm_clkdm" },
 197         .recalc         = &omap2_clksel_recalc,
 198 };
 199
 200 static const struct clksel_rate div2_rates[] = {
 201         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 202         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 203         { .div = 0 }
 204 };
 205
 206 static const struct clksel sys_clksel[] = {
 207         { .parent = &osc_sys_ck, .rates = div2_rates },
 208         { .parent = NULL }
 209 };
 210
 211 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 212 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 213 static struct clk sys_ck = {
 214         .name           = "sys_ck",
 215         .parent         = &osc_sys_ck,
 216         .init           = &omap2_init_clksel_parent,
 217         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSRC_CTRL,
 218         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 219         .clksel         = sys_clksel,
 220         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 221         .clkdm          = { .name = "prm_clkdm" },
 222         .recalc         = &omap2_clksel_recalc,
 223 };
 224
 225 static struct clk sys_altclk = {
 226         .name           = "sys_altclk",
 227         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 228         .clkdm          = { .name = "cm_clkdm" },
 229         .recalc         = &propagate_rate,
 230 };
 231
 232 /*
 233  * Optional external clock input for some McBSPs
 234  * Apparently this is not really in prm_clkdm, but rather is fed into
 235  * both CORE and PER separately.
 236  */
 237 static struct clk mcbsp_clks = {
 238         .name           = "mcbsp_clks",
 239         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 240         .clkdm          = { .name = "prm_clkdm" },
 241         .recalc         = &propagate_rate,
 242 };
 243
 244 /* PRM EXTERNAL CLOCK OUTPUT */
 245
 246 static struct clk sys_clkout1 = {
 247         .name           = "sys_clkout1",
 248         .parent         = &osc_sys_ck,
 249         .enable_reg     = (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
 250         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 251         .flags          = CLOCK_IN_OMAP343X,
 252         .clkdm          = { .name = "prm_clkdm" },
 253         .recalc         = &followparent_recalc,
 254 };
 255
 256 /* DPLLS */
 257
 258 /* CM CLOCKS */
 259
 260 static const struct clksel_rate dpll_bypass_rates[] = {
 261         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 262         { .div = 0 }
 263 };
 264
 265 static const struct clksel_rate dpll_locked_rates[] = {
 266         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 267         { .div = 0 }
 268 };
 269
 270 static const struct clksel_rate div16_dpll_rates[] = {
 271         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 272         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 273         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 274         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 275         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 276         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 277         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 278         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 279         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 280         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 281         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 282         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 283         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 284         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 285         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 286         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 287         { .div = 0 }
 288 };
 289
 290 #define _OMAP34XX_CM_REGADDR(module, reg)                               \
 291         ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
 292
 293 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
 294         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
 295
 296 /* DPLL1 */
 297 /* MPU clock source */
 298 /* Type: DPLL */
 299 static struct dpll_data dpll1_dd = {
 300         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 301         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 302         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 303         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 304         .control_reg    = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 305         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 306         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 307         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 308         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 309         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 310         .autoidle_reg   = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 311         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 312         .idlest_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 313         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 314         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 315         .max_divider    = OMAP3_MAX_DPLL_DIV,
 316         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 317 };
 318
 319 static struct clk dpll1_ck = {
 320         .name           = "dpll1_ck",
 321         .parent         = &sys_ck,
 322         .dpll_data      = &dpll1_dd,
 323         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 324         .round_rate     = &omap2_dpll_round_rate,
 325         .set_rate       = &omap3_noncore_dpll_set_rate,
 326         .clkdm          = { .name = "dpll1_clkdm" },
 327         .recalc         = &omap3_dpll_recalc,
 328 };
 329
 330 /*
 331  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 332  * DPLL isn't bypassed.
 333  */
 334 static struct clk dpll1_x2_ck = {
 335         .name           = "dpll1_x2_ck",
 336         .parent         = &dpll1_ck,
 337         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 338                                 PARENT_CONTROLS_CLOCK,
 339         .clkdm          = { .name = "dpll1_clkdm" },
 340         .recalc         = &omap3_clkoutx2_recalc,
 341 };
 342
 343 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 344 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 345         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 346         { .parent = NULL }
 347 };
 348
 349 /*
 350  * Does not exist in the TRM - needed to separate the M2 divider from
 351  * bypass selection in mpu_ck
 352  */
 353 static struct clk dpll1_x2m2_ck = {
 354         .name           = "dpll1_x2m2_ck",
 355         .parent         = &dpll1_x2_ck,
 356         .init           = &omap2_init_clksel_parent,
 357         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 358         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 359         .clksel         = div16_dpll1_x2m2_clksel,
 360         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 361                                 PARENT_CONTROLS_CLOCK,
 362         .clkdm          = { .name = "dpll1_clkdm" },
 363         .recalc         = &omap2_clksel_recalc,
 364 };
 365
 366 /* DPLL2 */
 367 /* IVA2 clock source */
 368 /* Type: DPLL */
 369
 370 static struct dpll_data dpll2_dd = {
 371         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 372         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 373         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 374         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 375         .control_reg    = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 376         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 377         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 378                                 (1 << DPLL_LOW_POWER_BYPASS),
 379         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 380         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 381         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 382         .autoidle_reg   = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 383         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 384         .idlest_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 385         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 386         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 387         .max_divider    = OMAP3_MAX_DPLL_DIV,
 388         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 389 };
 390
 391 static struct clk dpll2_ck = {
 392         .name           = "dpll2_ck",
 393         .parent         = &sys_ck,
 394         .dpll_data      = &dpll2_dd,
 395         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 396         .enable         = &omap3_noncore_dpll_enable,
 397         .disable        = &omap3_noncore_dpll_disable,
 398         .round_rate     = &omap2_dpll_round_rate,
 399         .set_rate       = &omap3_noncore_dpll_set_rate,
 400         .clkdm          = { .name = "dpll2_clkdm" },
 401         .recalc         = &omap3_dpll_recalc,
 402 };
 403
 404 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 405         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 406         { .parent = NULL }
 407 };
 408
 409 /*
 410  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 411  * or CLKOUTX2. CLKOUT seems most plausible.
 412  */
 413 static struct clk dpll2_m2_ck = {
 414         .name           = "dpll2_m2_ck",
 415         .parent         = &dpll2_ck,
 416         .init           = &omap2_init_clksel_parent,
 417         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 418                                           OMAP3430_CM_CLKSEL2_PLL),
 419         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 420         .clksel         = div16_dpll2_m2x2_clksel,
 421         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 422                                 PARENT_CONTROLS_CLOCK,
 423         .clkdm          = { .name = "dpll2_clkdm" },
 424         .recalc         = &omap2_clksel_recalc,
 425 };
 426
 427 /*
 428  * DPLL3
 429  * Source clock for all interfaces and for some device fclks
 430  * REVISIT: Also supports fast relock bypass - not included below
 431  */
 432 static struct dpll_data dpll3_dd = {
 433         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 434         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 435         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 436         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 437         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 438         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 439         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 440         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 441         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 442         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 443         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 444         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 445         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 446         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 447         .max_divider    = OMAP3_MAX_DPLL_DIV,
 448         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 449 };
 450
 451 static struct clk dpll3_ck = {
 452         .name           = "dpll3_ck",
 453         .parent         = &sys_ck,
 454         .dpll_data      = &dpll3_dd,
 455         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 456         .round_rate     = &omap2_dpll_round_rate,
 457         .clkdm          = { .name = "dpll3_clkdm" },
 458         .recalc         = &omap3_dpll_recalc,
 459 };
 460
 461 /*
 462  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 463  * DPLL isn't bypassed
 464  */
 465 static struct clk dpll3_x2_ck = {
 466         .name           = "dpll3_x2_ck",
 467         .parent         = &dpll3_ck,
 468         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 469                                 PARENT_CONTROLS_CLOCK,
 470         .clkdm          = { .name = "dpll3_clkdm" },
 471         .recalc         = &omap3_clkoutx2_recalc,
 472 };
 473
 474 static const struct clksel_rate div31_dpll3_rates[] = {
 475         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 476         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 477         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 478         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 479         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 480         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 481         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 482         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 483         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 484         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 485         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 486         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 487         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 488         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 489         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 490         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 491         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 492         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 493         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 494         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 495         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 496         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 497         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 498         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 499         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 500         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 501         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 502         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 503         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 504         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 505         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 506         { .div = 0 },
 507 };
 508
 509 static const struct clksel div31_dpll3m2_clksel[] = {
 510         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 511         { .parent = NULL }
 512 };
 513
 514 /* DPLL3 output M2 - primary control point for CORE speed */
 515 static struct clk dpll3_m2_ck = {
 516         .name           = "dpll3_m2_ck",
 517         .parent         = &dpll3_ck,
 518         .init           = &omap2_init_clksel_parent,
 519         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 520         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 521         .clksel         = div31_dpll3m2_clksel,
 522         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 523                                 PARENT_CONTROLS_CLOCK,
 524         .clkdm          = { .name = "dpll3_clkdm" },
 525         .round_rate     = &omap2_clksel_round_rate,
 526         .set_rate       = &omap3_core_dpll_m2_set_rate,
 527         .recalc         = &omap2_clksel_recalc,
 528 };
 529
 530 static const struct clksel core_ck_clksel[] = {
 531         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 532         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 533         { .parent = NULL }
 534 };
 535
 536 static struct clk core_ck = {
 537         .name           = "core_ck",
 538         .init           = &omap2_init_clksel_parent,
 539         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 540         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 541         .clksel         = core_ck_clksel,
 542         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 543                                 PARENT_CONTROLS_CLOCK,
 544         .clkdm          = { .name = "cm_clkdm" },
 545         .recalc         = &omap2_clksel_recalc,
 546 };
 547
 548 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 549         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 550         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 551         { .parent = NULL }
 552 };
 553
 554 static struct clk dpll3_m2x2_ck = {
 555         .name           = "dpll3_m2x2_ck",
 556         .init           = &omap2_init_clksel_parent,
 557         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 558         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 559         .clksel         = dpll3_m2x2_ck_clksel,
 560         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 561                                 PARENT_CONTROLS_CLOCK,
 562         .clkdm          = { .name = "dpll3_clkdm" },
 563         .recalc         = &omap2_clksel_recalc,
 564 };
 565
 566 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 567 static const struct clksel div16_dpll3_clksel[] = {
 568         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 569         { .parent = NULL }
 570 };
 571
 572 /* This virtual clock is the source for dpll3_m3x2_ck */
 573 static struct clk dpll3_m3_ck = {
 574         .name           = "dpll3_m3_ck",
 575         .parent         = &dpll3_ck,
 576         .init           = &omap2_init_clksel_parent,
 577         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 578         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 579         .clksel         = div16_dpll3_clksel,
 580         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 581                                 PARENT_CONTROLS_CLOCK,
 582         .clkdm          = { .name = "dpll3_clkdm" },
 583         .recalc         = &omap2_clksel_recalc,
 584 };
 585
 586 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 587 static struct clk dpll3_m3x2_ck = {
 588         .name           = "dpll3_m3x2_ck",
 589         .parent         = &dpll3_m3_ck,
 590         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 591         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 592         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 593         .clkdm          = { .name = "dpll3_clkdm" },
 594         .recalc         = &omap3_clkoutx2_recalc,
 595 };
 596
 597 static const struct clksel emu_core_alwon_ck_clksel[] = {
 598         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 599         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 600         { .parent = NULL }
 601 };
 602
 603 static struct clk emu_core_alwon_ck = {
 604         .name           = "emu_core_alwon_ck",
 605         .parent         = &dpll3_m3x2_ck,
 606         .init           = &omap2_init_clksel_parent,
 607         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 608         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 609         .clksel         = emu_core_alwon_ck_clksel,
 610         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 611                                 PARENT_CONTROLS_CLOCK,
 612         .clkdm          = { .name = "dpll3_clkdm" },
 613         .recalc         = &omap2_clksel_recalc,
 614 };
 615
 616 /* DPLL4 */
 617 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 618 /* Type: DPLL */
 619 static struct dpll_data dpll4_dd = {
 620         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 621         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 622         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 623         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 624         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 625         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 626         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 627         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 628         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 629         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 630         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 631         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 632         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 633         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 634         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 635         .max_divider    = OMAP3_MAX_DPLL_DIV,
 636         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 637 };
 638
 639 static struct clk dpll4_ck = {
 640         .name           = "dpll4_ck",
 641         .parent         = &sys_ck,
 642         .dpll_data      = &dpll4_dd,
 643         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 644         .enable         = &omap3_noncore_dpll_enable,
 645         .disable        = &omap3_noncore_dpll_disable,
 646         .round_rate     = &omap2_dpll_round_rate,
 647         .set_rate       = &omap3_noncore_dpll_set_rate,
 648         .clkdm          = { .name = "dpll4_clkdm" },
 649         .recalc         = &omap3_dpll_recalc,
 650 };
 651
 652 /*
 653  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 654  * DPLL isn't bypassed --
 655  * XXX does this serve any downstream clocks?
 656  */
 657 static struct clk dpll4_x2_ck = {
 658         .name           = "dpll4_x2_ck",
 659         .parent         = &dpll4_ck,
 660         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 661                                 PARENT_CONTROLS_CLOCK,
 662         .clkdm          = { .name = "dpll4_clkdm" },
 663         .recalc         = &omap3_clkoutx2_recalc,
 664 };
 665
 666 static const struct clksel div16_dpll4_clksel[] = {
 667         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 668         { .parent = NULL }
 669 };
 670
 671 /* This virtual clock is the source for dpll4_m2x2_ck */
 672 static struct clk dpll4_m2_ck = {
 673         .name           = "dpll4_m2_ck",
 674         .parent         = &dpll4_ck,
 675         .init           = &omap2_init_clksel_parent,
 676         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 677         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 678         .clksel         = div16_dpll4_clksel,
 679         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 680                                 PARENT_CONTROLS_CLOCK,
 681         .clkdm          = { .name = "dpll4_clkdm" },
 682         .recalc         = &omap2_clksel_recalc,
 683 };
 684
 685 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 686 static struct clk dpll4_m2x2_ck = {
 687         .name           = "dpll4_m2x2_ck",
 688         .parent         = &dpll4_m2_ck,
 689         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 690         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 691         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 692         .clkdm          = { .name = "dpll4_clkdm" },
 693         .recalc         = &omap3_clkoutx2_recalc,
 694 };
 695
 696 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 697         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 698         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 699         { .parent = NULL }
 700 };
 701
 702 /*
 703  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 704  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 705  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 706  * CM_96K_(F)CLK.
 707  */
 708 static struct clk omap_96m_alwon_fck = {
 709         .name           = "omap_96m_alwon_fck",
 710         .parent         = &dpll4_m2x2_ck,
 711         .init           = &omap2_init_clksel_parent,
 712         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 713         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 714         .clksel         = omap_96m_alwon_fck_clksel,
 715         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 716                                 PARENT_CONTROLS_CLOCK,
 717         .clkdm          = { .name = "prm_clkdm" },
 718         .recalc         = &omap2_clksel_recalc,
 719 };
 720
 721 static struct clk cm_96m_fck = {
 722         .name           = "cm_96m_fck",
 723         .parent         = &omap_96m_alwon_fck,
 724         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 725                                 PARENT_CONTROLS_CLOCK,
 726         .clkdm          = { .name = "cm_clkdm" },
 727         .recalc         = &followparent_recalc,
 728 };
 729
 730 static const struct clksel_rate omap_96m_dpll_rates[] = {
 731         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 732         { .div = 0 }
 733 };
 734
 735 static const struct clksel_rate omap_96m_sys_rates[] = {
 736         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 737         { .div = 0 }
 738 };
 739
 740 static const struct clksel omap_96m_fck_clksel[] = {
 741         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 742         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 743         { .parent = NULL }
 744 };
 745
 746 static struct clk omap_96m_fck = {
 747         .name           = "omap_96m_fck",
 748         .parent         = &sys_ck,
 749         .init           = &omap2_init_clksel_parent,
 750         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 751         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 752         .clksel         = omap_96m_fck_clksel,
 753         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 754                                 PARENT_CONTROLS_CLOCK,
 755         .clkdm          = { .name = "cm_clkdm" },
 756         .recalc         = &omap2_clksel_recalc,
 757 };
 758
 759 /* This virtual clock is the source for dpll4_m3x2_ck */
 760 static struct clk dpll4_m3_ck = {
 761         .name           = "dpll4_m3_ck",
 762         .parent         = &dpll4_ck,
 763         .init           = &omap2_init_clksel_parent,
 764         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 765         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 766         .clksel         = div16_dpll4_clksel,
 767         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 768                                 PARENT_CONTROLS_CLOCK,
 769         .clkdm          = { .name = "dpll4_clkdm" },
 770         .recalc         = &omap2_clksel_recalc,
 771 };
 772
 773 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 774 static struct clk dpll4_m3x2_ck = {
 775         .name           = "dpll4_m3x2_ck",
 776         .parent         = &dpll4_m3_ck,
 777         .init           = &omap2_init_clksel_parent,
 778         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 779         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 780         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 781         .clkdm          = { .name = "dpll4_clkdm" },
 782         .recalc         = &omap3_clkoutx2_recalc,
 783 };
 784
 785 static const struct clksel virt_omap_54m_fck_clksel[] = {
 786         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 787         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 788         { .parent = NULL }
 789 };
 790
 791 static struct clk virt_omap_54m_fck = {
 792         .name           = "virt_omap_54m_fck",
 793         .parent         = &dpll4_m3x2_ck,
 794         .init           = &omap2_init_clksel_parent,
 795         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 796         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 797         .clksel         = virt_omap_54m_fck_clksel,
 798         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 799                                 PARENT_CONTROLS_CLOCK,
 800         .clkdm          = { .name = "dpll4_clkdm" },
 801         .recalc         = &omap2_clksel_recalc,
 802 };
 803
 804 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 805         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 806         { .div = 0 }
 807 };
 808
 809 static const struct clksel_rate omap_54m_alt_rates[] = {
 810         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 811         { .div = 0 }
 812 };
 813
 814 static const struct clksel omap_54m_clksel[] = {
 815         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 816         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 817         { .parent = NULL }
 818 };
 819
 820 static struct clk omap_54m_fck = {
 821         .name           = "omap_54m_fck",
 822         .init           = &omap2_init_clksel_parent,
 823         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 824         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 825         .clksel         = omap_54m_clksel,
 826         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 827                                 PARENT_CONTROLS_CLOCK,
 828         .clkdm          = { .name = "cm_clkdm" },
 829         .recalc         = &omap2_clksel_recalc,
 830 };
 831
 832 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 833         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 834         { .div = 0 }
 835 };
 836
 837 static const struct clksel_rate omap_48m_alt_rates[] = {
 838         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 839         { .div = 0 }
 840 };
 841
 842 static const struct clksel omap_48m_clksel[] = {
 843         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 844         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 845         { .parent = NULL }
 846 };
 847
 848 static struct clk omap_48m_fck = {
 849         .name           = "omap_48m_fck",
 850         .init           = &omap2_init_clksel_parent,
 851         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 852         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 853         .clksel         = omap_48m_clksel,
 854         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 855                                 PARENT_CONTROLS_CLOCK,
 856         .clkdm          = { .name = "cm_clkdm" },
 857         .recalc         = &omap2_clksel_recalc,
 858 };
 859
 860 static struct clk omap_12m_fck = {
 861         .name           = "omap_12m_fck",
 862         .parent         = &omap_48m_fck,
 863         .fixed_div      = 4,
 864         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 865                                 PARENT_CONTROLS_CLOCK,
 866         .clkdm          = { .name = "cm_clkdm" },
 867         .recalc         = &omap2_fixed_divisor_recalc,
 868 };
 869
 870 /* This virstual clock is the source for dpll4_m4x2_ck */
 871 static struct clk dpll4_m4_ck = {
 872         .name           = "dpll4_m4_ck",
 873         .parent         = &dpll4_ck,
 874         .init           = &omap2_init_clksel_parent,
 875         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 876         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 877         .clksel         = div16_dpll4_clksel,
 878         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 879                                 PARENT_CONTROLS_CLOCK,
 880         .clkdm          = { .name = "dpll4_clkdm" },
 881         .recalc         = &omap2_clksel_recalc,
 882 };
 883
 884 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 885 static struct clk dpll4_m4x2_ck = {
 886         .name           = "dpll4_m4x2_ck",
 887         .parent         = &dpll4_m4_ck,
 888         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 889         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 890         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 891         .clkdm          = { .name = "dpll4_clkdm" },
 892         .recalc         = &omap3_clkoutx2_recalc,
 893 };
 894
 895 /* This virtual clock is the source for dpll4_m5x2_ck */
 896 static struct clk dpll4_m5_ck = {
 897         .name           = "dpll4_m5_ck",
 898         .parent         = &dpll4_ck,
 899         .init           = &omap2_init_clksel_parent,
 900         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 901         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 902         .clksel         = div16_dpll4_clksel,
 903         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 904                                 PARENT_CONTROLS_CLOCK,
 905         .clkdm          = { .name = "dpll4_clkdm" },
 906         .recalc         = &omap2_clksel_recalc,
 907 };
 908
 909 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 910 static struct clk dpll4_m5x2_ck = {
 911         .name           = "dpll4_m5x2_ck",
 912         .parent         = &dpll4_m5_ck,
 913         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 914         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 915         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 916         .clkdm          = { .name = "dpll4_clkdm" },
 917         .recalc         = &omap3_clkoutx2_recalc,
 918 };
 919
 920 /* This virtual clock is the source for dpll4_m6x2_ck */
 921 static struct clk dpll4_m6_ck = {
 922         .name           = "dpll4_m6_ck",
 923         .parent         = &dpll4_ck,
 924         .init           = &omap2_init_clksel_parent,
 925         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 926         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 927         .clksel         = div16_dpll4_clksel,
 928         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 929                                 PARENT_CONTROLS_CLOCK,
 930         .clkdm          = { .name = "dpll4_clkdm" },
 931         .recalc         = &omap2_clksel_recalc,
 932 };
 933
 934 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 935 static struct clk dpll4_m6x2_ck = {
 936         .name           = "dpll4_m6x2_ck",
 937         .parent         = &dpll4_m6_ck,
 938         .init           = &omap2_init_clksel_parent,
 939         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 940         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 941         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 942         .clkdm          = { .name = "dpll4_clkdm" },
 943         .recalc         = &omap3_clkoutx2_recalc,
 944 };
 945
 946 static struct clk emu_per_alwon_ck = {
 947         .name           = "emu_per_alwon_ck",
 948         .parent         = &dpll4_m6x2_ck,
 949         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 950                                 PARENT_CONTROLS_CLOCK,
 951         .clkdm          = { .name = "dpll4_clkdm" },
 952         .recalc         = &followparent_recalc,
 953 };
 954
 955 /* DPLL5 */
 956 /* Supplies 120MHz clock, USIM source clock */
 957 /* Type: DPLL */
 958 /* 3430ES2 only */
 959 static struct dpll_data dpll5_dd = {
 960         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 961         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 962         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 963         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 964         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 965         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 966         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 967         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 968         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 969         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 970         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 971         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 972         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 973         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 974         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 975         .max_divider    = OMAP3_MAX_DPLL_DIV,
 976         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 977 };
 978
 979 static struct clk dpll5_ck = {
 980         .name           = "dpll5_ck",
 981         .parent         = &sys_ck,
 982         .dpll_data      = &dpll5_dd,
 983         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 984         .enable         = &omap3_noncore_dpll_enable,
 985         .disable        = &omap3_noncore_dpll_disable,
 986         .round_rate     = &omap2_dpll_round_rate,
 987         .set_rate       = &omap3_noncore_dpll_set_rate,
 988         .clkdm          = { .name = "dpll5_clkdm" },
 989         .recalc         = &omap3_dpll_recalc,
 990 };
 991
 992 static const struct clksel div16_dpll5_clksel[] = {
 993         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 994         { .parent = NULL }
 995 };
 996
 997 static struct clk dpll5_m2_ck = {
 998         .name           = "dpll5_m2_ck",
 999         .parent         = &dpll5_ck,
1000         .init           = &omap2_init_clksel_parent,
1001         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1002         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
1003         .clksel         = div16_dpll5_clksel,
1004         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
1005                                 PARENT_CONTROLS_CLOCK,
1006         .clkdm          = { .name = "dpll5_clkdm" },
1007         .recalc         = &omap2_clksel_recalc,
1008 };
1009
1010 static const struct clksel omap_120m_fck_clksel[] = {
1011         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
1012         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
1013         { .parent = NULL }
1014 };
1015
1016 static struct clk omap_120m_fck = {
1017         .name           = "omap_120m_fck",
1018         .parent         = &dpll5_m2_ck,
1019         .init           = &omap2_init_clksel_parent,
1020         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
1021         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
1022         .clksel         = omap_120m_fck_clksel,
1023         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
1024                                 PARENT_CONTROLS_CLOCK,
1025         .clkdm          = { .name = "dpll5_clkdm" },
1026         .recalc         = &omap2_clksel_recalc,
1027 };
1028
1029 /* CM EXTERNAL CLOCK OUTPUTS */
1030
1031 static const struct clksel_rate clkout2_src_core_rates[] = {
1032         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1033         { .div = 0 }
1034 };
1035
1036 static const struct clksel_rate clkout2_src_sys_rates[] = {
1037         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1038         { .div = 0 }
1039 };
1040
1041 static const struct clksel_rate clkout2_src_96m_rates[] = {
1042         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1043         { .div = 0 }
1044 };
1045
1046 static const struct clksel_rate clkout2_src_54m_rates[] = {
1047         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1048         { .div = 0 }
1049 };
1050
1051 static const struct clksel clkout2_src_clksel[] = {
1052         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
1053         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
1054         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
1055         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
1056         { .parent = NULL }
1057 };
1058
1059 static struct clk clkout2_src_ck = {
1060         .name           = "clkout2_src_ck",
1061         .init           = &omap2_init_clksel_parent,
1062         .enable_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1063         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1064         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1065         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1066         .clksel         = clkout2_src_clksel,
1067         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1068         .clkdm          = { .name = "cm_clkdm" },
1069         .recalc         = &omap2_clksel_recalc,
1070 };
1071
1072 static const struct clksel_rate sys_clkout2_rates[] = {
1073         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1074         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1075         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1076         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1077         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1078         { .div = 0 },
1079 };
1080
1081 static const struct clksel sys_clkout2_clksel[] = {
1082         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1083         { .parent = NULL },
1084 };
1085
1086 static struct clk sys_clkout2 = {
1087         .name           = "sys_clkout2",
1088         .init           = &omap2_init_clksel_parent,
1089         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1090         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1091         .clksel         = sys_clkout2_clksel,
1092         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1093         .clkdm          = { .name = "cm_clkdm" },
1094         .recalc         = &omap2_clksel_recalc,
1095 };
1096
1097 /* CM OUTPUT CLOCKS */
1098
1099 static struct clk corex2_fck = {
1100         .name           = "corex2_fck",
1101         .parent         = &dpll3_m2x2_ck,
1102         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1103                                 PARENT_CONTROLS_CLOCK,
1104         .clkdm          = { .name = "cm_clkdm" },
1105         .recalc         = &followparent_recalc,
1106 };
1107
1108 /* DPLL power domain clock controls */
1109
1110 static const struct clksel_rate div4_rates[] = {
1111         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1112         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1113         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1114         { .div = 0 }
1115 };
1116
1117 static const struct clksel div4_core_clksel[] = {
1118         { .parent = &core_ck, .rates = div4_rates },
1119         { .parent = NULL }
1120 };
1121
1122 static struct clk dpll1_fck = {
1123         .name           = "dpll1_fck",
1124         .parent         = &core_ck,
1125         .init           = &omap2_init_clksel_parent,
1126         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1127         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1128         .clksel         = div4_core_clksel,
1129         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1130                                 PARENT_CONTROLS_CLOCK,
1131         .clkdm          = { .name = "cm_clkdm" },
1132         .recalc         = &omap2_clksel_recalc,
1133 };
1134
1135 /*
1136  * MPU clksel:
1137  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1138  * derives from the high-frequency bypass clock originating from DPLL3,
1139  * called 'dpll1_fck'
1140  */
1141 static const struct clksel mpu_clksel[] = {
1142         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1143         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1144         { .parent = NULL }
1145 };
1146
1147 static struct clk mpu_ck = {
1148         .name           = "mpu_ck",
1149         .parent         = &dpll1_x2m2_ck,
1150         .init           = &omap2_init_clksel_parent,
1151         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1152         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1153         .clksel         = mpu_clksel,
1154         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1155                                 PARENT_CONTROLS_CLOCK,
1156         .clkdm          = { .name = "mpu_clkdm" },
1157         .recalc         = &omap2_clksel_recalc,
1158 };
1159
1160 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1161 static const struct clksel_rate arm_fck_rates[] = {
1162         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1163         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1164         { .div = 0 },
1165 };
1166
1167 static const struct clksel arm_fck_clksel[] = {
1168         { .parent = &mpu_ck, .rates = arm_fck_rates },
1169         { .parent = NULL }
1170 };
1171
1172 static struct clk arm_fck = {
1173         .name           = "arm_fck",
1174         .parent         = &mpu_ck,
1175         .init           = &omap2_init_clksel_parent,
1176         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1177         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1178         .clksel         = arm_fck_clksel,
1179         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1180                                 PARENT_CONTROLS_CLOCK,
1181         .clkdm          = { .name = "mpu_clkdm" },
1182         .recalc         = &omap2_clksel_recalc,
1183 };
1184
1185 /* XXX What about neon_clkdm ? */
1186
1187 /*
1188  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1189  * although it is referenced - so this is a guess
1190  */
1191 static struct clk emu_mpu_alwon_ck = {
1192         .name           = "emu_mpu_alwon_ck",
1193         .parent         = &mpu_ck,
1194         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1195                                 PARENT_CONTROLS_CLOCK,
1196         .clkdm          = { .name = "mpu_clkdm" },
1197         .recalc         = &followparent_recalc,
1198 };
1199
1200 static struct clk dpll2_fck = {
1201         .name           = "dpll2_fck",
1202         .parent         = &core_ck,
1203         .init           = &omap2_init_clksel_parent,
1204         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1205         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1206         .clksel         = div4_core_clksel,
1207         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1208                                 PARENT_CONTROLS_CLOCK,
1209         .clkdm          = { .name = "cm_clkdm" },
1210         .recalc         = &omap2_clksel_recalc,
1211 };
1212
1213 /*
1214  * IVA2 clksel:
1215  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1216  * derives from the high-frequency bypass clock originating from DPLL3,
1217  * called 'dpll2_fck'
1218  */
1219
1220 static const struct clksel iva2_clksel[] = {
1221         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1222         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1223         { .parent = NULL }
1224 };
1225
1226 static struct clk iva2_ck = {
1227         .name           = "iva2_ck",
1228         .parent         = &dpll2_m2_ck,
1229         .init           = &omap2_init_clksel_parent,
1230         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1231         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1232         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
1233                                           OMAP3430_CM_IDLEST_PLL),
1234         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1235         .clksel         = iva2_clksel,
1236         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1237         .clkdm          = { .name = "iva2_clkdm" },
1238         .recalc         = &omap2_clksel_recalc,
1239 };
1240
1241 /* Common interface clocks */
1242
1243 static const struct clksel div2_core_clksel[] = {
1244         { .parent = &core_ck, .rates = div2_rates },
1245         { .parent = NULL }
1246 };
1247
1248 static struct clk l3_ick = {
1249         .name           = "l3_ick",
1250         .parent         = &core_ck,
1251         .init           = &omap2_init_clksel_parent,
1252         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1253         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1254         .clksel         = div2_core_clksel,
1255         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1256                                 PARENT_CONTROLS_CLOCK,
1257         .clkdm          = { .name = "core_l3_clkdm" },
1258         .recalc         = &omap2_clksel_recalc,
1259 };
1260
1261 static const struct clksel div2_l3_clksel[] = {
1262         { .parent = &l3_ick, .rates = div2_rates },
1263         { .parent = NULL }
1264 };
1265
1266 static struct clk l4_ick = {
1267         .name           = "l4_ick",
1268         .parent         = &l3_ick,
1269         .init           = &omap2_init_clksel_parent,
1270         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1271         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1272         .clksel         = div2_l3_clksel,
1273         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1274                                 PARENT_CONTROLS_CLOCK,
1275         .clkdm          = { .name = "core_l4_clkdm" },
1276         .recalc         = &omap2_clksel_recalc,
1277
1278 };
1279
1280 static const struct clksel div2_l4_clksel[] = {
1281         { .parent = &l4_ick, .rates = div2_rates },
1282         { .parent = NULL }
1283 };
1284
1285 static struct clk rm_ick = {
1286         .name           = "rm_ick",
1287         .parent         = &l4_ick,
1288         .init           = &omap2_init_clksel_parent,
1289         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1290         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1291         .clksel         = div2_l4_clksel,
1292         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1293         .clkdm          = { .name = "cm_clkdm" },
1294         .recalc         = &omap2_clksel_recalc,
1295 };
1296
1297 /* GFX power domain */
1298
1299 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1300
1301 static const struct clksel gfx_l3_clksel[] = {
1302         { .parent = &l3_ick, .rates = gfx_l3_rates },
1303         { .parent = NULL }
1304 };
1305
1306 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1307 static struct clk gfx_l3_ck = {
1308         .name           = "gfx_l3_ck",
1309         .parent         = &l3_ick,
1310         .init           = &omap2_init_clksel_parent,
1311         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1312         .enable_bit     = OMAP_EN_GFX_SHIFT,
1313         .flags          = CLOCK_IN_OMAP3430ES1,
1314         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1315         .recalc         = &followparent_recalc,
1316 };
1317
1318 static struct clk gfx_l3_fck = {
1319         .name           = "gfx_l3_fck",
1320         .parent         = &gfx_l3_ck,
1321         .init           = &omap2_init_clksel_parent,
1322         .clksel_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1323         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1324         .clksel         = gfx_l3_clksel,
1325         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1326                                 PARENT_CONTROLS_CLOCK,
1327         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1328         .recalc         = &omap2_clksel_recalc,
1329 };
1330
1331 static struct clk gfx_l3_ick = {
1332         .name           = "gfx_l3_ick",
1333         .parent         = &gfx_l3_ck,
1334         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1335         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1336         .recalc         = &followparent_recalc,
1337 };
1338
1339 static struct clk gfx_cg1_ck = {
1340         .name           = "gfx_cg1_ck",
1341         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1342         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1343         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1344         .flags          = CLOCK_IN_OMAP3430ES1,
1345         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1346         .recalc         = &followparent_recalc,
1347 };
1348
1349 static struct clk gfx_cg2_ck = {
1350         .name           = "gfx_cg2_ck",
1351         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1352         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1353         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1354         .flags          = CLOCK_IN_OMAP3430ES1,
1355         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1356         .recalc         = &followparent_recalc,
1357 };
1358
1359 /* SGX power domain - 3430ES2 only */
1360
1361 static const struct clksel_rate sgx_core_rates[] = {
1362         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1363         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1364         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1365         { .div = 0 },
1366 };
1367
1368 static const struct clksel_rate sgx_96m_rates[] = {
1369         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1370         { .div = 0 },
1371 };
1372
1373 static const struct clksel sgx_clksel[] = {
1374         { .parent = &core_ck,    .rates = sgx_core_rates },
1375         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1376         { .parent = NULL },
1377 };
1378
1379 static struct clk sgx_fck = {
1380         .name           = "sgx_fck",
1381         .init           = &omap2_init_clksel_parent,
1382         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1383         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1384         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1385         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1386         .clksel         = sgx_clksel,
1387         .flags          = CLOCK_IN_OMAP3430ES2,
1388         .clkdm          = { .name = "sgx_clkdm" },
1389         .recalc         = &omap2_clksel_recalc,
1390 };
1391
1392 static struct clk sgx_ick = {
1393         .name           = "sgx_ick",
1394         .parent         = &l3_ick,
1395         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1396         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1397         .flags          = CLOCK_IN_OMAP3430ES2,
1398         .clkdm          = { .name = "sgx_clkdm" },
1399         .recalc         = &followparent_recalc,
1400 };
1401
1402 /* CORE power domain */
1403
1404 static struct clk d2d_26m_fck = {
1405         .name           = "d2d_26m_fck",
1406         .parent         = &sys_ck,
1407         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1408         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1409         .flags          = CLOCK_IN_OMAP3430ES1,
1410         .clkdm          = { .name = "d2d_clkdm" },
1411         .recalc         = &followparent_recalc,
1412 };
1413
1414 static const struct clksel omap343x_gpt_clksel[] = {
1415         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1416         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1417         { .parent = NULL}
1418 };
1419
1420 static struct clk gpt10_fck = {
1421         .name           = "gpt10_fck",
1422         .parent         = &sys_ck,
1423         .init           = &omap2_init_clksel_parent,
1424         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1425         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1426         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1427         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1428         .clksel         = omap343x_gpt_clksel,
1429         .flags          = CLOCK_IN_OMAP343X,
1430         .clkdm          = { .name = "core_l4_clkdm" },
1431         .recalc         = &omap2_clksel_recalc,
1432 };
1433
1434 static struct clk gpt11_fck = {
1435         .name           = "gpt11_fck",
1436         .parent         = &sys_ck,
1437         .init           = &omap2_init_clksel_parent,
1438         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1439         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1440         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1441         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1442         .clksel         = omap343x_gpt_clksel,
1443         .flags          = CLOCK_IN_OMAP343X,
1444         .clkdm          = { .name = "core_l4_clkdm" },
1445         .recalc         = &omap2_clksel_recalc,
1446 };
1447
1448 static struct clk cpefuse_fck = {
1449         .name           = "cpefuse_fck",
1450         .parent         = &sys_ck,
1451         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1452         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1453         .flags          = CLOCK_IN_OMAP3430ES2,
1454         .clkdm          = { .name = "cm_clkdm" },
1455         .recalc         = &followparent_recalc,
1456 };
1457
1458 static struct clk ts_fck = {
1459         .name           = "ts_fck",
1460         .parent         = &omap_32k_fck,
1461         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1462         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1463         .flags          = CLOCK_IN_OMAP3430ES2,
1464         .clkdm          = { .name = "core_l4_clkdm" },
1465         .recalc         = &followparent_recalc,
1466 };
1467
1468 static struct clk usbtll_fck = {
1469         .name           = "usbtll_fck",
1470         .parent         = &omap_120m_fck,
1471         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1472         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1473         .flags          = CLOCK_IN_OMAP3430ES2,
1474         .clkdm          = { .name = "core_l4_clkdm" },
1475         .recalc         = &followparent_recalc,
1476 };
1477
1478 /* CORE 96M FCLK-derived clocks */
1479
1480 static struct clk core_96m_fck = {
1481         .name           = "core_96m_fck",
1482         .parent         = &omap_96m_fck,
1483         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1484                                 PARENT_CONTROLS_CLOCK,
1485         .clkdm          = { .name = "core_l4_clkdm" },
1486         .recalc         = &followparent_recalc,
1487 };
1488
1489 static struct clk mmchs3_fck = {
1490         .name           = "mmchs_fck",
1491         .id             = 3,
1492         .parent         = &core_96m_fck,
1493         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1494         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1495         .flags          = CLOCK_IN_OMAP3430ES2,
1496         .clkdm          = { .name = "core_l4_clkdm" },
1497         .recalc         = &followparent_recalc,
1498 };
1499
1500 static struct clk mmchs2_fck = {
1501         .name           = "mmchs_fck",
1502         .id             = 2,
1503         .parent         = &core_96m_fck,
1504         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1505         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1506         .flags          = CLOCK_IN_OMAP343X,
1507         .clkdm          = { .name = "core_l4_clkdm" },
1508         .recalc         = &followparent_recalc,
1509 };
1510
1511 static struct clk mspro_fck = {
1512         .name           = "mspro_fck",
1513         .parent         = &core_96m_fck,
1514         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1515         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1516         .flags          = CLOCK_IN_OMAP343X,
1517         .clkdm          = { .name = "core_l4_clkdm" },
1518         .recalc         = &followparent_recalc,
1519 };
1520
1521 static struct clk mmchs1_fck = {
1522         .name           = "mmchs_fck",
1523         .id             = 1,
1524         .parent         = &core_96m_fck,
1525         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1526         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1527         .flags          = CLOCK_IN_OMAP343X,
1528         .clkdm          = { .name = "core_l4_clkdm" },
1529         .recalc         = &followparent_recalc,
1530 };
1531
1532 static struct clk i2c3_fck = {
1533         .name           = "i2c_fck",
1534         .id             = 3,
1535         .parent         = &core_96m_fck,
1536         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1537         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1538         .flags          = CLOCK_IN_OMAP343X,
1539         .clkdm          = { .name = "core_l4_clkdm" },
1540         .recalc         = &followparent_recalc,
1541 };
1542
1543 static struct clk i2c2_fck = {
1544         .name           = "i2c_fck",
1545         .id             = 2,
1546         .parent         = &core_96m_fck,
1547         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1548         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1549         .flags          = CLOCK_IN_OMAP343X,
1550         .clkdm          = { .name = "core_l4_clkdm" },
1551         .recalc         = &followparent_recalc,
1552 };
1553
1554 static struct clk i2c1_fck = {
1555         .name           = "i2c_fck",
1556         .id             = 1,
1557         .parent         = &core_96m_fck,
1558         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1560         .flags          = CLOCK_IN_OMAP343X,
1561         .clkdm          = { .name = "core_l4_clkdm" },
1562         .recalc         = &followparent_recalc,
1563 };
1564
1565 /*
1566  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1567  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1568  */
1569 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1570         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1571         { .div = 0 }
1572 };
1573
1574 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1575         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1576         { .div = 0 }
1577 };
1578
1579 static const struct clksel mcbsp_15_clksel[] = {
1580         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1581         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1582         { .parent = NULL }
1583 };
1584
1585 static struct clk mcbsp5_fck = {
1586         .name           = "mcbsp_fck",
1587         .id             = 5,
1588         .init           = &omap2_init_clksel_parent,
1589         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1590         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1591         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1592         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1593         .clksel         = mcbsp_15_clksel,
1594         .flags          = CLOCK_IN_OMAP343X,
1595         .clkdm          = { .name = "core_l4_clkdm" },
1596         .recalc         = &omap2_clksel_recalc,
1597 };
1598
1599 static struct clk mcbsp1_fck = {
1600         .name           = "mcbsp_fck",
1601         .id             = 1,
1602         .init           = &omap2_init_clksel_parent,
1603         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1604         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1605         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1606         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1607         .clksel         = mcbsp_15_clksel,
1608         .flags          = CLOCK_IN_OMAP343X,
1609         .clkdm          = { .name = "core_l4_clkdm" },
1610         .recalc         = &omap2_clksel_recalc,
1611 };
1612
1613 /* CORE_48M_FCK-derived clocks */
1614
1615 static struct clk core_48m_fck = {
1616         .name           = "core_48m_fck",
1617         .parent         = &omap_48m_fck,
1618         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1619                                 PARENT_CONTROLS_CLOCK,
1620         .clkdm          = { .name = "core_l4_clkdm" },
1621         .recalc         = &followparent_recalc,
1622 };
1623
1624 static struct clk mcspi4_fck = {
1625         .name           = "mcspi_fck",
1626         .id             = 4,
1627         .parent         = &core_48m_fck,
1628         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1629         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1630         .flags          = CLOCK_IN_OMAP343X,
1631         .clkdm          = { .name = "core_l4_clkdm" },
1632         .recalc         = &followparent_recalc,
1633 };
1634
1635 static struct clk mcspi3_fck = {
1636         .name           = "mcspi_fck",
1637         .id             = 3,
1638         .parent         = &core_48m_fck,
1639         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1640         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1641         .flags          = CLOCK_IN_OMAP343X,
1642         .clkdm          = { .name = "core_l4_clkdm" },
1643         .recalc         = &followparent_recalc,
1644 };
1645
1646 static struct clk mcspi2_fck = {
1647         .name           = "mcspi_fck",
1648         .id             = 2,
1649         .parent         = &core_48m_fck,
1650         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1651         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1652         .flags          = CLOCK_IN_OMAP343X,
1653         .clkdm          = { .name = "core_l4_clkdm" },
1654         .recalc         = &followparent_recalc,
1655 };
1656
1657 static struct clk mcspi1_fck = {
1658         .name           = "mcspi_fck",
1659         .id             = 1,
1660         .parent         = &core_48m_fck,
1661         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1662         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1663         .flags          = CLOCK_IN_OMAP343X,
1664         .clkdm          = { .name = "core_l4_clkdm" },
1665         .recalc         = &followparent_recalc,
1666 };
1667
1668 static struct clk uart2_fck = {
1669         .name           = "uart2_fck",
1670         .parent         = &core_48m_fck,
1671         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1672         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1673         .flags          = CLOCK_IN_OMAP343X,
1674         .clkdm          = { .name = "core_l4_clkdm" },
1675         .recalc         = &followparent_recalc,
1676 };
1677
1678 static struct clk uart1_fck = {
1679         .name           = "uart1_fck",
1680         .parent         = &core_48m_fck,
1681         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1682         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1683         .flags          = CLOCK_IN_OMAP343X,
1684         .clkdm          = { .name = "core_l4_clkdm" },
1685         .recalc         = &followparent_recalc,
1686 };
1687
1688 static struct clk fshostusb_fck = {
1689         .name           = "fshostusb_fck",
1690         .parent         = &core_48m_fck,
1691         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1692         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1693         .flags          = CLOCK_IN_OMAP3430ES1,
1694         .clkdm          = { .name = "core_l4_clkdm" },
1695         .recalc         = &followparent_recalc,
1696 };
1697
1698 /* CORE_12M_FCK based clocks */
1699
1700 static struct clk core_12m_fck = {
1701         .name           = "core_12m_fck",
1702         .parent         = &omap_12m_fck,
1703         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1704                                 PARENT_CONTROLS_CLOCK,
1705         .clkdm          = { .name = "core_l4_clkdm" },
1706         .recalc         = &followparent_recalc,
1707 };
1708
1709 static struct clk hdq_fck = {
1710         .name           = "hdq_fck",
1711         .parent         = &core_12m_fck,
1712         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1713         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1714         .flags          = CLOCK_IN_OMAP343X,
1715         .clkdm          = { .name = "core_l4_clkdm" },
1716         .recalc         = &followparent_recalc,
1717 };
1718
1719 /* DPLL3-derived clock */
1720
1721 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1722         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1723         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1724         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1725         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1726         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1727         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1728         { .div = 0 }
1729 };
1730
1731 static const struct clksel ssi_ssr_clksel[] = {
1732         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1733         { .parent = NULL }
1734 };
1735
1736 static struct clk ssi_ssr_fck = {
1737         .name           = "ssi_ssr_fck",
1738         .init           = &omap2_init_clksel_parent,
1739         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1740         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1741         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1742         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1743         .clksel         = ssi_ssr_clksel,
1744         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1745         .clkdm          = { .name = "core_l4_clkdm" },
1746         .recalc         = &omap2_clksel_recalc,
1747 };
1748
1749 static struct clk ssi_sst_fck = {
1750         .name           = "ssi_sst_fck",
1751         .parent         = &ssi_ssr_fck,
1752         .fixed_div      = 2,
1753         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1754         .clkdm          = { .name = "core_l4_clkdm" },
1755         .recalc         = &omap2_fixed_divisor_recalc,
1756 };
1757
1758
1759
1760 /* CORE_L3_ICK based clocks */
1761
1762 /*
1763  * XXX must add clk_enable/clk_disable for these if standard code won't
1764  * handle it
1765  */
1766 static struct clk core_l3_ick = {
1767         .name           = "core_l3_ick",
1768         .parent         = &l3_ick,
1769         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1770                                 PARENT_CONTROLS_CLOCK,
1771         .clkdm          = { .name = "core_l3_clkdm" },
1772         .recalc         = &followparent_recalc,
1773 };
1774
1775 static struct clk hsotgusb_ick = {
1776         .name           = "hsotgusb_ick",
1777         .parent         = &core_l3_ick,
1778         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1779         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1780         .flags          = CLOCK_IN_OMAP343X,
1781         .clkdm          = { .name = "core_l3_clkdm" },
1782         .recalc         = &followparent_recalc,
1783 };
1784
1785 static struct clk sdrc_ick = {
1786         .name           = "sdrc_ick",
1787         .parent         = &core_l3_ick,
1788         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1789         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1790         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1791         .clkdm          = { .name = "core_l3_clkdm" },
1792         .recalc         = &followparent_recalc,
1793 };
1794
1795 static struct clk gpmc_fck = {
1796         .name           = "gpmc_fck",
1797         .parent         = &core_l3_ick,
1798         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1799                                 ENABLE_ON_INIT,
1800         .clkdm          = { .name = "core_l3_clkdm" },
1801         .recalc         = &followparent_recalc,
1802 };
1803
1804 /* SECURITY_L3_ICK based clocks */
1805
1806 static struct clk security_l3_ick = {
1807         .name           = "security_l3_ick",
1808         .parent         = &l3_ick,
1809         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1810                                 PARENT_CONTROLS_CLOCK,
1811         .clkdm          = { .name = "core_l3_clkdm" },
1812         .recalc         = &followparent_recalc,
1813 };
1814
1815 static struct clk pka_ick = {
1816         .name           = "pka_ick",
1817         .parent         = &security_l3_ick,
1818         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1819         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1820         .flags          = CLOCK_IN_OMAP343X,
1821         .clkdm          = { .name = "core_l3_clkdm" },
1822         .recalc         = &followparent_recalc,
1823 };
1824
1825 /* CORE_L4_ICK based clocks */
1826
1827 static struct clk core_l4_ick = {
1828         .name           = "core_l4_ick",
1829         .parent         = &l4_ick,
1830         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1831                                 PARENT_CONTROLS_CLOCK,
1832         .clkdm          = { .name = "core_l4_clkdm" },
1833         .recalc         = &followparent_recalc,
1834 };
1835
1836 static struct clk usbtll_ick = {
1837         .name           = "usbtll_ick",
1838         .parent         = &core_l4_ick,
1839         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1840         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1841         .flags          = CLOCK_IN_OMAP3430ES2,
1842         .clkdm          = { .name = "core_l4_clkdm" },
1843         .recalc         = &followparent_recalc,
1844 };
1845
1846 static struct clk mmchs3_ick = {
1847         .name           = "mmchs_ick",
1848         .id             = 3,
1849         .parent         = &core_l4_ick,
1850         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1851         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1852         .flags          = CLOCK_IN_OMAP3430ES2,
1853         .clkdm          = { .name = "core_l4_clkdm" },
1854         .recalc         = &followparent_recalc,
1855 };
1856
1857 /* Intersystem Communication Registers - chassis mode only */
1858 static struct clk icr_ick = {
1859         .name           = "icr_ick",
1860         .parent         = &core_l4_ick,
1861         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1862         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1863         .flags          = CLOCK_IN_OMAP343X,
1864         .clkdm          = { .name = "core_l4_clkdm" },
1865         .recalc         = &followparent_recalc,
1866 };
1867
1868 static struct clk aes2_ick = {
1869         .name           = "aes2_ick",
1870         .parent         = &core_l4_ick,
1871         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1872         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1873         .flags          = CLOCK_IN_OMAP343X,
1874         .clkdm          = { .name = "core_l4_clkdm" },
1875         .recalc         = &followparent_recalc,
1876 };
1877
1878 static struct clk sha12_ick = {
1879         .name           = "sha12_ick",
1880         .parent         = &core_l4_ick,
1881         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1882         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1883         .flags          = CLOCK_IN_OMAP343X,
1884         .clkdm          = { .name = "core_l4_clkdm" },
1885         .recalc         = &followparent_recalc,
1886 };
1887
1888 static struct clk des2_ick = {
1889         .name           = "des2_ick",
1890         .parent         = &core_l4_ick,
1891         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1892         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1893         .flags          = CLOCK_IN_OMAP343X,
1894         .clkdm          = { .name = "core_l4_clkdm" },
1895         .recalc         = &followparent_recalc,
1896 };
1897
1898 static struct clk mmchs2_ick = {
1899         .name           = "mmchs_ick",
1900         .id             = 2,
1901         .parent         = &core_l4_ick,
1902         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1903         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1904         .flags          = CLOCK_IN_OMAP343X,
1905         .clkdm          = { .name = "core_l4_clkdm" },
1906         .recalc         = &followparent_recalc,
1907 };
1908
1909 static struct clk mmchs1_ick = {
1910         .name           = "mmchs_ick",
1911         .id             = 1,
1912         .parent         = &core_l4_ick,
1913         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1914         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1915         .flags          = CLOCK_IN_OMAP343X,
1916         .clkdm          = { .name = "core_l4_clkdm" },
1917         .recalc         = &followparent_recalc,
1918 };
1919
1920 static struct clk mspro_ick = {
1921         .name           = "mspro_ick",
1922         .parent         = &core_l4_ick,
1923         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1924         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1925         .flags          = CLOCK_IN_OMAP343X,
1926         .clkdm          = { .name = "core_l4_clkdm" },
1927         .recalc         = &followparent_recalc,
1928 };
1929
1930 static struct clk hdq_ick = {
1931         .name           = "hdq_ick",
1932         .parent         = &core_l4_ick,
1933         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1934         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1935         .flags          = CLOCK_IN_OMAP343X,
1936         .clkdm          = { .name = "core_l4_clkdm" },
1937         .recalc         = &followparent_recalc,
1938 };
1939
1940 static struct clk mcspi4_ick = {
1941         .name           = "mcspi_ick",
1942         .id             = 4,
1943         .parent         = &core_l4_ick,
1944         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1945         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1946         .flags          = CLOCK_IN_OMAP343X,
1947         .clkdm          = { .name = "core_l4_clkdm" },
1948         .recalc         = &followparent_recalc,
1949 };
1950
1951 static struct clk mcspi3_ick = {
1952         .name           = "mcspi_ick",
1953         .id             = 3,
1954         .parent         = &core_l4_ick,
1955         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1956         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1957         .flags          = CLOCK_IN_OMAP343X,
1958         .clkdm          = { .name = "core_l4_clkdm" },
1959         .recalc         = &followparent_recalc,
1960 };
1961
1962 static struct clk mcspi2_ick = {
1963         .name           = "mcspi_ick",
1964         .id             = 2,
1965         .parent         = &core_l4_ick,
1966         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1967         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1968         .flags          = CLOCK_IN_OMAP343X,
1969         .clkdm          = { .name = "core_l4_clkdm" },
1970         .recalc         = &followparent_recalc,
1971 };
1972
1973 static struct clk mcspi1_ick = {
1974         .name           = "mcspi_ick",
1975         .id             = 1,
1976         .parent         = &core_l4_ick,
1977         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1978         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1979         .flags          = CLOCK_IN_OMAP343X,
1980         .clkdm          = { .name = "core_l4_clkdm" },
1981         .recalc         = &followparent_recalc,
1982 };
1983
1984 static struct clk i2c3_ick = {
1985         .name           = "i2c_ick",
1986         .id             = 3,
1987         .parent         = &core_l4_ick,
1988         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1989         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1990         .flags          = CLOCK_IN_OMAP343X,
1991         .clkdm          = { .name = "core_l4_clkdm" },
1992         .recalc         = &followparent_recalc,
1993 };
1994
1995 static struct clk i2c2_ick = {
1996         .name           = "i2c_ick",
1997         .id             = 2,
1998         .parent         = &core_l4_ick,
1999         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2000         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
2001         .flags          = CLOCK_IN_OMAP343X,
2002         .clkdm          = { .name = "core_l4_clkdm" },
2003         .recalc         = &followparent_recalc,
2004 };
2005
2006 static struct clk i2c1_ick = {
2007         .name           = "i2c_ick",
2008         .id             = 1,
2009         .parent         = &core_l4_ick,
2010         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2011         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
2012         .flags          = CLOCK_IN_OMAP343X,
2013         .clkdm          = { .name = "core_l4_clkdm" },
2014         .recalc         = &followparent_recalc,
2015 };
2016
2017 static struct clk uart2_ick = {
2018         .name           = "uart2_ick",
2019         .parent         = &core_l4_ick,
2020         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2021         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2022         .flags          = CLOCK_IN_OMAP343X,
2023         .clkdm          = { .name = "core_l4_clkdm" },
2024         .recalc         = &followparent_recalc,
2025 };
2026
2027 static struct clk uart1_ick = {
2028         .name           = "uart1_ick",
2029         .parent         = &core_l4_ick,
2030         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2031         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2032         .flags          = CLOCK_IN_OMAP343X,
2033         .clkdm          = { .name = "core_l4_clkdm" },
2034         .recalc         = &followparent_recalc,
2035 };
2036
2037 static struct clk gpt11_ick = {
2038         .name           = "gpt11_ick",
2039         .parent         = &core_l4_ick,
2040         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2041         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
2042         .flags          = CLOCK_IN_OMAP343X,
2043         .clkdm          = { .name = "core_l4_clkdm" },
2044         .recalc         = &followparent_recalc,
2045 };
2046
2047 static struct clk gpt10_ick = {
2048         .name           = "gpt10_ick",
2049         .parent         = &core_l4_ick,
2050         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2051         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
2052         .flags          = CLOCK_IN_OMAP343X,
2053         .clkdm          = { .name = "core_l4_clkdm" },
2054         .recalc         = &followparent_recalc,
2055 };
2056
2057 static struct clk mcbsp5_ick = {
2058         .name           = "mcbsp_ick",
2059         .id             = 5,
2060         .parent         = &core_l4_ick,
2061         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2062         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2063         .flags          = CLOCK_IN_OMAP343X,
2064         .clkdm          = { .name = "core_l4_clkdm" },
2065         .recalc         = &followparent_recalc,
2066 };
2067
2068 static struct clk mcbsp1_ick = {
2069         .name           = "mcbsp_ick",
2070         .id             = 1,
2071         .parent         = &core_l4_ick,
2072         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2073         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2074         .flags          = CLOCK_IN_OMAP343X,
2075         .clkdm          = { .name = "core_l4_clkdm" },
2076         .recalc         = &followparent_recalc,
2077 };
2078
2079 static struct clk fac_ick = {
2080         .name           = "fac_ick",
2081         .parent         = &core_l4_ick,
2082         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2083         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2084         .flags          = CLOCK_IN_OMAP3430ES1,
2085         .clkdm          = { .name = "core_l4_clkdm" },
2086         .recalc         = &followparent_recalc,
2087 };
2088
2089 static struct clk mailboxes_ick = {
2090         .name           = "mailboxes_ick",
2091         .parent         = &core_l4_ick,
2092         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2093         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2094         .flags          = CLOCK_IN_OMAP343X,
2095         .clkdm          = { .name = "core_l4_clkdm" },
2096         .recalc         = &followparent_recalc,
2097 };
2098
2099 static struct clk omapctrl_ick = {
2100         .name           = "omapctrl_ick",
2101         .parent         = &core_l4_ick,
2102         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2103         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2104         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
2105         .clkdm          = { .name = "core_l4_clkdm" },
2106         .recalc         = &followparent_recalc,
2107 };
2108
2109 /* SSI_L4_ICK based clocks */
2110
2111 static struct clk ssi_l4_ick = {
2112         .name           = "ssi_l4_ick",
2113         .parent         = &l4_ick,
2114         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2115                                 PARENT_CONTROLS_CLOCK,
2116         .clkdm          = { .name = "core_l4_clkdm" },
2117         .recalc         = &followparent_recalc,
2118 };
2119
2120 static struct clk ssi_ick = {
2121         .name           = "ssi_ick",
2122         .parent         = &ssi_l4_ick,
2123         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2124         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2125         .flags          = CLOCK_IN_OMAP343X,
2126         .clkdm          = { .name = "core_l4_clkdm" },
2127         .recalc         = &followparent_recalc,
2128 };
2129
2130 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2131  * but l4_ick makes more sense to me */
2132
2133 static const struct clksel usb_l4_clksel[] = {
2134         { .parent = &l4_ick, .rates = div2_rates },
2135         { .parent = NULL },
2136 };
2137
2138 static struct clk usb_l4_ick = {
2139         .name           = "usb_l4_ick",
2140         .parent         = &l4_ick,
2141         .init           = &omap2_init_clksel_parent,
2142         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2143         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2144         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2145         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2146         .clksel         = usb_l4_clksel,
2147         .flags          = CLOCK_IN_OMAP3430ES1,
2148         .clkdm          = { .name = "core_l4_clkdm" },
2149         .recalc         = &omap2_clksel_recalc,
2150 };
2151
2152 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2153
2154 /* SECURITY_L4_ICK2 based clocks */
2155
2156 static struct clk security_l4_ick2 = {
2157         .name           = "security_l4_ick2",
2158         .parent         = &l4_ick,
2159         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2160                                 PARENT_CONTROLS_CLOCK,
2161         .clkdm          = { .name = "core_l4_clkdm" },
2162         .recalc         = &followparent_recalc,
2163 };
2164
2165 static struct clk aes1_ick = {
2166         .name           = "aes1_ick",
2167         .parent         = &security_l4_ick2,
2168         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2169         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2170         .flags          = CLOCK_IN_OMAP343X,
2171         .clkdm          = { .name = "core_l4_clkdm" },
2172         .recalc         = &followparent_recalc,
2173 };
2174
2175 static struct clk rng_ick = {
2176         .name           = "rng_ick",
2177         .parent         = &security_l4_ick2,
2178         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2179         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2180         .flags          = CLOCK_IN_OMAP343X,
2181         .clkdm          = { .name = "core_l4_clkdm" },
2182         .recalc         = &followparent_recalc,
2183 };
2184
2185 static struct clk sha11_ick = {
2186         .name           = "sha11_ick",
2187         .parent         = &security_l4_ick2,
2188         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2189         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2190         .flags          = CLOCK_IN_OMAP343X,
2191         .clkdm          = { .name = "core_l4_clkdm" },
2192         .recalc         = &followparent_recalc,
2193 };
2194
2195 static struct clk des1_ick = {
2196         .name           = "des1_ick",
2197         .parent         = &security_l4_ick2,
2198         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2199         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2200         .flags          = CLOCK_IN_OMAP343X,
2201         .clkdm          = { .name = "core_l4_clkdm" },
2202         .recalc         = &followparent_recalc,
2203 };
2204
2205 /* DSS */
2206 static const struct clksel dss1_alwon_fck_clksel[] = {
2207         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2208         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2209         { .parent = NULL }
2210 };
2211
2212 static struct clk dss1_alwon_fck = {
2213         .name           = "dss1_alwon_fck",
2214         .parent         = &dpll4_m4x2_ck,
2215         .init           = &omap2_init_clksel_parent,
2216         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2217         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2218         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2219         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2220         .clksel         = dss1_alwon_fck_clksel,
2221         .flags          = CLOCK_IN_OMAP343X,
2222         .clkdm          = { .name = "dss_clkdm" },
2223         .recalc         = &omap2_clksel_recalc,
2224 };
2225
2226 static struct clk dss_tv_fck = {
2227         .name           = "dss_tv_fck",
2228         .parent         = &omap_54m_fck,
2229         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2230         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2231         .flags          = CLOCK_IN_OMAP343X,
2232         .clkdm          = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2233         .recalc         = &followparent_recalc,
2234 };
2235
2236 static struct clk dss_96m_fck = {
2237         .name           = "dss_96m_fck",
2238         .parent         = &omap_96m_fck,
2239         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2240         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2241         .flags          = CLOCK_IN_OMAP343X,
2242         .clkdm          = { .name = "dss_clkdm" },
2243         .recalc         = &followparent_recalc,
2244 };
2245
2246 static struct clk dss2_alwon_fck = {
2247         .name           = "dss2_alwon_fck",
2248         .parent         = &sys_ck,
2249         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2250         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2251         .flags          = CLOCK_IN_OMAP343X,
2252         .clkdm          = { .name = "dss_clkdm" },
2253         .recalc         = &followparent_recalc,
2254 };
2255
2256 static struct clk dss_ick = {
2257         /* Handles both L3 and L4 clocks */
2258         .name           = "dss_ick",
2259         .parent         = &l4_ick,
2260         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2261         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2262         .flags          = CLOCK_IN_OMAP343X,
2263         .clkdm          = { .name = "dss_clkdm" },
2264         .recalc         = &followparent_recalc,
2265 };
2266
2267 /* CAM */
2268
2269 static const struct clksel cam_mclk_clksel[] = {
2270         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2271         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2272         { .parent = NULL }
2273 };
2274
2275 static struct clk cam_mclk = {
2276         .name           = "cam_mclk",
2277         .parent         = &dpll4_m5x2_ck,
2278         .init           = &omap2_init_clksel_parent,
2279         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2280         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2281         .clksel         = cam_mclk_clksel,
2282         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2283         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2284         .flags          = CLOCK_IN_OMAP343X,
2285         .clkdm          = { .name = "cam_clkdm" },
2286         .recalc         = &omap2_clksel_recalc,
2287 };
2288
2289 static struct clk cam_ick = {
2290         /* Handles both L3 and L4 clocks */
2291         .name           = "cam_ick",
2292         .parent         = &l4_ick,
2293         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2294         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2295         .flags          = CLOCK_IN_OMAP343X,
2296         .clkdm          = { .name = "cam_clkdm" },
2297         .recalc         = &followparent_recalc,
2298 };
2299
2300 static struct clk csi2_96m_fck = {
2301         .name           = "csi2_96m_fck",
2302         .parent         = &core_96m_fck,
2303         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2304         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2305         .flags          = CLOCK_IN_OMAP343X,
2306         .clkdm          = { .name = "cam_clkdm" },
2307         .recalc         = &followparent_recalc,
2308 };
2309
2310 /* USBHOST - 3430ES2 only */
2311
2312 static struct clk usbhost_120m_fck = {
2313         .name           = "usbhost_120m_fck",
2314         .parent         = &omap_120m_fck,
2315         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2316         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2317         .flags          = CLOCK_IN_OMAP3430ES2,
2318         .clkdm          = { .name = "usbhost_clkdm" },
2319         .recalc         = &followparent_recalc,
2320 };
2321
2322 static struct clk usbhost_48m_fck = {
2323         .name           = "usbhost_48m_fck",
2324         .parent         = &omap_48m_fck,
2325         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2326         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2327         .flags          = CLOCK_IN_OMAP3430ES2,
2328         .clkdm          = { .name = "usbhost_clkdm" },
2329         .recalc         = &followparent_recalc,
2330 };
2331
2332 static struct clk usbhost_ick = {
2333         /* Handles both L3 and L4 clocks */
2334         .name           = "usbhost_ick",
2335         .parent         = &l4_ick,
2336         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2337         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2338         .flags          = CLOCK_IN_OMAP3430ES2,
2339         .clkdm          = { .name = "usbhost_clkdm" },
2340         .recalc         = &followparent_recalc,
2341 };
2342
2343 /* WKUP */
2344
2345 static const struct clksel_rate usim_96m_rates[] = {
2346         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2347         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2348         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2349         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2350         { .div = 0 },
2351 };
2352
2353 static const struct clksel_rate usim_120m_rates[] = {
2354         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2355         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2356         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2357         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2358         { .div = 0 },
2359 };
2360
2361 static const struct clksel usim_clksel[] = {
2362         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2363         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2364         { .parent = &sys_ck,            .rates = div2_rates },
2365         { .parent = NULL },
2366 };
2367
2368 /* 3430ES2 only */
2369 static struct clk usim_fck = {
2370         .name           = "usim_fck",
2371         .init           = &omap2_init_clksel_parent,
2372         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2373         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2374         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2375         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2376         .clksel         = usim_clksel,
2377         .flags          = CLOCK_IN_OMAP3430ES2,
2378         .clkdm          = { .name = "prm_clkdm" },
2379         .recalc         = &omap2_clksel_recalc,
2380 };
2381
2382 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2383 static struct clk gpt1_fck = {
2384         .name           = "gpt1_fck",
2385         .init           = &omap2_init_clksel_parent,
2386         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2387         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2388         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2389         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2390         .clksel         = omap343x_gpt_clksel,
2391         .flags          = CLOCK_IN_OMAP343X,
2392         .clkdm          = { .name = "prm_clkdm" },
2393         .recalc         = &omap2_clksel_recalc,
2394 };
2395
2396 static struct clk wkup_32k_fck = {
2397         .name           = "wkup_32k_fck",
2398         .parent         = &omap_32k_fck,
2399         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2400         .clkdm          = { .name = "prm_clkdm" },
2401         .recalc         = &followparent_recalc,
2402 };
2403
2404 static struct clk gpio1_fck = {
2405         .name           = "gpio1_fck",
2406         .parent         = &wkup_32k_fck,
2407         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2408         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2409         .flags          = CLOCK_IN_OMAP343X,
2410         .clkdm          = { .name = "prm_clkdm" },
2411         .recalc         = &followparent_recalc,
2412 };
2413
2414 static struct clk wdt2_fck = {
2415         .name           = "wdt2_fck",
2416         .parent         = &wkup_32k_fck,
2417         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2418         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2419         .flags          = CLOCK_IN_OMAP343X,
2420         .clkdm          = { .name = "prm_clkdm" },
2421         .recalc         = &followparent_recalc,
2422 };
2423
2424 static struct clk wkup_l4_ick = {
2425         .name           = "wkup_l4_ick",
2426         .parent         = &sys_ck,
2427         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2428         .clkdm          = { .name = "prm_clkdm" },
2429         .recalc         = &followparent_recalc,
2430 };
2431
2432 /* 3430ES2 only */
2433 /* Never specifically named in the TRM, so we have to infer a likely name */
2434 static struct clk usim_ick = {
2435         .name           = "usim_ick",
2436         .parent         = &wkup_l4_ick,
2437         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2438         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2439         .flags          = CLOCK_IN_OMAP3430ES2,
2440         .clkdm          = { .name = "prm_clkdm" },
2441         .recalc         = &followparent_recalc,
2442 };
2443
2444 static struct clk wdt2_ick = {
2445         .name           = "wdt2_ick",
2446         .parent         = &wkup_l4_ick,
2447         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2448         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2449         .flags          = CLOCK_IN_OMAP343X,
2450         .clkdm          = { .name = "prm_clkdm" },
2451         .recalc         = &followparent_recalc,
2452 };
2453
2454 static struct clk wdt1_ick = {
2455         .name           = "wdt1_ick",
2456         .parent         = &wkup_l4_ick,
2457         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2458         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2459         .flags          = CLOCK_IN_OMAP343X,
2460         .clkdm          = { .name = "prm_clkdm" },
2461         .recalc         = &followparent_recalc,
2462 };
2463
2464 static struct clk gpio1_ick = {
2465         .name           = "gpio1_ick",
2466         .parent         = &wkup_l4_ick,
2467         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2468         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2469         .flags          = CLOCK_IN_OMAP343X,
2470         .clkdm          = { .name = "prm_clkdm" },
2471         .recalc         = &followparent_recalc,
2472 };
2473
2474 static struct clk omap_32ksync_ick = {
2475         .name           = "omap_32ksync_ick",
2476         .parent         = &wkup_l4_ick,
2477         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2478         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2479         .flags          = CLOCK_IN_OMAP343X,
2480         .clkdm          = { .name = "prm_clkdm" },
2481         .recalc         = &followparent_recalc,
2482 };
2483
2484 static struct clk gpt12_ick = {
2485         .name           = "gpt12_ick",
2486         .parent         = &wkup_l4_ick,
2487         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2488         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2489         .flags          = CLOCK_IN_OMAP343X,
2490         .clkdm          = { .name = "prm_clkdm" },
2491         .recalc         = &followparent_recalc,
2492 };
2493
2494 static struct clk gpt1_ick = {
2495         .name           = "gpt1_ick",
2496         .parent         = &wkup_l4_ick,
2497         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2498         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2499         .flags          = CLOCK_IN_OMAP343X,
2500         .clkdm          = { .name = "prm_clkdm" },
2501         .recalc         = &followparent_recalc,
2502 };
2503
2504
2505
2506 /* PER clock domain */
2507
2508 static struct clk per_96m_fck = {
2509         .name           = "per_96m_fck",
2510         .parent         = &omap_96m_alwon_fck,
2511         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2512                                 PARENT_CONTROLS_CLOCK,
2513         .clkdm          = { .name = "per_clkdm" },
2514         .recalc         = &followparent_recalc,
2515 };
2516
2517 static struct clk per_48m_fck = {
2518         .name           = "per_48m_fck",
2519         .parent         = &omap_48m_fck,
2520         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2521                                 PARENT_CONTROLS_CLOCK,
2522         .clkdm          = { .name = "per_clkdm" },
2523         .recalc         = &followparent_recalc,
2524 };
2525
2526 static struct clk uart3_fck = {
2527         .name           = "uart3_fck",
2528         .parent         = &per_48m_fck,
2529         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2530         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2531         .flags          = CLOCK_IN_OMAP343X,
2532         .clkdm          = { .name = "per_clkdm" },
2533         .recalc         = &followparent_recalc,
2534 };
2535
2536 static struct clk gpt2_fck = {
2537         .name           = "gpt2_fck",
2538         .init           = &omap2_init_clksel_parent,
2539         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2540         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2541         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2542         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2543         .clksel         = omap343x_gpt_clksel,
2544         .flags          = CLOCK_IN_OMAP343X,
2545         .clkdm          = { .name = "per_clkdm" },
2546         .recalc         = &omap2_clksel_recalc,
2547 };
2548
2549 static struct clk gpt3_fck = {
2550         .name           = "gpt3_fck",
2551         .init           = &omap2_init_clksel_parent,
2552         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2553         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2554         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2555         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2556         .clksel         = omap343x_gpt_clksel,
2557         .flags          = CLOCK_IN_OMAP343X,
2558         .clkdm          = { .name = "per_clkdm" },
2559         .recalc         = &omap2_clksel_recalc,
2560 };
2561
2562 static struct clk gpt4_fck = {
2563         .name           = "gpt4_fck",
2564         .init           = &omap2_init_clksel_parent,
2565         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2566         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2567         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2568         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2569         .clksel         = omap343x_gpt_clksel,
2570         .flags          = CLOCK_IN_OMAP343X,
2571         .clkdm          = { .name = "per_clkdm" },
2572         .recalc         = &omap2_clksel_recalc,
2573 };
2574
2575 static struct clk gpt5_fck = {
2576         .name           = "gpt5_fck",
2577         .init           = &omap2_init_clksel_parent,
2578         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2579         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2580         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2581         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2582         .clksel         = omap343x_gpt_clksel,
2583         .flags          = CLOCK_IN_OMAP343X,
2584         .clkdm          = { .name = "per_clkdm" },
2585         .recalc         = &omap2_clksel_recalc,
2586 };
2587
2588 static struct clk gpt6_fck = {
2589         .name           = "gpt6_fck",
2590         .init           = &omap2_init_clksel_parent,
2591         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2592         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2593         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2594         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2595         .clksel         = omap343x_gpt_clksel,
2596         .flags          = CLOCK_IN_OMAP343X,
2597         .clkdm          = { .name = "per_clkdm" },
2598         .recalc         = &omap2_clksel_recalc,
2599 };
2600
2601 static struct clk gpt7_fck = {
2602         .name           = "gpt7_fck",
2603         .init           = &omap2_init_clksel_parent,
2604         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2605         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2606         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2607         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2608         .clksel         = omap343x_gpt_clksel,
2609         .flags          = CLOCK_IN_OMAP343X,
2610         .clkdm          = { .name = "per_clkdm" },
2611         .recalc         = &omap2_clksel_recalc,
2612 };
2613
2614 static struct clk gpt8_fck = {
2615         .name           = "gpt8_fck",
2616         .init           = &omap2_init_clksel_parent,
2617         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2618         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2619         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2620         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2621         .clksel         = omap343x_gpt_clksel,
2622         .flags          = CLOCK_IN_OMAP343X,
2623         .clkdm          = { .name = "per_clkdm" },
2624         .recalc         = &omap2_clksel_recalc,
2625 };
2626
2627 static struct clk gpt9_fck = {
2628         .name           = "gpt9_fck",
2629         .init           = &omap2_init_clksel_parent,
2630         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2631         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2632         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2633         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2634         .clksel         = omap343x_gpt_clksel,
2635         .flags          = CLOCK_IN_OMAP343X,
2636         .clkdm          = { .name = "per_clkdm" },
2637         .recalc         = &omap2_clksel_recalc,
2638 };
2639
2640 static struct clk per_32k_alwon_fck = {
2641         .name           = "per_32k_alwon_fck",
2642         .parent         = &omap_32k_fck,
2643         .clkdm          = { .name = "per_clkdm" },
2644         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2645         .recalc         = &followparent_recalc,
2646 };
2647
2648 static struct clk gpio6_fck = {
2649         .name           = "gpio6_fck",
2650         .parent         = &per_32k_alwon_fck,
2651         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2652         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2653         .flags          = CLOCK_IN_OMAP343X,
2654         .clkdm          = { .name = "per_clkdm" },
2655         .recalc         = &followparent_recalc,
2656 };
2657
2658 static struct clk gpio5_fck = {
2659         .name           = "gpio5_fck",
2660         .parent         = &per_32k_alwon_fck,
2661         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2662         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2663         .flags          = CLOCK_IN_OMAP343X,
2664         .clkdm          = { .name = "per_clkdm" },
2665         .recalc         = &followparent_recalc,
2666 };
2667
2668 static struct clk gpio4_fck = {
2669         .name           = "gpio4_fck",
2670         .parent         = &per_32k_alwon_fck,
2671         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2672         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2673         .flags          = CLOCK_IN_OMAP343X,
2674         .clkdm          = { .name = "per_clkdm" },
2675         .recalc         = &followparent_recalc,
2676 };
2677
2678 static struct clk gpio3_fck = {
2679         .name           = "gpio3_fck",
2680         .parent         = &per_32k_alwon_fck,
2681         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2682         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2683         .flags          = CLOCK_IN_OMAP343X,
2684         .clkdm          = { .name = "per_clkdm" },
2685         .recalc         = &followparent_recalc,
2686 };
2687
2688 static struct clk gpio2_fck = {
2689         .name           = "gpio2_fck",
2690         .parent         = &per_32k_alwon_fck,
2691         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2692         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2693         .flags          = CLOCK_IN_OMAP343X,
2694         .clkdm          = { .name = "per_clkdm" },
2695         .recalc         = &followparent_recalc,
2696 };
2697
2698 static struct clk wdt3_fck = {
2699         .name           = "wdt3_fck",
2700         .parent         = &per_32k_alwon_fck,
2701         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2702         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2703         .flags          = CLOCK_IN_OMAP343X,
2704         .clkdm          = { .name = "per_clkdm" },
2705         .recalc         = &followparent_recalc,
2706 };
2707
2708 static struct clk per_l4_ick = {
2709         .name           = "per_l4_ick",
2710         .parent         = &l4_ick,
2711         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2712                                 PARENT_CONTROLS_CLOCK,
2713         .clkdm          = { .name = "per_clkdm" },
2714         .recalc         = &followparent_recalc,
2715 };
2716
2717 static struct clk gpio6_ick = {
2718         .name           = "gpio6_ick",
2719         .parent         = &per_l4_ick,
2720         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2721         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2722         .flags          = CLOCK_IN_OMAP343X,
2723         .clkdm          = { .name = "per_clkdm" },
2724         .recalc         = &followparent_recalc,
2725 };
2726
2727 static struct clk gpio5_ick = {
2728         .name           = "gpio5_ick",
2729         .parent         = &per_l4_ick,
2730         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2731         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2732         .flags          = CLOCK_IN_OMAP343X,
2733         .clkdm          = { .name = "per_clkdm" },
2734         .recalc         = &followparent_recalc,
2735 };
2736
2737 static struct clk gpio4_ick = {
2738         .name           = "gpio4_ick",
2739         .parent         = &per_l4_ick,
2740         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2741         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2742         .flags          = CLOCK_IN_OMAP343X,
2743         .clkdm          = { .name = "per_clkdm" },
2744         .recalc         = &followparent_recalc,
2745 };
2746
2747 static struct clk gpio3_ick = {
2748         .name           = "gpio3_ick",
2749         .parent         = &per_l4_ick,
2750         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2751         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2752         .flags          = CLOCK_IN_OMAP343X,
2753         .clkdm          = { .name = "per_clkdm" },
2754         .recalc         = &followparent_recalc,
2755 };
2756
2757 static struct clk gpio2_ick = {
2758         .name           = "gpio2_ick",
2759         .parent         = &per_l4_ick,
2760         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2761         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2762         .flags          = CLOCK_IN_OMAP343X,
2763         .clkdm          = { .name = "per_clkdm" },
2764         .recalc         = &followparent_recalc,
2765 };
2766
2767 static struct clk wdt3_ick = {
2768         .name           = "wdt3_ick",
2769         .parent         = &per_l4_ick,
2770         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2771         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2772         .flags          = CLOCK_IN_OMAP343X,
2773         .clkdm          = { .name = "per_clkdm" },
2774         .recalc         = &followparent_recalc,
2775 };
2776
2777 static struct clk uart3_ick = {
2778         .name           = "uart3_ick",
2779         .parent         = &per_l4_ick,
2780         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2781         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2782         .flags          = CLOCK_IN_OMAP343X,
2783         .clkdm          = { .name = "per_clkdm" },
2784         .recalc         = &followparent_recalc,
2785 };
2786
2787 static struct clk gpt9_ick = {
2788         .name           = "gpt9_ick",
2789         .parent         = &per_l4_ick,
2790         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2791         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2792         .flags          = CLOCK_IN_OMAP343X,
2793         .clkdm          = { .name = "per_clkdm" },
2794         .recalc         = &followparent_recalc,
2795 };
2796
2797 static struct clk gpt8_ick = {
2798         .name           = "gpt8_ick",
2799         .parent         = &per_l4_ick,
2800         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2801         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2802         .flags          = CLOCK_IN_OMAP343X,
2803         .clkdm          = { .name = "per_clkdm" },
2804         .recalc         = &followparent_recalc,
2805 };
2806
2807 static struct clk gpt7_ick = {
2808         .name           = "gpt7_ick",
2809         .parent         = &per_l4_ick,
2810         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2811         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2812         .flags          = CLOCK_IN_OMAP343X,
2813         .clkdm          = { .name = "per_clkdm" },
2814         .recalc         = &followparent_recalc,
2815 };
2816
2817 static struct clk gpt6_ick = {
2818         .name           = "gpt6_ick",
2819         .parent         = &per_l4_ick,
2820         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2821         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2822         .flags          = CLOCK_IN_OMAP343X,
2823         .clkdm          = { .name = "per_clkdm" },
2824         .recalc         = &followparent_recalc,
2825 };
2826
2827 static struct clk gpt5_ick = {
2828         .name           = "gpt5_ick",
2829         .parent         = &per_l4_ick,
2830         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2831         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2832         .flags          = CLOCK_IN_OMAP343X,
2833         .clkdm          = { .name = "per_clkdm" },
2834         .recalc         = &followparent_recalc,
2835 };
2836
2837 static struct clk gpt4_ick = {
2838         .name           = "gpt4_ick",
2839         .parent         = &per_l4_ick,
2840         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2841         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2842         .flags          = CLOCK_IN_OMAP343X,
2843         .clkdm          = { .name = "per_clkdm" },
2844         .recalc         = &followparent_recalc,
2845 };
2846
2847 static struct clk gpt3_ick = {
2848         .name           = "gpt3_ick",
2849         .parent         = &per_l4_ick,
2850         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2851         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2852         .flags          = CLOCK_IN_OMAP343X,
2853         .clkdm          = { .name = "per_clkdm" },
2854         .recalc         = &followparent_recalc,
2855 };
2856
2857 static struct clk gpt2_ick = {
2858         .name           = "gpt2_ick",
2859         .parent         = &per_l4_ick,
2860         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2861         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2862         .flags          = CLOCK_IN_OMAP343X,
2863         .clkdm          = { .name = "per_clkdm" },
2864         .recalc         = &followparent_recalc,
2865 };
2866
2867 static struct clk mcbsp2_ick = {
2868         .name           = "mcbsp_ick",
2869         .id             = 2,
2870         .parent         = &per_l4_ick,
2871         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2872         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2873         .flags          = CLOCK_IN_OMAP343X,
2874         .clkdm          = { .name = "per_clkdm" },
2875         .recalc         = &followparent_recalc,
2876 };
2877
2878 static struct clk mcbsp3_ick = {
2879         .name           = "mcbsp_ick",
2880         .id             = 3,
2881         .parent         = &per_l4_ick,
2882         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2883         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2884         .flags          = CLOCK_IN_OMAP343X,
2885         .clkdm          = { .name = "per_clkdm" },
2886         .recalc         = &followparent_recalc,
2887 };
2888
2889 static struct clk mcbsp4_ick = {
2890         .name           = "mcbsp_ick",
2891         .id             = 4,
2892         .parent         = &per_l4_ick,
2893         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2894         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2895         .flags          = CLOCK_IN_OMAP343X,
2896         .clkdm          = { .name = "per_clkdm" },
2897         .recalc         = &followparent_recalc,
2898 };
2899
2900 static const struct clksel mcbsp_234_clksel[] = {
2901         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2902         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2903         { .parent = NULL }
2904 };
2905
2906 static struct clk mcbsp2_fck = {
2907         .name           = "mcbsp_fck",
2908         .id             = 2,
2909         .init           = &omap2_init_clksel_parent,
2910         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2911         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2912         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2913         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2914         .clksel         = mcbsp_234_clksel,
2915         .flags          = CLOCK_IN_OMAP343X,
2916         .clkdm          = { .name = "per_clkdm" },
2917         .recalc         = &omap2_clksel_recalc,
2918 };
2919
2920 static struct clk mcbsp3_fck = {
2921         .name           = "mcbsp_fck",
2922         .id             = 3,
2923         .init           = &omap2_init_clksel_parent,
2924         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2925         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2926         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2927         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2928         .clksel         = mcbsp_234_clksel,
2929         .flags          = CLOCK_IN_OMAP343X,
2930         .clkdm          = { .name = "per_clkdm" },
2931         .recalc         = &omap2_clksel_recalc,
2932 };
2933
2934 static struct clk mcbsp4_fck = {
2935         .name           = "mcbsp_fck",
2936         .id             = 4,
2937         .init           = &omap2_init_clksel_parent,
2938         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2939         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2940         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2941         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2942         .clksel         = mcbsp_234_clksel,
2943         .flags          = CLOCK_IN_OMAP343X,
2944         .clkdm          = { .name = "per_clkdm" },
2945         .recalc         = &omap2_clksel_recalc,
2946 };
2947
2948 /* EMU clocks */
2949
2950 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2951
2952 static const struct clksel_rate emu_src_sys_rates[] = {
2953         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2954         { .div = 0 },
2955 };
2956
2957 static const struct clksel_rate emu_src_core_rates[] = {
2958         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2959         { .div = 0 },
2960 };
2961
2962 static const struct clksel_rate emu_src_per_rates[] = {
2963         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2964         { .div = 0 },
2965 };
2966
2967 static const struct clksel_rate emu_src_mpu_rates[] = {
2968         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2969         { .div = 0 },
2970 };
2971
2972 static const struct clksel emu_src_clksel[] = {
2973         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2974         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2975         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2976         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2977         { .parent = NULL },
2978 };
2979
2980 /*
2981  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2982  * to switch the source of some of the EMU clocks.
2983  * XXX Are there CLKEN bits for these EMU clks?
2984  */
2985 static struct clk emu_src_ck = {
2986         .name           = "emu_src_ck",
2987         .init           = &omap2_init_clksel_parent,
2988         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2989         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2990         .clksel         = emu_src_clksel,
2991         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2992         .clkdm          = { .name = "emu_clkdm" },
2993         .recalc         = &omap2_clksel_recalc,
2994 };
2995
2996 static const struct clksel_rate pclk_emu_rates[] = {
2997         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2998         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2999         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3000         { .div = 6, .val = 6, .flags = RATE_IN_343X },
3001         { .div = 0 },
3002 };
3003
3004 static const struct clksel pclk_emu_clksel[] = {
3005         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3006         { .parent = NULL },
3007 };
3008
3009 static struct clk pclk_fck = {
3010         .name           = "pclk_fck",
3011         .init           = &omap2_init_clksel_parent,
3012         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3013         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
3014         .clksel         = pclk_emu_clksel,
3015         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3016         .clkdm          = { .name = "emu_clkdm" },
3017         .recalc         = &omap2_clksel_recalc,
3018 };
3019
3020 static const struct clksel_rate pclkx2_emu_rates[] = {
3021         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3022         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3023         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3024         { .div = 0 },
3025 };
3026
3027 static const struct clksel pclkx2_emu_clksel[] = {
3028         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3029         { .parent = NULL },
3030 };
3031
3032 static struct clk pclkx2_fck = {
3033         .name           = "pclkx2_fck",
3034         .init           = &omap2_init_clksel_parent,
3035         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3036         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3037         .clksel         = pclkx2_emu_clksel,
3038         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3039         .clkdm          = { .name = "emu_clkdm" },
3040         .recalc         = &omap2_clksel_recalc,
3041 };
3042
3043 static const struct clksel atclk_emu_clksel[] = {
3044         { .parent = &emu_src_ck, .rates = div2_rates },
3045         { .parent = NULL },
3046 };
3047
3048 static struct clk atclk_fck = {
3049         .name           = "atclk_fck",
3050         .init           = &omap2_init_clksel_parent,
3051         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3052         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3053         .clksel         = atclk_emu_clksel,
3054         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3055         .clkdm          = { .name = "emu_clkdm" },
3056         .recalc         = &omap2_clksel_recalc,
3057 };
3058
3059 static struct clk traceclk_src_fck = {
3060         .name           = "traceclk_src_fck",
3061         .init           = &omap2_init_clksel_parent,
3062         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3063         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3064         .clksel         = emu_src_clksel,
3065         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3066         .clkdm          = { .name = "emu_clkdm" },
3067         .recalc         = &omap2_clksel_recalc,
3068 };
3069
3070 static const struct clksel_rate traceclk_rates[] = {
3071         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3072         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3073         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3074         { .div = 0 },
3075 };
3076
3077 static const struct clksel traceclk_clksel[] = {
3078         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3079         { .parent = NULL },
3080 };
3081
3082 static struct clk traceclk_fck = {
3083         .name           = "traceclk_fck",
3084         .init           = &omap2_init_clksel_parent,
3085         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3086         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3087         .clksel         = traceclk_clksel,
3088         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3089         .clkdm          = { .name = "emu_clkdm" },
3090         .recalc         = &omap2_clksel_recalc,
3091 };
3092
3093 /* SR clocks */
3094
3095 /* SmartReflex fclk (VDD1) */
3096 static struct clk sr1_fck = {
3097         .name           = "sr1_fck",
3098         .parent         = &sys_ck,
3099         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3100         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3101         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3102         .clkdm          = { .name = "prm_clkdm" },
3103         .recalc         = &followparent_recalc,
3104 };
3105
3106 /* SmartReflex fclk (VDD2) */
3107 static struct clk sr2_fck = {
3108         .name           = "sr2_fck",
3109         .parent         = &sys_ck,
3110         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3111         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3112         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3113         .clkdm          = { .name = "prm_clkdm" },
3114         .recalc         = &followparent_recalc,
3115 };
3116
3117 static struct clk sr_l4_ick = {
3118         .name           = "sr_l4_ick",
3119         .parent         = &l4_ick,
3120         .flags          = CLOCK_IN_OMAP343X,
3121         .clkdm          = { .name = "core_l4_clkdm" },
3122         .recalc         = &followparent_recalc,
3123 };
3124
3125 /* SECURE_32K_FCK clocks */
3126
3127 /* XXX This clock no longer exists in 3430 TRM rev F */
3128 static struct clk gpt12_fck = {
3129         .name           = "gpt12_fck",
3130         .parent         = &secure_32k_fck,
3131         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3132         .clkdm          = { .name = "prm_clkdm" },
3133         .recalc         = &followparent_recalc,
3134 };
3135
3136 static struct clk wdt1_fck = {
3137         .name           = "wdt1_fck",
3138         .parent         = &secure_32k_fck,
3139         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3140         .clkdm          = { .name = "prm_clkdm" },
3141         .recalc         = &followparent_recalc,
3142 };
3143
3144 static struct clk *onchip_34xx_clks[] __initdata = {
3145         &omap_32k_fck,
3146         &virt_12m_ck,
3147         &virt_13m_ck,
3148         &virt_16_8m_ck,
3149         &virt_19_2m_ck,
3150         &virt_26m_ck,
3151         &virt_38_4m_ck,
3152         &osc_sys_ck,
3153         &sys_ck,
3154         &sys_altclk,
3155         &mcbsp_clks,
3156         &sys_clkout1,
3157         &dpll1_ck,
3158         &dpll1_x2_ck,
3159         &dpll1_x2m2_ck,
3160         &dpll2_ck,
3161         &dpll2_m2_ck,
3162         &dpll3_ck,
3163         &core_ck,
3164         &dpll3_x2_ck,
3165         &dpll3_m2_ck,
3166         &dpll3_m2x2_ck,
3167         &dpll3_m3_ck,
3168         &dpll3_m3x2_ck,
3169         &emu_core_alwon_ck,
3170         &dpll4_ck,
3171         &dpll4_x2_ck,
3172         &omap_96m_alwon_fck,
3173         &omap_96m_fck,
3174         &cm_96m_fck,
3175         &virt_omap_54m_fck,
3176         &omap_54m_fck,
3177         &omap_48m_fck,
3178         &omap_12m_fck,
3179         &dpll4_m2_ck,
3180         &dpll4_m2x2_ck,
3181         &dpll4_m3_ck,
3182         &dpll4_m3x2_ck,
3183         &dpll4_m4_ck,
3184         &dpll4_m4x2_ck,
3185         &dpll4_m5_ck,
3186         &dpll4_m5x2_ck,
3187         &dpll4_m6_ck,
3188         &dpll4_m6x2_ck,
3189         &emu_per_alwon_ck,
3190         &dpll5_ck,
3191         &dpll5_m2_ck,
3192         &omap_120m_fck,
3193         &clkout2_src_ck,
3194         &sys_clkout2,
3195         &corex2_fck,
3196         &dpll1_fck,
3197         &mpu_ck,
3198         &arm_fck,
3199         &emu_mpu_alwon_ck,
3200         &dpll2_fck,
3201         &iva2_ck,
3202         &l3_ick,
3203         &l4_ick,
3204         &rm_ick,
3205         &gfx_l3_ck,
3206         &gfx_l3_fck,
3207         &gfx_l3_ick,
3208         &gfx_cg1_ck,
3209         &gfx_cg2_ck,
3210         &sgx_fck,
3211         &sgx_ick,
3212         &d2d_26m_fck,
3213         &gpt10_fck,
3214         &gpt11_fck,
3215         &cpefuse_fck,
3216         &ts_fck,
3217         &usbtll_fck,
3218         &core_96m_fck,
3219         &mmchs3_fck,
3220         &mmchs2_fck,
3221         &mspro_fck,
3222         &mmchs1_fck,
3223         &i2c3_fck,
3224         &i2c2_fck,
3225         &i2c1_fck,
3226         &mcbsp5_fck,
3227         &mcbsp1_fck,
3228         &core_48m_fck,
3229         &mcspi4_fck,
3230         &mcspi3_fck,
3231         &mcspi2_fck,
3232         &mcspi1_fck,
3233         &uart2_fck,
3234         &uart1_fck,
3235         &fshostusb_fck,
3236         &core_12m_fck,
3237         &hdq_fck,
3238         &ssi_ssr_fck,
3239         &ssi_sst_fck,
3240         &core_l3_ick,
3241         &hsotgusb_ick,
3242         &sdrc_ick,
3243         &gpmc_fck,
3244         &security_l3_ick,
3245         &pka_ick,
3246         &core_l4_ick,
3247         &usbtll_ick,
3248         &mmchs3_ick,
3249         &icr_ick,
3250         &aes2_ick,
3251         &sha12_ick,
3252         &des2_ick,
3253         &mmchs2_ick,
3254         &mmchs1_ick,
3255         &mspro_ick,
3256         &hdq_ick,
3257         &mcspi4_ick,
3258         &mcspi3_ick,
3259         &mcspi2_ick,
3260         &mcspi1_ick,
3261         &i2c3_ick,
3262         &i2c2_ick,
3263         &i2c1_ick,
3264         &uart2_ick,
3265         &uart1_ick,
3266         &gpt11_ick,
3267         &gpt10_ick,
3268         &mcbsp5_ick,
3269         &mcbsp1_ick,
3270         &fac_ick,
3271         &mailboxes_ick,
3272         &omapctrl_ick,
3273         &ssi_l4_ick,
3274         &ssi_ick,
3275         &usb_l4_ick,
3276         &security_l4_ick2,
3277         &aes1_ick,
3278         &rng_ick,
3279         &sha11_ick,
3280         &des1_ick,
3281         &dss1_alwon_fck,
3282         &dss_tv_fck,
3283         &dss_96m_fck,
3284         &dss2_alwon_fck,
3285         &dss_ick,
3286         &cam_mclk,
3287         &cam_ick,
3288         &csi2_96m_fck,
3289         &usbhost_120m_fck,
3290         &usbhost_48m_fck,
3291         &usbhost_ick,
3292         &usim_fck,
3293         &gpt1_fck,
3294         &wkup_32k_fck,
3295         &gpio1_fck,
3296         &wdt2_fck,
3297         &wkup_l4_ick,
3298         &usim_ick,
3299         &wdt2_ick,
3300         &wdt1_ick,
3301         &gpio1_ick,
3302         &omap_32ksync_ick,
3303         &gpt12_ick,
3304         &gpt1_ick,
3305         &per_96m_fck,
3306         &per_48m_fck,
3307         &uart3_fck,
3308         &gpt2_fck,
3309         &gpt3_fck,
3310         &gpt4_fck,
3311         &gpt5_fck,
3312         &gpt6_fck,
3313         &gpt7_fck,
3314         &gpt8_fck,
3315         &gpt9_fck,
3316         &per_32k_alwon_fck,
3317         &gpio6_fck,
3318         &gpio5_fck,
3319         &gpio4_fck,
3320         &gpio3_fck,
3321         &gpio2_fck,
3322         &wdt3_fck,
3323         &per_l4_ick,
3324         &gpio6_ick,
3325         &gpio5_ick,
3326         &gpio4_ick,
3327         &gpio3_ick,
3328         &gpio2_ick,
3329         &wdt3_ick,
3330         &uart3_ick,
3331         &gpt9_ick,
3332         &gpt8_ick,
3333         &gpt7_ick,
3334         &gpt6_ick,
3335         &gpt5_ick,
3336         &gpt4_ick,
3337         &gpt3_ick,
3338         &gpt2_ick,
3339         &mcbsp2_ick,
3340         &mcbsp3_ick,
3341         &mcbsp4_ick,
3342         &mcbsp2_fck,
3343         &mcbsp3_fck,
3344         &mcbsp4_fck,
3345         &emu_src_ck,
3346         &pclk_fck,
3347         &pclkx2_fck,
3348         &atclk_fck,
3349         &traceclk_src_fck,
3350         &traceclk_fck,
3351         &sr1_fck,
3352         &sr2_fck,
3353         &sr_l4_ick,
3354         &secure_32k_fck,
3355         &gpt12_fck,
3356         &wdt1_fck,
3357 };
3358
3359 #endif