arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  18
  19 #include "clock.h"
  20
  21 #include "prm.h"
  22 #include "cm.h"
  23 #include "prm-regbits-24xx.h"
  24 #include "cm-regbits-24xx.h"
  25 #include "sdrc.h"
  26
  27 static void omap2_table_mpu_recalc(struct clk *clk);
  28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  30 static void omap2_sys_clk_recalc(struct clk *clk);
  31 static void omap2_osc_clk_recalc(struct clk *clk);
  32 static void omap2_sys_clk_recalc(struct clk *clk);
  33 static void omap2_dpllcore_recalc(struct clk *clk);
  34 static int omap2_clk_fixed_enable(struct clk *clk);
  35 static void omap2_clk_fixed_disable(struct clk *clk);
  36 static int omap2_enable_osc_ck(struct clk *clk);
  37 static void omap2_disable_osc_ck(struct clk *clk);
  38 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
  39
  40 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  41  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  42  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  43  */
  44 struct prcm_config {
  45         unsigned long xtal_speed;       /* crystal rate */
  46         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  47         unsigned long mpu_speed;        /* speed of MPU */
  48         unsigned long cm_clksel_mpu;    /* mpu divider */
  49         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  50         unsigned long cm_clksel_gfx;    /* gfx dividers */
  51         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  52         unsigned long cm_clksel1_pll;   /* m,n */
  53         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  54         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  55         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  56         unsigned char flags;
  57 };
  58
  59 /*
  60  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  61  * These configurations are characterized by voltage and speed for clocks.
  62  * The device is only validated for certain combinations. One way to express
  63  * these combinations is via the 'ratio's' which the clocks operate with
  64  * respect to each other. These ratio sets are for a given voltage/DPLL
  65  * setting. All configurations can be described by a DPLL setting and a ratio
  66  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  67  *
  68  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  69  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  70  * 2430 (iva2.1, NOdsp, mdm)
  71  */
  72
  73 /* Core fields for cm_clksel, not ratio governed */
  74 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  75 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  76 #define RX_CLKSEL_SSI                   (0x5 << 20)
  77
  78 /*-------------------------------------------------------------------------
  79  * Voltage/DPLL ratios
  80  *-------------------------------------------------------------------------*/
  81
  82 /* 2430 Ratio's, 2430-Ratio Config 1 */
  83 #define R1_CLKSEL_L3                    (4 << 0)
  84 #define R1_CLKSEL_L4                    (2 << 5)
  85 #define R1_CLKSEL_USB                   (4 << 25)
  86 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  87                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  88                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  89 #define R1_CLKSEL_MPU                   (2 << 0)
  90 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  91 #define R1_CLKSEL_DSP                   (2 << 0)
  92 #define R1_CLKSEL_DSP_IF                (2 << 5)
  93 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  94 #define R1_CLKSEL_GFX                   (2 << 0)
  95 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  96 #define R1_CLKSEL_MDM                   (4 << 0)
  97 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
  98
  99 /* 2430-Ratio Config 2 */
 100 #define R2_CLKSEL_L3                    (6 << 0)
 101 #define R2_CLKSEL_L4                    (2 << 5)
 102 #define R2_CLKSEL_USB                   (2 << 25)
 103 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 104                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 105                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 106 #define R2_CLKSEL_MPU                   (2 << 0)
 107 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 108 #define R2_CLKSEL_DSP                   (2 << 0)
 109 #define R2_CLKSEL_DSP_IF                (3 << 5)
 110 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 111 #define R2_CLKSEL_GFX                   (2 << 0)
 112 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 113 #define R2_CLKSEL_MDM                   (6 << 0)
 114 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 115
 116 /* 2430-Ratio Bootm (BYPASS) */
 117 #define RB_CLKSEL_L3                    (1 << 0)
 118 #define RB_CLKSEL_L4                    (1 << 5)
 119 #define RB_CLKSEL_USB                   (1 << 25)
 120 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 121                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 122                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 123 #define RB_CLKSEL_MPU                   (1 << 0)
 124 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 125 #define RB_CLKSEL_DSP                   (1 << 0)
 126 #define RB_CLKSEL_DSP_IF                (1 << 5)
 127 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 128 #define RB_CLKSEL_GFX                   (1 << 0)
 129 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 130 #define RB_CLKSEL_MDM                   (1 << 0)
 131 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 132
 133 /* 2420 Ratio Equivalents */
 134 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 135 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 136
 137 /* 2420-PRCM III 532MHz core */
 138 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 139 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 140 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 141 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 142                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 143                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 144                                         RIII_CLKSEL_L3
 145 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 146 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 147 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 148 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 149 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 150 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 151 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 152 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 153                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 154                                         RIII_CLKSEL_DSP
 155 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 156 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 157
 158 /* 2420-PRCM II 600MHz core */
 159 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 160 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 161 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 162 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 163                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 164                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 165                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 166 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 167 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 168 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 169 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 170 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 171 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 172 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 173 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 174                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 175                                         RII_CLKSEL_DSP
 176 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 177 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 178
 179 /* 2420-PRCM I 660MHz core */
 180 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 181 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 182 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 183 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 184                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 185                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 186                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 187 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 188 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 189 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 190 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 191 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 192 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 193 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 194 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 195                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 196                                         RI_CLKSEL_DSP
 197 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 198 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 199
 200 /* 2420-PRCM VII (boot) */
 201 #define RVII_CLKSEL_L3                  (1 << 0)
 202 #define RVII_CLKSEL_L4                  (1 << 5)
 203 #define RVII_CLKSEL_DSS1                (1 << 8)
 204 #define RVII_CLKSEL_DSS2                (0 << 13)
 205 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 206 #define RVII_CLKSEL_SSI                 (1 << 20)
 207 #define RVII_CLKSEL_USB                 (1 << 25)
 208
 209 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 210                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 211                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 212
 213 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 214 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 215
 216 #define RVII_CLKSEL_DSP                 (1 << 0)
 217 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 218 #define RVII_SYNC_DSP                   (0 << 7)
 219 #define RVII_CLKSEL_IVA                 (1 << 8)
 220 #define RVII_SYNC_IVA                   (0 << 13)
 221 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 222                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 223
 224 #define RVII_CLKSEL_GFX                 (1 << 0)
 225 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 226
 227 /*-------------------------------------------------------------------------
 228  * 2430 Target modes: Along with each configuration the CPU has several
 229  * modes which goes along with them. Modes mainly are the addition of
 230  * describe DPLL combinations to go along with a ratio.
 231  *-------------------------------------------------------------------------*/
 232
 233 /* Hardware governed */
 234 #define MX_48M_SRC                      (0 << 3)
 235 #define MX_54M_SRC                      (0 << 5)
 236 #define MX_APLLS_CLIKIN_12              (3 << 23)
 237 #define MX_APLLS_CLIKIN_13              (2 << 23)
 238 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 239
 240 /*
 241  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 242  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 243  */
 244 #define M5A_DPLL_MULT_12                (133 << 12)
 245 #define M5A_DPLL_DIV_12                 (5 << 8)
 246 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 247                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 248                                         MX_APLLS_CLIKIN_12
 249 #define M5A_DPLL_MULT_13                (61 << 12)
 250 #define M5A_DPLL_DIV_13                 (2 << 8)
 251 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 252                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 253                                         MX_APLLS_CLIKIN_13
 254 #define M5A_DPLL_MULT_19                (55 << 12)
 255 #define M5A_DPLL_DIV_19                 (3 << 8)
 256 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 257                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 258                                         MX_APLLS_CLIKIN_19_2
 259 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 260 #define M5B_DPLL_MULT_12                (50 << 12)
 261 #define M5B_DPLL_DIV_12                 (2 << 8)
 262 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 263                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 264                                         MX_APLLS_CLIKIN_12
 265 #define M5B_DPLL_MULT_13                (200 << 12)
 266 #define M5B_DPLL_DIV_13                 (12 << 8)
 267
 268 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 269                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 270                                         MX_APLLS_CLIKIN_13
 271 #define M5B_DPLL_MULT_19                (125 << 12)
 272 #define M5B_DPLL_DIV_19                 (31 << 8)
 273 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 274                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 275                                         MX_APLLS_CLIKIN_19_2
 276 /*
 277  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 278  */
 279 #define M4_DPLL_MULT_12                 (133 << 12)
 280 #define M4_DPLL_DIV_12                  (3 << 8)
 281 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 282                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 283                                         MX_APLLS_CLIKIN_12
 284
 285 #define M4_DPLL_MULT_13                 (399 << 12)
 286 #define M4_DPLL_DIV_13                  (12 << 8)
 287 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 288                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 289                                         MX_APLLS_CLIKIN_13
 290
 291 #define M4_DPLL_MULT_19                 (145 << 12)
 292 #define M4_DPLL_DIV_19                  (6 << 8)
 293 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 294                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 295                                         MX_APLLS_CLIKIN_19_2
 296
 297 /*
 298  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 299  */
 300 #define M3_DPLL_MULT_12                 (55 << 12)
 301 #define M3_DPLL_DIV_12                  (1 << 8)
 302 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 303                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 304                                         MX_APLLS_CLIKIN_12
 305 #define M3_DPLL_MULT_13                 (76 << 12)
 306 #define M3_DPLL_DIV_13                  (2 << 8)
 307 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 308                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 309                                         MX_APLLS_CLIKIN_13
 310 #define M3_DPLL_MULT_19                 (17 << 12)
 311 #define M3_DPLL_DIV_19                  (0 << 8)
 312 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 313                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 314                                         MX_APLLS_CLIKIN_19_2
 315
 316 /*
 317  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 318  */
 319 #define M2_DPLL_MULT_12                 (55 << 12)
 320 #define M2_DPLL_DIV_12                  (1 << 8)
 321 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 322                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 323                                         MX_APLLS_CLIKIN_12
 324
 325 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 326  * relock time issue */
 327 /* Core frequency changed from 330/165 to 329/164 MHz*/
 328 #define M2_DPLL_MULT_13                 (76 << 12)
 329 #define M2_DPLL_DIV_13                  (2 << 8)
 330 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 331                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 332                                         MX_APLLS_CLIKIN_13
 333
 334 #define M2_DPLL_MULT_19                 (17 << 12)
 335 #define M2_DPLL_DIV_19                  (0 << 8)
 336 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 337                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 338                                         MX_APLLS_CLIKIN_19_2
 339
 340 /* boot (boot) */
 341 #define MB_DPLL_MULT                    (1 << 12)
 342 #define MB_DPLL_DIV                     (0 << 8)
 343 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 344                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 345
 346 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 347                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 348
 349 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 350                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 351
 352 /*
 353  * 2430 - chassis (sedna)
 354  * 165 (ratio1) same as above #2
 355  * 150 (ratio1)
 356  * 133 (ratio2) same as above #4
 357  * 110 (ratio2) same as above #3
 358  * 104 (ratio2)
 359  * boot (boot)
 360  */
 361
 362 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 363 #define MI_DPLL_MULT_12                 (55 << 12)
 364 #define MI_DPLL_DIV_12                  (1 << 8)
 365 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 366                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 367                                         MX_APLLS_CLIKIN_12
 368
 369 /*
 370  * 2420 Equivalent - mode registers
 371  * PRCM II , target DPLL = 2*300MHz = 600MHz
 372  */
 373 #define MII_DPLL_MULT_12                (50 << 12)
 374 #define MII_DPLL_DIV_12                 (1 << 8)
 375 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 376                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 377                                         MX_APLLS_CLIKIN_12
 378 #define MII_DPLL_MULT_13                (300 << 12)
 379 #define MII_DPLL_DIV_13                 (12 << 8)
 380 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 381                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 382                                         MX_APLLS_CLIKIN_13
 383
 384 /* PRCM III target DPLL = 2*266 = 532MHz*/
 385 #define MIII_DPLL_MULT_12               (133 << 12)
 386 #define MIII_DPLL_DIV_12                (5 << 8)
 387 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 388                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 389                                         MX_APLLS_CLIKIN_12
 390 #define MIII_DPLL_MULT_13               (266 << 12)
 391 #define MIII_DPLL_DIV_13                (12 << 8)
 392 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 393                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 394                                         MX_APLLS_CLIKIN_13
 395
 396 /* PRCM VII (boot bypass) */
 397 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 398 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 399
 400 /* High and low operation value */
 401 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 402 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 403
 404 /* MPU speed defines */
 405 #define S12M    12000000
 406 #define S13M    13000000
 407 #define S19M    19200000
 408 #define S26M    26000000
 409 #define S100M   100000000
 410 #define S133M   133000000
 411 #define S150M   150000000
 412 #define S164M   164000000
 413 #define S165M   165000000
 414 #define S199M   199000000
 415 #define S200M   200000000
 416 #define S266M   266000000
 417 #define S300M   300000000
 418 #define S329M   329000000
 419 #define S330M   330000000
 420 #define S399M   399000000
 421 #define S400M   400000000
 422 #define S532M   532000000
 423 #define S600M   600000000
 424 #define S658M   658000000
 425 #define S660M   660000000
 426 #define S798M   798000000
 427
 428 /*-------------------------------------------------------------------------
 429  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 430  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 431  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 432  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 433  *
 434  * Filling in table based on H4 boards and 2430-SDPs variants available.
 435  * There are quite a few more rates combinations which could be defined.
 436  *
 437  * When multiple values are defined the start up will try and choose the
 438  * fastest one. If a 'fast' value is defined, then automatically, the /2
 439  * one should be included as it can be used.    Generally having more that
 440  * one fast set does not make sense, as static timings need to be changed
 441  * to change the set.    The exception is the bypass setting which is
 442  * availble for low power bypass.
 443  *
 444  * Note: This table needs to be sorted, fastest to slowest.
 445  *-------------------------------------------------------------------------*/
 446 static struct prcm_config rate_table[] = {
 447         /* PRCM I - FAST */
 448         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 449                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 450                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 451                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 452                 RATE_IN_242X},
 453
 454         /* PRCM II - FAST */
 455         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 456                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 457                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 458                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 459                 RATE_IN_242X},
 460
 461         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 462                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 463                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 464                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 465                 RATE_IN_242X},
 466
 467         /* PRCM III - FAST */
 468         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 469                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 470                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 471                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 472                 RATE_IN_242X},
 473
 474         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 475                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 476                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 477                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 478                 RATE_IN_242X},
 479
 480         /* PRCM II - SLOW */
 481         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 482                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 483                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 484                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 485                 RATE_IN_242X},
 486
 487         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 488                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 489                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 490                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 491                 RATE_IN_242X},
 492
 493         /* PRCM III - SLOW */
 494         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 495                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 496                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 497                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 498                 RATE_IN_242X},
 499
 500         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 501                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 502                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 503                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 504                 RATE_IN_242X},
 505
 506         /* PRCM-VII (boot-bypass) */
 507         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 508                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 509                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 510                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 511                 RATE_IN_242X},
 512
 513         /* PRCM-VII (boot-bypass) */
 514         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 515                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 516                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 517                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 518                 RATE_IN_242X},
 519
 520         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 521         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 522                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 523                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 524                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 525                 SDRC_RFR_CTRL_133MHz,
 526                 RATE_IN_243X},
 527
 528         /* PRCM #2 - ratio1 (ES2) - FAST */
 529         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 530                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 531                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 532                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 533                 SDRC_RFR_CTRL_165MHz,
 534                 RATE_IN_243X},
 535
 536         /* PRCM #5a - ratio1 - FAST */
 537         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 538                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 539                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 540                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 541                 SDRC_RFR_CTRL_133MHz,
 542                 RATE_IN_243X},
 543
 544         /* PRCM #5b - ratio1 - FAST */
 545         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 546                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 547                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 548                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 549                 SDRC_RFR_CTRL_100MHz,
 550                 RATE_IN_243X},
 551
 552         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 553         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 554                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 555                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 556                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 557                 SDRC_RFR_CTRL_133MHz,
 558                 RATE_IN_243X},
 559
 560         /* PRCM #2 - ratio1 (ES2) - SLOW */
 561         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 562                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 563                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 564                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 565                 SDRC_RFR_CTRL_165MHz,
 566                 RATE_IN_243X},
 567
 568         /* PRCM #5a - ratio1 - SLOW */
 569         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 570                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 571                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 572                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 573                 SDRC_RFR_CTRL_133MHz,
 574                 RATE_IN_243X},
 575
 576         /* PRCM #5b - ratio1 - SLOW*/
 577         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 578                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 579                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 580                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 581                 SDRC_RFR_CTRL_100MHz,
 582                 RATE_IN_243X},
 583
 584         /* PRCM-boot/bypass */
 585         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 586                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 587                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 588                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 589                 SDRC_RFR_CTRL_BYPASS,
 590                 RATE_IN_243X},
 591
 592         /* PRCM-boot/bypass */
 593         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 594                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 595                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 596                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 597                 SDRC_RFR_CTRL_BYPASS,
 598                 RATE_IN_243X},
 599
 600         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 601 };
 602
 603 /*-------------------------------------------------------------------------
 604  * 24xx clock tree.
 605  *
 606  * NOTE:In many cases here we are assigning a 'default' parent. In many
 607  *      cases the parent is selectable. The get/set parent calls will also
 608  *      switch sources.
 609  *
 610  *      Many some clocks say always_enabled, but they can be auto idled for
 611  *      power savings. They will always be available upon clock request.
 612  *
 613  *      Several sources are given initial rates which may be wrong, this will
 614  *      be fixed up in the init func.
 615  *
 616  *      Things are broadly separated below by clock domains. It is
 617  *      noteworthy that most periferals have dependencies on multiple clock
 618  *      domains. Many get their interface clocks from the L4 domain, but get
 619  *      functional clocks from fixed sources or other core domain derived
 620  *      clocks.
 621  *-------------------------------------------------------------------------*/
 622
 623 /* Base external input clocks */
 624 static struct clk func_32k_ck = {
 625         .name           = "func_32k_ck",
 626         .rate           = 32000,
 627         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 628                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 629         .clkdm          = { .name = "prm_clkdm" },
 630         .recalc         = &propagate_rate,
 631 };
 632
 633 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 634 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 635         .name           = "osc_ck",
 636         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 637                                 RATE_PROPAGATES,
 638         .clkdm          = { .name = "prm_clkdm" },
 639         .enable         = &omap2_enable_osc_ck,
 640         .disable        = &omap2_disable_osc_ck,
 641         .recalc         = &omap2_osc_clk_recalc,
 642 };
 643
 644 /* Without modem likely 12MHz, with modem likely 13MHz */
 645 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 646         .name           = "sys_ck",             /* ~ ref_clk also */
 647         .parent         = &osc_ck,
 648         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 649                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 650         .clkdm          = { .name = "prm_clkdm" },
 651         .recalc         = &omap2_sys_clk_recalc,
 652 };
 653
 654 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 655         .name           = "alt_ck",
 656         .rate           = 54000000,
 657         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 658                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 659         .clkdm          = { .name = "prm_clkdm" },
 660         .recalc         = &propagate_rate,
 661 };
 662
 663 /*
 664  * Analog domain root source clocks
 665  */
 666
 667 /* dpll_ck, is broken out in to special cases through clksel */
 668 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 669  * deal with this
 670  */
 671
 672 static struct dpll_data dpll_dd = {
 673         .mult_div1_reg          = CM_CLKSEL1,
 674         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 675         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 676         .idlest_reg             = CM_IDLEST,
 677         .idlest_mask            = OMAP24XX_ST_CORE_CLK_MASK,
 678         .max_multiplier         = 1024,
 679         .max_divider            = 16,
 680         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 681 };
 682
 683 /*
 684  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 685  * not just a DPLL
 686  */
 687 static struct clk dpll_ck = {
 688         .name           = "dpll_ck",
 689         .parent         = &sys_ck,              /* Can be func_32k also */
 690         .prcm_mod       = PLL_MOD,
 691         .dpll_data      = &dpll_dd,
 692         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 693                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 694         .clkdm          = { .name = "prm_clkdm" },
 695         .recalc         = &omap2_dpllcore_recalc,
 696         .set_rate       = &omap2_reprogram_dpllcore,
 697 };
 698
 699 static struct clk apll96_ck = {
 700         .name           = "apll96_ck",
 701         .parent         = &sys_ck,
 702         .prcm_mod       = PLL_MOD,
 703         .rate           = 96000000,
 704         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 705                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 706         .clkdm          = { .name = "prm_clkdm" },
 707         .enable_reg     = CM_CLKEN,
 708         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 709         .enable         = &omap2_clk_fixed_enable,
 710         .disable        = &omap2_clk_fixed_disable,
 711         .recalc         = &propagate_rate,
 712 };
 713
 714 static struct clk apll54_ck = {
 715         .name           = "apll54_ck",
 716         .parent         = &sys_ck,
 717         .prcm_mod       = PLL_MOD,
 718         .rate           = 54000000,
 719         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 720                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 721         .clkdm          = { .name = "prm_clkdm" },
 722         .enable_reg     = CM_CLKEN,
 723         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 724         .enable         = &omap2_clk_fixed_enable,
 725         .disable        = &omap2_clk_fixed_disable,
 726         .recalc         = &propagate_rate,
 727 };
 728
 729 /*
 730  * PRCM digital base sources
 731  */
 732
 733 /* func_54m_ck */
 734
 735 static const struct clksel_rate func_54m_apll54_rates[] = {
 736         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 737         { .div = 0 },
 738 };
 739
 740 static const struct clksel_rate func_54m_alt_rates[] = {
 741         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 742         { .div = 0 },
 743 };
 744
 745 static const struct clksel func_54m_clksel[] = {
 746         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 747         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 748         { .parent = NULL },
 749 };
 750
 751 static struct clk func_54m_ck = {
 752         .name           = "func_54m_ck",
 753         .parent         = &apll54_ck,   /* can also be alt_clk */
 754         .prcm_mod       = PLL_MOD,
 755         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 756                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 757         .clkdm          = { .name = "cm_clkdm" },
 758         .init           = &omap2_init_clksel_parent,
 759         .clksel_reg     = CM_CLKSEL1,
 760         .clksel_mask    = OMAP24XX_54M_SOURCE,
 761         .clksel         = func_54m_clksel,
 762         .recalc         = &omap2_clksel_recalc,
 763 };
 764
 765 static struct clk core_ck = {
 766         .name           = "core_ck",
 767         .parent         = &dpll_ck,             /* can also be 32k */
 768         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 769                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 770         .clkdm          = { .name = "cm_clkdm" },
 771         .recalc         = &followparent_recalc,
 772 };
 773
 774 /* func_96m_ck */
 775 static const struct clksel_rate func_96m_apll96_rates[] = {
 776         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 777         { .div = 0 },
 778 };
 779
 780 static const struct clksel_rate func_96m_alt_rates[] = {
 781         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 782         { .div = 0 },
 783 };
 784
 785 static const struct clksel func_96m_clksel[] = {
 786         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 787         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 788         { .parent = NULL }
 789 };
 790
 791 /* The parent of this clock is not selectable on 2420. */
 792 static struct clk func_96m_ck = {
 793         .name           = "func_96m_ck",
 794         .parent         = &apll96_ck,
 795         .prcm_mod       = PLL_MOD,
 796         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 797                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 798         .clkdm          = { .name = "cm_clkdm" },
 799         .init           = &omap2_init_clksel_parent,
 800         .clksel_reg     = CM_CLKSEL1,
 801         .clksel_mask    = OMAP2430_96M_SOURCE,
 802         .clksel         = func_96m_clksel,
 803         .recalc         = &omap2_clksel_recalc,
 804         .round_rate     = &omap2_clksel_round_rate,
 805         .set_rate       = &omap2_clksel_set_rate
 806 };
 807
 808 /* func_48m_ck */
 809
 810 static const struct clksel_rate func_48m_apll96_rates[] = {
 811         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 812         { .div = 0 },
 813 };
 814
 815 static const struct clksel_rate func_48m_alt_rates[] = {
 816         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 817         { .div = 0 },
 818 };
 819
 820 static const struct clksel func_48m_clksel[] = {
 821         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 822         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 823         { .parent = NULL }
 824 };
 825
 826 static struct clk func_48m_ck = {
 827         .name           = "func_48m_ck",
 828         .parent         = &apll96_ck,    /* 96M or Alt */
 829         .prcm_mod       = PLL_MOD,
 830         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 831                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 832         .clkdm          = { .name = "cm_clkdm" },
 833         .init           = &omap2_init_clksel_parent,
 834         .clksel_reg     = CM_CLKSEL1,
 835         .clksel_mask    = OMAP24XX_48M_SOURCE,
 836         .clksel         = func_48m_clksel,
 837         .recalc         = &omap2_clksel_recalc,
 838         .round_rate     = &omap2_clksel_round_rate,
 839         .set_rate       = &omap2_clksel_set_rate
 840 };
 841
 842 static struct clk func_12m_ck = {
 843         .name           = "func_12m_ck",
 844         .parent         = &func_48m_ck,
 845         .fixed_div      = 4,
 846         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 847                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 848         .clkdm          = { .name = "cm_clkdm" },
 849         .recalc         = &omap2_fixed_divisor_recalc,
 850 };
 851
 852 /* Secure timer, only available in secure mode */
 853 static struct clk wdt1_osc_ck = {
 854         .name           = "wdt1_osc_ck",
 855         .parent         = &osc_ck,
 856         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 857         .clkdm          = { .name = "prm_clkdm" },
 858         .recalc         = &followparent_recalc,
 859 };
 860
 861 /*
 862  * The common_clkout* clksel_rate structs are common to
 863  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 864  * sys_clkout2_* are 2420-only, so the
 865  * clksel_rate flags fields are inaccurate for those clocks. This is
 866  * harmless since access to those clocks are gated by the struct clk
 867  * flags fields, which mark them as 2420-only.
 868  */
 869 static const struct clksel_rate common_clkout_src_core_rates[] = {
 870         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 871         { .div = 0 }
 872 };
 873
 874 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 875         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 876         { .div = 0 }
 877 };
 878
 879 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 880         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 881         { .div = 0 }
 882 };
 883
 884 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 885         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 886         { .div = 0 }
 887 };
 888
 889 static const struct clksel common_clkout_src_clksel[] = {
 890         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 891         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 892         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 893         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 894         { .parent = NULL }
 895 };
 896
 897 static struct clk sys_clkout_src = {
 898         .name           = "sys_clkout_src",
 899         .parent         = &func_54m_ck,
 900         .prcm_mod       = OMAP24XX_GR_MOD,
 901         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 902                                 RATE_PROPAGATES,
 903         .clkdm          = { .name = "prm_clkdm" },
 904         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 905         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 906         .init           = &omap2_init_clksel_parent,
 907         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 908         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 909         .clksel         = common_clkout_src_clksel,
 910         .recalc         = &omap2_clksel_recalc,
 911         .round_rate     = &omap2_clksel_round_rate,
 912         .set_rate       = &omap2_clksel_set_rate
 913 };
 914
 915 static const struct clksel_rate common_clkout_rates[] = {
 916         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 917         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 918         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 919         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 920         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 921         { .div = 0 },
 922 };
 923
 924 static const struct clksel sys_clkout_clksel[] = {
 925         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 926         { .parent = NULL }
 927 };
 928
 929 static struct clk sys_clkout = {
 930         .name           = "sys_clkout",
 931         .parent         = &sys_clkout_src,
 932         .prcm_mod       = OMAP24XX_GR_MOD,
 933         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 934                                 PARENT_CONTROLS_CLOCK,
 935         .clkdm          = { .name = "prm_clkdm" },
 936         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 937         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 938         .clksel         = sys_clkout_clksel,
 939         .recalc         = &omap2_clksel_recalc,
 940         .round_rate     = &omap2_clksel_round_rate,
 941         .set_rate       = &omap2_clksel_set_rate
 942 };
 943
 944 /* In 2430, new in 2420 ES2 */
 945 static struct clk sys_clkout2_src = {
 946         .name           = "sys_clkout2_src",
 947         .parent         = &func_54m_ck,
 948         .prcm_mod       = OMAP24XX_GR_MOD,
 949         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
 950         .clkdm          = { .name = "cm_clkdm" },
 951         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 952         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 953         .init           = &omap2_init_clksel_parent,
 954         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 955         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 956         .clksel         = common_clkout_src_clksel,
 957         .recalc         = &omap2_clksel_recalc,
 958         .round_rate     = &omap2_clksel_round_rate,
 959         .set_rate       = &omap2_clksel_set_rate
 960 };
 961
 962 static const struct clksel sys_clkout2_clksel[] = {
 963         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 964         { .parent = NULL }
 965 };
 966
 967 /* In 2430, new in 2420 ES2 */
 968 static struct clk sys_clkout2 = {
 969         .name           = "sys_clkout2",
 970         .parent         = &sys_clkout2_src,
 971         .prcm_mod       = OMAP24XX_GR_MOD,
 972         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
 973         .clkdm          = { .name = "cm_clkdm" },
 974         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 975         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 976         .clksel         = sys_clkout2_clksel,
 977         .recalc         = &omap2_clksel_recalc,
 978         .round_rate     = &omap2_clksel_round_rate,
 979         .set_rate       = &omap2_clksel_set_rate
 980 };
 981
 982 static struct clk emul_ck = {
 983         .name           = "emul_ck",
 984         .parent         = &func_54m_ck,
 985         .prcm_mod       = OMAP24XX_GR_MOD,
 986         .flags          = CLOCK_IN_OMAP242X,
 987         .clkdm          = { .name = "cm_clkdm" },
 988         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET,
 989         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 990         .recalc         = &followparent_recalc,
 991
 992 };
 993
 994 /*
 995  * MPU clock domain
 996  *      Clocks:
 997  *              MPU_FCLK, MPU_ICLK
 998  *              INT_M_FCLK, INT_M_I_CLK
 999  *
1000  * - Individual clocks are hardware managed.
1001  * - Base divider comes from: CM_CLKSEL_MPU
1002  *
1003  */
1004 static const struct clksel_rate mpu_core_rates[] = {
1005         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1006         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1007         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1008         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1009         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1010         { .div = 0 },
1011 };
1012
1013 static const struct clksel mpu_clksel[] = {
1014         { .parent = &core_ck, .rates = mpu_core_rates },
1015         { .parent = NULL }
1016 };
1017
1018 static struct clk mpu_ck = {    /* Control cpu */
1019         .name           = "mpu_ck",
1020         .parent         = &core_ck,
1021         .prcm_mod       = MPU_MOD,
1022         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1023                                 ALWAYS_ENABLED | DELAYED_APP |
1024                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1025         .clkdm          = { .name = "mpu_clkdm" },
1026         .init           = &omap2_init_clksel_parent,
1027         .clksel_reg     = CM_CLKSEL,
1028         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
1029         .clksel         = mpu_clksel,
1030         .recalc         = &omap2_clksel_recalc,
1031         .round_rate     = &omap2_clksel_round_rate,
1032         .set_rate       = &omap2_clksel_set_rate
1033 };
1034
1035 /*
1036  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1037  * Clocks:
1038  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1039  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1040  *
1041  * Won't be too specific here. The core clock comes into this block
1042  * it is divided then tee'ed. One branch goes directly to xyz enable
1043  * controls. The other branch gets further divided by 2 then possibly
1044  * routed into a synchronizer and out of clocks abc.
1045  */
1046 static const struct clksel_rate dsp_fck_core_rates[] = {
1047         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1048         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1049         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1050         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1051         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1052         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1053         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1054         { .div = 0 },
1055 };
1056
1057 static const struct clksel dsp_fck_clksel[] = {
1058         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1059         { .parent = NULL }
1060 };
1061
1062 static struct clk dsp_fck = {
1063         .name           = "dsp_fck",
1064         .parent         = &core_ck,
1065         .prcm_mod       = OMAP24XX_DSP_MOD,
1066         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1067                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1068         .clkdm          = { .name = "dsp_clkdm" },
1069         .enable_reg     = CM_FCLKEN,
1070         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1071         .clksel_reg     = CM_CLKSEL,
1072         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1073         .clksel         = dsp_fck_clksel,
1074         .recalc         = &omap2_clksel_recalc,
1075         .round_rate     = &omap2_clksel_round_rate,
1076         .set_rate       = &omap2_clksel_set_rate
1077 };
1078
1079 /* DSP interface clock */
1080 static const struct clksel_rate dsp_irate_ick_rates[] = {
1081         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1082         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1083         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1084         { .div = 0 },
1085 };
1086
1087 static const struct clksel dsp_irate_ick_clksel[] = {
1088         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1089         { .parent = NULL }
1090 };
1091
1092 /* This clock does not exist as such in the TRM. */
1093 static struct clk dsp_irate_ick = {
1094         .name           = "dsp_irate_ick",
1095         .parent         = &dsp_fck,
1096         .prcm_mod       = OMAP24XX_DSP_MOD,
1097         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1098                                 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1099         .clkdm          = { .name = "dsp_clkdm" },
1100         .clksel_reg     = CM_CLKSEL,
1101         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1102         .clksel         = dsp_irate_ick_clksel,
1103         .recalc         = &omap2_clksel_recalc,
1104         .round_rate     = &omap2_clksel_round_rate,
1105         .set_rate       = &omap2_clksel_set_rate
1106 };
1107
1108 /* 2420 only */
1109 static struct clk dsp_ick = {
1110         .name           = "dsp_ick",     /* apparently ipi and isp */
1111         .parent         = &dsp_irate_ick,
1112         .prcm_mod       = OMAP24XX_DSP_MOD,
1113         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1114         .clkdm          = { .name = "dsp_clkdm" },
1115         .enable_reg     = CM_ICLKEN,
1116         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1117 };
1118
1119 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1120 static struct clk iva2_1_ick = {
1121         .name           = "iva2_1_ick",
1122         .parent         = &dsp_irate_ick,
1123         .prcm_mod       = OMAP24XX_DSP_MOD,
1124         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1125         .clkdm          = { .name = "dsp_clkdm" },
1126         .enable_reg     = CM_FCLKEN,
1127         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1128 };
1129
1130 /*
1131  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1132  * the C54x, but which is contained in the DSP powerdomain.  Does not
1133  * exist on later OMAPs.
1134  */
1135 static struct clk iva1_ifck = {
1136         .name           = "iva1_ifck",
1137         .parent         = &core_ck,
1138         .prcm_mod       = OMAP24XX_DSP_MOD,
1139         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1140                                 RATE_PROPAGATES | DELAYED_APP,
1141         .clkdm          = { .name = "iva1_clkdm" },
1142         .enable_reg     = CM_FCLKEN,
1143         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1144         .clksel_reg     = CM_CLKSEL,
1145         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1146         .clksel         = dsp_fck_clksel,
1147         .recalc         = &omap2_clksel_recalc,
1148         .round_rate     = &omap2_clksel_round_rate,
1149         .set_rate       = &omap2_clksel_set_rate
1150 };
1151
1152 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1153 static struct clk iva1_mpu_int_ifck = {
1154         .name           = "iva1_mpu_int_ifck",
1155         .parent         = &iva1_ifck,
1156         .prcm_mod       = OMAP24XX_DSP_MOD,
1157         .flags          = CLOCK_IN_OMAP242X,
1158         .clkdm          = { .name = "iva1_clkdm" },
1159         .enable_reg     = CM_FCLKEN,
1160         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1161         .fixed_div      = 2,
1162         .recalc         = &omap2_fixed_divisor_recalc,
1163 };
1164
1165 /*
1166  * L3 clock domain
1167  * L3 clocks are used for both interface and functional clocks to
1168  * multiple entities. Some of these clocks are completely managed
1169  * by hardware, and some others allow software control. Hardware
1170  * managed ones general are based on directly CLK_REQ signals and
1171  * various auto idle settings. The functional spec sets many of these
1172  * as 'tie-high' for their enables.
1173  *
1174  * I-CLOCKS:
1175  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1176  *      CAM, HS-USB.
1177  * F-CLOCK
1178  *      SSI.
1179  *
1180  * GPMC memories and SDRC have timing and clock sensitive registers which
1181  * may very well need notification when the clock changes. Currently for low
1182  * operating points, these are taken care of in sleep.S.
1183  */
1184 static const struct clksel_rate core_l3_core_rates[] = {
1185         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1186         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1187         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1188         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1189         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1190         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1191         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1192         { .div = 0 }
1193 };
1194
1195 static const struct clksel core_l3_clksel[] = {
1196         { .parent = &core_ck, .rates = core_l3_core_rates },
1197         { .parent = NULL }
1198 };
1199
1200 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1201         .name           = "core_l3_ck",
1202         .parent         = &core_ck,
1203         .prcm_mod       = CORE_MOD,
1204         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1205                                 ALWAYS_ENABLED | DELAYED_APP |
1206                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1207         .clkdm          = { .name = "core_l3_clkdm" },
1208         .clksel_reg     = CM_CLKSEL1,
1209         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1210         .clksel         = core_l3_clksel,
1211         .recalc         = &omap2_clksel_recalc,
1212         .round_rate     = &omap2_clksel_round_rate,
1213         .set_rate       = &omap2_clksel_set_rate
1214 };
1215
1216 /* usb_l4_ick */
1217 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1218         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1219         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1220         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1221         { .div = 0 }
1222 };
1223
1224 static const struct clksel usb_l4_ick_clksel[] = {
1225         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1226         { .parent = NULL },
1227 };
1228
1229 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1230 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1231         .name           = "usb_l4_ick",
1232         .parent         = &core_l3_ck,
1233         .prcm_mod       = CORE_MOD,
1234         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1235                                 DELAYED_APP | CONFIG_PARTICIPANT | WAIT_READY,
1236         .clkdm          = { .name = "core_l4_clkdm" },
1237         .enable_reg     = CM_ICLKEN2,
1238         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1239         .idlest_bit     = OMAP24XX_ST_USB_SHIFT,
1240         .clksel_reg     = CM_CLKSEL1,
1241         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1242         .clksel         = usb_l4_ick_clksel,
1243         .recalc         = &omap2_clksel_recalc,
1244         .round_rate     = &omap2_clksel_round_rate,
1245         .set_rate       = &omap2_clksel_set_rate
1246 };
1247
1248 /*
1249  * L4 clock management domain
1250  *
1251  * This domain contains lots of interface clocks from the L4 interface, some
1252  * functional clocks.   Fixed APLL functional source clocks are managed in
1253  * this domain.
1254  */
1255 static const struct clksel_rate l4_core_l3_rates[] = {
1256         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1257         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1258         { .div = 0 }
1259 };
1260
1261 static const struct clksel l4_clksel[] = {
1262         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1263         { .parent = NULL }
1264 };
1265
1266 static struct clk l4_ck = {             /* used both as an ick and fck */
1267         .name           = "l4_ck",
1268         .parent         = &core_l3_ck,
1269         .prcm_mod       = CORE_MOD,
1270         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1271                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1272         .clkdm          = { .name = "core_l4_clkdm" },
1273         .clksel_reg     = CM_CLKSEL1,
1274         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1275         .clksel         = l4_clksel,
1276         .recalc         = &omap2_clksel_recalc,
1277         .round_rate     = &omap2_clksel_round_rate,
1278         .set_rate       = &omap2_clksel_set_rate
1279 };
1280
1281 /*
1282  * SSI is in L3 management domain, its direct parent is core not l3,
1283  * many core power domain entities are grouped into the L3 clock
1284  * domain.
1285  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1286  *
1287  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1288  */
1289 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1290         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1291         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1292         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1293         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1294         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1295         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1296         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1297         { .div = 0 }
1298 };
1299
1300 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1301         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1302         { .parent = NULL }
1303 };
1304
1305 static struct clk ssi_ssr_sst_fck = {
1306         .name           = "ssi_fck",
1307         .parent         = &core_ck,
1308         .prcm_mod       = CORE_MOD,
1309         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY |
1310                                 DELAYED_APP,
1311         .clkdm          = { .name = "core_l3_clkdm" },
1312         .enable_reg     = OMAP24XX_CM_FCLKEN2,
1313         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1314         .idlest_bit     = OMAP24XX_ST_SSI_SHIFT,
1315         .clksel_reg     = CM_CLKSEL1,
1316         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1317         .clksel         = ssi_ssr_sst_fck_clksel,
1318         .recalc         = &omap2_clksel_recalc,
1319         .round_rate     = &omap2_clksel_round_rate,
1320         .set_rate       = &omap2_clksel_set_rate
1321 };
1322
1323 /*
1324  * Presumably this is the same as SSI_ICLK.
1325  * TRM contradicts itself on what clockdomain SSI_ICLK is in
1326  */
1327 static struct clk ssi_l4_ick = {
1328         .name           = "ssi_l4_ick",
1329         .parent         = &l4_ck,
1330         .prcm_mod       = CORE_MOD,
1331         .clkdm          = { .name = "core_l4_clkdm" },
1332         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1333         .enable_reg     = CM_ICLKEN2,
1334         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1335         .idlest_bit     = OMAP24XX_ST_SSI_SHIFT,
1336         .recalc         = &followparent_recalc,
1337 };
1338
1339
1340 /*
1341  * GFX clock domain
1342  *      Clocks:
1343  * GFX_FCLK, GFX_ICLK
1344  * GFX_CG1(2d), GFX_CG2(3d)
1345  *
1346  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1347  * The 2d and 3d clocks run at a hardware determined
1348  * divided value of fclk.
1349  *
1350  */
1351 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1352
1353 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1354 static const struct clksel gfx_fck_clksel[] = {
1355         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1356         { .parent = NULL },
1357 };
1358
1359 static struct clk gfx_3d_fck = {
1360         .name           = "gfx_3d_fck",
1361         .parent         = &core_l3_ck,
1362         .prcm_mod       = GFX_MOD,
1363         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1364         .clkdm          = { .name = "gfx_clkdm" },
1365         .enable_reg     = CM_FCLKEN,
1366         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1367         .clksel_reg     = CM_CLKSEL,
1368         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1369         .clksel         = gfx_fck_clksel,
1370         .recalc         = &omap2_clksel_recalc,
1371         .round_rate     = &omap2_clksel_round_rate,
1372         .set_rate       = &omap2_clksel_set_rate
1373 };
1374
1375 static struct clk gfx_2d_fck = {
1376         .name           = "gfx_2d_fck",
1377         .parent         = &core_l3_ck,
1378         .prcm_mod       = GFX_MOD,
1379         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1380         .clkdm          = { .name = "gfx_clkdm" },
1381         .enable_reg     = CM_FCLKEN,
1382         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1383         .clksel_reg     = CM_CLKSEL,
1384         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1385         .clksel         = gfx_fck_clksel,
1386         .recalc         = &omap2_clksel_recalc,
1387         .round_rate     = &omap2_clksel_round_rate,
1388         .set_rate       = &omap2_clksel_set_rate
1389 };
1390
1391 static struct clk gfx_ick = {
1392         .name           = "gfx_ick",            /* From l3 */
1393         .parent         = &core_l3_ck,
1394         .prcm_mod       = GFX_MOD,
1395         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1396         .clkdm          = { .name = "gfx_clkdm" },
1397         .enable_reg     = CM_ICLKEN,
1398         .enable_bit     = OMAP_EN_GFX_SHIFT,
1399         .recalc         = &followparent_recalc,
1400 };
1401
1402 /*
1403  * Modem clock domain (2430)
1404  *      CLOCKS:
1405  *              MDM_OSC_CLK
1406  *              MDM_ICLK
1407  * These clocks are usable in chassis mode only.
1408  */
1409 static const struct clksel_rate mdm_ick_core_rates[] = {
1410         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1411         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1412         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1413         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1414         { .div = 0 }
1415 };
1416
1417 static const struct clksel mdm_ick_clksel[] = {
1418         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1419         { .parent = NULL }
1420 };
1421
1422 static struct clk mdm_ick = {           /* used both as a ick and fck */
1423         .name           = "mdm_ick",
1424         .parent         = &core_ck,
1425         .prcm_mod       = OMAP2430_MDM_MOD,
1426         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1427         .clkdm          = { .name = "mdm_clkdm" },
1428         .enable_reg     = CM_ICLKEN,
1429         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1430         .clksel_reg     = CM_CLKSEL,
1431         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1432         .clksel         = mdm_ick_clksel,
1433         .recalc         = &omap2_clksel_recalc,
1434         .round_rate     = &omap2_clksel_round_rate,
1435         .set_rate       = &omap2_clksel_set_rate
1436 };
1437
1438 static struct clk mdm_osc_ck = {
1439         .name           = "mdm_osc_ck",
1440         .parent         = &osc_ck,
1441         .prcm_mod       = OMAP2430_MDM_MOD,
1442         .flags          = CLOCK_IN_OMAP243X,
1443         .clkdm          = { .name = "mdm_clkdm" },
1444         .enable_reg     = CM_FCLKEN,
1445         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1446         .recalc         = &followparent_recalc,
1447 };
1448
1449 /*
1450  * DSS clock domain
1451  * CLOCKs:
1452  * DSS_L4_ICLK, DSS_L3_ICLK,
1453  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1454  *
1455  * DSS is both initiator and target.
1456  */
1457 /* XXX Add RATE_NOT_VALIDATED */
1458
1459 static const struct clksel_rate dss1_fck_sys_rates[] = {
1460         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1461         { .div = 0 }
1462 };
1463
1464 static const struct clksel_rate dss1_fck_core_rates[] = {
1465         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1466         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1467         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1468         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1469         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1470         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1471         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1472         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1473         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1474         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1475         { .div = 0 }
1476 };
1477
1478 static const struct clksel dss1_fck_clksel[] = {
1479         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1480         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1481         { .parent = NULL },
1482 };
1483
1484 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1485         .name           = "dss_ick",
1486         .parent         = &l4_ck,       /* really both l3 and l4 */
1487         .prcm_mod       = CORE_MOD,
1488         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1489         .clkdm          = { .name = "dss_clkdm" },
1490         .enable_reg     = CM_ICLKEN1,
1491         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1492         .recalc         = &followparent_recalc,
1493 };
1494
1495 static struct clk dss1_fck = {
1496         .name           = "dss1_fck",
1497         .parent         = &core_ck,             /* Core or sys */
1498         .prcm_mod       = CORE_MOD,
1499         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1500                                 DELAYED_APP,
1501         .clkdm          = { .name = "dss_clkdm" },
1502         .enable_reg     = CM_FCLKEN1,
1503         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1504         .init           = &omap2_init_clksel_parent,
1505         .clksel_reg     = CM_CLKSEL1,
1506         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1507         .clksel         = dss1_fck_clksel,
1508         .recalc         = &omap2_clksel_recalc,
1509         .round_rate     = &omap2_clksel_round_rate,
1510         .set_rate       = &omap2_clksel_set_rate
1511 };
1512
1513 static const struct clksel_rate dss2_fck_sys_rates[] = {
1514         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1515         { .div = 0 }
1516 };
1517
1518 static const struct clksel_rate dss2_fck_48m_rates[] = {
1519         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1520         { .div = 0 }
1521 };
1522
1523 static const struct clksel dss2_fck_clksel[] = {
1524         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1525         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1526         { .parent = NULL }
1527 };
1528
1529 static struct clk dss2_fck = {          /* Alt clk used in power management */
1530         .name           = "dss2_fck",
1531         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1532         .prcm_mod       = CORE_MOD,
1533         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1534                                 DELAYED_APP,
1535         .clkdm          = { .name = "dss_clkdm" },
1536         .enable_reg     = CM_FCLKEN1,
1537         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1538         .init           = &omap2_init_clksel_parent,
1539         .clksel_reg     = CM_CLKSEL1,
1540         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1541         .clksel         = dss2_fck_clksel,
1542         .recalc         = &followparent_recalc,
1543 };
1544
1545 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1546         .name           = "dss_54m_fck",        /* 54m tv clk */
1547         .parent         = &func_54m_ck,
1548         .prcm_mod       = CORE_MOD,
1549         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1550         .clkdm          = { .name = "dss_clkdm" },
1551         .enable_reg     = CM_FCLKEN1,
1552         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1553         .recalc         = &followparent_recalc,
1554 };
1555
1556 /*
1557  * CORE power domain ICLK & FCLK defines.
1558  * Many of the these can have more than one possible parent. Entries
1559  * here will likely have an L4 interface parent, and may have multiple
1560  * functional clock parents.
1561  */
1562 static const struct clksel_rate gpt_alt_rates[] = {
1563         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1564         { .div = 0 }
1565 };
1566
1567 static const struct clksel omap24xx_gpt_clksel[] = {
1568         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1569         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1570         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1571         { .parent = NULL },
1572 };
1573
1574 static struct clk gpt1_ick = {
1575         .name           = "gpt1_ick",
1576         .parent         = &l4_ck,
1577         .prcm_mod       = WKUP_MOD,
1578         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1579         .clkdm          = { .name = "core_l4_clkdm" },
1580         .enable_reg     = CM_ICLKEN,
1581         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1582         .idlest_bit     = OMAP24XX_ST_GPT1_SHIFT,
1583         .recalc         = &followparent_recalc,
1584 };
1585
1586 static struct clk gpt1_fck = {
1587         .name           = "gpt1_fck",
1588         .parent         = &func_32k_ck,
1589         .prcm_mod       = WKUP_MOD,
1590         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1591         .clkdm          = { .name = "core_l4_clkdm" },
1592         .enable_reg     = CM_FCLKEN,
1593         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1594         .init           = &omap2_init_clksel_parent,
1595         .clksel_reg     = CM_CLKSEL1,
1596         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1597         .clksel         = omap24xx_gpt_clksel,
1598         .recalc         = &omap2_clksel_recalc,
1599         .round_rate     = &omap2_clksel_round_rate,
1600         .set_rate       = &omap2_clksel_set_rate
1601 };
1602
1603 static struct clk gpt2_ick = {
1604         .name           = "gpt2_ick",
1605         .parent         = &l4_ck,
1606         .prcm_mod       = CORE_MOD,
1607         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1608         .clkdm          = { .name = "core_l4_clkdm" },
1609         .enable_reg     = CM_ICLKEN1,
1610         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1611         .idlest_bit     = OMAP24XX_ST_GPT2_SHIFT,
1612         .recalc         = &followparent_recalc,
1613 };
1614
1615 static struct clk gpt2_fck = {
1616         .name           = "gpt2_fck",
1617         .parent         = &func_32k_ck,
1618         .prcm_mod       = CORE_MOD,
1619         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1620         .clkdm          = { .name = "core_l4_clkdm" },
1621         .enable_reg     = CM_FCLKEN1,
1622         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1623         .init           = &omap2_init_clksel_parent,
1624         .clksel_reg     = CM_CLKSEL2,
1625         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1626         .clksel         = omap24xx_gpt_clksel,
1627         .recalc         = &omap2_clksel_recalc,
1628 };
1629
1630 static struct clk gpt3_ick = {
1631         .name           = "gpt3_ick",
1632         .parent         = &l4_ck,
1633         .prcm_mod       = CORE_MOD,
1634         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1635         .clkdm          = { .name = "core_l4_clkdm" },
1636         .enable_reg     = CM_ICLKEN1,
1637         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1638         .idlest_bit     = OMAP24XX_ST_GPT3_SHIFT,
1639         .recalc         = &followparent_recalc,
1640 };
1641
1642 static struct clk gpt3_fck = {
1643         .name           = "gpt3_fck",
1644         .parent         = &func_32k_ck,
1645         .prcm_mod       = CORE_MOD,
1646         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1647         .clkdm          = { .name = "core_l4_clkdm" },
1648         .enable_reg     = CM_FCLKEN1,
1649         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1650         .init           = &omap2_init_clksel_parent,
1651         .clksel_reg     = CM_CLKSEL2,
1652         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1653         .clksel         = omap24xx_gpt_clksel,
1654         .recalc         = &omap2_clksel_recalc,
1655 };
1656
1657 static struct clk gpt4_ick = {
1658         .name           = "gpt4_ick",
1659         .parent         = &l4_ck,
1660         .prcm_mod       = CORE_MOD,
1661         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1662         .clkdm          = { .name = "core_l4_clkdm" },
1663         .enable_reg     = CM_ICLKEN1,
1664         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1665         .idlest_bit     = OMAP24XX_ST_GPT4_SHIFT,
1666         .recalc         = &followparent_recalc,
1667 };
1668
1669 static struct clk gpt4_fck = {
1670         .name           = "gpt4_fck",
1671         .parent         = &func_32k_ck,
1672         .prcm_mod       = CORE_MOD,
1673         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1674         .clkdm          = { .name = "core_l4_clkdm" },
1675         .enable_reg     = CM_FCLKEN1,
1676         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1677         .init           = &omap2_init_clksel_parent,
1678         .clksel_reg     = CM_CLKSEL2,
1679         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1680         .clksel         = omap24xx_gpt_clksel,
1681         .recalc         = &omap2_clksel_recalc,
1682 };
1683
1684 static struct clk gpt5_ick = {
1685         .name           = "gpt5_ick",
1686         .parent         = &l4_ck,
1687         .prcm_mod       = CORE_MOD,
1688         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1689         .clkdm          = { .name = "core_l4_clkdm" },
1690         .enable_reg     = CM_ICLKEN1,
1691         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1692         .idlest_bit     = OMAP24XX_ST_GPT5_SHIFT,
1693         .recalc         = &followparent_recalc,
1694 };
1695
1696 static struct clk gpt5_fck = {
1697         .name           = "gpt5_fck",
1698         .parent         = &func_32k_ck,
1699         .prcm_mod       = CORE_MOD,
1700         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1701         .clkdm          = { .name = "core_l4_clkdm" },
1702         .enable_reg     = CM_FCLKEN1,
1703         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1704         .init           = &omap2_init_clksel_parent,
1705         .clksel_reg     = CM_CLKSEL2,
1706         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1707         .clksel         = omap24xx_gpt_clksel,
1708         .recalc         = &omap2_clksel_recalc,
1709 };
1710
1711 static struct clk gpt6_ick = {
1712         .name           = "gpt6_ick",
1713         .parent         = &l4_ck,
1714         .prcm_mod       = CORE_MOD,
1715         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1716         .clkdm          = { .name = "core_l4_clkdm" },
1717         .enable_reg     = CM_ICLKEN1,
1718         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1719         .idlest_bit     = OMAP24XX_ST_GPT6_SHIFT,
1720         .recalc         = &followparent_recalc,
1721 };
1722
1723 static struct clk gpt6_fck = {
1724         .name           = "gpt6_fck",
1725         .parent         = &func_32k_ck,
1726         .prcm_mod       = CORE_MOD,
1727         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1728         .clkdm          = { .name = "core_l4_clkdm" },
1729         .enable_reg     = CM_FCLKEN1,
1730         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1731         .init           = &omap2_init_clksel_parent,
1732         .clksel_reg     = CM_CLKSEL2,
1733         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1734         .clksel         = omap24xx_gpt_clksel,
1735         .recalc         = &omap2_clksel_recalc,
1736 };
1737
1738 static struct clk gpt7_ick = {
1739         .name           = "gpt7_ick",
1740         .parent         = &l4_ck,
1741         .prcm_mod       = CORE_MOD,
1742         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1743         .clkdm          = { .name = "core_l4_clkdm" },
1744         .enable_reg     = CM_ICLKEN1,
1745         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1746         .idlest_bit     = OMAP24XX_ST_GPT7_SHIFT,
1747         .recalc         = &followparent_recalc,
1748 };
1749
1750 static struct clk gpt7_fck = {
1751         .name           = "gpt7_fck",
1752         .parent         = &func_32k_ck,
1753         .prcm_mod       = CORE_MOD,
1754         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1755         .clkdm          = { .name = "core_l4_clkdm" },
1756         .enable_reg     = CM_FCLKEN1,
1757         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1758         .init           = &omap2_init_clksel_parent,
1759         .clksel_reg     = CM_CLKSEL2,
1760         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1761         .clksel         = omap24xx_gpt_clksel,
1762         .recalc         = &omap2_clksel_recalc,
1763 };
1764
1765 static struct clk gpt8_ick = {
1766         .name           = "gpt8_ick",
1767         .parent         = &l4_ck,
1768         .prcm_mod       = CORE_MOD,
1769         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1770         .clkdm          = { .name = "core_l4_clkdm" },
1771         .enable_reg     = CM_ICLKEN1,
1772         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1773         .idlest_bit     = OMAP24XX_ST_GPT8_SHIFT,
1774         .recalc         = &followparent_recalc,
1775 };
1776
1777 static struct clk gpt8_fck = {
1778         .name           = "gpt8_fck",
1779         .parent         = &func_32k_ck,
1780         .prcm_mod       = CORE_MOD,
1781         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1782         .clkdm          = { .name = "core_l4_clkdm" },
1783         .enable_reg     = CM_FCLKEN1,
1784         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1785         .init           = &omap2_init_clksel_parent,
1786         .clksel_reg     = CM_CLKSEL2,
1787         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1788         .clksel         = omap24xx_gpt_clksel,
1789         .recalc         = &omap2_clksel_recalc,
1790 };
1791
1792 static struct clk gpt9_ick = {
1793         .name           = "gpt9_ick",
1794         .parent         = &l4_ck,
1795         .prcm_mod       = CORE_MOD,
1796         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1797         .clkdm          = { .name = "core_l4_clkdm" },
1798         .enable_reg     = CM_ICLKEN1,
1799         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1800         .idlest_bit     = OMAP24XX_ST_GPT9_SHIFT,
1801         .recalc         = &followparent_recalc,
1802 };
1803
1804 static struct clk gpt9_fck = {
1805         .name           = "gpt9_fck",
1806         .parent         = &func_32k_ck,
1807         .prcm_mod       = CORE_MOD,
1808         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1809         .clkdm          = { .name = "core_l4_clkdm" },
1810         .enable_reg     = CM_FCLKEN1,
1811         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1812         .init           = &omap2_init_clksel_parent,
1813         .clksel_reg     = CM_CLKSEL2,
1814         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1815         .clksel         = omap24xx_gpt_clksel,
1816         .recalc         = &omap2_clksel_recalc,
1817 };
1818
1819 static struct clk gpt10_ick = {
1820         .name           = "gpt10_ick",
1821         .parent         = &l4_ck,
1822         .prcm_mod       = CORE_MOD,
1823         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1824         .clkdm          = { .name = "core_l4_clkdm" },
1825         .enable_reg     = CM_ICLKEN1,
1826         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1827         .idlest_bit     = OMAP24XX_ST_GPT10_SHIFT,
1828         .recalc         = &followparent_recalc,
1829 };
1830
1831 static struct clk gpt10_fck = {
1832         .name           = "gpt10_fck",
1833         .parent         = &func_32k_ck,
1834         .prcm_mod       = CORE_MOD,
1835         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1836         .clkdm          = { .name = "core_l4_clkdm" },
1837         .enable_reg     = CM_FCLKEN1,
1838         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1839         .init           = &omap2_init_clksel_parent,
1840         .clksel_reg     = CM_CLKSEL2,
1841         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1842         .clksel         = omap24xx_gpt_clksel,
1843         .recalc         = &omap2_clksel_recalc,
1844 };
1845
1846 static struct clk gpt11_ick = {
1847         .name           = "gpt11_ick",
1848         .parent         = &l4_ck,
1849         .prcm_mod       = CORE_MOD,
1850         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1851         .clkdm          = { .name = "core_l4_clkdm" },
1852         .enable_reg     = CM_ICLKEN1,
1853         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1854         .idlest_bit     = OMAP24XX_ST_GPT11_SHIFT,
1855         .recalc         = &followparent_recalc,
1856 };
1857
1858 static struct clk gpt11_fck = {
1859         .name           = "gpt11_fck",
1860         .parent         = &func_32k_ck,
1861         .prcm_mod       = CORE_MOD,
1862         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1863         .clkdm          = { .name = "core_l4_clkdm" },
1864         .enable_reg     = CM_FCLKEN1,
1865         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1866         .init           = &omap2_init_clksel_parent,
1867         .clksel_reg     = CM_CLKSEL2,
1868         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1869         .clksel         = omap24xx_gpt_clksel,
1870         .recalc         = &omap2_clksel_recalc,
1871 };
1872
1873 static struct clk gpt12_ick = {
1874         .name           = "gpt12_ick",
1875         .parent         = &l4_ck,
1876         .prcm_mod       = CORE_MOD,
1877         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1878         .clkdm          = { .name = "core_l4_clkdm" },
1879         .enable_reg     = CM_ICLKEN1,
1880         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1881         .idlest_bit     = OMAP24XX_ST_GPT12_SHIFT,
1882         .recalc         = &followparent_recalc,
1883 };
1884
1885 static struct clk gpt12_fck = {
1886         .name           = "gpt12_fck",
1887         .parent         = &func_32k_ck,
1888         .prcm_mod       = CORE_MOD,
1889         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1890         .clkdm          = { .name = "core_l4_clkdm" },
1891         .enable_reg     = CM_FCLKEN1,
1892         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1893         .init           = &omap2_init_clksel_parent,
1894         .clksel_reg     = CM_CLKSEL2,
1895         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1896         .clksel         = omap24xx_gpt_clksel,
1897         .recalc         = &omap2_clksel_recalc,
1898 };
1899
1900 static struct clk mcbsp1_ick = {
1901         .name           = "mcbsp_ick",
1902         .id             = 1,
1903         .parent         = &l4_ck,
1904         .prcm_mod       = CORE_MOD,
1905         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1906         .clkdm          = { .name = "core_l4_clkdm" },
1907         .enable_reg     = CM_ICLKEN1,
1908         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1909         .idlest_bit     = OMAP24XX_ST_MCBSP1_SHIFT,
1910         .recalc         = &followparent_recalc,
1911 };
1912
1913 static struct clk mcbsp1_fck = {
1914         .name           = "mcbsp_fck",
1915         .id             = 1,
1916         .parent         = &func_96m_ck,
1917         .prcm_mod       = CORE_MOD,
1918         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1919         .clkdm          = { .name = "core_l4_clkdm" },
1920         .enable_reg     = CM_FCLKEN1,
1921         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1922         .recalc         = &followparent_recalc,
1923 };
1924
1925 static struct clk mcbsp2_ick = {
1926         .name           = "mcbsp_ick",
1927         .id             = 2,
1928         .parent         = &l4_ck,
1929         .prcm_mod       = CORE_MOD,
1930         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1931         .clkdm          = { .name = "core_l4_clkdm" },
1932         .enable_reg     = CM_ICLKEN1,
1933         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1934         .idlest_bit     = OMAP24XX_ST_MCBSP2_SHIFT,
1935         .recalc         = &followparent_recalc,
1936 };
1937
1938 static struct clk mcbsp2_fck = {
1939         .name           = "mcbsp_fck",
1940         .id             = 2,
1941         .parent         = &func_96m_ck,
1942         .prcm_mod       = CORE_MOD,
1943         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1944         .clkdm          = { .name = "core_l4_clkdm" },
1945         .enable_reg     = CM_FCLKEN1,
1946         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1947         .recalc         = &followparent_recalc,
1948 };
1949
1950 static struct clk mcbsp3_ick = {
1951         .name           = "mcbsp_ick",
1952         .id             = 3,
1953         .parent         = &l4_ck,
1954         .prcm_mod       = CORE_MOD,
1955         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
1956         .clkdm          = { .name = "core_l4_clkdm" },
1957         .enable_reg     = CM_ICLKEN2,
1958         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1959         .idlest_bit     = OMAP2430_ST_MCBSP3_SHIFT,
1960         .recalc         = &followparent_recalc,
1961 };
1962
1963 static struct clk mcbsp3_fck = {
1964         .name           = "mcbsp_fck",
1965         .id             = 3,
1966         .parent         = &func_96m_ck,
1967         .prcm_mod       = CORE_MOD,
1968         .flags          = CLOCK_IN_OMAP243X,
1969         .clkdm          = { .name = "core_l4_clkdm" },
1970         .enable_reg     = OMAP24XX_CM_FCLKEN2,
1971         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1972         .recalc         = &followparent_recalc,
1973 };
1974
1975 static struct clk mcbsp4_ick = {
1976         .name           = "mcbsp_ick",
1977         .id             = 4,
1978         .parent         = &l4_ck,
1979         .prcm_mod       = CORE_MOD,
1980         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
1981         .clkdm          = { .name = "core_l4_clkdm" },
1982         .enable_reg     = CM_ICLKEN2,
1983         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1984         .idlest_bit     = OMAP2430_ST_MCBSP4_SHIFT,
1985         .recalc         = &followparent_recalc,
1986 };
1987
1988 static struct clk mcbsp4_fck = {
1989         .name           = "mcbsp_fck",
1990         .id             = 4,
1991         .parent         = &func_96m_ck,
1992         .prcm_mod       = CORE_MOD,
1993         .flags          = CLOCK_IN_OMAP243X,
1994         .clkdm          = { .name = "core_l4_clkdm" },
1995         .enable_reg     = OMAP24XX_CM_FCLKEN2,
1996         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1997         .recalc         = &followparent_recalc,
1998 };
1999
2000 static struct clk mcbsp5_ick = {
2001         .name           = "mcbsp_ick",
2002         .id             = 5,
2003         .parent         = &l4_ck,
2004         .prcm_mod       = CORE_MOD,
2005         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2006         .clkdm          = { .name = "core_l4_clkdm" },
2007         .enable_reg     = CM_ICLKEN2,
2008         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
2009         .idlest_bit     = OMAP2430_ST_MCBSP5_SHIFT,
2010         .recalc         = &followparent_recalc,
2011 };
2012
2013 static struct clk mcbsp5_fck = {
2014         .name           = "mcbsp_fck",
2015         .id             = 5,
2016         .parent         = &func_96m_ck,
2017         .prcm_mod       = CORE_MOD,
2018         .flags          = CLOCK_IN_OMAP243X,
2019         .clkdm          = { .name = "core_l4_clkdm" },
2020         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2021         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
2022         .recalc         = &followparent_recalc,
2023 };
2024
2025 static struct clk mcspi1_ick = {
2026         .name           = "mcspi_ick",
2027         .id             = 1,
2028         .parent         = &l4_ck,
2029         .prcm_mod       = CORE_MOD,
2030         .clkdm          = { .name = "core_l4_clkdm" },
2031         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2032         .enable_reg     = CM_ICLKEN1,
2033         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
2034         .idlest_bit     = OMAP24XX_ST_MCSPI1_SHIFT,
2035         .recalc         = &followparent_recalc,
2036 };
2037
2038 static struct clk mcspi1_fck = {
2039         .name           = "mcspi_fck",
2040         .id             = 1,
2041         .parent         = &func_48m_ck,
2042         .prcm_mod       = CORE_MOD,
2043         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2044         .clkdm          = { .name = "core_l4_clkdm" },
2045         .enable_reg     = CM_FCLKEN1,
2046         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
2047         .recalc         = &followparent_recalc,
2048 };
2049
2050 static struct clk mcspi2_ick = {
2051         .name           = "mcspi_ick",
2052         .id             = 2,
2053         .parent         = &l4_ck,
2054         .prcm_mod       = CORE_MOD,
2055         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2056         .clkdm          = { .name = "core_l4_clkdm" },
2057         .enable_reg     = CM_ICLKEN1,
2058         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
2059         .idlest_bit     = OMAP24XX_ST_MCSPI2_SHIFT,
2060         .recalc         = &followparent_recalc,
2061 };
2062
2063 static struct clk mcspi2_fck = {
2064         .name           = "mcspi_fck",
2065         .id             = 2,
2066         .parent         = &func_48m_ck,
2067         .prcm_mod       = CORE_MOD,
2068         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2069         .clkdm          = { .name = "core_l4_clkdm" },
2070         .enable_reg     = CM_FCLKEN1,
2071         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
2072         .recalc         = &followparent_recalc,
2073 };
2074
2075 static struct clk mcspi3_ick = {
2076         .name           = "mcspi_ick",
2077         .id             = 3,
2078         .parent         = &l4_ck,
2079         .prcm_mod       = CORE_MOD,
2080         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2081         .clkdm          = { .name = "core_l4_clkdm" },
2082         .enable_reg     = CM_ICLKEN2,
2083         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2084         .idlest_bit     = OMAP2430_ST_MCSPI3_SHIFT,
2085         .recalc         = &followparent_recalc,
2086 };
2087
2088 static struct clk mcspi3_fck = {
2089         .name           = "mcspi_fck",
2090         .id             = 3,
2091         .parent         = &func_48m_ck,
2092         .prcm_mod       = CORE_MOD,
2093         .flags          = CLOCK_IN_OMAP243X,
2094         .clkdm          = { .name = "core_l4_clkdm" },
2095         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2096         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2097         .recalc         = &followparent_recalc,
2098 };
2099
2100 static struct clk uart1_ick = {
2101         .name           = "uart1_ick",
2102         .parent         = &l4_ck,
2103         .prcm_mod       = CORE_MOD,
2104         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2105         .clkdm          = { .name = "core_l4_clkdm" },
2106         .enable_reg     = CM_ICLKEN1,
2107         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2108         .idlest_bit     = OMAP24XX_ST_UART1_SHIFT,
2109         .recalc         = &followparent_recalc,
2110 };
2111
2112 static struct clk uart1_fck = {
2113         .name           = "uart1_fck",
2114         .parent         = &func_48m_ck,
2115         .prcm_mod       = CORE_MOD,
2116         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2117         .clkdm          = { .name = "core_l4_clkdm" },
2118         .enable_reg     = CM_FCLKEN1,
2119         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2120         .recalc         = &followparent_recalc,
2121 };
2122
2123 static struct clk uart2_ick = {
2124         .name           = "uart2_ick",
2125         .parent         = &l4_ck,
2126         .prcm_mod       = CORE_MOD,
2127         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2128         .clkdm          = { .name = "core_l4_clkdm" },
2129         .enable_reg     = CM_ICLKEN1,
2130         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2131         .idlest_bit     = OMAP24XX_ST_UART2_SHIFT,
2132         .recalc         = &followparent_recalc,
2133 };
2134
2135 static struct clk uart2_fck = {
2136         .name           = "uart2_fck",
2137         .parent         = &func_48m_ck,
2138         .prcm_mod       = CORE_MOD,
2139         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2140         .clkdm          = { .name = "core_l4_clkdm" },
2141         .enable_reg     = CM_FCLKEN1,
2142         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2143         .recalc         = &followparent_recalc,
2144 };
2145
2146 static struct clk uart3_ick = {
2147         .name           = "uart3_ick",
2148         .parent         = &l4_ck,
2149         .prcm_mod       = CORE_MOD,
2150         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2151         .clkdm          = { .name = "core_l4_clkdm" },
2152         .enable_reg     = CM_ICLKEN2,
2153         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2154         .idlest_bit     = OMAP24XX_ST_UART3_SHIFT,
2155         .recalc         = &followparent_recalc,
2156 };
2157
2158 static struct clk uart3_fck = {
2159         .name           = "uart3_fck",
2160         .parent         = &func_48m_ck,
2161         .prcm_mod       = CORE_MOD,
2162         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2163         .clkdm          = { .name = "core_l4_clkdm" },
2164         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2165         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2166         .recalc         = &followparent_recalc,
2167 };
2168
2169 static struct clk gpios_ick = {
2170         .name           = "gpios_ick",
2171         .parent         = &l4_ck,
2172         .prcm_mod       = WKUP_MOD,
2173         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2174         .clkdm          = { .name = "core_l4_clkdm" },
2175         .enable_reg     = CM_ICLKEN,
2176         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2177         .idlest_bit     = OMAP24XX_ST_GPIOS_SHIFT,
2178         .recalc         = &followparent_recalc,
2179 };
2180
2181 static struct clk gpios_fck = {
2182         .name           = "gpios_fck",
2183         .parent         = &func_32k_ck,
2184         .prcm_mod       = WKUP_MOD,
2185         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2186         .clkdm          = { .name = "prm_clkdm" },
2187         .enable_reg     = CM_FCLKEN,
2188         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2189         .idlest_bit     = OMAP24XX_ST_GPIOS_SHIFT,
2190         .recalc         = &followparent_recalc,
2191 };
2192
2193 /* aka WDT2 - REVISIT: we should split wu_l4_iclk from l4_ck */
2194 static struct clk mpu_wdt_ick = {
2195         .name           = "mpu_wdt_ick",
2196         .parent         = &l4_ck,
2197         .prcm_mod       = WKUP_MOD,
2198         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2199         .clkdm          = { .name = "prm_clkdm" },
2200         .enable_reg     = CM_ICLKEN,
2201         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2202         .idlest_bit     = OMAP24XX_ST_MPU_WDT_SHIFT,
2203         .recalc         = &followparent_recalc,
2204 };
2205
2206 /* aka WDT2 */
2207 static struct clk mpu_wdt_fck = {
2208         .name           = "mpu_wdt_fck",
2209         .parent         = &func_32k_ck,
2210         .prcm_mod       = WKUP_MOD,
2211         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2212         .clkdm          = { .name = "prm_clkdm" },
2213         .enable_reg     = CM_FCLKEN,
2214         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2215         .idlest_bit     = OMAP24XX_ST_MPU_WDT_SHIFT,
2216         .recalc         = &followparent_recalc,
2217 };
2218
2219 static struct clk sync_32k_ick = {
2220         .name           = "sync_32k_ick",
2221         .parent         = &l4_ck,
2222         .prcm_mod       = WKUP_MOD,
2223         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2224                                 ENABLE_ON_INIT | WAIT_READY,
2225         .clkdm          = { .name = "core_l4_clkdm" },
2226         .enable_reg     = CM_ICLKEN,
2227         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2228         .idlest_bit     = OMAP24XX_ST_32KSYNC_SHIFT,
2229         .recalc         = &followparent_recalc,
2230 };
2231
2232 /* REVISIT: parent is really wu_l4_iclk */
2233 static struct clk wdt1_ick = {
2234         .name           = "wdt1_ick",
2235         .parent         = &l4_ck,
2236         .prcm_mod       = WKUP_MOD,
2237         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2238         .clkdm          = { .name = "prm_clkdm" },
2239         .enable_reg     = CM_ICLKEN,
2240         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2241         .idlest_bit     = OMAP24XX_ST_WDT1_SHIFT,
2242         .recalc         = &followparent_recalc,
2243 };
2244
2245 static struct clk omapctrl_ick = {
2246         .name           = "omapctrl_ick",
2247         .parent         = &l4_ck,
2248         .prcm_mod       = WKUP_MOD,
2249         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2250                                 ENABLE_ON_INIT,
2251         .clkdm          = { .name = "core_l4_clkdm" },
2252         .enable_reg     = CM_ICLKEN,
2253         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2254         .idlest_bit     = OMAP24XX_ST_OMAPCTRL_SHIFT,
2255         .recalc         = &followparent_recalc,
2256 };
2257
2258 static struct clk icr_ick = {
2259         .name           = "icr_ick",
2260         .parent         = &l4_ck,
2261         .prcm_mod       = WKUP_MOD,
2262         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2263         .clkdm          = { .name = "core_l4_clkdm" },
2264         .enable_reg     = CM_ICLKEN,
2265         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2266         .idlest_bit     = OMAP2430_ST_ICR_SHIFT,
2267         .recalc         = &followparent_recalc,
2268 };
2269
2270 static struct clk cam_ick = {
2271         .name           = "cam_ick",
2272         .parent         = &l4_ck,
2273         .prcm_mod       = CORE_MOD,
2274         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2275         .clkdm          = { .name = "core_l4_clkdm" },
2276         .enable_reg     = CM_ICLKEN1,
2277         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2278         .recalc         = &followparent_recalc,
2279 };
2280
2281 /*
2282  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
2283  * split into two separate clocks, since the parent clocks are different
2284  * and the clockdomains are also different.
2285  */
2286 static struct clk cam_fck = {
2287         .name           = "cam_fck",
2288         .parent         = &func_96m_ck,
2289         .prcm_mod       = CORE_MOD,
2290         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2291         .clkdm          = { .name = "core_l3_clkdm" },
2292         .enable_reg     = CM_FCLKEN1,
2293         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2294         .recalc         = &followparent_recalc,
2295 };
2296
2297 static struct clk mailboxes_ick = {
2298         .name           = "mailboxes_ick",
2299         .parent         = &l4_ck,
2300         .prcm_mod       = CORE_MOD,
2301         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2302         .clkdm          = { .name = "core_l4_clkdm" },
2303         .enable_reg     = CM_ICLKEN1,
2304         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2305         .idlest_bit     = OMAP24XX_ST_MAILBOXES_SHIFT,
2306         .recalc         = &followparent_recalc,
2307 };
2308
2309 static struct clk wdt4_ick = {
2310         .name           = "wdt4_ick",
2311         .parent         = &l4_ck,
2312         .prcm_mod       = CORE_MOD,
2313         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2314         .clkdm          = { .name = "core_l4_clkdm" },
2315         .enable_reg     = CM_ICLKEN1,
2316         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2317         .idlest_bit     = OMAP24XX_ST_WDT4_SHIFT,
2318         .recalc         = &followparent_recalc,
2319 };
2320
2321 static struct clk wdt4_fck = {
2322         .name           = "wdt4_fck",
2323         .parent         = &func_32k_ck,
2324         .prcm_mod       = CORE_MOD,
2325         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2326         .clkdm          = { .name = "core_l4_clkdm" },
2327         .enable_reg     = CM_FCLKEN1,
2328         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2329         .recalc         = &followparent_recalc,
2330 };
2331
2332 static struct clk wdt3_ick = {
2333         .name           = "wdt3_ick",
2334         .parent         = &l4_ck,
2335         .prcm_mod       = CORE_MOD,
2336         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2337         .clkdm          = { .name = "core_l4_clkdm" },
2338         .enable_reg     = CM_ICLKEN1,
2339         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2340         .idlest_bit     = OMAP2420_ST_WDT3_SHIFT,
2341         .recalc         = &followparent_recalc,
2342 };
2343
2344 static struct clk wdt3_fck = {
2345         .name           = "wdt3_fck",
2346         .parent         = &func_32k_ck,
2347         .prcm_mod       = CORE_MOD,
2348         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2349         .clkdm          = { .name = "core_l4_clkdm" },
2350         .enable_reg     = CM_FCLKEN1,
2351         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2352         .enable_bit     = OMAP2420_ST_WDT3_SHIFT,
2353         .recalc         = &followparent_recalc,
2354 };
2355
2356 static struct clk mspro_ick = {
2357         .name           = "mspro_ick",
2358         .parent         = &l4_ck,
2359         .prcm_mod       = CORE_MOD,
2360         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2361         .clkdm          = { .name = "core_l4_clkdm" },
2362         .enable_reg     = CM_ICLKEN1,
2363         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2364         .idlest_bit     = OMAP24XX_ST_MSPRO_SHIFT,
2365         .recalc         = &followparent_recalc,
2366 };
2367
2368 static struct clk mspro_fck = {
2369         .name           = "mspro_fck",
2370         .parent         = &func_96m_ck,
2371         .prcm_mod       = CORE_MOD,
2372         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2373         .clkdm          = { .name = "core_l4_clkdm" },
2374         .enable_reg     = CM_FCLKEN1,
2375         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2376         .idlest_bit     = OMAP24XX_ST_MSPRO_SHIFT,
2377         .recalc         = &followparent_recalc,
2378 };
2379
2380 static struct clk mmc_ick = {
2381         .name           = "mmc_ick",
2382         .parent         = &l4_ck,
2383         .prcm_mod       = CORE_MOD,
2384         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2385         .clkdm          = { .name = "core_l4_clkdm" },
2386         .enable_reg     = CM_ICLKEN1,
2387         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2388         .idlest_bit     = OMAP2420_ST_MMC_SHIFT,
2389         .recalc         = &followparent_recalc,
2390 };
2391
2392 static struct clk mmc_fck = {
2393         .name           = "mmc_fck",
2394         .parent         = &func_96m_ck,
2395         .prcm_mod       = CORE_MOD,
2396         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2397         .clkdm          = { .name = "core_l4_clkdm" },
2398         .enable_reg     = CM_FCLKEN1,
2399         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2400         .idlest_bit     = OMAP2420_ST_MMC_SHIFT,
2401         .recalc         = &followparent_recalc,
2402 };
2403
2404 static struct clk fac_ick = {
2405         .name           = "fac_ick",
2406         .parent         = &l4_ck,
2407         .prcm_mod       = CORE_MOD,
2408         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2409         .clkdm          = { .name = "core_l4_clkdm" },
2410         .enable_reg     = CM_ICLKEN1,
2411         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2412         .idlest_bit     = OMAP24XX_ST_FAC_SHIFT,
2413         .recalc         = &followparent_recalc,
2414 };
2415
2416 static struct clk fac_fck = {
2417         .name           = "fac_fck",
2418         .parent         = &func_12m_ck,
2419         .prcm_mod       = CORE_MOD,
2420         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2421         .clkdm          = { .name = "core_l4_clkdm" },
2422         .enable_reg     = CM_FCLKEN1,
2423         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2424         .idlest_bit     = OMAP24XX_ST_FAC_SHIFT,
2425         .recalc         = &followparent_recalc,
2426 };
2427
2428 static struct clk eac_ick = {
2429         .name           = "eac_ick",
2430         .parent         = &l4_ck,
2431         .prcm_mod       = CORE_MOD,
2432         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2433         .clkdm          = { .name = "core_l4_clkdm" },
2434         .enable_reg     = CM_ICLKEN1,
2435         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2436         .idlest_bit     = OMAP2420_ST_EAC_SHIFT,
2437         .recalc         = &followparent_recalc,
2438 };
2439
2440 static struct clk eac_fck = {
2441         .name           = "eac_fck",
2442         .parent         = &func_96m_ck,
2443         .prcm_mod       = CORE_MOD,
2444         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2445         .clkdm          = { .name = "core_l4_clkdm" },
2446         .enable_reg     = CM_FCLKEN1,
2447         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2448         .idlest_bit     = OMAP2420_ST_EAC_SHIFT,
2449         .recalc         = &followparent_recalc,
2450 };
2451
2452 static struct clk hdq_ick = {
2453         .name           = "hdq_ick",
2454         .parent         = &l4_ck,
2455         .prcm_mod       = CORE_MOD,
2456         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2457         .clkdm          = { .name = "core_l4_clkdm" },
2458         .enable_reg     = CM_ICLKEN1,
2459         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2460         .idlest_bit     = OMAP24XX_ST_HDQ_SHIFT,
2461         .recalc         = &followparent_recalc,
2462 };
2463
2464 static struct clk hdq_fck = {
2465         .name           = "hdq_fck",
2466         .parent         = &func_12m_ck,
2467         .prcm_mod       = CORE_MOD,
2468         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2469         .clkdm          = { .name = "core_l4_clkdm" },
2470         .enable_reg     = CM_FCLKEN1,
2471         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2472         .idlest_bit     = OMAP24XX_ST_HDQ_SHIFT,
2473         .recalc         = &followparent_recalc,
2474 };
2475
2476 static struct clk i2c2_ick = {
2477         .name           = "i2c_ick",
2478         .id             = 2,
2479         .parent         = &l4_ck,
2480         .prcm_mod       = CORE_MOD,
2481         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2482         .clkdm          = { .name = "core_l4_clkdm" },
2483         .enable_reg     = CM_ICLKEN1,
2484         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2485         .idlest_bit     = OMAP2420_ST_I2C2_SHIFT,
2486         .recalc         = &followparent_recalc,
2487 };
2488
2489 static struct clk i2c2_fck = {
2490         .name           = "i2c_fck",
2491         .id             = 2,
2492         .parent         = &func_12m_ck,
2493         .prcm_mod       = CORE_MOD,
2494         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2495         .clkdm          = { .name = "core_l4_clkdm" },
2496         .enable_reg     = CM_FCLKEN1,
2497         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2498         .idlest_bit     = OMAP2420_ST_I2C2_SHIFT,
2499         .recalc         = &followparent_recalc,
2500 };
2501
2502 static struct clk i2chs2_fck = {
2503         .name           = "i2chs_fck",
2504         .id             = 2,
2505         .parent         = &func_96m_ck,
2506         .prcm_mod       = CORE_MOD,
2507         .flags          = CLOCK_IN_OMAP243X,
2508         .clkdm          = { .name = "core_l4_clkdm" },
2509         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2510         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2511         .recalc         = &followparent_recalc,
2512 };
2513
2514 static struct clk i2c1_ick = {
2515         .name           = "i2c_ick",
2516         .id             = 1,
2517         .parent         = &l4_ck,
2518         .prcm_mod       = CORE_MOD,
2519         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2520         .clkdm          = { .name = "core_l4_clkdm" },
2521         .enable_reg     = CM_ICLKEN1,
2522         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2523         .idlest_bit     = OMAP2420_ST_I2C1_SHIFT,
2524         .recalc         = &followparent_recalc,
2525 };
2526
2527 static struct clk i2c1_fck = {
2528         .name           = "i2c_fck",
2529         .id             = 1,
2530         .parent         = &func_12m_ck,
2531         .prcm_mod       = CORE_MOD,
2532         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2533         .clkdm          = { .name = "core_l4_clkdm" },
2534         .enable_reg     = CM_FCLKEN1,
2535         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2536         .idlest_bit     = OMAP2420_ST_I2C1_SHIFT,
2537         .recalc         = &followparent_recalc,
2538 };
2539
2540 static struct clk i2chs1_fck = {
2541         .name           = "i2chs_fck",
2542         .id             = 1,
2543         .parent         = &func_96m_ck,
2544         .prcm_mod       = CORE_MOD,
2545         .flags          = CLOCK_IN_OMAP243X,
2546         .clkdm          = { .name = "core_l4_clkdm" },
2547         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2548         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2549         .recalc         = &followparent_recalc,
2550 };
2551
2552 static struct clk gpmc_fck = {
2553         .name           = "gpmc_fck",
2554         .parent         = &core_l3_ck,
2555         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2556                                 ENABLE_ON_INIT,
2557         .clkdm          = { .name = "core_l3_clkdm" },
2558         .recalc         = &followparent_recalc,
2559 };
2560
2561 static struct clk sdma_fck = {
2562         .name           = "sdma_fck",
2563         .parent         = &core_l3_ck,
2564         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2565         .clkdm          = { .name = "core_l3_clkdm" },
2566         .recalc         = &followparent_recalc,
2567 };
2568
2569 static struct clk sdma_ick = {
2570         .name           = "sdma_ick",
2571         .parent         = &l4_ck,
2572         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2573         .clkdm          = { .name = "core_l3_clkdm" },
2574         .recalc         = &followparent_recalc,
2575 };
2576
2577 static struct clk vlynq_ick = {
2578         .name           = "vlynq_ick",
2579         .parent         = &core_l3_ck,
2580         .prcm_mod       = CORE_MOD,
2581         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2582         .clkdm          = { .name = "core_l3_clkdm" },
2583         .enable_reg     = CM_ICLKEN1,
2584         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2585         .idlest_bit     = OMAP2420_ST_VLYNQ_SHIFT,
2586         .recalc         = &followparent_recalc,
2587 };
2588
2589 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2590         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2591         { .div = 0 }
2592 };
2593
2594 static const struct clksel_rate vlynq_fck_core_rates[] = {
2595         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2596         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2597         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2598         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2599         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2600         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2601         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2602         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2603         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2604         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2605         { .div = 0 }
2606 };
2607
2608 static const struct clksel vlynq_fck_clksel[] = {
2609         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2610         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2611         { .parent = NULL }
2612 };
2613
2614 static struct clk vlynq_fck = {
2615         .name           = "vlynq_fck",
2616         .parent         = &func_96m_ck,
2617         .prcm_mod       = CORE_MOD,
2618         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | WAIT_READY,
2619         .clkdm          = { .name = "core_l3_clkdm" },
2620         .enable_reg     = CM_FCLKEN1,
2621         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2622         .idlest_bit     = OMAP2420_ST_VLYNQ_SHIFT,
2623         .init           = &omap2_init_clksel_parent,
2624         .clksel_reg     = CM_CLKSEL1,
2625         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2626         .clksel         = vlynq_fck_clksel,
2627         .recalc         = &omap2_clksel_recalc,
2628         .round_rate     = &omap2_clksel_round_rate,
2629         .set_rate       = &omap2_clksel_set_rate
2630 };
2631
2632 static struct clk sdrc_ick = {
2633         .name           = "sdrc_ick",
2634         .parent         = &l4_ck,
2635         .prcm_mod       = CORE_MOD,
2636         .flags          = CLOCK_IN_OMAP243X | WAIT_READY | ENABLE_ON_INIT,
2637         .clkdm          = { .name = "core_l4_clkdm" },
2638         .enable_reg     = CM_ICLKEN3,
2639         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2640         .idlest_bit     = OMAP2430_ST_SDRC_SHIFT,
2641         .recalc         = &followparent_recalc,
2642 };
2643
2644 static struct clk des_ick = {
2645         .name           = "des_ick",
2646         .parent         = &l4_ck,
2647         .prcm_mod       = CORE_MOD,
2648         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2649         .clkdm          = { .name = "core_l4_clkdm" },
2650         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2651         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2652         .idlest_bit     = OMAP24XX_ST_DES_SHIFT,
2653         .recalc         = &followparent_recalc,
2654 };
2655
2656 static struct clk sha_ick = {
2657         .name           = "sha_ick",
2658         .parent         = &l4_ck,
2659         .prcm_mod       = CORE_MOD,
2660         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2661         .clkdm          = { .name = "core_l4_clkdm" },
2662         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2663         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2664         .idlest_bit     = OMAP24XX_ST_SHA_SHIFT,
2665         .recalc         = &followparent_recalc,
2666 };
2667
2668 static struct clk rng_ick = {
2669         .name           = "rng_ick",
2670         .parent         = &l4_ck,
2671         .prcm_mod       = CORE_MOD,
2672         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2673         .clkdm          = { .name = "core_l4_clkdm" },
2674         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2675         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2676         .idlest_bit     = OMAP24XX_ST_RNG_SHIFT,
2677         .recalc         = &followparent_recalc,
2678 };
2679
2680 static struct clk aes_ick = {
2681         .name           = "aes_ick",
2682         .parent         = &l4_ck,
2683         .prcm_mod       = CORE_MOD,
2684         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2685         .clkdm          = { .name = "core_l4_clkdm" },
2686         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2687         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2688         .idlest_bit     = OMAP24XX_ST_AES_SHIFT,
2689         .recalc         = &followparent_recalc,
2690 };
2691
2692 static struct clk pka_ick = {
2693         .name           = "pka_ick",
2694         .parent         = &l4_ck,
2695         .prcm_mod       = CORE_MOD,
2696         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2697         .clkdm          = { .name = "core_l4_clkdm" },
2698         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2699         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2700         .idlest_bit     = OMAP24XX_ST_PKA_SHIFT,
2701         .recalc         = &followparent_recalc,
2702 };
2703
2704 static struct clk usb_fck = {
2705         .name           = "usb_fck",
2706         .parent         = &func_48m_ck,
2707         .prcm_mod       = CORE_MOD,
2708         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2709         .clkdm          = { .name = "core_l3_clkdm" },
2710         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2711         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2712         .idlest_bit     = OMAP24XX_ST_USB_SHIFT,
2713         .recalc         = &followparent_recalc,
2714 };
2715
2716 static struct clk usbhs_ick = {
2717         .name           = "usbhs_ick",
2718         .parent         = &core_l3_ck,
2719         .prcm_mod       = CORE_MOD,
2720         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2721         .clkdm          = { .name = "core_l3_clkdm" },
2722         .enable_reg     = CM_ICLKEN2,
2723         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2724         .idlest_bit     = OMAP2430_ST_USBHS_SHIFT,
2725         .recalc         = &followparent_recalc,
2726 };
2727
2728 static struct clk mmchs1_ick = {
2729         .name           = "mmchs_ick",
2730         .parent         = &l4_ck,
2731         .prcm_mod       = CORE_MOD,
2732         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2733         .clkdm          = { .name = "core_l4_clkdm" },
2734         .enable_reg     = CM_ICLKEN2,
2735         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2736         .idlest_bit     = OMAP2430_ST_MMCHS1_SHIFT,
2737         .recalc         = &followparent_recalc,
2738 };
2739
2740 static struct clk mmchs1_fck = {
2741         .name           = "mmchs_fck",
2742         .parent         = &func_96m_ck,
2743         .prcm_mod       = CORE_MOD,
2744         .flags          = CLOCK_IN_OMAP243X,
2745         .clkdm          = { .name = "core_l3_clkdm" },
2746         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2747         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2748         .recalc         = &followparent_recalc,
2749 };
2750
2751 static struct clk mmchs2_ick = {
2752         .name           = "mmchs_ick",
2753         .id             = 1,
2754         .parent         = &l4_ck,
2755         .prcm_mod       = CORE_MOD,
2756         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2757         .clkdm          = { .name = "core_l4_clkdm" },
2758         .enable_reg     = CM_ICLKEN2,
2759         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2760         .idlest_bit     = OMAP2430_ST_MMCHS2_SHIFT,
2761         .recalc         = &followparent_recalc,
2762 };
2763
2764 static struct clk mmchs2_fck = {
2765         .name           = "mmchs_fck",
2766         .id             = 1,
2767         .parent         = &func_96m_ck,
2768         .prcm_mod       = CORE_MOD,
2769         .flags          = CLOCK_IN_OMAP243X,
2770         .clkdm          = { .name = "core_l4_clkdm" },
2771         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2772         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2773         .recalc         = &followparent_recalc,
2774 };
2775
2776 static struct clk gpio5_ick = {
2777         .name           = "gpio5_ick",
2778         .parent         = &l4_ck,
2779         .prcm_mod       = CORE_MOD,
2780         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2781         .clkdm          = { .name = "core_l4_clkdm" },
2782         .enable_reg     = CM_ICLKEN2,
2783         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2784         .idlest_bit     = OMAP2430_ST_GPIO5_SHIFT,
2785         .recalc         = &followparent_recalc,
2786 };
2787
2788 static struct clk gpio5_fck = {
2789         .name           = "gpio5_fck",
2790         .parent         = &func_32k_ck,
2791         .prcm_mod       = CORE_MOD,
2792         .flags          = CLOCK_IN_OMAP243X,
2793         .clkdm          = { .name = "core_l4_clkdm" },
2794         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2795         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2796         .recalc         = &followparent_recalc,
2797 };
2798
2799 static struct clk mdm_intc_ick = {
2800         .name           = "mdm_intc_ick",
2801         .parent         = &l4_ck,
2802         .prcm_mod       = CORE_MOD,
2803         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2804         .clkdm          = { .name = "core_l4_clkdm" },
2805         .enable_reg     = CM_ICLKEN2,
2806         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2807         .idlest_bit     = OMAP2430_ST_MDM_INTC_SHIFT,
2808         .recalc         = &followparent_recalc,
2809 };
2810
2811 static struct clk mmchsdb1_fck = {
2812         .name           = "mmchsdb_fck",
2813         .parent         = &func_32k_ck,
2814         .prcm_mod       = CORE_MOD,
2815         .flags          = CLOCK_IN_OMAP243X,
2816         .clkdm          = { .name = "core_l4_clkdm" },
2817         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2818         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2819         .recalc         = &followparent_recalc,
2820 };
2821
2822 static struct clk mmchsdb2_fck = {
2823         .name           = "mmchsdb_fck",
2824         .id             = 1,
2825         .parent         = &func_32k_ck,
2826         .prcm_mod       = CORE_MOD,
2827         .flags          = CLOCK_IN_OMAP243X,
2828         .clkdm          = { .name = "core_l4_clkdm" },
2829         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2830         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2831         .recalc         = &followparent_recalc,
2832 };
2833
2834 /*
2835  * This clock is a composite clock which does entire set changes then
2836  * forces a rebalance. It keys on the MPU speed, but it really could
2837  * be any key speed part of a set in the rate table.
2838  *
2839  * to really change a set, you need memory table sets which get changed
2840  * in sram, pre-notifiers & post notifiers, changing the top set, without
2841  * having low level display recalc's won't work... this is why dpm notifiers
2842  * work, isr's off, walk a list of clocks already _off_ and not messing with
2843  * the bus.
2844  *
2845  * This clock should have no parent. It embodies the entire upper level
2846  * active set. A parent will mess up some of the init also.
2847  */
2848 static struct clk virt_prcm_set = {
2849         .name           = "virt_prcm_set",
2850         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2851                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2852         .clkdm          = { .name = "virt_opp_clkdm" },
2853         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2854         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2855         .set_rate       = &omap2_select_table_rate,
2856         .round_rate     = &omap2_round_to_table_rate,
2857 };
2858
2859 static struct clk *onchip_24xx_clks[] __initdata = {
2860         /* external root sources */
2861         &func_32k_ck,
2862         &osc_ck,
2863         &sys_ck,
2864         &alt_ck,
2865         /* internal analog sources */
2866         &dpll_ck,
2867         &apll96_ck,
2868         &apll54_ck,
2869         /* internal prcm root sources */
2870         &func_54m_ck,
2871         &core_ck,
2872         &func_96m_ck,
2873         &func_48m_ck,
2874         &func_12m_ck,
2875         &wdt1_osc_ck,
2876         &sys_clkout_src,
2877         &sys_clkout,
2878         &sys_clkout2_src,
2879         &sys_clkout2,
2880         &emul_ck,
2881         /* mpu domain clocks */
2882         &mpu_ck,
2883         /* dsp domain clocks */
2884         &dsp_fck,
2885         &dsp_irate_ick,
2886         &dsp_ick,               /* 242x */
2887         &iva2_1_ick,            /* 243x */
2888         &iva1_ifck,             /* 242x */
2889         &iva1_mpu_int_ifck,     /* 242x */
2890         /* GFX domain clocks */
2891         &gfx_3d_fck,
2892         &gfx_2d_fck,
2893         &gfx_ick,
2894         /* Modem domain clocks */
2895         &mdm_ick,
2896         &mdm_osc_ck,
2897         /* DSS domain clocks */
2898         &dss_ick,
2899         &dss1_fck,
2900         &dss2_fck,
2901         &dss_54m_fck,
2902         /* L3 domain clocks */
2903         &core_l3_ck,
2904         &ssi_ssr_sst_fck,
2905         &usb_l4_ick,
2906         /* L4 domain clocks */
2907         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2908         &ssi_l4_ick,
2909         /* virtual meta-group clock */
2910         &virt_prcm_set,
2911         /* general l4 interface ck, multi-parent functional clk */
2912         &gpt1_ick,
2913         &gpt1_fck,
2914         &gpt2_ick,
2915         &gpt2_fck,
2916         &gpt3_ick,
2917         &gpt3_fck,
2918         &gpt4_ick,
2919         &gpt4_fck,
2920         &gpt5_ick,
2921         &gpt5_fck,
2922         &gpt6_ick,
2923         &gpt6_fck,
2924         &gpt7_ick,
2925         &gpt7_fck,
2926         &gpt8_ick,
2927         &gpt8_fck,
2928         &gpt9_ick,
2929         &gpt9_fck,
2930         &gpt10_ick,
2931         &gpt10_fck,
2932         &gpt11_ick,
2933         &gpt11_fck,
2934         &gpt12_ick,
2935         &gpt12_fck,
2936         &mcbsp1_ick,
2937         &mcbsp1_fck,
2938         &mcbsp2_ick,
2939         &mcbsp2_fck,
2940         &mcbsp3_ick,
2941         &mcbsp3_fck,
2942         &mcbsp4_ick,
2943         &mcbsp4_fck,
2944         &mcbsp5_ick,
2945         &mcbsp5_fck,
2946         &mcspi1_ick,
2947         &mcspi1_fck,
2948         &mcspi2_ick,
2949         &mcspi2_fck,
2950         &mcspi3_ick,
2951         &mcspi3_fck,
2952         &uart1_ick,
2953         &uart1_fck,
2954         &uart2_ick,
2955         &uart2_fck,
2956         &uart3_ick,
2957         &uart3_fck,
2958         &gpios_ick,
2959         &gpios_fck,
2960         &mpu_wdt_ick,
2961         &mpu_wdt_fck,
2962         &sync_32k_ick,
2963         &wdt1_ick,
2964         &omapctrl_ick,
2965         &icr_ick,
2966         &cam_fck,
2967         &cam_ick,
2968         &mailboxes_ick,
2969         &wdt4_ick,
2970         &wdt4_fck,
2971         &wdt3_ick,
2972         &wdt3_fck,
2973         &mspro_ick,
2974         &mspro_fck,
2975         &mmc_ick,
2976         &mmc_fck,
2977         &fac_ick,
2978         &fac_fck,
2979         &eac_ick,
2980         &eac_fck,
2981         &hdq_ick,
2982         &hdq_fck,
2983         &i2c1_ick,
2984         &i2c1_fck,
2985         &i2chs1_fck,
2986         &i2c2_ick,
2987         &i2c2_fck,
2988         &i2chs2_fck,
2989         &gpmc_fck,
2990         &sdma_fck,
2991         &sdma_ick,
2992         &vlynq_ick,
2993         &vlynq_fck,
2994         &sdrc_ick,
2995         &des_ick,
2996         &sha_ick,
2997         &rng_ick,
2998         &aes_ick,
2999         &pka_ick,
3000         &usb_fck,
3001         &usbhs_ick,
3002         &mmchs1_ick,
3003         &mmchs1_fck,
3004         &mmchs2_ick,
3005         &mmchs2_fck,
3006         &gpio5_ick,
3007         &gpio5_fck,
3008         &mdm_intc_ick,
3009         &mmchsdb1_fck,
3010         &mmchsdb2_fck,
3011 };
3012
3013 #endif
3014