arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  18
  19 #include "clock.h"
  20
  21 #include "prm.h"
  22 #include "cm.h"
  23 #include "prm-regbits-24xx.h"
  24 #include "cm-regbits-24xx.h"
  25 #include "sdrc.h"
  26
  27 static unsigned long omap2_table_mpu_recalc(struct clk *clk);
  28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  30 static unsigned long omap2_sys_clk_recalc(struct clk *clk);
  31 static unsigned long omap2_osc_clk_recalc(struct clk *clk);
  32 static unsigned long omap2_sys_clk_recalc(struct clk *clk);
  33 static unsigned long omap2_dpllcore_recalc(struct clk *clk);
  34 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
  35
  36 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  37  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  38  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  39  */
  40 struct prcm_config {
  41         unsigned long xtal_speed;       /* crystal rate */
  42         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  43         unsigned long mpu_speed;        /* speed of MPU */
  44         unsigned long cm_clksel_mpu;    /* mpu divider */
  45         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  46         unsigned long cm_clksel_gfx;    /* gfx dividers */
  47         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  48         unsigned long cm_clksel1_pll;   /* m,n */
  49         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  50         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  51         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  52         unsigned char flags;
  53 };
  54
  55 /*
  56  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  57  * These configurations are characterized by voltage and speed for clocks.
  58  * The device is only validated for certain combinations. One way to express
  59  * these combinations is via the 'ratio's' which the clocks operate with
  60  * respect to each other. These ratio sets are for a given voltage/DPLL
  61  * setting. All configurations can be described by a DPLL setting and a ratio
  62  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  63  *
  64  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  65  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  66  * 2430 (iva2.1, NOdsp, mdm)
  67  */
  68
  69 /* Core fields for cm_clksel, not ratio governed */
  70 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  71 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  72 #define RX_CLKSEL_SSI                   (0x5 << 20)
  73
  74 /*-------------------------------------------------------------------------
  75  * Voltage/DPLL ratios
  76  *-------------------------------------------------------------------------*/
  77
  78 /* 2430 Ratio's, 2430-Ratio Config 1 */
  79 #define R1_CLKSEL_L3                    (4 << 0)
  80 #define R1_CLKSEL_L4                    (2 << 5)
  81 #define R1_CLKSEL_USB                   (4 << 25)
  82 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  83                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  84                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  85 #define R1_CLKSEL_MPU                   (2 << 0)
  86 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  87 #define R1_CLKSEL_DSP                   (2 << 0)
  88 #define R1_CLKSEL_DSP_IF                (2 << 5)
  89 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  90 #define R1_CLKSEL_GFX                   (2 << 0)
  91 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  92 #define R1_CLKSEL_MDM                   (4 << 0)
  93 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
  94
  95 /* 2430-Ratio Config 2 */
  96 #define R2_CLKSEL_L3                    (6 << 0)
  97 #define R2_CLKSEL_L4                    (2 << 5)
  98 #define R2_CLKSEL_USB                   (2 << 25)
  99 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 100                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 101                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 102 #define R2_CLKSEL_MPU                   (2 << 0)
 103 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 104 #define R2_CLKSEL_DSP                   (2 << 0)
 105 #define R2_CLKSEL_DSP_IF                (3 << 5)
 106 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 107 #define R2_CLKSEL_GFX                   (2 << 0)
 108 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 109 #define R2_CLKSEL_MDM                   (6 << 0)
 110 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 111
 112 /* 2430-Ratio Bootm (BYPASS) */
 113 #define RB_CLKSEL_L3                    (1 << 0)
 114 #define RB_CLKSEL_L4                    (1 << 5)
 115 #define RB_CLKSEL_USB                   (1 << 25)
 116 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 117                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 118                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 119 #define RB_CLKSEL_MPU                   (1 << 0)
 120 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 121 #define RB_CLKSEL_DSP                   (1 << 0)
 122 #define RB_CLKSEL_DSP_IF                (1 << 5)
 123 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 124 #define RB_CLKSEL_GFX                   (1 << 0)
 125 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 126 #define RB_CLKSEL_MDM                   (1 << 0)
 127 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 128
 129 /* 2420 Ratio Equivalents */
 130 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 131 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 132
 133 /* 2420-PRCM III 532MHz core */
 134 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 135 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 136 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 137 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 138                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 139                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 140                                         RIII_CLKSEL_L3
 141 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 142 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 143 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 144 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 145 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 146 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 147 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 148 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 149                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 150                                         RIII_CLKSEL_DSP
 151 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 152 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 153
 154 /* 2420-PRCM II 600MHz core */
 155 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 156 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 157 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 158 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 159                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 160                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 161                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 162 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 163 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 164 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 165 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 166 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 167 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 168 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 169 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 170                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 171                                         RII_CLKSEL_DSP
 172 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 173 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 174
 175 /* 2420-PRCM I 660MHz core */
 176 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 177 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 178 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 179 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 180                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 181                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 182                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 183 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 184 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 185 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 186 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 187 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 188 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 189 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 190 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 191                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 192                                         RI_CLKSEL_DSP
 193 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 194 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 195
 196 /* 2420-PRCM VII (boot) */
 197 #define RVII_CLKSEL_L3                  (1 << 0)
 198 #define RVII_CLKSEL_L4                  (1 << 5)
 199 #define RVII_CLKSEL_DSS1                (1 << 8)
 200 #define RVII_CLKSEL_DSS2                (0 << 13)
 201 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 202 #define RVII_CLKSEL_SSI                 (1 << 20)
 203 #define RVII_CLKSEL_USB                 (1 << 25)
 204
 205 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 206                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 207                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 208
 209 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 210 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 211
 212 #define RVII_CLKSEL_DSP                 (1 << 0)
 213 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 214 #define RVII_SYNC_DSP                   (0 << 7)
 215 #define RVII_CLKSEL_IVA                 (1 << 8)
 216 #define RVII_SYNC_IVA                   (0 << 13)
 217 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 218                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 219
 220 #define RVII_CLKSEL_GFX                 (1 << 0)
 221 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 222
 223 /*-------------------------------------------------------------------------
 224  * 2430 Target modes: Along with each configuration the CPU has several
 225  * modes which goes along with them. Modes mainly are the addition of
 226  * describe DPLL combinations to go along with a ratio.
 227  *-------------------------------------------------------------------------*/
 228
 229 /* Hardware governed */
 230 #define MX_48M_SRC                      (0 << 3)
 231 #define MX_54M_SRC                      (0 << 5)
 232 #define MX_APLLS_CLIKIN_12              (3 << 23)
 233 #define MX_APLLS_CLIKIN_13              (2 << 23)
 234 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 235
 236 /*
 237  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 238  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 239  */
 240 #define M5A_DPLL_MULT_12                (133 << 12)
 241 #define M5A_DPLL_DIV_12                 (5 << 8)
 242 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 243                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 244                                         MX_APLLS_CLIKIN_12
 245 #define M5A_DPLL_MULT_13                (61 << 12)
 246 #define M5A_DPLL_DIV_13                 (2 << 8)
 247 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 248                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 249                                         MX_APLLS_CLIKIN_13
 250 #define M5A_DPLL_MULT_19                (55 << 12)
 251 #define M5A_DPLL_DIV_19                 (3 << 8)
 252 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 253                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 254                                         MX_APLLS_CLIKIN_19_2
 255 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 256 #define M5B_DPLL_MULT_12                (50 << 12)
 257 #define M5B_DPLL_DIV_12                 (2 << 8)
 258 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 259                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 260                                         MX_APLLS_CLIKIN_12
 261 #define M5B_DPLL_MULT_13                (200 << 12)
 262 #define M5B_DPLL_DIV_13                 (12 << 8)
 263
 264 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 265                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 266                                         MX_APLLS_CLIKIN_13
 267 #define M5B_DPLL_MULT_19                (125 << 12)
 268 #define M5B_DPLL_DIV_19                 (31 << 8)
 269 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 270                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 271                                         MX_APLLS_CLIKIN_19_2
 272 /*
 273  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 274  */
 275 #define M4_DPLL_MULT_12                 (133 << 12)
 276 #define M4_DPLL_DIV_12                  (3 << 8)
 277 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 278                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 279                                         MX_APLLS_CLIKIN_12
 280
 281 #define M4_DPLL_MULT_13                 (399 << 12)
 282 #define M4_DPLL_DIV_13                  (12 << 8)
 283 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 284                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 285                                         MX_APLLS_CLIKIN_13
 286
 287 #define M4_DPLL_MULT_19                 (145 << 12)
 288 #define M4_DPLL_DIV_19                  (6 << 8)
 289 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 290                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 291                                         MX_APLLS_CLIKIN_19_2
 292
 293 /*
 294  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 295  */
 296 #define M3_DPLL_MULT_12                 (55 << 12)
 297 #define M3_DPLL_DIV_12                  (1 << 8)
 298 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 299                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 300                                         MX_APLLS_CLIKIN_12
 301 #define M3_DPLL_MULT_13                 (76 << 12)
 302 #define M3_DPLL_DIV_13                  (2 << 8)
 303 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 304                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 305                                         MX_APLLS_CLIKIN_13
 306 #define M3_DPLL_MULT_19                 (17 << 12)
 307 #define M3_DPLL_DIV_19                  (0 << 8)
 308 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 309                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 310                                         MX_APLLS_CLIKIN_19_2
 311
 312 /*
 313  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 314  */
 315 #define M2_DPLL_MULT_12                 (55 << 12)
 316 #define M2_DPLL_DIV_12                  (1 << 8)
 317 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 318                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 319                                         MX_APLLS_CLIKIN_12
 320
 321 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 322  * relock time issue */
 323 /* Core frequency changed from 330/165 to 329/164 MHz*/
 324 #define M2_DPLL_MULT_13                 (76 << 12)
 325 #define M2_DPLL_DIV_13                  (2 << 8)
 326 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 327                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 328                                         MX_APLLS_CLIKIN_13
 329
 330 #define M2_DPLL_MULT_19                 (17 << 12)
 331 #define M2_DPLL_DIV_19                  (0 << 8)
 332 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 333                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 334                                         MX_APLLS_CLIKIN_19_2
 335
 336 /* boot (boot) */
 337 #define MB_DPLL_MULT                    (1 << 12)
 338 #define MB_DPLL_DIV                     (0 << 8)
 339 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 340                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 341
 342 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 343                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 344
 345 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 346                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 347
 348 /*
 349  * 2430 - chassis (sedna)
 350  * 165 (ratio1) same as above #2
 351  * 150 (ratio1)
 352  * 133 (ratio2) same as above #4
 353  * 110 (ratio2) same as above #3
 354  * 104 (ratio2)
 355  * boot (boot)
 356  */
 357
 358 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 359 #define MI_DPLL_MULT_12                 (55 << 12)
 360 #define MI_DPLL_DIV_12                  (1 << 8)
 361 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 362                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 363                                         MX_APLLS_CLIKIN_12
 364
 365 /*
 366  * 2420 Equivalent - mode registers
 367  * PRCM II , target DPLL = 2*300MHz = 600MHz
 368  */
 369 #define MII_DPLL_MULT_12                (50 << 12)
 370 #define MII_DPLL_DIV_12                 (1 << 8)
 371 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 372                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 373                                         MX_APLLS_CLIKIN_12
 374 #define MII_DPLL_MULT_13                (300 << 12)
 375 #define MII_DPLL_DIV_13                 (12 << 8)
 376 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 377                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 378                                         MX_APLLS_CLIKIN_13
 379
 380 /* PRCM III target DPLL = 2*266 = 532MHz*/
 381 #define MIII_DPLL_MULT_12               (133 << 12)
 382 #define MIII_DPLL_DIV_12                (5 << 8)
 383 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 384                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 385                                         MX_APLLS_CLIKIN_12
 386 #define MIII_DPLL_MULT_13               (266 << 12)
 387 #define MIII_DPLL_DIV_13                (12 << 8)
 388 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 389                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 390                                         MX_APLLS_CLIKIN_13
 391
 392 /* PRCM VII (boot bypass) */
 393 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 394 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 395
 396 /* High and low operation value */
 397 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 398 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 399
 400 /* MPU speed defines */
 401 #define S12M    12000000
 402 #define S13M    13000000
 403 #define S19M    19200000
 404 #define S26M    26000000
 405 #define S100M   100000000
 406 #define S133M   133000000
 407 #define S150M   150000000
 408 #define S164M   164000000
 409 #define S165M   165000000
 410 #define S199M   199000000
 411 #define S200M   200000000
 412 #define S266M   266000000
 413 #define S300M   300000000
 414 #define S329M   329000000
 415 #define S330M   330000000
 416 #define S399M   399000000
 417 #define S400M   400000000
 418 #define S532M   532000000
 419 #define S600M   600000000
 420 #define S658M   658000000
 421 #define S660M   660000000
 422 #define S798M   798000000
 423
 424 /*-------------------------------------------------------------------------
 425  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 426  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 427  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 428  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 429  *
 430  * Filling in table based on H4 boards and 2430-SDPs variants available.
 431  * There are quite a few more rates combinations which could be defined.
 432  *
 433  * When multiple values are defined the start up will try and choose the
 434  * fastest one. If a 'fast' value is defined, then automatically, the /2
 435  * one should be included as it can be used.    Generally having more that
 436  * one fast set does not make sense, as static timings need to be changed
 437  * to change the set.    The exception is the bypass setting which is
 438  * availble for low power bypass.
 439  *
 440  * Note: This table needs to be sorted, fastest to slowest.
 441  *-------------------------------------------------------------------------*/
 442 static struct prcm_config rate_table[] = {
 443         /* PRCM I - FAST */
 444         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 445                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 446                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 447                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 448                 RATE_IN_242X},
 449
 450         /* PRCM II - FAST */
 451         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 452                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 453                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 454                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 455                 RATE_IN_242X},
 456
 457         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 458                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 459                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 460                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 461                 RATE_IN_242X},
 462
 463         /* PRCM III - FAST */
 464         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 465                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 466                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 467                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 468                 RATE_IN_242X},
 469
 470         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 471                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 472                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 473                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 474                 RATE_IN_242X},
 475
 476         /* PRCM II - SLOW */
 477         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 478                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 479                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 480                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 481                 RATE_IN_242X},
 482
 483         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 484                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 485                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 486                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 487                 RATE_IN_242X},
 488
 489         /* PRCM III - SLOW */
 490         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 491                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 492                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 493                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 494                 RATE_IN_242X},
 495
 496         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 497                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 498                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 499                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 500                 RATE_IN_242X},
 501
 502         /* PRCM-VII (boot-bypass) */
 503         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 504                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 505                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 506                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 507                 RATE_IN_242X},
 508
 509         /* PRCM-VII (boot-bypass) */
 510         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 511                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 512                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 513                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 514                 RATE_IN_242X},
 515
 516         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 517         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 518                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 519                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 520                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 521                 SDRC_RFR_CTRL_133MHz,
 522                 RATE_IN_243X},
 523
 524         /* PRCM #2 - ratio1 (ES2) - FAST */
 525         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 526                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 527                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 528                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 529                 SDRC_RFR_CTRL_165MHz,
 530                 RATE_IN_243X},
 531
 532         /* PRCM #5a - ratio1 - FAST */
 533         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 534                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 535                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 536                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 537                 SDRC_RFR_CTRL_133MHz,
 538                 RATE_IN_243X},
 539
 540         /* PRCM #5b - ratio1 - FAST */
 541         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 542                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 543                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 544                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 545                 SDRC_RFR_CTRL_100MHz,
 546                 RATE_IN_243X},
 547
 548         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 549         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 550                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 551                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 552                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 553                 SDRC_RFR_CTRL_133MHz,
 554                 RATE_IN_243X},
 555
 556         /* PRCM #2 - ratio1 (ES2) - SLOW */
 557         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 558                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 559                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 560                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 561                 SDRC_RFR_CTRL_165MHz,
 562                 RATE_IN_243X},
 563
 564         /* PRCM #5a - ratio1 - SLOW */
 565         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 566                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 567                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 568                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 569                 SDRC_RFR_CTRL_133MHz,
 570                 RATE_IN_243X},
 571
 572         /* PRCM #5b - ratio1 - SLOW*/
 573         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 574                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 575                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 576                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 577                 SDRC_RFR_CTRL_100MHz,
 578                 RATE_IN_243X},
 579
 580         /* PRCM-boot/bypass */
 581         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 582                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 583                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 584                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 585                 SDRC_RFR_CTRL_BYPASS,
 586                 RATE_IN_243X},
 587
 588         /* PRCM-boot/bypass */
 589         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 590                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 591                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 592                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 593                 SDRC_RFR_CTRL_BYPASS,
 594                 RATE_IN_243X},
 595
 596         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 597 };
 598
 599 /*-------------------------------------------------------------------------
 600  * 24xx clock tree.
 601  *
 602  * NOTE:In many cases here we are assigning a 'default' parent. In many
 603  *      cases the parent is selectable. The get/set parent calls will also
 604  *      switch sources.
 605  *
 606  *      Many some clocks say always_enabled, but they can be auto idled for
 607  *      power savings. They will always be available upon clock request.
 608  *
 609  *      Several sources are given initial rates which may be wrong, this will
 610  *      be fixed up in the init func.
 611  *
 612  *      Things are broadly separated below by clock domains. It is
 613  *      noteworthy that most periferals have dependencies on multiple clock
 614  *      domains. Many get their interface clocks from the L4 domain, but get
 615  *      functional clocks from fixed sources or other core domain derived
 616  *      clocks.
 617  *-------------------------------------------------------------------------*/
 618
 619 /* Base external input clocks */
 620 static struct clk func_32k_ck = {
 621         .name           = "func_32k_ck",
 622         .ops            = &clkops_null,
 623         .rate           = 32000,
 624         .flags          = RATE_FIXED,
 625         .clkdm_name     = "wkup_clkdm",
 626 };
 627
 628 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 629 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 630         .name           = "osc_ck",
 631         .ops            = &clkops_oscck,
 632         .clkdm_name     = "wkup_clkdm",
 633         .recalc         = &omap2_osc_clk_recalc,
 634 };
 635
 636 /* Without modem likely 12MHz, with modem likely 13MHz */
 637 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 638         .name           = "sys_ck",             /* ~ ref_clk also */
 639         .ops            = &clkops_null,
 640         .parent         = &osc_ck,
 641         .clkdm_name     = "wkup_clkdm",
 642         .recalc         = &omap2_sys_clk_recalc,
 643 };
 644
 645 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 646         .name           = "alt_ck",
 647         .ops            = &clkops_null,
 648         .rate           = 54000000,
 649         .flags          = RATE_FIXED,
 650         .clkdm_name     = "wkup_clkdm",
 651 };
 652
 653 /*
 654  * Analog domain root source clocks
 655  */
 656
 657 /* dpll_ck, is broken out in to special cases through clksel */
 658 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 659  * deal with this
 660  */
 661
 662 static struct dpll_data dpll_dd = {
 663         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 664         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 665         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 666         .clk_bypass             = &sys_ck,
 667         .clk_ref                = &sys_ck,
 668         .control_reg            = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 669         .enable_mask            = OMAP24XX_EN_DPLL_MASK,
 670         .max_multiplier         = 1024,
 671         .min_divider            = 1,
 672         .max_divider            = 16,
 673         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 674 };
 675
 676 /*
 677  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 678  * not just a DPLL
 679  */
 680 static struct clk dpll_ck = {
 681         .name           = "dpll_ck",
 682         .ops            = &clkops_null,
 683         .parent         = &sys_ck,              /* Can be func_32k also */
 684         .dpll_data      = &dpll_dd,
 685         .clkdm_name     = "wkup_clkdm",
 686         .recalc         = &omap2_dpllcore_recalc,
 687         .set_rate       = &omap2_reprogram_dpllcore,
 688 };
 689
 690 static struct clk apll96_ck = {
 691         .name           = "apll96_ck",
 692         .ops            = &clkops_fixed,
 693         .parent         = &sys_ck,
 694         .rate           = 96000000,
 695         .flags          = RATE_FIXED | ENABLE_ON_INIT,
 696         .clkdm_name     = "wkup_clkdm",
 697         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 698         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 699 };
 700
 701 static struct clk apll54_ck = {
 702         .name           = "apll54_ck",
 703         .ops            = &clkops_fixed,
 704         .parent         = &sys_ck,
 705         .rate           = 54000000,
 706         .flags          = RATE_FIXED | ENABLE_ON_INIT,
 707         .clkdm_name     = "wkup_clkdm",
 708         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 709         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 710 };
 711
 712 /*
 713  * PRCM digital base sources
 714  */
 715
 716 /* func_54m_ck */
 717
 718 static const struct clksel_rate func_54m_apll54_rates[] = {
 719         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 720         { .div = 0 },
 721 };
 722
 723 static const struct clksel_rate func_54m_alt_rates[] = {
 724         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 725         { .div = 0 },
 726 };
 727
 728 static const struct clksel func_54m_clksel[] = {
 729         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 730         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 731         { .parent = NULL },
 732 };
 733
 734 static struct clk func_54m_ck = {
 735         .name           = "func_54m_ck",
 736         .ops            = &clkops_null,
 737         .parent         = &apll54_ck,   /* can also be alt_clk */
 738         .clkdm_name     = "wkup_clkdm",
 739         .init           = &omap2_init_clksel_parent,
 740         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 741         .clksel_mask    = OMAP24XX_54M_SOURCE,
 742         .clksel         = func_54m_clksel,
 743         .recalc         = &omap2_clksel_recalc,
 744 };
 745
 746 static struct clk core_ck = {
 747         .name           = "core_ck",
 748         .ops            = &clkops_null,
 749         .parent         = &dpll_ck,             /* can also be 32k */
 750         .clkdm_name     = "wkup_clkdm",
 751         .recalc         = &followparent_recalc,
 752 };
 753
 754 /* func_96m_ck */
 755 static const struct clksel_rate func_96m_apll96_rates[] = {
 756         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 757         { .div = 0 },
 758 };
 759
 760 static const struct clksel_rate func_96m_alt_rates[] = {
 761         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 762         { .div = 0 },
 763 };
 764
 765 static const struct clksel func_96m_clksel[] = {
 766         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 767         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 768         { .parent = NULL }
 769 };
 770
 771 /* The parent of this clock is not selectable on 2420. */
 772 static struct clk func_96m_ck = {
 773         .name           = "func_96m_ck",
 774         .ops            = &clkops_null,
 775         .parent         = &apll96_ck,
 776         .clkdm_name     = "wkup_clkdm",
 777         .init           = &omap2_init_clksel_parent,
 778         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 779         .clksel_mask    = OMAP2430_96M_SOURCE,
 780         .clksel         = func_96m_clksel,
 781         .recalc         = &omap2_clksel_recalc,
 782         .round_rate     = &omap2_clksel_round_rate,
 783         .set_rate       = &omap2_clksel_set_rate
 784 };
 785
 786 /* func_48m_ck */
 787
 788 static const struct clksel_rate func_48m_apll96_rates[] = {
 789         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 790         { .div = 0 },
 791 };
 792
 793 static const struct clksel_rate func_48m_alt_rates[] = {
 794         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 795         { .div = 0 },
 796 };
 797
 798 static const struct clksel func_48m_clksel[] = {
 799         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 800         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 801         { .parent = NULL }
 802 };
 803
 804 static struct clk func_48m_ck = {
 805         .name           = "func_48m_ck",
 806         .ops            = &clkops_null,
 807         .parent         = &apll96_ck,    /* 96M or Alt */
 808         .clkdm_name     = "wkup_clkdm",
 809         .init           = &omap2_init_clksel_parent,
 810         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 811         .clksel_mask    = OMAP24XX_48M_SOURCE,
 812         .clksel         = func_48m_clksel,
 813         .recalc         = &omap2_clksel_recalc,
 814         .round_rate     = &omap2_clksel_round_rate,
 815         .set_rate       = &omap2_clksel_set_rate
 816 };
 817
 818 static struct clk func_12m_ck = {
 819         .name           = "func_12m_ck",
 820         .ops            = &clkops_null,
 821         .parent         = &func_48m_ck,
 822         .fixed_div      = 4,
 823         .clkdm_name     = "wkup_clkdm",
 824         .recalc         = &omap2_fixed_divisor_recalc,
 825 };
 826
 827 /* Secure timer, only available in secure mode */
 828 static struct clk wdt1_osc_ck = {
 829         .name           = "ck_wdt1_osc",
 830         .ops            = &clkops_null, /* RMK: missing? */
 831         .parent         = &osc_ck,
 832         .recalc         = &followparent_recalc,
 833 };
 834
 835 /*
 836  * The common_clkout* clksel_rate structs are common to
 837  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 838  * sys_clkout2_* are 2420-only, so the
 839  * clksel_rate flags fields are inaccurate for those clocks. This is
 840  * harmless since access to those clocks are gated by the struct clk
 841  * flags fields, which mark them as 2420-only.
 842  */
 843 static const struct clksel_rate common_clkout_src_core_rates[] = {
 844         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 845         { .div = 0 }
 846 };
 847
 848 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 849         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 850         { .div = 0 }
 851 };
 852
 853 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 854         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 855         { .div = 0 }
 856 };
 857
 858 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 859         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 860         { .div = 0 }
 861 };
 862
 863 static const struct clksel common_clkout_src_clksel[] = {
 864         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 865         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 866         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 867         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 868         { .parent = NULL }
 869 };
 870
 871 static struct clk sys_clkout_src = {
 872         .name           = "sys_clkout_src",
 873         .ops            = &clkops_omap2_dflt,
 874         .parent         = &func_54m_ck,
 875         .clkdm_name     = "wkup_clkdm",
 876         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 877         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 878         .init           = &omap2_init_clksel_parent,
 879         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 880         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 881         .clksel         = common_clkout_src_clksel,
 882         .recalc         = &omap2_clksel_recalc,
 883         .round_rate     = &omap2_clksel_round_rate,
 884         .set_rate       = &omap2_clksel_set_rate
 885 };
 886
 887 static const struct clksel_rate common_clkout_rates[] = {
 888         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 889         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 890         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 891         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 892         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 893         { .div = 0 },
 894 };
 895
 896 static const struct clksel sys_clkout_clksel[] = {
 897         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 898         { .parent = NULL }
 899 };
 900
 901 static struct clk sys_clkout = {
 902         .name           = "sys_clkout",
 903         .ops            = &clkops_null,
 904         .parent         = &sys_clkout_src,
 905         .clkdm_name     = "wkup_clkdm",
 906         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 907         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 908         .clksel         = sys_clkout_clksel,
 909         .recalc         = &omap2_clksel_recalc,
 910         .round_rate     = &omap2_clksel_round_rate,
 911         .set_rate       = &omap2_clksel_set_rate
 912 };
 913
 914 /* In 2430, new in 2420 ES2 */
 915 static struct clk sys_clkout2_src = {
 916         .name           = "sys_clkout2_src",
 917         .ops            = &clkops_omap2_dflt,
 918         .parent         = &func_54m_ck,
 919         .clkdm_name     = "wkup_clkdm",
 920         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 921         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 922         .init           = &omap2_init_clksel_parent,
 923         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 924         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 925         .clksel         = common_clkout_src_clksel,
 926         .recalc         = &omap2_clksel_recalc,
 927         .round_rate     = &omap2_clksel_round_rate,
 928         .set_rate       = &omap2_clksel_set_rate
 929 };
 930
 931 static const struct clksel sys_clkout2_clksel[] = {
 932         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 933         { .parent = NULL }
 934 };
 935
 936 /* In 2430, new in 2420 ES2 */
 937 static struct clk sys_clkout2 = {
 938         .name           = "sys_clkout2",
 939         .ops            = &clkops_null,
 940         .parent         = &sys_clkout2_src,
 941         .clkdm_name     = "wkup_clkdm",
 942         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 943         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 944         .clksel         = sys_clkout2_clksel,
 945         .recalc         = &omap2_clksel_recalc,
 946         .round_rate     = &omap2_clksel_round_rate,
 947         .set_rate       = &omap2_clksel_set_rate
 948 };
 949
 950 static struct clk emul_ck = {
 951         .name           = "emul_ck",
 952         .ops            = &clkops_omap2_dflt,
 953         .parent         = &func_54m_ck,
 954         .clkdm_name     = "wkup_clkdm",
 955         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 956         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 957         .recalc         = &followparent_recalc,
 958
 959 };
 960
 961 /*
 962  * MPU clock domain
 963  *      Clocks:
 964  *              MPU_FCLK, MPU_ICLK
 965  *              INT_M_FCLK, INT_M_I_CLK
 966  *
 967  * - Individual clocks are hardware managed.
 968  * - Base divider comes from: CM_CLKSEL_MPU
 969  *
 970  */
 971 static const struct clksel_rate mpu_core_rates[] = {
 972         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 973         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 974         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 975         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 976         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 977         { .div = 0 },
 978 };
 979
 980 static const struct clksel mpu_clksel[] = {
 981         { .parent = &core_ck, .rates = mpu_core_rates },
 982         { .parent = NULL }
 983 };
 984
 985 static struct clk mpu_ck = {    /* Control cpu */
 986         .name           = "mpu_ck",
 987         .ops            = &clkops_null,
 988         .parent         = &core_ck,
 989         .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
 990         .clkdm_name     = "mpu_clkdm",
 991         .init           = &omap2_init_clksel_parent,
 992         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 993         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 994         .clksel         = mpu_clksel,
 995         .recalc         = &omap2_clksel_recalc,
 996         .round_rate     = &omap2_clksel_round_rate,
 997         .set_rate       = &omap2_clksel_set_rate
 998 };
 999
1000 /*
1001  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1002  * Clocks:
1003  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1004  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1005  *
1006  * Won't be too specific here. The core clock comes into this block
1007  * it is divided then tee'ed. One branch goes directly to xyz enable
1008  * controls. The other branch gets further divided by 2 then possibly
1009  * routed into a synchronizer and out of clocks abc.
1010  */
1011 static const struct clksel_rate dsp_fck_core_rates[] = {
1012         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1013         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1014         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1015         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1016         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1017         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1018         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1019         { .div = 0 },
1020 };
1021
1022 static const struct clksel dsp_fck_clksel[] = {
1023         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1024         { .parent = NULL }
1025 };
1026
1027 static struct clk dsp_fck = {
1028         .name           = "dsp_fck",
1029         .ops            = &clkops_omap2_dflt_wait,
1030         .parent         = &core_ck,
1031         .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1032         .clkdm_name     = "dsp_clkdm",
1033         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1034         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1035         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1036         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1037         .clksel         = dsp_fck_clksel,
1038         .recalc         = &omap2_clksel_recalc,
1039         .round_rate     = &omap2_clksel_round_rate,
1040         .set_rate       = &omap2_clksel_set_rate
1041 };
1042
1043 /* DSP interface clock */
1044 static const struct clksel_rate dsp_irate_ick_rates[] = {
1045         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1046         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1047         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1048         { .div = 0 },
1049 };
1050
1051 static const struct clksel dsp_irate_ick_clksel[] = {
1052         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1053         { .parent = NULL }
1054 };
1055
1056 /* This clock does not exist as such in the TRM. */
1057 static struct clk dsp_irate_ick = {
1058         .name           = "dsp_irate_ick",
1059         .ops            = &clkops_null,
1060         .parent         = &dsp_fck,
1061         .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1062         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1063         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1064         .clksel         = dsp_irate_ick_clksel,
1065         .recalc         = &omap2_clksel_recalc,
1066         .round_rate     = &omap2_clksel_round_rate,
1067         .set_rate             = &omap2_clksel_set_rate
1068 };
1069
1070 /* 2420 only */
1071 static struct clk dsp_ick = {
1072         .name           = "dsp_ick",     /* apparently ipi and isp */
1073         .ops            = &clkops_omap2_dflt_wait,
1074         .parent         = &dsp_irate_ick,
1075         .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1076         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1077         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1078 };
1079
1080 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1081 static struct clk iva2_1_ick = {
1082         .name           = "iva2_1_ick",
1083         .ops            = &clkops_omap2_dflt_wait,
1084         .parent         = &dsp_irate_ick,
1085         .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1086         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1087         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1088 };
1089
1090 /*
1091  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1092  * the C54x, but which is contained in the DSP powerdomain.  Does not
1093  * exist on later OMAPs.
1094  */
1095 static struct clk iva1_ifck = {
1096         .name           = "iva1_ifck",
1097         .ops            = &clkops_omap2_dflt_wait,
1098         .parent         = &core_ck,
1099         .flags          = CONFIG_PARTICIPANT | DELAYED_APP,
1100         .clkdm_name     = "iva1_clkdm",
1101         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1102         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1103         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1104         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1105         .clksel         = dsp_fck_clksel,
1106         .recalc         = &omap2_clksel_recalc,
1107         .round_rate     = &omap2_clksel_round_rate,
1108         .set_rate       = &omap2_clksel_set_rate
1109 };
1110
1111 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1112 static struct clk iva1_mpu_int_ifck = {
1113         .name           = "iva1_mpu_int_ifck",
1114         .ops            = &clkops_omap2_dflt_wait,
1115         .parent         = &iva1_ifck,
1116         .clkdm_name     = "iva1_clkdm",
1117         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1118         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1119         .fixed_div      = 2,
1120         .recalc         = &omap2_fixed_divisor_recalc,
1121 };
1122
1123 /*
1124  * L3 clock domain
1125  * L3 clocks are used for both interface and functional clocks to
1126  * multiple entities. Some of these clocks are completely managed
1127  * by hardware, and some others allow software control. Hardware
1128  * managed ones general are based on directly CLK_REQ signals and
1129  * various auto idle settings. The functional spec sets many of these
1130  * as 'tie-high' for their enables.
1131  *
1132  * I-CLOCKS:
1133  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1134  *      CAM, HS-USB.
1135  * F-CLOCK
1136  *      SSI.
1137  *
1138  * GPMC memories and SDRC have timing and clock sensitive registers which
1139  * may very well need notification when the clock changes. Currently for low
1140  * operating points, these are taken care of in sleep.S.
1141  */
1142 static const struct clksel_rate core_l3_core_rates[] = {
1143         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1144         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1145         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1146         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1147         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1148         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1149         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1150         { .div = 0 }
1151 };
1152
1153 static const struct clksel core_l3_clksel[] = {
1154         { .parent = &core_ck, .rates = core_l3_core_rates },
1155         { .parent = NULL }
1156 };
1157
1158 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1159         .name           = "core_l3_ck",
1160         .ops            = &clkops_null,
1161         .parent         = &core_ck,
1162         .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1163         .clkdm_name     = "core_l3_clkdm",
1164         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1165         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1166         .clksel         = core_l3_clksel,
1167         .recalc         = &omap2_clksel_recalc,
1168         .round_rate     = &omap2_clksel_round_rate,
1169         .set_rate       = &omap2_clksel_set_rate
1170 };
1171
1172 /* usb_l4_ick */
1173 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1174         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1175         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1176         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1177         { .div = 0 }
1178 };
1179
1180 static const struct clksel usb_l4_ick_clksel[] = {
1181         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1182         { .parent = NULL },
1183 };
1184
1185 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1186 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1187         .name           = "usb_l4_ick",
1188         .ops            = &clkops_omap2_dflt_wait,
1189         .parent         = &core_l3_ck,
1190         .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1191         .clkdm_name     = "core_l4_clkdm",
1192         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1193         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1194         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1195         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1196         .clksel         = usb_l4_ick_clksel,
1197         .recalc         = &omap2_clksel_recalc,
1198         .round_rate     = &omap2_clksel_round_rate,
1199         .set_rate       = &omap2_clksel_set_rate
1200 };
1201
1202 /*
1203  * L4 clock management domain
1204  *
1205  * This domain contains lots of interface clocks from the L4 interface, some
1206  * functional clocks.   Fixed APLL functional source clocks are managed in
1207  * this domain.
1208  */
1209 static const struct clksel_rate l4_core_l3_rates[] = {
1210         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1211         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1212         { .div = 0 }
1213 };
1214
1215 static const struct clksel l4_clksel[] = {
1216         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1217         { .parent = NULL }
1218 };
1219
1220 static struct clk l4_ck = {             /* used both as an ick and fck */
1221         .name           = "l4_ck",
1222         .ops            = &clkops_null,
1223         .parent         = &core_l3_ck,
1224         .flags          = DELAYED_APP,
1225         .clkdm_name     = "core_l4_clkdm",
1226         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1227         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1228         .clksel         = l4_clksel,
1229         .recalc         = &omap2_clksel_recalc,
1230         .round_rate     = &omap2_clksel_round_rate,
1231         .set_rate       = &omap2_clksel_set_rate
1232 };
1233
1234 /*
1235  * SSI is in L3 management domain, its direct parent is core not l3,
1236  * many core power domain entities are grouped into the L3 clock
1237  * domain.
1238  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1239  *
1240  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1241  */
1242 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1243         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1244         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1245         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1246         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1247         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1248         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1249         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1250         { .div = 0 }
1251 };
1252
1253 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1254         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1255         { .parent = NULL }
1256 };
1257
1258 static struct clk ssi_ssr_sst_fck = {
1259         .name           = "ssi_fck",
1260         .ops            = &clkops_omap2_dflt_wait,
1261         .parent         = &core_ck,
1262         .flags          = DELAYED_APP,
1263         .clkdm_name     = "core_l3_clkdm",
1264         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1265         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1266         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1267         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1268         .clksel         = ssi_ssr_sst_fck_clksel,
1269         .recalc         = &omap2_clksel_recalc,
1270         .round_rate     = &omap2_clksel_round_rate,
1271         .set_rate       = &omap2_clksel_set_rate
1272 };
1273
1274 /*
1275  * Presumably this is the same as SSI_ICLK.
1276  * TRM contradicts itself on what clockdomain SSI_ICLK is in
1277  */
1278 static struct clk ssi_l4_ick = {
1279         .name           = "ssi_l4_ick",
1280         .ops            = &clkops_omap2_dflt_wait,
1281         .parent         = &l4_ck,
1282         .clkdm_name     = "core_l4_clkdm",
1283         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1284         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1285         .recalc         = &followparent_recalc,
1286 };
1287
1288
1289 /*
1290  * GFX clock domain
1291  *      Clocks:
1292  * GFX_FCLK, GFX_ICLK
1293  * GFX_CG1(2d), GFX_CG2(3d)
1294  *
1295  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1296  * The 2d and 3d clocks run at a hardware determined
1297  * divided value of fclk.
1298  *
1299  */
1300 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1301
1302 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1303 static const struct clksel gfx_fck_clksel[] = {
1304         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1305         { .parent = NULL },
1306 };
1307
1308 static struct clk gfx_3d_fck = {
1309         .name           = "gfx_3d_fck",
1310         .ops            = &clkops_omap2_dflt_wait,
1311         .parent         = &core_l3_ck,
1312         .clkdm_name     = "gfx_clkdm",
1313         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1314         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1315         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1316         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1317         .clksel         = gfx_fck_clksel,
1318         .recalc         = &omap2_clksel_recalc,
1319         .round_rate     = &omap2_clksel_round_rate,
1320         .set_rate       = &omap2_clksel_set_rate
1321 };
1322
1323 static struct clk gfx_2d_fck = {
1324         .name           = "gfx_2d_fck",
1325         .ops            = &clkops_omap2_dflt_wait,
1326         .parent         = &core_l3_ck,
1327         .clkdm_name     = "gfx_clkdm",
1328         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1329         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1330         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1331         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1332         .clksel         = gfx_fck_clksel,
1333         .recalc         = &omap2_clksel_recalc,
1334         .round_rate     = &omap2_clksel_round_rate,
1335         .set_rate       = &omap2_clksel_set_rate
1336 };
1337
1338 static struct clk gfx_ick = {
1339         .name           = "gfx_ick",            /* From l3 */
1340         .ops            = &clkops_omap2_dflt_wait,
1341         .parent         = &core_l3_ck,
1342         .clkdm_name     = "gfx_clkdm",
1343         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1344         .enable_bit     = OMAP_EN_GFX_SHIFT,
1345         .recalc         = &followparent_recalc,
1346 };
1347
1348 /*
1349  * Modem clock domain (2430)
1350  *      CLOCKS:
1351  *              MDM_OSC_CLK
1352  *              MDM_ICLK
1353  * These clocks are usable in chassis mode only.
1354  */
1355 static const struct clksel_rate mdm_ick_core_rates[] = {
1356         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1357         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1358         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1359         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1360         { .div = 0 }
1361 };
1362
1363 static const struct clksel mdm_ick_clksel[] = {
1364         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1365         { .parent = NULL }
1366 };
1367
1368 static struct clk mdm_ick = {           /* used both as a ick and fck */
1369         .name           = "mdm_ick",
1370         .ops            = &clkops_omap2_dflt_wait,
1371         .parent         = &core_ck,
1372         .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1373         .clkdm_name     = "mdm_clkdm",
1374         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1375         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1376         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1377         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1378         .clksel         = mdm_ick_clksel,
1379         .recalc         = &omap2_clksel_recalc,
1380         .round_rate     = &omap2_clksel_round_rate,
1381         .set_rate       = &omap2_clksel_set_rate
1382 };
1383
1384 static struct clk mdm_osc_ck = {
1385         .name           = "mdm_osc_ck",
1386         .ops            = &clkops_omap2_dflt_wait,
1387         .parent         = &osc_ck,
1388         .clkdm_name     = "mdm_clkdm",
1389         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1390         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1391         .recalc         = &followparent_recalc,
1392 };
1393
1394 /*
1395  * DSS clock domain
1396  * CLOCKs:
1397  * DSS_L4_ICLK, DSS_L3_ICLK,
1398  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1399  *
1400  * DSS is both initiator and target.
1401  */
1402 /* XXX Add RATE_NOT_VALIDATED */
1403
1404 static const struct clksel_rate dss1_fck_sys_rates[] = {
1405         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1406         { .div = 0 }
1407 };
1408
1409 static const struct clksel_rate dss1_fck_core_rates[] = {
1410         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1411         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1412         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1413         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1414         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1415         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1416         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1417         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1418         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1419         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1420         { .div = 0 }
1421 };
1422
1423 static const struct clksel dss1_fck_clksel[] = {
1424         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1425         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1426         { .parent = NULL },
1427 };
1428
1429 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1430         .name           = "dss_ick",
1431         .ops            = &clkops_omap2_dflt,
1432         .parent         = &l4_ck,       /* really both l3 and l4 */
1433         .clkdm_name     = "dss_clkdm",
1434         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1435         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1436         .recalc         = &followparent_recalc,
1437 };
1438
1439 static struct clk dss1_fck = {
1440         .name           = "dss1_fck",
1441         .ops            = &clkops_omap2_dflt,
1442         .parent         = &core_ck,             /* Core or sys */
1443         .flags          = DELAYED_APP,
1444         .clkdm_name     = "dss_clkdm",
1445         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1446         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1447         .init           = &omap2_init_clksel_parent,
1448         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1449         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1450         .clksel         = dss1_fck_clksel,
1451         .recalc         = &omap2_clksel_recalc,
1452         .round_rate     = &omap2_clksel_round_rate,
1453         .set_rate       = &omap2_clksel_set_rate
1454 };
1455
1456 static const struct clksel_rate dss2_fck_sys_rates[] = {
1457         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1458         { .div = 0 }
1459 };
1460
1461 static const struct clksel_rate dss2_fck_48m_rates[] = {
1462         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1463         { .div = 0 }
1464 };
1465
1466 static const struct clksel dss2_fck_clksel[] = {
1467         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1468         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1469         { .parent = NULL }
1470 };
1471
1472 static struct clk dss2_fck = {          /* Alt clk used in power management */
1473         .name           = "dss2_fck",
1474         .ops            = &clkops_omap2_dflt,
1475         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1476         .flags          = DELAYED_APP,
1477         .clkdm_name     = "dss_clkdm",
1478         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1479         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1480         .init           = &omap2_init_clksel_parent,
1481         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1482         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1483         .clksel         = dss2_fck_clksel,
1484         .recalc         = &followparent_recalc,
1485 };
1486
1487 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1488         .name           = "dss_54m_fck",        /* 54m tv clk */
1489         .ops            = &clkops_omap2_dflt_wait,
1490         .parent         = &func_54m_ck,
1491         .clkdm_name     = "dss_clkdm",
1492         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1493         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1494         .recalc         = &followparent_recalc,
1495 };
1496
1497 /*
1498  * CORE power domain ICLK & FCLK defines.
1499  * Many of the these can have more than one possible parent. Entries
1500  * here will likely have an L4 interface parent, and may have multiple
1501  * functional clock parents.
1502  */
1503 static const struct clksel_rate gpt_alt_rates[] = {
1504         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1505         { .div = 0 }
1506 };
1507
1508 static const struct clksel omap24xx_gpt_clksel[] = {
1509         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1510         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1511         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1512         { .parent = NULL },
1513 };
1514
1515 static struct clk gpt1_ick = {
1516         .name           = "gpt1_ick",
1517         .ops            = &clkops_omap2_dflt_wait,
1518         .parent         = &l4_ck,
1519         .clkdm_name     = "core_l4_clkdm",
1520         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1521         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1522         .recalc         = &followparent_recalc,
1523 };
1524
1525 static struct clk gpt1_fck = {
1526         .name           = "gpt1_fck",
1527         .ops            = &clkops_omap2_dflt_wait,
1528         .parent         = &func_32k_ck,
1529         .clkdm_name     = "core_l4_clkdm",
1530         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1531         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1532         .init           = &omap2_init_clksel_parent,
1533         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1534         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1535         .clksel         = omap24xx_gpt_clksel,
1536         .recalc         = &omap2_clksel_recalc,
1537         .round_rate     = &omap2_clksel_round_rate,
1538         .set_rate       = &omap2_clksel_set_rate
1539 };
1540
1541 static struct clk gpt2_ick = {
1542         .name           = "gpt2_ick",
1543         .ops            = &clkops_omap2_dflt_wait,
1544         .parent         = &l4_ck,
1545         .clkdm_name     = "core_l4_clkdm",
1546         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1547         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1548         .recalc         = &followparent_recalc,
1549 };
1550
1551 static struct clk gpt2_fck = {
1552         .name           = "gpt2_fck",
1553         .ops            = &clkops_omap2_dflt_wait,
1554         .parent         = &func_32k_ck,
1555         .clkdm_name     = "core_l4_clkdm",
1556         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1557         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1558         .init           = &omap2_init_clksel_parent,
1559         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1560         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1561         .clksel         = omap24xx_gpt_clksel,
1562         .recalc         = &omap2_clksel_recalc,
1563 };
1564
1565 static struct clk gpt3_ick = {
1566         .name           = "gpt3_ick",
1567         .ops            = &clkops_omap2_dflt_wait,
1568         .parent         = &l4_ck,
1569         .clkdm_name     = "core_l4_clkdm",
1570         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1571         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1572         .recalc         = &followparent_recalc,
1573 };
1574
1575 static struct clk gpt3_fck = {
1576         .name           = "gpt3_fck",
1577         .ops            = &clkops_omap2_dflt_wait,
1578         .parent         = &func_32k_ck,
1579         .clkdm_name     = "core_l4_clkdm",
1580         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1581         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1582         .init           = &omap2_init_clksel_parent,
1583         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1584         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1585         .clksel         = omap24xx_gpt_clksel,
1586         .recalc         = &omap2_clksel_recalc,
1587 };
1588
1589 static struct clk gpt4_ick = {
1590         .name           = "gpt4_ick",
1591         .ops            = &clkops_omap2_dflt_wait,
1592         .parent         = &l4_ck,
1593         .clkdm_name     = "core_l4_clkdm",
1594         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1595         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1596         .recalc         = &followparent_recalc,
1597 };
1598
1599 static struct clk gpt4_fck = {
1600         .name           = "gpt4_fck",
1601         .ops            = &clkops_omap2_dflt_wait,
1602         .parent         = &func_32k_ck,
1603         .clkdm_name     = "core_l4_clkdm",
1604         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1605         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1606         .init           = &omap2_init_clksel_parent,
1607         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1608         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1609         .clksel         = omap24xx_gpt_clksel,
1610         .recalc         = &omap2_clksel_recalc,
1611 };
1612
1613 static struct clk gpt5_ick = {
1614         .name           = "gpt5_ick",
1615         .ops            = &clkops_omap2_dflt_wait,
1616         .parent         = &l4_ck,
1617         .clkdm_name     = "core_l4_clkdm",
1618         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1619         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1620         .recalc         = &followparent_recalc,
1621 };
1622
1623 static struct clk gpt5_fck = {
1624         .name           = "gpt5_fck",
1625         .ops            = &clkops_omap2_dflt_wait,
1626         .parent         = &func_32k_ck,
1627         .clkdm_name     = "core_l4_clkdm",
1628         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1629         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1630         .init           = &omap2_init_clksel_parent,
1631         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1632         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1633         .clksel         = omap24xx_gpt_clksel,
1634         .recalc         = &omap2_clksel_recalc,
1635 };
1636
1637 static struct clk gpt6_ick = {
1638         .name           = "gpt6_ick",
1639         .ops            = &clkops_omap2_dflt_wait,
1640         .parent         = &l4_ck,
1641         .clkdm_name     = "core_l4_clkdm",
1642         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1643         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1644         .recalc         = &followparent_recalc,
1645 };
1646
1647 static struct clk gpt6_fck = {
1648         .name           = "gpt6_fck",
1649         .ops            = &clkops_omap2_dflt_wait,
1650         .parent         = &func_32k_ck,
1651         .clkdm_name     = "core_l4_clkdm",
1652         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1653         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1654         .init           = &omap2_init_clksel_parent,
1655         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1656         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1657         .clksel         = omap24xx_gpt_clksel,
1658         .recalc         = &omap2_clksel_recalc,
1659 };
1660
1661 static struct clk gpt7_ick = {
1662         .name           = "gpt7_ick",
1663         .ops            = &clkops_omap2_dflt_wait,
1664         .parent         = &l4_ck,
1665         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1666         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1667         .recalc         = &followparent_recalc,
1668 };
1669
1670 static struct clk gpt7_fck = {
1671         .name           = "gpt7_fck",
1672         .ops            = &clkops_omap2_dflt_wait,
1673         .parent         = &func_32k_ck,
1674         .clkdm_name     = "core_l4_clkdm",
1675         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1676         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1677         .init           = &omap2_init_clksel_parent,
1678         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1679         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1680         .clksel         = omap24xx_gpt_clksel,
1681         .recalc         = &omap2_clksel_recalc,
1682 };
1683
1684 static struct clk gpt8_ick = {
1685         .name           = "gpt8_ick",
1686         .ops            = &clkops_omap2_dflt_wait,
1687         .parent         = &l4_ck,
1688         .clkdm_name     = "core_l4_clkdm",
1689         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1690         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1691         .recalc         = &followparent_recalc,
1692 };
1693
1694 static struct clk gpt8_fck = {
1695         .name           = "gpt8_fck",
1696         .ops            = &clkops_omap2_dflt_wait,
1697         .parent         = &func_32k_ck,
1698         .clkdm_name     = "core_l4_clkdm",
1699         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1700         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1701         .init           = &omap2_init_clksel_parent,
1702         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1703         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1704         .clksel         = omap24xx_gpt_clksel,
1705         .recalc         = &omap2_clksel_recalc,
1706 };
1707
1708 static struct clk gpt9_ick = {
1709         .name           = "gpt9_ick",
1710         .ops            = &clkops_omap2_dflt_wait,
1711         .parent         = &l4_ck,
1712         .clkdm_name     = "core_l4_clkdm",
1713         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1714         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1715         .recalc         = &followparent_recalc,
1716 };
1717
1718 static struct clk gpt9_fck = {
1719         .name           = "gpt9_fck",
1720         .ops            = &clkops_omap2_dflt_wait,
1721         .parent         = &func_32k_ck,
1722         .clkdm_name     = "core_l4_clkdm",
1723         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1724         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1725         .init           = &omap2_init_clksel_parent,
1726         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1727         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1728         .clksel         = omap24xx_gpt_clksel,
1729         .recalc         = &omap2_clksel_recalc,
1730 };
1731
1732 static struct clk gpt10_ick = {
1733         .name           = "gpt10_ick",
1734         .ops            = &clkops_omap2_dflt_wait,
1735         .parent         = &l4_ck,
1736         .clkdm_name     = "core_l4_clkdm",
1737         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1738         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1739         .recalc         = &followparent_recalc,
1740 };
1741
1742 static struct clk gpt10_fck = {
1743         .name           = "gpt10_fck",
1744         .ops            = &clkops_omap2_dflt_wait,
1745         .parent         = &func_32k_ck,
1746         .clkdm_name     = "core_l4_clkdm",
1747         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1748         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1749         .init           = &omap2_init_clksel_parent,
1750         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1751         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1752         .clksel         = omap24xx_gpt_clksel,
1753         .recalc         = &omap2_clksel_recalc,
1754 };
1755
1756 static struct clk gpt11_ick = {
1757         .name           = "gpt11_ick",
1758         .ops            = &clkops_omap2_dflt_wait,
1759         .parent         = &l4_ck,
1760         .clkdm_name     = "core_l4_clkdm",
1761         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1762         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1763         .recalc         = &followparent_recalc,
1764 };
1765
1766 static struct clk gpt11_fck = {
1767         .name           = "gpt11_fck",
1768         .ops            = &clkops_omap2_dflt_wait,
1769         .parent         = &func_32k_ck,
1770         .clkdm_name     = "core_l4_clkdm",
1771         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1772         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1773         .init           = &omap2_init_clksel_parent,
1774         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1775         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1776         .clksel         = omap24xx_gpt_clksel,
1777         .recalc         = &omap2_clksel_recalc,
1778 };
1779
1780 static struct clk gpt12_ick = {
1781         .name           = "gpt12_ick",
1782         .ops            = &clkops_omap2_dflt_wait,
1783         .parent         = &l4_ck,
1784         .clkdm_name     = "core_l4_clkdm",
1785         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1786         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1787         .recalc         = &followparent_recalc,
1788 };
1789
1790 static struct clk gpt12_fck = {
1791         .name           = "gpt12_fck",
1792         .ops            = &clkops_omap2_dflt_wait,
1793         .parent         = &func_32k_ck,
1794         .clkdm_name     = "core_l4_clkdm",
1795         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1796         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1797         .init           = &omap2_init_clksel_parent,
1798         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1799         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1800         .clksel         = omap24xx_gpt_clksel,
1801         .recalc         = &omap2_clksel_recalc,
1802 };
1803
1804 static struct clk mcbsp1_ick = {
1805         .name           = "mcbsp_ick",
1806         .ops            = &clkops_omap2_dflt_wait,
1807         .id             = 1,
1808         .parent         = &l4_ck,
1809         .clkdm_name     = "core_l4_clkdm",
1810         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1811         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1812         .recalc         = &followparent_recalc,
1813 };
1814
1815 static struct clk mcbsp1_fck = {
1816         .name           = "mcbsp_fck",
1817         .ops            = &clkops_omap2_dflt_wait,
1818         .id             = 1,
1819         .parent         = &func_96m_ck,
1820         .clkdm_name     = "core_l4_clkdm",
1821         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1822         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk mcbsp2_ick = {
1827         .name           = "mcbsp_ick",
1828         .ops            = &clkops_omap2_dflt_wait,
1829         .id             = 2,
1830         .parent         = &l4_ck,
1831         .clkdm_name     = "core_l4_clkdm",
1832         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1833         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1834         .recalc         = &followparent_recalc,
1835 };
1836
1837 static struct clk mcbsp2_fck = {
1838         .name           = "mcbsp_fck",
1839         .ops            = &clkops_omap2_dflt_wait,
1840         .id             = 2,
1841         .parent         = &func_96m_ck,
1842         .clkdm_name     = "core_l4_clkdm",
1843         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1844         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk mcbsp3_ick = {
1849         .name           = "mcbsp_ick",
1850         .ops            = &clkops_omap2_dflt_wait,
1851         .id             = 3,
1852         .parent         = &l4_ck,
1853         .clkdm_name     = "core_l4_clkdm",
1854         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1855         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1856         .recalc         = &followparent_recalc,
1857 };
1858
1859 static struct clk mcbsp3_fck = {
1860         .name           = "mcbsp_fck",
1861         .ops            = &clkops_omap2_dflt_wait,
1862         .id             = 3,
1863         .parent         = &func_96m_ck,
1864         .clkdm_name     = "core_l4_clkdm",
1865         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1866         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1867         .recalc         = &followparent_recalc,
1868 };
1869
1870 static struct clk mcbsp4_ick = {
1871         .name           = "mcbsp_ick",
1872         .ops            = &clkops_omap2_dflt_wait,
1873         .id             = 4,
1874         .parent         = &l4_ck,
1875         .clkdm_name     = "core_l4_clkdm",
1876         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1877         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1878         .recalc         = &followparent_recalc,
1879 };
1880
1881 static struct clk mcbsp4_fck = {
1882         .name           = "mcbsp_fck",
1883         .ops            = &clkops_omap2_dflt_wait,
1884         .id             = 4,
1885         .parent         = &func_96m_ck,
1886         .clkdm_name     = "core_l4_clkdm",
1887         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1888         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1889         .recalc         = &followparent_recalc,
1890 };
1891
1892 static struct clk mcbsp5_ick = {
1893         .name           = "mcbsp_ick",
1894         .ops            = &clkops_omap2_dflt_wait,
1895         .id             = 5,
1896         .parent         = &l4_ck,
1897         .clkdm_name     = "core_l4_clkdm",
1898         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1899         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1900         .recalc         = &followparent_recalc,
1901 };
1902
1903 static struct clk mcbsp5_fck = {
1904         .name           = "mcbsp_fck",
1905         .ops            = &clkops_omap2_dflt_wait,
1906         .id             = 5,
1907         .parent         = &func_96m_ck,
1908         .clkdm_name     = "core_l4_clkdm",
1909         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1910         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1911         .recalc         = &followparent_recalc,
1912 };
1913
1914 static struct clk mcspi1_ick = {
1915         .name           = "mcspi_ick",
1916         .ops            = &clkops_omap2_dflt_wait,
1917         .id             = 1,
1918         .parent         = &l4_ck,
1919         .clkdm_name     = "core_l4_clkdm",
1920         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1921         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1922         .recalc         = &followparent_recalc,
1923 };
1924
1925 static struct clk mcspi1_fck = {
1926         .name           = "mcspi_fck",
1927         .ops            = &clkops_omap2_dflt_wait,
1928         .id             = 1,
1929         .parent         = &func_48m_ck,
1930         .clkdm_name     = "core_l4_clkdm",
1931         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1932         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1933         .recalc         = &followparent_recalc,
1934 };
1935
1936 static struct clk mcspi2_ick = {
1937         .name           = "mcspi_ick",
1938         .ops            = &clkops_omap2_dflt_wait,
1939         .id             = 2,
1940         .parent         = &l4_ck,
1941         .clkdm_name     = "core_l4_clkdm",
1942         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1943         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1944         .recalc         = &followparent_recalc,
1945 };
1946
1947 static struct clk mcspi2_fck = {
1948         .name           = "mcspi_fck",
1949         .ops            = &clkops_omap2_dflt_wait,
1950         .id             = 2,
1951         .parent         = &func_48m_ck,
1952         .clkdm_name     = "core_l4_clkdm",
1953         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1954         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1955         .recalc         = &followparent_recalc,
1956 };
1957
1958 static struct clk mcspi3_ick = {
1959         .name           = "mcspi_ick",
1960         .ops            = &clkops_omap2_dflt_wait,
1961         .id             = 3,
1962         .parent         = &l4_ck,
1963         .clkdm_name     = "core_l4_clkdm",
1964         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1965         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1966         .recalc         = &followparent_recalc,
1967 };
1968
1969 static struct clk mcspi3_fck = {
1970         .name           = "mcspi_fck",
1971         .ops            = &clkops_omap2_dflt_wait,
1972         .id             = 3,
1973         .parent         = &func_48m_ck,
1974         .clkdm_name     = "core_l4_clkdm",
1975         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1976         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1977         .recalc         = &followparent_recalc,
1978 };
1979
1980 static struct clk uart1_ick = {
1981         .name           = "uart1_ick",
1982         .ops            = &clkops_omap2_dflt_wait,
1983         .parent         = &l4_ck,
1984         .clkdm_name     = "core_l4_clkdm",
1985         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1986         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1987         .recalc         = &followparent_recalc,
1988 };
1989
1990 static struct clk uart1_fck = {
1991         .name           = "uart1_fck",
1992         .ops            = &clkops_omap2_dflt_wait,
1993         .parent         = &func_48m_ck,
1994         .clkdm_name     = "core_l4_clkdm",
1995         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1996         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1997         .recalc         = &followparent_recalc,
1998 };
1999
2000 static struct clk uart2_ick = {
2001         .name           = "uart2_ick",
2002         .ops            = &clkops_omap2_dflt_wait,
2003         .parent         = &l4_ck,
2004         .clkdm_name     = "core_l4_clkdm",
2005         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2006         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2007         .recalc         = &followparent_recalc,
2008 };
2009
2010 static struct clk uart2_fck = {
2011         .name           = "uart2_fck",
2012         .ops            = &clkops_omap2_dflt_wait,
2013         .parent         = &func_48m_ck,
2014         .clkdm_name     = "core_l4_clkdm",
2015         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2016         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2017         .recalc         = &followparent_recalc,
2018 };
2019
2020 static struct clk uart3_ick = {
2021         .name           = "uart3_ick",
2022         .ops            = &clkops_omap2_dflt_wait,
2023         .parent         = &l4_ck,
2024         .clkdm_name     = "core_l4_clkdm",
2025         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2026         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2027         .recalc         = &followparent_recalc,
2028 };
2029
2030 static struct clk uart3_fck = {
2031         .name           = "uart3_fck",
2032         .ops            = &clkops_omap2_dflt_wait,
2033         .parent         = &func_48m_ck,
2034         .clkdm_name     = "core_l4_clkdm",
2035         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2036         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2037         .recalc         = &followparent_recalc,
2038 };
2039
2040 static struct clk gpios_ick = {
2041         .name           = "gpios_ick",
2042         .ops            = &clkops_omap2_dflt_wait,
2043         .parent         = &l4_ck,
2044         .clkdm_name     = "core_l4_clkdm",
2045         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2046         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2047         .recalc         = &followparent_recalc,
2048 };
2049
2050 static struct clk gpios_fck = {
2051         .name           = "gpios_fck",
2052         .ops            = &clkops_omap2_dflt_wait,
2053         .parent         = &func_32k_ck,
2054         .clkdm_name     = "wkup_clkdm",
2055         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2056         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2057         .recalc         = &followparent_recalc,
2058 };
2059
2060 static struct clk mpu_wdt_ick = {
2061         .name           = "mpu_wdt_ick",
2062         .ops            = &clkops_omap2_dflt_wait,
2063         .parent         = &l4_ck,
2064         .clkdm_name     = "core_l4_clkdm",
2065         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2066         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2067         .recalc         = &followparent_recalc,
2068 };
2069
2070 static struct clk mpu_wdt_fck = {
2071         .name           = "mpu_wdt_fck",
2072         .ops            = &clkops_omap2_dflt_wait,
2073         .parent         = &func_32k_ck,
2074         .clkdm_name     = "wkup_clkdm",
2075         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2076         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2077         .recalc         = &followparent_recalc,
2078 };
2079
2080 static struct clk sync_32k_ick = {
2081         .name           = "sync_32k_ick",
2082         .ops            = &clkops_omap2_dflt_wait,
2083         .parent         = &l4_ck,
2084         .flags          = ENABLE_ON_INIT,
2085         .clkdm_name     = "core_l4_clkdm",
2086         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2087         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2088         .recalc         = &followparent_recalc,
2089 };
2090
2091 static struct clk wdt1_ick = {
2092         .name           = "wdt1_ick",
2093         .ops            = &clkops_omap2_dflt_wait,
2094         .parent         = &l4_ck,
2095         .clkdm_name     = "core_l4_clkdm",
2096         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2097         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2098         .recalc         = &followparent_recalc,
2099 };
2100
2101 static struct clk omapctrl_ick = {
2102         .name           = "omapctrl_ick",
2103         .ops            = &clkops_omap2_dflt_wait,
2104         .parent         = &l4_ck,
2105         .flags          = ENABLE_ON_INIT,
2106         .clkdm_name     = "core_l4_clkdm",
2107         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2108         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2109         .recalc         = &followparent_recalc,
2110 };
2111
2112 static struct clk icr_ick = {
2113         .name           = "icr_ick",
2114         .ops            = &clkops_omap2_dflt_wait,
2115         .parent         = &l4_ck,
2116         .clkdm_name     = "core_l4_clkdm",
2117         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2118         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2119         .recalc         = &followparent_recalc,
2120 };
2121
2122 static struct clk cam_ick = {
2123         .name           = "cam_ick",
2124         .ops            = &clkops_omap2_dflt,
2125         .parent         = &l4_ck,
2126         .clkdm_name     = "core_l4_clkdm",
2127         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2128         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2129         .recalc         = &followparent_recalc,
2130 };
2131
2132 /*
2133  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
2134  * split into two separate clocks, since the parent clocks are different
2135  * and the clockdomains are also different.
2136  */
2137 static struct clk cam_fck = {
2138         .name           = "cam_fck",
2139         .ops            = &clkops_omap2_dflt,
2140         .parent         = &func_96m_ck,
2141         .clkdm_name     = "core_l3_clkdm",
2142         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2143         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2144         .recalc         = &followparent_recalc,
2145 };
2146
2147 static struct clk mailboxes_ick = {
2148         .name           = "mailboxes_ick",
2149         .ops            = &clkops_omap2_dflt_wait,
2150         .parent         = &l4_ck,
2151         .clkdm_name     = "core_l4_clkdm",
2152         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2153         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2154         .recalc         = &followparent_recalc,
2155 };
2156
2157 static struct clk wdt4_ick = {
2158         .name           = "wdt4_ick",
2159         .ops            = &clkops_omap2_dflt_wait,
2160         .parent         = &l4_ck,
2161         .clkdm_name     = "core_l4_clkdm",
2162         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2163         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2164         .recalc         = &followparent_recalc,
2165 };
2166
2167 static struct clk wdt4_fck = {
2168         .name           = "wdt4_fck",
2169         .ops            = &clkops_omap2_dflt_wait,
2170         .parent         = &func_32k_ck,
2171         .clkdm_name     = "core_l4_clkdm",
2172         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2173         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2174         .recalc         = &followparent_recalc,
2175 };
2176
2177 static struct clk wdt3_ick = {
2178         .name           = "wdt3_ick",
2179         .ops            = &clkops_omap2_dflt_wait,
2180         .parent         = &l4_ck,
2181         .clkdm_name     = "core_l4_clkdm",
2182         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2183         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2184         .recalc         = &followparent_recalc,
2185 };
2186
2187 static struct clk wdt3_fck = {
2188         .name           = "wdt3_fck",
2189         .ops            = &clkops_omap2_dflt_wait,
2190         .parent         = &func_32k_ck,
2191         .clkdm_name     = "core_l4_clkdm",
2192         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2193         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2194         .recalc         = &followparent_recalc,
2195 };
2196
2197 static struct clk mspro_ick = {
2198         .name           = "mspro_ick",
2199         .ops            = &clkops_omap2_dflt_wait,
2200         .parent         = &l4_ck,
2201         .clkdm_name     = "core_l4_clkdm",
2202         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2203         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2204         .recalc         = &followparent_recalc,
2205 };
2206
2207 static struct clk mspro_fck = {
2208         .name           = "mspro_fck",
2209         .ops            = &clkops_omap2_dflt_wait,
2210         .parent         = &func_96m_ck,
2211         .clkdm_name     = "core_l4_clkdm",
2212         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2213         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2214         .recalc         = &followparent_recalc,
2215 };
2216
2217 static struct clk mmc_ick = {
2218         .name           = "mmc_ick",
2219         .ops            = &clkops_omap2_dflt_wait,
2220         .parent         = &l4_ck,
2221         .clkdm_name     = "core_l4_clkdm",
2222         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2223         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2224         .recalc         = &followparent_recalc,
2225 };
2226
2227 static struct clk mmc_fck = {
2228         .name           = "mmc_fck",
2229         .ops            = &clkops_omap2_dflt_wait,
2230         .parent         = &func_96m_ck,
2231         .clkdm_name     = "core_l4_clkdm",
2232         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2233         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2234         .recalc         = &followparent_recalc,
2235 };
2236
2237 static struct clk fac_ick = {
2238         .name           = "fac_ick",
2239         .ops            = &clkops_omap2_dflt_wait,
2240         .parent         = &l4_ck,
2241         .clkdm_name     = "core_l4_clkdm",
2242         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2243         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2244         .recalc         = &followparent_recalc,
2245 };
2246
2247 static struct clk fac_fck = {
2248         .name           = "fac_fck",
2249         .ops            = &clkops_omap2_dflt_wait,
2250         .parent         = &func_12m_ck,
2251         .clkdm_name     = "core_l4_clkdm",
2252         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2253         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2254         .recalc         = &followparent_recalc,
2255 };
2256
2257 static struct clk eac_ick = {
2258         .name           = "eac_ick",
2259         .ops            = &clkops_omap2_dflt_wait,
2260         .parent         = &l4_ck,
2261         .clkdm_name     = "core_l4_clkdm",
2262         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2263         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2264         .recalc         = &followparent_recalc,
2265 };
2266
2267 static struct clk eac_fck = {
2268         .name           = "eac_fck",
2269         .ops            = &clkops_omap2_dflt_wait,
2270         .parent         = &func_96m_ck,
2271         .clkdm_name     = "core_l4_clkdm",
2272         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2273         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2274         .recalc         = &followparent_recalc,
2275 };
2276
2277 static struct clk hdq_ick = {
2278         .name           = "hdq_ick",
2279         .ops            = &clkops_omap2_dflt_wait,
2280         .parent         = &l4_ck,
2281         .clkdm_name     = "core_l4_clkdm",
2282         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2283         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2284         .recalc         = &followparent_recalc,
2285 };
2286
2287 static struct clk hdq_fck = {
2288         .name           = "hdq_fck",
2289         .ops            = &clkops_omap2_dflt_wait,
2290         .parent         = &func_12m_ck,
2291         .clkdm_name     = "core_l4_clkdm",
2292         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2293         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2294         .recalc         = &followparent_recalc,
2295 };
2296
2297 static struct clk i2c2_ick = {
2298         .name           = "i2c_ick",
2299         .ops            = &clkops_omap2_dflt_wait,
2300         .id             = 2,
2301         .parent         = &l4_ck,
2302         .clkdm_name     = "core_l4_clkdm",
2303         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2304         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2305         .recalc         = &followparent_recalc,
2306 };
2307
2308 static struct clk i2c2_fck = {
2309         .name           = "i2c_fck",
2310         .ops            = &clkops_omap2_dflt_wait,
2311         .id             = 2,
2312         .parent         = &func_12m_ck,
2313         .clkdm_name     = "core_l4_clkdm",
2314         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2315         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2316         .recalc         = &followparent_recalc,
2317 };
2318
2319 static struct clk i2chs2_fck = {
2320         .name           = "i2c_fck",
2321         .ops            = &clkops_omap2_dflt_wait,
2322         .id             = 2,
2323         .parent         = &func_96m_ck,
2324         .clkdm_name     = "core_l4_clkdm",
2325         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2326         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2327         .recalc         = &followparent_recalc,
2328 };
2329
2330 static struct clk i2c1_ick = {
2331         .name           = "i2c_ick",
2332         .ops            = &clkops_omap2_dflt_wait,
2333         .id             = 1,
2334         .parent         = &l4_ck,
2335         .clkdm_name     = "core_l4_clkdm",
2336         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2337         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2338         .recalc         = &followparent_recalc,
2339 };
2340
2341 static struct clk i2c1_fck = {
2342         .name           = "i2c_fck",
2343         .ops            = &clkops_omap2_dflt_wait,
2344         .id             = 1,
2345         .parent         = &func_12m_ck,
2346         .clkdm_name     = "core_l4_clkdm",
2347         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2348         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2349         .recalc         = &followparent_recalc,
2350 };
2351
2352 static struct clk i2chs1_fck = {
2353         .name           = "i2c_fck",
2354         .ops            = &clkops_omap2_dflt_wait,
2355         .id             = 1,
2356         .parent         = &func_96m_ck,
2357         .clkdm_name     = "core_l4_clkdm",
2358         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2359         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2360         .recalc         = &followparent_recalc,
2361 };
2362
2363 static struct clk gpmc_fck = {
2364         .name           = "gpmc_fck",
2365         .ops            = &clkops_null, /* RMK: missing? */
2366         .parent         = &core_l3_ck,
2367         .flags          = ENABLE_ON_INIT,
2368         .clkdm_name     = "core_l3_clkdm",
2369         .recalc         = &followparent_recalc,
2370 };
2371
2372 static struct clk sdma_fck = {
2373         .name           = "sdma_fck",
2374         .ops            = &clkops_null, /* RMK: missing? */
2375         .parent         = &core_l3_ck,
2376         .clkdm_name     = "core_l3_clkdm",
2377         .recalc         = &followparent_recalc,
2378 };
2379
2380 static struct clk sdma_ick = {
2381         .name           = "sdma_ick",
2382         .ops            = &clkops_null, /* RMK: missing? */
2383         .parent         = &l4_ck,
2384         .clkdm_name     = "core_l3_clkdm",
2385         .recalc         = &followparent_recalc,
2386 };
2387
2388 static struct clk vlynq_ick = {
2389         .name           = "vlynq_ick",
2390         .ops            = &clkops_omap2_dflt_wait,
2391         .parent         = &core_l3_ck,
2392         .clkdm_name     = "core_l3_clkdm",
2393         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2394         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2395         .recalc         = &followparent_recalc,
2396 };
2397
2398 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2399         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2400         { .div = 0 }
2401 };
2402
2403 static const struct clksel_rate vlynq_fck_core_rates[] = {
2404         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2405         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2406         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2407         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2408         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2409         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2410         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2411         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2412         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2413         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2414         { .div = 0 }
2415 };
2416
2417 static const struct clksel vlynq_fck_clksel[] = {
2418         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2419         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2420         { .parent = NULL }
2421 };
2422
2423 static struct clk vlynq_fck = {
2424         .name           = "vlynq_fck",
2425         .ops            = &clkops_omap2_dflt_wait,
2426         .parent         = &func_96m_ck,
2427         .flags          = DELAYED_APP,
2428         .clkdm_name     = "core_l3_clkdm",
2429         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2430         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2431         .init           = &omap2_init_clksel_parent,
2432         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2433         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2434         .clksel         = vlynq_fck_clksel,
2435         .recalc         = &omap2_clksel_recalc,
2436         .round_rate     = &omap2_clksel_round_rate,
2437         .set_rate       = &omap2_clksel_set_rate
2438 };
2439
2440 static struct clk sdrc_ick = {
2441         .name           = "sdrc_ick",
2442         .ops            = &clkops_omap2_dflt_wait,
2443         .parent         = &l4_ck,
2444         .flags          = ENABLE_ON_INIT,
2445         .clkdm_name     = "core_l4_clkdm",
2446         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2447         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2448         .recalc         = &followparent_recalc,
2449 };
2450
2451 static struct clk des_ick = {
2452         .name           = "des_ick",
2453         .ops            = &clkops_omap2_dflt_wait,
2454         .parent         = &l4_ck,
2455         .clkdm_name     = "core_l4_clkdm",
2456         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2457         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2458         .recalc         = &followparent_recalc,
2459 };
2460
2461 static struct clk sha_ick = {
2462         .name           = "sha_ick",
2463         .ops            = &clkops_omap2_dflt_wait,
2464         .parent         = &l4_ck,
2465         .clkdm_name     = "core_l4_clkdm",
2466         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2467         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2468         .recalc         = &followparent_recalc,
2469 };
2470
2471 static struct clk rng_ick = {
2472         .name           = "rng_ick",
2473         .ops            = &clkops_omap2_dflt_wait,
2474         .parent         = &l4_ck,
2475         .clkdm_name     = "core_l4_clkdm",
2476         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2477         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2478         .recalc         = &followparent_recalc,
2479 };
2480
2481 static struct clk aes_ick = {
2482         .name           = "aes_ick",
2483         .ops            = &clkops_omap2_dflt_wait,
2484         .parent         = &l4_ck,
2485         .clkdm_name     = "core_l4_clkdm",
2486         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2487         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2488         .recalc         = &followparent_recalc,
2489 };
2490
2491 static struct clk pka_ick = {
2492         .name           = "pka_ick",
2493         .ops            = &clkops_omap2_dflt_wait,
2494         .parent         = &l4_ck,
2495         .clkdm_name     = "core_l4_clkdm",
2496         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2497         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2498         .recalc         = &followparent_recalc,
2499 };
2500
2501 static struct clk usb_fck = {
2502         .name           = "usb_fck",
2503         .ops            = &clkops_omap2_dflt_wait,
2504         .parent         = &func_48m_ck,
2505         .clkdm_name     = "core_l3_clkdm",
2506         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2507         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2508         .recalc         = &followparent_recalc,
2509 };
2510
2511 static struct clk usbhs_ick = {
2512         .name           = "usbhs_ick",
2513         .ops            = &clkops_omap2_dflt_wait,
2514         .parent         = &core_l3_ck,
2515         .clkdm_name     = "core_l3_clkdm",
2516         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2517         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2518         .recalc         = &followparent_recalc,
2519 };
2520
2521 static struct clk mmchs1_ick = {
2522         .name           = "mmchs_ick",
2523         .ops            = &clkops_omap2_dflt_wait,
2524         .parent         = &l4_ck,
2525         .clkdm_name     = "core_l4_clkdm",
2526         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2527         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2528         .recalc         = &followparent_recalc,
2529 };
2530
2531 static struct clk mmchs1_fck = {
2532         .name           = "mmchs_fck",
2533         .ops            = &clkops_omap2_dflt_wait,
2534         .parent         = &func_96m_ck,
2535         .clkdm_name     = "core_l3_clkdm",
2536         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2537         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2538         .recalc         = &followparent_recalc,
2539 };
2540
2541 static struct clk mmchs2_ick = {
2542         .name           = "mmchs_ick",
2543         .ops            = &clkops_omap2_dflt_wait,
2544         .id             = 1,
2545         .parent         = &l4_ck,
2546         .clkdm_name     = "core_l4_clkdm",
2547         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2548         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2549         .recalc         = &followparent_recalc,
2550 };
2551
2552 static struct clk mmchs2_fck = {
2553         .name           = "mmchs_fck",
2554         .ops            = &clkops_omap2_dflt_wait,
2555         .id             = 1,
2556         .parent         = &func_96m_ck,
2557         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2558         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2559         .recalc         = &followparent_recalc,
2560 };
2561
2562 static struct clk gpio5_ick = {
2563         .name           = "gpio5_ick",
2564         .ops            = &clkops_omap2_dflt_wait,
2565         .parent         = &l4_ck,
2566         .clkdm_name     = "core_l4_clkdm",
2567         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2568         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2569         .recalc         = &followparent_recalc,
2570 };
2571
2572 static struct clk gpio5_fck = {
2573         .name           = "gpio5_fck",
2574         .ops            = &clkops_omap2_dflt_wait,
2575         .parent         = &func_32k_ck,
2576         .clkdm_name     = "core_l4_clkdm",
2577         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2578         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2579         .recalc         = &followparent_recalc,
2580 };
2581
2582 static struct clk mdm_intc_ick = {
2583         .name           = "mdm_intc_ick",
2584         .ops            = &clkops_omap2_dflt_wait,
2585         .parent         = &l4_ck,
2586         .clkdm_name     = "core_l4_clkdm",
2587         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2588         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2589         .recalc         = &followparent_recalc,
2590 };
2591
2592 static struct clk mmchsdb1_fck = {
2593         .name           = "mmchsdb_fck",
2594         .ops            = &clkops_omap2_dflt_wait,
2595         .parent         = &func_32k_ck,
2596         .clkdm_name     = "core_l4_clkdm",
2597         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2598         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2599         .recalc         = &followparent_recalc,
2600 };
2601
2602 static struct clk mmchsdb2_fck = {
2603         .name           = "mmchsdb_fck",
2604         .ops            = &clkops_omap2_dflt_wait,
2605         .id             = 1,
2606         .parent         = &func_32k_ck,
2607         .clkdm_name     = "core_l4_clkdm",
2608         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2609         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2610         .recalc         = &followparent_recalc,
2611 };
2612
2613 /*
2614  * This clock is a composite clock which does entire set changes then
2615  * forces a rebalance. It keys on the MPU speed, but it really could
2616  * be any key speed part of a set in the rate table.
2617  *
2618  * to really change a set, you need memory table sets which get changed
2619  * in sram, pre-notifiers & post notifiers, changing the top set, without
2620  * having low level display recalc's won't work... this is why dpm notifiers
2621  * work, isr's off, walk a list of clocks already _off_ and not messing with
2622  * the bus.
2623  *
2624  * This clock should have no parent. It embodies the entire upper level
2625  * active set. A parent will mess up some of the init also.
2626  */
2627 static struct clk virt_prcm_set = {
2628         .name           = "virt_prcm_set",
2629         .ops            = &clkops_null,
2630         .flags          = DELAYED_APP,
2631         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2632         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2633         .set_rate       = &omap2_select_table_rate,
2634         .round_rate     = &omap2_round_to_table_rate,
2635 };
2636
2637 #endif
2638