2 * linux/arch/arm/mach-omap2/clock2420_data.c
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/clk.h>
18 #include <linux/list.h>
20 #include <plat/clkdev_omap.h>
23 #include "clock2xxx.h"
25 #include "cm2xxx_3xxx.h"
26 #include "prm2xxx_3xxx.h"
27 #include "prm-regbits-24xx.h"
28 #include "cm-regbits-24xx.h"
32 #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
37 * NOTE:In many cases here we are assigning a 'default' parent. In many
38 * cases the parent is selectable. The get/set parent calls will also
41 * Many some clocks say always_enabled, but they can be auto idled for
42 * power savings. They will always be available upon clock request.
44 * Several sources are given initial rates which may be wrong, this will
45 * be fixed up in the init func.
47 * Things are broadly separated below by clock domains. It is
48 * noteworthy that most periferals have dependencies on multiple clock
49 * domains. Many get their interface clocks from the L4 domain, but get
50 * functional clocks from fixed sources or other core domain derived
54 /* Base external input clocks */
55 static struct clk func_32k_ck = {
56 .name = "func_32k_ck",
59 .clkdm_name = "wkup_clkdm",
62 static struct clk secure_32k_ck = {
63 .name = "secure_32k_ck",
66 .clkdm_name = "wkup_clkdm",
69 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
70 static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
73 .clkdm_name = "wkup_clkdm",
74 .recalc = &omap2_osc_clk_recalc,
77 /* Without modem likely 12MHz, with modem likely 13MHz */
78 static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
79 .name = "sys_ck", /* ~ ref_clk also */
82 .clkdm_name = "wkup_clkdm",
83 .recalc = &omap2xxx_sys_clk_recalc,
86 static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
90 .clkdm_name = "wkup_clkdm",
93 /* Optional external clock input for McBSP CLKS */
94 static struct clk mcbsp_clks = {
100 * Analog domain root source clocks
103 /* dpll_ck, is broken out in to special cases through clksel */
104 /* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
108 static struct dpll_data dpll_dd = {
109 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
110 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
111 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
112 .clk_bypass = &sys_ck,
114 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
115 .enable_mask = OMAP24XX_EN_DPLL_MASK,
116 .max_multiplier = 1023,
119 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
123 * XXX Cannot add round_rate here yet, as this is still a composite clock,
126 static struct clk dpll_ck = {
128 .ops = &clkops_omap2xxx_dpll_ops,
129 .parent = &sys_ck, /* Can be func_32k also */
130 .dpll_data = &dpll_dd,
131 .clkdm_name = "wkup_clkdm",
132 .recalc = &omap2_dpllcore_recalc,
133 .set_rate = &omap2_reprogram_dpllcore,
136 static struct clk apll96_ck = {
138 .ops = &clkops_apll96,
141 .flags = ENABLE_ON_INIT,
142 .clkdm_name = "wkup_clkdm",
143 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
144 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
147 static struct clk apll54_ck = {
149 .ops = &clkops_apll54,
152 .flags = ENABLE_ON_INIT,
153 .clkdm_name = "wkup_clkdm",
154 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
155 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
159 * PRCM digital base sources
164 static const struct clksel_rate func_54m_apll54_rates[] = {
165 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
169 static const struct clksel_rate func_54m_alt_rates[] = {
170 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
174 static const struct clksel func_54m_clksel[] = {
175 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
176 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
180 static struct clk func_54m_ck = {
181 .name = "func_54m_ck",
183 .parent = &apll54_ck, /* can also be alt_clk */
184 .clkdm_name = "wkup_clkdm",
185 .init = &omap2_init_clksel_parent,
186 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
187 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
188 .clksel = func_54m_clksel,
189 .recalc = &omap2_clksel_recalc,
192 static struct clk core_ck = {
195 .parent = &dpll_ck, /* can also be 32k */
196 .clkdm_name = "wkup_clkdm",
197 .recalc = &followparent_recalc,
200 static struct clk func_96m_ck = {
201 .name = "func_96m_ck",
203 .parent = &apll96_ck,
204 .clkdm_name = "wkup_clkdm",
205 .recalc = &followparent_recalc,
210 static const struct clksel_rate func_48m_apll96_rates[] = {
211 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
215 static const struct clksel_rate func_48m_alt_rates[] = {
216 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
220 static const struct clksel func_48m_clksel[] = {
221 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
222 { .parent = &alt_ck, .rates = func_48m_alt_rates },
226 static struct clk func_48m_ck = {
227 .name = "func_48m_ck",
229 .parent = &apll96_ck, /* 96M or Alt */
230 .clkdm_name = "wkup_clkdm",
231 .init = &omap2_init_clksel_parent,
232 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
233 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
234 .clksel = func_48m_clksel,
235 .recalc = &omap2_clksel_recalc,
236 .round_rate = &omap2_clksel_round_rate,
237 .set_rate = &omap2_clksel_set_rate
240 static struct clk func_12m_ck = {
241 .name = "func_12m_ck",
243 .parent = &func_48m_ck,
245 .clkdm_name = "wkup_clkdm",
246 .recalc = &omap_fixed_divisor_recalc,
249 /* Secure timer, only available in secure mode */
250 static struct clk wdt1_osc_ck = {
251 .name = "ck_wdt1_osc",
252 .ops = &clkops_null, /* RMK: missing? */
254 .recalc = &followparent_recalc,
258 * The common_clkout* clksel_rate structs are common to
259 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
260 * sys_clkout2_* are 2420-only, so the
261 * clksel_rate flags fields are inaccurate for those clocks. This is
262 * harmless since access to those clocks are gated by the struct clk
263 * flags fields, which mark them as 2420-only.
265 static const struct clksel_rate common_clkout_src_core_rates[] = {
266 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
270 static const struct clksel_rate common_clkout_src_sys_rates[] = {
271 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
275 static const struct clksel_rate common_clkout_src_96m_rates[] = {
276 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
280 static const struct clksel_rate common_clkout_src_54m_rates[] = {
281 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
285 static const struct clksel common_clkout_src_clksel[] = {
286 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
287 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
288 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
289 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
293 static struct clk sys_clkout_src = {
294 .name = "sys_clkout_src",
295 .ops = &clkops_omap2_dflt,
296 .parent = &func_54m_ck,
297 .clkdm_name = "wkup_clkdm",
298 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
299 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
300 .init = &omap2_init_clksel_parent,
301 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
302 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
303 .clksel = common_clkout_src_clksel,
304 .recalc = &omap2_clksel_recalc,
305 .round_rate = &omap2_clksel_round_rate,
306 .set_rate = &omap2_clksel_set_rate
309 static const struct clksel_rate common_clkout_rates[] = {
310 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
311 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
312 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
313 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
314 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
318 static const struct clksel sys_clkout_clksel[] = {
319 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
323 static struct clk sys_clkout = {
324 .name = "sys_clkout",
326 .parent = &sys_clkout_src,
327 .clkdm_name = "wkup_clkdm",
328 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
329 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
330 .clksel = sys_clkout_clksel,
331 .recalc = &omap2_clksel_recalc,
332 .round_rate = &omap2_clksel_round_rate,
333 .set_rate = &omap2_clksel_set_rate
336 /* In 2430, new in 2420 ES2 */
337 static struct clk sys_clkout2_src = {
338 .name = "sys_clkout2_src",
339 .ops = &clkops_omap2_dflt,
340 .parent = &func_54m_ck,
341 .clkdm_name = "wkup_clkdm",
342 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
343 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
344 .init = &omap2_init_clksel_parent,
345 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
346 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
347 .clksel = common_clkout_src_clksel,
348 .recalc = &omap2_clksel_recalc,
349 .round_rate = &omap2_clksel_round_rate,
350 .set_rate = &omap2_clksel_set_rate
353 static const struct clksel sys_clkout2_clksel[] = {
354 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
358 /* In 2430, new in 2420 ES2 */
359 static struct clk sys_clkout2 = {
360 .name = "sys_clkout2",
362 .parent = &sys_clkout2_src,
363 .clkdm_name = "wkup_clkdm",
364 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
365 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
366 .clksel = sys_clkout2_clksel,
367 .recalc = &omap2_clksel_recalc,
368 .round_rate = &omap2_clksel_round_rate,
369 .set_rate = &omap2_clksel_set_rate
372 static struct clk emul_ck = {
374 .ops = &clkops_omap2_dflt,
375 .parent = &func_54m_ck,
376 .clkdm_name = "wkup_clkdm",
377 .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
378 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
379 .recalc = &followparent_recalc,
387 * INT_M_FCLK, INT_M_I_CLK
389 * - Individual clocks are hardware managed.
390 * - Base divider comes from: CM_CLKSEL_MPU
393 static const struct clksel_rate mpu_core_rates[] = {
394 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
395 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
396 { .div = 4, .val = 4, .flags = RATE_IN_242X },
397 { .div = 6, .val = 6, .flags = RATE_IN_242X },
398 { .div = 8, .val = 8, .flags = RATE_IN_242X },
402 static const struct clksel mpu_clksel[] = {
403 { .parent = &core_ck, .rates = mpu_core_rates },
407 static struct clk mpu_ck = { /* Control cpu */
411 .clkdm_name = "mpu_clkdm",
412 .init = &omap2_init_clksel_parent,
413 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
414 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
415 .clksel = mpu_clksel,
416 .recalc = &omap2_clksel_recalc,
420 * DSP (2420-UMA+IVA1) clock domain
422 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
424 * Won't be too specific here. The core clock comes into this block
425 * it is divided then tee'ed. One branch goes directly to xyz enable
426 * controls. The other branch gets further divided by 2 then possibly
427 * routed into a synchronizer and out of clocks abc.
429 static const struct clksel_rate dsp_fck_core_rates[] = {
430 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
431 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
432 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
433 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
434 { .div = 6, .val = 6, .flags = RATE_IN_242X },
435 { .div = 8, .val = 8, .flags = RATE_IN_242X },
436 { .div = 12, .val = 12, .flags = RATE_IN_242X },
440 static const struct clksel dsp_fck_clksel[] = {
441 { .parent = &core_ck, .rates = dsp_fck_core_rates },
445 static struct clk dsp_fck = {
447 .ops = &clkops_omap2_dflt_wait,
449 .clkdm_name = "dsp_clkdm",
450 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
451 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
452 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
453 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
454 .clksel = dsp_fck_clksel,
455 .recalc = &omap2_clksel_recalc,
458 /* DSP interface clock */
459 static const struct clksel_rate dsp_irate_ick_rates[] = {
460 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
461 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
465 static const struct clksel dsp_irate_ick_clksel[] = {
466 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
470 /* This clock does not exist as such in the TRM. */
471 static struct clk dsp_irate_ick = {
472 .name = "dsp_irate_ick",
475 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
476 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
477 .clksel = dsp_irate_ick_clksel,
478 .recalc = &omap2_clksel_recalc,
482 static struct clk dsp_ick = {
483 .name = "dsp_ick", /* apparently ipi and isp */
484 .ops = &clkops_omap2_iclk_dflt_wait,
485 .parent = &dsp_irate_ick,
486 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
487 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
491 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
492 * the C54x, but which is contained in the DSP powerdomain. Does not
493 * exist on later OMAPs.
495 static struct clk iva1_ifck = {
497 .ops = &clkops_omap2_dflt_wait,
499 .clkdm_name = "iva1_clkdm",
500 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
501 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
502 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
503 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
504 .clksel = dsp_fck_clksel,
505 .recalc = &omap2_clksel_recalc,
508 /* IVA1 mpu/int/i/f clocks are /2 of parent */
509 static struct clk iva1_mpu_int_ifck = {
510 .name = "iva1_mpu_int_ifck",
511 .ops = &clkops_omap2_dflt_wait,
512 .parent = &iva1_ifck,
513 .clkdm_name = "iva1_clkdm",
514 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
515 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
517 .recalc = &omap_fixed_divisor_recalc,
522 * L3 clocks are used for both interface and functional clocks to
523 * multiple entities. Some of these clocks are completely managed
524 * by hardware, and some others allow software control. Hardware
525 * managed ones general are based on directly CLK_REQ signals and
526 * various auto idle settings. The functional spec sets many of these
527 * as 'tie-high' for their enables.
530 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
535 * GPMC memories and SDRC have timing and clock sensitive registers which
536 * may very well need notification when the clock changes. Currently for low
537 * operating points, these are taken care of in sleep.S.
539 static const struct clksel_rate core_l3_core_rates[] = {
540 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
541 { .div = 2, .val = 2, .flags = RATE_IN_242X },
542 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
543 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
544 { .div = 8, .val = 8, .flags = RATE_IN_242X },
545 { .div = 12, .val = 12, .flags = RATE_IN_242X },
546 { .div = 16, .val = 16, .flags = RATE_IN_242X },
550 static const struct clksel core_l3_clksel[] = {
551 { .parent = &core_ck, .rates = core_l3_core_rates },
555 static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
556 .name = "core_l3_ck",
559 .clkdm_name = "core_l3_clkdm",
560 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
561 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
562 .clksel = core_l3_clksel,
563 .recalc = &omap2_clksel_recalc,
567 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
568 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
569 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
570 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
574 static const struct clksel usb_l4_ick_clksel[] = {
575 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
579 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
580 static struct clk usb_l4_ick = { /* FS-USB interface clock */
581 .name = "usb_l4_ick",
582 .ops = &clkops_omap2_iclk_dflt_wait,
583 .parent = &core_l3_ck,
584 .clkdm_name = "core_l4_clkdm",
585 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
586 .enable_bit = OMAP24XX_EN_USB_SHIFT,
587 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
588 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
589 .clksel = usb_l4_ick_clksel,
590 .recalc = &omap2_clksel_recalc,
594 * L4 clock management domain
596 * This domain contains lots of interface clocks from the L4 interface, some
597 * functional clocks. Fixed APLL functional source clocks are managed in
600 static const struct clksel_rate l4_core_l3_rates[] = {
601 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
602 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
606 static const struct clksel l4_clksel[] = {
607 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
611 static struct clk l4_ck = { /* used both as an ick and fck */
614 .parent = &core_l3_ck,
615 .clkdm_name = "core_l4_clkdm",
616 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
617 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
619 .recalc = &omap2_clksel_recalc,
623 * SSI is in L3 management domain, its direct parent is core not l3,
624 * many core power domain entities are grouped into the L3 clock
626 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
628 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
630 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
631 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
632 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
633 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
634 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
635 { .div = 6, .val = 6, .flags = RATE_IN_242X },
636 { .div = 8, .val = 8, .flags = RATE_IN_242X },
640 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
641 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
645 static struct clk ssi_ssr_sst_fck = {
647 .ops = &clkops_omap2_dflt_wait,
649 .clkdm_name = "core_l3_clkdm",
650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
651 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
652 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
653 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
654 .clksel = ssi_ssr_sst_fck_clksel,
655 .recalc = &omap2_clksel_recalc,
659 * Presumably this is the same as SSI_ICLK.
660 * TRM contradicts itself on what clockdomain SSI_ICLK is in
662 static struct clk ssi_l4_ick = {
663 .name = "ssi_l4_ick",
664 .ops = &clkops_omap2_iclk_dflt_wait,
666 .clkdm_name = "core_l4_clkdm",
667 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
668 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
669 .recalc = &followparent_recalc,
677 * GFX_CG1(2d), GFX_CG2(3d)
679 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
680 * The 2d and 3d clocks run at a hardware determined
681 * divided value of fclk.
685 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
686 static const struct clksel gfx_fck_clksel[] = {
687 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
691 static struct clk gfx_3d_fck = {
692 .name = "gfx_3d_fck",
693 .ops = &clkops_omap2_dflt_wait,
694 .parent = &core_l3_ck,
695 .clkdm_name = "gfx_clkdm",
696 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
697 .enable_bit = OMAP24XX_EN_3D_SHIFT,
698 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
699 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
700 .clksel = gfx_fck_clksel,
701 .recalc = &omap2_clksel_recalc,
702 .round_rate = &omap2_clksel_round_rate,
703 .set_rate = &omap2_clksel_set_rate
706 static struct clk gfx_2d_fck = {
707 .name = "gfx_2d_fck",
708 .ops = &clkops_omap2_dflt_wait,
709 .parent = &core_l3_ck,
710 .clkdm_name = "gfx_clkdm",
711 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
712 .enable_bit = OMAP24XX_EN_2D_SHIFT,
713 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
714 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
715 .clksel = gfx_fck_clksel,
716 .recalc = &omap2_clksel_recalc,
719 /* This interface clock does not have a CM_AUTOIDLE bit */
720 static struct clk gfx_ick = {
721 .name = "gfx_ick", /* From l3 */
722 .ops = &clkops_omap2_dflt_wait,
723 .parent = &core_l3_ck,
724 .clkdm_name = "gfx_clkdm",
725 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
726 .enable_bit = OMAP_EN_GFX_SHIFT,
727 .recalc = &followparent_recalc,
733 * DSS_L4_ICLK, DSS_L3_ICLK,
734 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
736 * DSS is both initiator and target.
738 /* XXX Add RATE_NOT_VALIDATED */
740 static const struct clksel_rate dss1_fck_sys_rates[] = {
741 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
745 static const struct clksel_rate dss1_fck_core_rates[] = {
746 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
747 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
748 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
749 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
750 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
751 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
752 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
753 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
754 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
755 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
759 static const struct clksel dss1_fck_clksel[] = {
760 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
761 { .parent = &core_ck, .rates = dss1_fck_core_rates },
765 static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
767 .ops = &clkops_omap2_iclk_dflt,
768 .parent = &l4_ck, /* really both l3 and l4 */
769 .clkdm_name = "dss_clkdm",
770 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
771 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
772 .recalc = &followparent_recalc,
775 static struct clk dss1_fck = {
777 .ops = &clkops_omap2_dflt,
778 .parent = &core_ck, /* Core or sys */
779 .clkdm_name = "dss_clkdm",
780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
781 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
782 .init = &omap2_init_clksel_parent,
783 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
784 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
785 .clksel = dss1_fck_clksel,
786 .recalc = &omap2_clksel_recalc,
789 static const struct clksel_rate dss2_fck_sys_rates[] = {
790 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
794 static const struct clksel_rate dss2_fck_48m_rates[] = {
795 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
799 static const struct clksel dss2_fck_clksel[] = {
800 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
801 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
805 static struct clk dss2_fck = { /* Alt clk used in power management */
807 .ops = &clkops_omap2_dflt,
808 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
809 .clkdm_name = "dss_clkdm",
810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
811 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
812 .init = &omap2_init_clksel_parent,
813 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
814 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
815 .clksel = dss2_fck_clksel,
816 .recalc = &omap2_clksel_recalc,
819 static struct clk dss_54m_fck = { /* Alt clk used in power management */
820 .name = "dss_54m_fck", /* 54m tv clk */
821 .ops = &clkops_omap2_dflt_wait,
822 .parent = &func_54m_ck,
823 .clkdm_name = "dss_clkdm",
824 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
825 .enable_bit = OMAP24XX_EN_TV_SHIFT,
826 .recalc = &followparent_recalc,
829 static struct clk wu_l4_ick = {
833 .clkdm_name = "wkup_clkdm",
834 .recalc = &followparent_recalc,
838 * CORE power domain ICLK & FCLK defines.
839 * Many of the these can have more than one possible parent. Entries
840 * here will likely have an L4 interface parent, and may have multiple
841 * functional clock parents.
843 static const struct clksel_rate gpt_alt_rates[] = {
844 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
848 static const struct clksel omap24xx_gpt_clksel[] = {
849 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
850 { .parent = &sys_ck, .rates = gpt_sys_rates },
851 { .parent = &alt_ck, .rates = gpt_alt_rates },
855 static struct clk gpt1_ick = {
857 .ops = &clkops_omap2_iclk_dflt_wait,
858 .parent = &wu_l4_ick,
859 .clkdm_name = "wkup_clkdm",
860 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
861 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
862 .recalc = &followparent_recalc,
865 static struct clk gpt1_fck = {
867 .ops = &clkops_omap2_dflt_wait,
868 .parent = &func_32k_ck,
869 .clkdm_name = "core_l4_clkdm",
870 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
871 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
872 .init = &omap2_init_clksel_parent,
873 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
874 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
875 .clksel = omap24xx_gpt_clksel,
876 .recalc = &omap2_clksel_recalc,
877 .round_rate = &omap2_clksel_round_rate,
878 .set_rate = &omap2_clksel_set_rate
881 static struct clk gpt2_ick = {
883 .ops = &clkops_omap2_iclk_dflt_wait,
885 .clkdm_name = "core_l4_clkdm",
886 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
887 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
888 .recalc = &followparent_recalc,
891 static struct clk gpt2_fck = {
893 .ops = &clkops_omap2_dflt_wait,
894 .parent = &func_32k_ck,
895 .clkdm_name = "core_l4_clkdm",
896 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
897 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
898 .init = &omap2_init_clksel_parent,
899 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
900 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
901 .clksel = omap24xx_gpt_clksel,
902 .recalc = &omap2_clksel_recalc,
905 static struct clk gpt3_ick = {
907 .ops = &clkops_omap2_iclk_dflt_wait,
909 .clkdm_name = "core_l4_clkdm",
910 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
911 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
912 .recalc = &followparent_recalc,
915 static struct clk gpt3_fck = {
917 .ops = &clkops_omap2_dflt_wait,
918 .parent = &func_32k_ck,
919 .clkdm_name = "core_l4_clkdm",
920 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
921 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
922 .init = &omap2_init_clksel_parent,
923 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
924 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
925 .clksel = omap24xx_gpt_clksel,
926 .recalc = &omap2_clksel_recalc,
929 static struct clk gpt4_ick = {
931 .ops = &clkops_omap2_iclk_dflt_wait,
933 .clkdm_name = "core_l4_clkdm",
934 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
935 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
936 .recalc = &followparent_recalc,
939 static struct clk gpt4_fck = {
941 .ops = &clkops_omap2_dflt_wait,
942 .parent = &func_32k_ck,
943 .clkdm_name = "core_l4_clkdm",
944 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
945 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
946 .init = &omap2_init_clksel_parent,
947 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
948 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
949 .clksel = omap24xx_gpt_clksel,
950 .recalc = &omap2_clksel_recalc,
953 static struct clk gpt5_ick = {
955 .ops = &clkops_omap2_iclk_dflt_wait,
957 .clkdm_name = "core_l4_clkdm",
958 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
959 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
960 .recalc = &followparent_recalc,
963 static struct clk gpt5_fck = {
965 .ops = &clkops_omap2_dflt_wait,
966 .parent = &func_32k_ck,
967 .clkdm_name = "core_l4_clkdm",
968 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
969 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
970 .init = &omap2_init_clksel_parent,
971 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
972 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
973 .clksel = omap24xx_gpt_clksel,
974 .recalc = &omap2_clksel_recalc,
977 static struct clk gpt6_ick = {
979 .ops = &clkops_omap2_iclk_dflt_wait,
981 .clkdm_name = "core_l4_clkdm",
982 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
983 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
984 .recalc = &followparent_recalc,
987 static struct clk gpt6_fck = {
989 .ops = &clkops_omap2_dflt_wait,
990 .parent = &func_32k_ck,
991 .clkdm_name = "core_l4_clkdm",
992 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
993 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
994 .init = &omap2_init_clksel_parent,
995 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
996 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
997 .clksel = omap24xx_gpt_clksel,
998 .recalc = &omap2_clksel_recalc,
1001 static struct clk gpt7_ick = {
1003 .ops = &clkops_omap2_iclk_dflt_wait,
1005 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1006 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1007 .recalc = &followparent_recalc,
1010 static struct clk gpt7_fck = {
1012 .ops = &clkops_omap2_dflt_wait,
1013 .parent = &func_32k_ck,
1014 .clkdm_name = "core_l4_clkdm",
1015 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1016 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1017 .init = &omap2_init_clksel_parent,
1018 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1019 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1020 .clksel = omap24xx_gpt_clksel,
1021 .recalc = &omap2_clksel_recalc,
1024 static struct clk gpt8_ick = {
1026 .ops = &clkops_omap2_iclk_dflt_wait,
1028 .clkdm_name = "core_l4_clkdm",
1029 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1030 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1031 .recalc = &followparent_recalc,
1034 static struct clk gpt8_fck = {
1036 .ops = &clkops_omap2_dflt_wait,
1037 .parent = &func_32k_ck,
1038 .clkdm_name = "core_l4_clkdm",
1039 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1040 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1041 .init = &omap2_init_clksel_parent,
1042 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1043 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1044 .clksel = omap24xx_gpt_clksel,
1045 .recalc = &omap2_clksel_recalc,
1048 static struct clk gpt9_ick = {
1050 .ops = &clkops_omap2_iclk_dflt_wait,
1052 .clkdm_name = "core_l4_clkdm",
1053 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1054 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1055 .recalc = &followparent_recalc,
1058 static struct clk gpt9_fck = {
1060 .ops = &clkops_omap2_dflt_wait,
1061 .parent = &func_32k_ck,
1062 .clkdm_name = "core_l4_clkdm",
1063 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1064 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1065 .init = &omap2_init_clksel_parent,
1066 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1067 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1068 .clksel = omap24xx_gpt_clksel,
1069 .recalc = &omap2_clksel_recalc,
1072 static struct clk gpt10_ick = {
1073 .name = "gpt10_ick",
1074 .ops = &clkops_omap2_iclk_dflt_wait,
1076 .clkdm_name = "core_l4_clkdm",
1077 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1078 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1079 .recalc = &followparent_recalc,
1082 static struct clk gpt10_fck = {
1083 .name = "gpt10_fck",
1084 .ops = &clkops_omap2_dflt_wait,
1085 .parent = &func_32k_ck,
1086 .clkdm_name = "core_l4_clkdm",
1087 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1088 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1089 .init = &omap2_init_clksel_parent,
1090 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1091 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1092 .clksel = omap24xx_gpt_clksel,
1093 .recalc = &omap2_clksel_recalc,
1096 static struct clk gpt11_ick = {
1097 .name = "gpt11_ick",
1098 .ops = &clkops_omap2_iclk_dflt_wait,
1100 .clkdm_name = "core_l4_clkdm",
1101 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1102 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1103 .recalc = &followparent_recalc,
1106 static struct clk gpt11_fck = {
1107 .name = "gpt11_fck",
1108 .ops = &clkops_omap2_dflt_wait,
1109 .parent = &func_32k_ck,
1110 .clkdm_name = "core_l4_clkdm",
1111 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1112 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1113 .init = &omap2_init_clksel_parent,
1114 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1115 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1116 .clksel = omap24xx_gpt_clksel,
1117 .recalc = &omap2_clksel_recalc,
1120 static struct clk gpt12_ick = {
1121 .name = "gpt12_ick",
1122 .ops = &clkops_omap2_iclk_dflt_wait,
1124 .clkdm_name = "core_l4_clkdm",
1125 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1126 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1127 .recalc = &followparent_recalc,
1130 static struct clk gpt12_fck = {
1131 .name = "gpt12_fck",
1132 .ops = &clkops_omap2_dflt_wait,
1133 .parent = &secure_32k_ck,
1134 .clkdm_name = "core_l4_clkdm",
1135 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1136 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1137 .init = &omap2_init_clksel_parent,
1138 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1139 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1140 .clksel = omap24xx_gpt_clksel,
1141 .recalc = &omap2_clksel_recalc,
1144 static struct clk mcbsp1_ick = {
1145 .name = "mcbsp1_ick",
1146 .ops = &clkops_omap2_iclk_dflt_wait,
1148 .clkdm_name = "core_l4_clkdm",
1149 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1150 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1151 .recalc = &followparent_recalc,
1154 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1155 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1159 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1160 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1164 static const struct clksel mcbsp_fck_clksel[] = {
1165 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1166 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1170 static struct clk mcbsp1_fck = {
1171 .name = "mcbsp1_fck",
1172 .ops = &clkops_omap2_dflt_wait,
1173 .parent = &func_96m_ck,
1174 .init = &omap2_init_clksel_parent,
1175 .clkdm_name = "core_l4_clkdm",
1176 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1177 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1178 .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1179 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1180 .clksel = mcbsp_fck_clksel,
1181 .recalc = &omap2_clksel_recalc,
1184 static struct clk mcbsp2_ick = {
1185 .name = "mcbsp2_ick",
1186 .ops = &clkops_omap2_iclk_dflt_wait,
1188 .clkdm_name = "core_l4_clkdm",
1189 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1190 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1191 .recalc = &followparent_recalc,
1194 static struct clk mcbsp2_fck = {
1195 .name = "mcbsp2_fck",
1196 .ops = &clkops_omap2_dflt_wait,
1197 .parent = &func_96m_ck,
1198 .init = &omap2_init_clksel_parent,
1199 .clkdm_name = "core_l4_clkdm",
1200 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1201 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1202 .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1203 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
1204 .clksel = mcbsp_fck_clksel,
1205 .recalc = &omap2_clksel_recalc,
1208 static struct clk mcspi1_ick = {
1209 .name = "mcspi1_ick",
1210 .ops = &clkops_omap2_iclk_dflt_wait,
1212 .clkdm_name = "core_l4_clkdm",
1213 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1214 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1215 .recalc = &followparent_recalc,
1218 static struct clk mcspi1_fck = {
1219 .name = "mcspi1_fck",
1220 .ops = &clkops_omap2_dflt_wait,
1221 .parent = &func_48m_ck,
1222 .clkdm_name = "core_l4_clkdm",
1223 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1224 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1225 .recalc = &followparent_recalc,
1228 static struct clk mcspi2_ick = {
1229 .name = "mcspi2_ick",
1230 .ops = &clkops_omap2_iclk_dflt_wait,
1232 .clkdm_name = "core_l4_clkdm",
1233 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1234 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1235 .recalc = &followparent_recalc,
1238 static struct clk mcspi2_fck = {
1239 .name = "mcspi2_fck",
1240 .ops = &clkops_omap2_dflt_wait,
1241 .parent = &func_48m_ck,
1242 .clkdm_name = "core_l4_clkdm",
1243 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1244 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1245 .recalc = &followparent_recalc,
1248 static struct clk uart1_ick = {
1249 .name = "uart1_ick",
1250 .ops = &clkops_omap2_iclk_dflt_wait,
1252 .clkdm_name = "core_l4_clkdm",
1253 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1254 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1255 .recalc = &followparent_recalc,
1258 static struct clk uart1_fck = {
1259 .name = "uart1_fck",
1260 .ops = &clkops_omap2_dflt_wait,
1261 .parent = &func_48m_ck,
1262 .clkdm_name = "core_l4_clkdm",
1263 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1264 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1265 .recalc = &followparent_recalc,
1268 static struct clk uart2_ick = {
1269 .name = "uart2_ick",
1270 .ops = &clkops_omap2_iclk_dflt_wait,
1272 .clkdm_name = "core_l4_clkdm",
1273 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1274 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1275 .recalc = &followparent_recalc,
1278 static struct clk uart2_fck = {
1279 .name = "uart2_fck",
1280 .ops = &clkops_omap2_dflt_wait,
1281 .parent = &func_48m_ck,
1282 .clkdm_name = "core_l4_clkdm",
1283 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1284 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1285 .recalc = &followparent_recalc,
1288 static struct clk uart3_ick = {
1289 .name = "uart3_ick",
1290 .ops = &clkops_omap2_iclk_dflt_wait,
1292 .clkdm_name = "core_l4_clkdm",
1293 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1294 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1295 .recalc = &followparent_recalc,
1298 static struct clk uart3_fck = {
1299 .name = "uart3_fck",
1300 .ops = &clkops_omap2_dflt_wait,
1301 .parent = &func_48m_ck,
1302 .clkdm_name = "core_l4_clkdm",
1303 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1304 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1305 .recalc = &followparent_recalc,
1308 static struct clk gpios_ick = {
1309 .name = "gpios_ick",
1310 .ops = &clkops_omap2_iclk_dflt_wait,
1311 .parent = &wu_l4_ick,
1312 .clkdm_name = "wkup_clkdm",
1313 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1314 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1315 .recalc = &followparent_recalc,
1318 static struct clk gpios_fck = {
1319 .name = "gpios_fck",
1320 .ops = &clkops_omap2_dflt_wait,
1321 .parent = &func_32k_ck,
1322 .clkdm_name = "wkup_clkdm",
1323 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1324 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1325 .recalc = &followparent_recalc,
1328 static struct clk mpu_wdt_ick = {
1329 .name = "mpu_wdt_ick",
1330 .ops = &clkops_omap2_iclk_dflt_wait,
1331 .parent = &wu_l4_ick,
1332 .clkdm_name = "wkup_clkdm",
1333 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1334 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1335 .recalc = &followparent_recalc,
1338 static struct clk mpu_wdt_fck = {
1339 .name = "mpu_wdt_fck",
1340 .ops = &clkops_omap2_dflt_wait,
1341 .parent = &func_32k_ck,
1342 .clkdm_name = "wkup_clkdm",
1343 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1344 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1345 .recalc = &followparent_recalc,
1348 static struct clk sync_32k_ick = {
1349 .name = "sync_32k_ick",
1350 .ops = &clkops_omap2_iclk_dflt_wait,
1351 .parent = &wu_l4_ick,
1352 .clkdm_name = "wkup_clkdm",
1353 .flags = ENABLE_ON_INIT,
1354 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1355 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1356 .recalc = &followparent_recalc,
1359 static struct clk wdt1_ick = {
1361 .ops = &clkops_omap2_iclk_dflt_wait,
1362 .parent = &wu_l4_ick,
1363 .clkdm_name = "wkup_clkdm",
1364 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1365 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1366 .recalc = &followparent_recalc,
1369 static struct clk omapctrl_ick = {
1370 .name = "omapctrl_ick",
1371 .ops = &clkops_omap2_iclk_dflt_wait,
1372 .parent = &wu_l4_ick,
1373 .clkdm_name = "wkup_clkdm",
1374 .flags = ENABLE_ON_INIT,
1375 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1376 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1377 .recalc = &followparent_recalc,
1380 static struct clk cam_ick = {
1382 .ops = &clkops_omap2_iclk_dflt,
1384 .clkdm_name = "core_l4_clkdm",
1385 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1386 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1387 .recalc = &followparent_recalc,
1391 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
1392 * split into two separate clocks, since the parent clocks are different
1393 * and the clockdomains are also different.
1395 static struct clk cam_fck = {
1397 .ops = &clkops_omap2_dflt,
1398 .parent = &func_96m_ck,
1399 .clkdm_name = "core_l3_clkdm",
1400 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1401 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1402 .recalc = &followparent_recalc,
1405 static struct clk mailboxes_ick = {
1406 .name = "mailboxes_ick",
1407 .ops = &clkops_omap2_iclk_dflt_wait,
1409 .clkdm_name = "core_l4_clkdm",
1410 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1411 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1412 .recalc = &followparent_recalc,
1415 static struct clk wdt4_ick = {
1417 .ops = &clkops_omap2_iclk_dflt_wait,
1419 .clkdm_name = "core_l4_clkdm",
1420 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1421 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1422 .recalc = &followparent_recalc,
1425 static struct clk wdt4_fck = {
1427 .ops = &clkops_omap2_dflt_wait,
1428 .parent = &func_32k_ck,
1429 .clkdm_name = "core_l4_clkdm",
1430 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1431 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1432 .recalc = &followparent_recalc,
1435 static struct clk wdt3_ick = {
1437 .ops = &clkops_omap2_iclk_dflt_wait,
1439 .clkdm_name = "core_l4_clkdm",
1440 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1441 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1442 .recalc = &followparent_recalc,
1445 static struct clk wdt3_fck = {
1447 .ops = &clkops_omap2_dflt_wait,
1448 .parent = &func_32k_ck,
1449 .clkdm_name = "core_l4_clkdm",
1450 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1451 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1452 .recalc = &followparent_recalc,
1455 static struct clk mspro_ick = {
1456 .name = "mspro_ick",
1457 .ops = &clkops_omap2_iclk_dflt_wait,
1459 .clkdm_name = "core_l4_clkdm",
1460 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1461 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1462 .recalc = &followparent_recalc,
1465 static struct clk mspro_fck = {
1466 .name = "mspro_fck",
1467 .ops = &clkops_omap2_dflt_wait,
1468 .parent = &func_96m_ck,
1469 .clkdm_name = "core_l4_clkdm",
1470 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1471 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1472 .recalc = &followparent_recalc,
1475 static struct clk mmc_ick = {
1477 .ops = &clkops_omap2_iclk_dflt_wait,
1479 .clkdm_name = "core_l4_clkdm",
1480 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1481 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1482 .recalc = &followparent_recalc,
1485 static struct clk mmc_fck = {
1487 .ops = &clkops_omap2_dflt_wait,
1488 .parent = &func_96m_ck,
1489 .clkdm_name = "core_l4_clkdm",
1490 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1491 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1492 .recalc = &followparent_recalc,
1495 static struct clk fac_ick = {
1497 .ops = &clkops_omap2_iclk_dflt_wait,
1499 .clkdm_name = "core_l4_clkdm",
1500 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1501 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1502 .recalc = &followparent_recalc,
1505 static struct clk fac_fck = {
1507 .ops = &clkops_omap2_dflt_wait,
1508 .parent = &func_12m_ck,
1509 .clkdm_name = "core_l4_clkdm",
1510 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1511 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1512 .recalc = &followparent_recalc,
1515 static struct clk eac_ick = {
1517 .ops = &clkops_omap2_iclk_dflt_wait,
1519 .clkdm_name = "core_l4_clkdm",
1520 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1521 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1522 .recalc = &followparent_recalc,
1525 static struct clk eac_fck = {
1527 .ops = &clkops_omap2_dflt_wait,
1528 .parent = &func_96m_ck,
1529 .clkdm_name = "core_l4_clkdm",
1530 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1531 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1532 .recalc = &followparent_recalc,
1535 static struct clk hdq_ick = {
1537 .ops = &clkops_omap2_iclk_dflt_wait,
1539 .clkdm_name = "core_l4_clkdm",
1540 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1541 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1542 .recalc = &followparent_recalc,
1545 static struct clk hdq_fck = {
1547 .ops = &clkops_omap2_dflt_wait,
1548 .parent = &func_12m_ck,
1549 .clkdm_name = "core_l4_clkdm",
1550 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1551 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1552 .recalc = &followparent_recalc,
1555 static struct clk i2c2_ick = {
1557 .ops = &clkops_omap2_iclk_dflt_wait,
1559 .clkdm_name = "core_l4_clkdm",
1560 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1561 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1562 .recalc = &followparent_recalc,
1565 static struct clk i2c2_fck = {
1567 .ops = &clkops_omap2_dflt_wait,
1568 .parent = &func_12m_ck,
1569 .clkdm_name = "core_l4_clkdm",
1570 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1571 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1572 .recalc = &followparent_recalc,
1575 static struct clk i2c1_ick = {
1577 .ops = &clkops_omap2_iclk_dflt_wait,
1579 .clkdm_name = "core_l4_clkdm",
1580 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1581 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1582 .recalc = &followparent_recalc,
1585 static struct clk i2c1_fck = {
1587 .ops = &clkops_omap2_dflt_wait,
1588 .parent = &func_12m_ck,
1589 .clkdm_name = "core_l4_clkdm",
1590 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1591 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1592 .recalc = &followparent_recalc,
1596 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1597 * accesses derived from this data.
1599 static struct clk gpmc_fck = {
1601 .ops = &clkops_omap2_iclk_idle_only,
1602 .parent = &core_l3_ck,
1603 .flags = ENABLE_ON_INIT,
1604 .clkdm_name = "core_l3_clkdm",
1605 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1606 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
1607 .recalc = &followparent_recalc,
1610 static struct clk sdma_fck = {
1612 .ops = &clkops_null, /* RMK: missing? */
1613 .parent = &core_l3_ck,
1614 .clkdm_name = "core_l3_clkdm",
1615 .recalc = &followparent_recalc,
1619 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1620 * accesses derived from this data.
1622 static struct clk sdma_ick = {
1624 .ops = &clkops_omap2_iclk_idle_only,
1625 .parent = &core_l3_ck,
1626 .clkdm_name = "core_l3_clkdm",
1627 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1628 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1629 .recalc = &followparent_recalc,
1633 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1634 * accesses derived from this data.
1636 static struct clk sdrc_ick = {
1638 .ops = &clkops_omap2_iclk_idle_only,
1639 .parent = &core_l3_ck,
1640 .flags = ENABLE_ON_INIT,
1641 .clkdm_name = "core_l3_clkdm",
1642 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1643 .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
1644 .recalc = &followparent_recalc,
1647 static struct clk vlynq_ick = {
1648 .name = "vlynq_ick",
1649 .ops = &clkops_omap2_iclk_dflt_wait,
1650 .parent = &core_l3_ck,
1651 .clkdm_name = "core_l3_clkdm",
1652 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1653 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1654 .recalc = &followparent_recalc,
1657 static const struct clksel_rate vlynq_fck_96m_rates[] = {
1658 { .div = 1, .val = 0, .flags = RATE_IN_242X },
1662 static const struct clksel_rate vlynq_fck_core_rates[] = {
1663 { .div = 1, .val = 1, .flags = RATE_IN_242X },
1664 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1665 { .div = 3, .val = 3, .flags = RATE_IN_242X },
1666 { .div = 4, .val = 4, .flags = RATE_IN_242X },
1667 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1668 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1669 { .div = 9, .val = 9, .flags = RATE_IN_242X },
1670 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1671 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1672 { .div = 18, .val = 18, .flags = RATE_IN_242X },
1676 static const struct clksel vlynq_fck_clksel[] = {
1677 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
1678 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
1682 static struct clk vlynq_fck = {
1683 .name = "vlynq_fck",
1684 .ops = &clkops_omap2_dflt_wait,
1685 .parent = &func_96m_ck,
1686 .clkdm_name = "core_l3_clkdm",
1687 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1688 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1689 .init = &omap2_init_clksel_parent,
1690 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1691 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
1692 .clksel = vlynq_fck_clksel,
1693 .recalc = &omap2_clksel_recalc,
1696 static struct clk des_ick = {
1698 .ops = &clkops_omap2_iclk_dflt_wait,
1700 .clkdm_name = "core_l4_clkdm",
1701 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1702 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1703 .recalc = &followparent_recalc,
1706 static struct clk sha_ick = {
1708 .ops = &clkops_omap2_iclk_dflt_wait,
1710 .clkdm_name = "core_l4_clkdm",
1711 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1712 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1713 .recalc = &followparent_recalc,
1716 static struct clk rng_ick = {
1718 .ops = &clkops_omap2_iclk_dflt_wait,
1720 .clkdm_name = "core_l4_clkdm",
1721 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1722 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1723 .recalc = &followparent_recalc,
1726 static struct clk aes_ick = {
1728 .ops = &clkops_omap2_iclk_dflt_wait,
1730 .clkdm_name = "core_l4_clkdm",
1731 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1732 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1733 .recalc = &followparent_recalc,
1736 static struct clk pka_ick = {
1738 .ops = &clkops_omap2_iclk_dflt_wait,
1740 .clkdm_name = "core_l4_clkdm",
1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1742 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1743 .recalc = &followparent_recalc,
1746 static struct clk usb_fck = {
1748 .ops = &clkops_omap2_dflt_wait,
1749 .parent = &func_48m_ck,
1750 .clkdm_name = "core_l3_clkdm",
1751 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1752 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1753 .recalc = &followparent_recalc,
1757 * This clock is a composite clock which does entire set changes then
1758 * forces a rebalance. It keys on the MPU speed, but it really could
1759 * be any key speed part of a set in the rate table.
1761 * to really change a set, you need memory table sets which get changed
1762 * in sram, pre-notifiers & post notifiers, changing the top set, without
1763 * having low level display recalc's won't work... this is why dpm notifiers
1764 * work, isr's off, walk a list of clocks already _off_ and not messing with
1767 * This clock should have no parent. It embodies the entire upper level
1768 * active set. A parent will mess up some of the init also.
1770 static struct clk virt_prcm_set = {
1771 .name = "virt_prcm_set",
1772 .ops = &clkops_null,
1773 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1774 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
1775 .set_rate = &omap2_select_table_rate,
1776 .round_rate = &omap2_round_to_table_rate,
1781 * clkdev integration
1784 static struct omap_clk omap2420_clks[] = {
1785 /* external root sources */
1786 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X),
1787 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X),
1788 CLK(NULL, "osc_ck", &osc_ck, CK_242X),
1789 CLK(NULL, "sys_ck", &sys_ck, CK_242X),
1790 CLK(NULL, "alt_ck", &alt_ck, CK_242X),
1791 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_242X),
1792 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_242X),
1793 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X),
1794 /* internal analog sources */
1795 CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
1796 CLK(NULL, "apll96_ck", &apll96_ck, CK_242X),
1797 CLK(NULL, "apll54_ck", &apll54_ck, CK_242X),
1798 /* internal prcm root sources */
1799 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
1800 CLK(NULL, "core_ck", &core_ck, CK_242X),
1801 CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_242X),
1802 CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_242X),
1803 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
1804 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
1805 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
1806 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X),
1807 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
1808 CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
1809 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
1810 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
1811 CLK(NULL, "emul_ck", &emul_ck, CK_242X),
1812 /* mpu domain clocks */
1813 CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
1814 /* dsp domain clocks */
1815 CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
1816 CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_242X),
1817 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
1818 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
1819 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
1820 /* GFX domain clocks */
1821 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X),
1822 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X),
1823 CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
1824 /* DSS domain clocks */
1825 CLK("omapdss", "ick", &dss_ick, CK_242X),
1826 CLK("omapdss", "dss1_fck", &dss1_fck, CK_242X),
1827 CLK("omapdss", "dss2_fck", &dss2_fck, CK_242X),
1828 CLK("omapdss", "tv_fck", &dss_54m_fck, CK_242X),
1829 /* L3 domain clocks */
1830 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
1831 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
1832 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X),
1833 /* L4 domain clocks */
1834 CLK(NULL, "l4_ck", &l4_ck, CK_242X),
1835 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
1836 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X),
1837 /* virtual meta-group clock */
1838 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
1839 /* general l4 interface ck, multi-parent functional clk */
1840 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
1841 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
1842 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
1843 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X),
1844 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
1845 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X),
1846 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X),
1847 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X),
1848 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X),
1849 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X),
1850 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X),
1851 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X),
1852 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X),
1853 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X),
1854 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X),
1855 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X),
1856 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X),
1857 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X),
1858 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X),
1859 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X),
1860 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X),
1861 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X),
1862 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
1863 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
1864 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
1865 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_242X),
1866 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
1867 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_242X),
1868 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
1869 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_242X),
1870 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
1871 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_242X),
1872 CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
1873 CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
1874 CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
1875 CLK(NULL, "uart2_fck", &uart2_fck, CK_242X),
1876 CLK(NULL, "uart3_ick", &uart3_ick, CK_242X),
1877 CLK(NULL, "uart3_fck", &uart3_fck, CK_242X),
1878 CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
1879 CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
1880 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
1881 CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_242X),
1882 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
1883 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
1884 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
1885 CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
1886 CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
1887 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
1888 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
1889 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
1890 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
1891 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
1892 CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
1893 CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
1894 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
1895 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
1896 CLK(NULL, "fac_ick", &fac_ick, CK_242X),
1897 CLK(NULL, "fac_fck", &fac_fck, CK_242X),
1898 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
1899 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
1900 CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
1901 CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X),
1902 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
1903 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_242X),
1904 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
1905 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_242X),
1906 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
1907 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
1908 CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
1909 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
1910 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
1911 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
1912 CLK(NULL, "des_ick", &des_ick, CK_242X),
1913 CLK("omap-sham", "ick", &sha_ick, CK_242X),
1914 CLK("omap_rng", "ick", &rng_ick, CK_242X),
1915 CLK("omap-aes", "ick", &aes_ick, CK_242X),
1916 CLK(NULL, "pka_ick", &pka_ick, CK_242X),
1917 CLK(NULL, "usb_fck", &usb_fck, CK_242X),
1918 CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
1925 int __init omap2420_clk_init(void)
1927 const struct prcm_config *prcm;
1931 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1932 cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
1933 cpu_mask = RATE_IN_242X;
1934 rate_table = omap2420_rate_table;
1936 clk_init(&omap2_clk_functions);
1938 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1940 clk_preinit(c->lk.clk);
1942 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
1943 propagate_rate(&osc_ck);
1944 sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
1945 propagate_rate(&sys_ck);
1947 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1950 clk_register(c->lk.clk);
1951 omap2_init_clk_clkdm(c->lk.clk);
1954 /* Disable autoidle on all clocks; let the PM code enable it later */
1955 omap_clk_disable_autoidle_all();
1957 /* Check the MPU rate set by bootloader */
1958 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
1959 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1960 if (!(prcm->flags & cpu_mask))
1962 if (prcm->xtal_speed != sys_ck.rate)
1964 if (prcm->dpll_speed <= clkrate)
1967 curr_prcm_set = prcm;
1969 recalculate_root_clocks();
1971 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
1972 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1973 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1976 * Only enable those clocks we will need, let the drivers
1977 * enable other clocks as necessary
1979 clk_enable_init_clocks();
1981 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1982 vclk = clk_get(NULL, "virt_prcm_set");
1983 sclk = clk_get(NULL, "sys_ck");
1984 dclk = clk_get(NULL, "dpll_ck");