2 * linux/arch/arm/mach-omap1/time.c
6 * Copyright (C) 2004 Nokia Corporation
7 * Partial timer rewrite and additional dynamic tick timer support by
8 * Tony Lindgen <tony@atomide.com> and
9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
11 * MPU timer code based on the older MPU timer code for OMAP
12 * Copyright (C) 2000 RidgeRun, Inc.
13 * Author: Greg Lonnon <glonnon@ridgerun.com>
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 #include <linux/kernel.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/spinlock.h>
42 #include <linux/clk.h>
43 #include <linux/err.h>
44 #include <linux/clocksource.h>
45 #include <linux/clockchips.h>
48 #include <asm/system.h>
49 #include <mach/hardware.h>
52 #include <asm/sched_clock.h>
54 #include <asm/mach/irq.h>
55 #include <asm/mach/time.h>
57 #include <plat/common.h>
59 #ifdef CONFIG_OMAP_MPU_TIMER
61 #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
62 #define OMAP_MPU_TIMER_OFFSET 0x100
65 u32 cntl; /* CNTL_TIMER, R/W */
66 u32 load_tim; /* LOAD_TIM, W */
67 u32 read_tim; /* READ_TIM, R */
68 } omap_mpu_timer_regs_t;
70 #define omap_mpu_timer_base(n) \
71 ((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
72 (n)*OMAP_MPU_TIMER_OFFSET))
74 static inline unsigned long notrace omap_mpu_timer_read(int nr)
76 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
77 return timer->read_tim;
80 static inline void omap_mpu_set_autoreset(int nr)
82 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
84 timer->cntl = timer->cntl | MPU_TIMER_AR;
87 static inline void omap_mpu_remove_autoreset(int nr)
89 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
91 timer->cntl = timer->cntl & ~MPU_TIMER_AR;
94 static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
97 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
98 unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST);
100 if (autoreset) timerflags |= MPU_TIMER_AR;
102 timer->cntl = MPU_TIMER_CLOCK_ENABLE;
104 timer->load_tim = load_val;
106 timer->cntl = timerflags;
109 static inline void omap_mpu_timer_stop(int nr)
111 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
113 timer->cntl &= ~MPU_TIMER_ST;
117 * ---------------------------------------------------------------------------
118 * MPU timer 1 ... count down to zero, interrupt, reload
119 * ---------------------------------------------------------------------------
121 static int omap_mpu_set_next_event(unsigned long cycles,
122 struct clock_event_device *evt)
124 omap_mpu_timer_start(0, cycles, 0);
128 static void omap_mpu_set_mode(enum clock_event_mode mode,
129 struct clock_event_device *evt)
132 case CLOCK_EVT_MODE_PERIODIC:
133 omap_mpu_set_autoreset(0);
135 case CLOCK_EVT_MODE_ONESHOT:
136 omap_mpu_timer_stop(0);
137 omap_mpu_remove_autoreset(0);
139 case CLOCK_EVT_MODE_UNUSED:
140 case CLOCK_EVT_MODE_SHUTDOWN:
141 case CLOCK_EVT_MODE_RESUME:
146 static struct clock_event_device clockevent_mpu_timer1 = {
147 .name = "mpu_timer1",
148 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
150 .set_next_event = omap_mpu_set_next_event,
151 .set_mode = omap_mpu_set_mode,
154 static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
156 struct clock_event_device *evt = &clockevent_mpu_timer1;
158 evt->event_handler(evt);
163 static struct irqaction omap_mpu_timer1_irq = {
164 .name = "mpu_timer1",
165 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
166 .handler = omap_mpu_timer1_interrupt,
169 static __init void omap_init_mpu_timer(unsigned long rate)
171 setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
172 omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
174 clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC,
175 clockevent_mpu_timer1.shift);
176 clockevent_mpu_timer1.max_delta_ns =
177 clockevent_delta2ns(-1, &clockevent_mpu_timer1);
178 clockevent_mpu_timer1.min_delta_ns =
179 clockevent_delta2ns(1, &clockevent_mpu_timer1);
181 clockevent_mpu_timer1.cpumask = cpumask_of(0);
182 clockevents_register_device(&clockevent_mpu_timer1);
187 * ---------------------------------------------------------------------------
188 * MPU timer 2 ... free running 32-bit clock source and scheduler clock
189 * ---------------------------------------------------------------------------
192 static cycle_t mpu_read(struct clocksource *cs)
194 return ~omap_mpu_timer_read(1);
197 static struct clocksource clocksource_mpu = {
198 .name = "mpu_timer2",
201 .mask = CLOCKSOURCE_MASK(32),
202 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
205 static DEFINE_CLOCK_DATA(cd);
207 static inline unsigned long long notrace _omap_mpu_sched_clock(void)
209 u32 cyc = mpu_read(&clocksource_mpu);
210 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
213 #ifndef CONFIG_OMAP_32K_TIMER
214 unsigned long long notrace sched_clock(void)
216 return _omap_mpu_sched_clock();
219 static unsigned long long notrace omap_mpu_sched_clock(void)
221 return _omap_mpu_sched_clock();
225 static void notrace mpu_update_sched_clock(void)
227 u32 cyc = mpu_read(&clocksource_mpu);
228 update_sched_clock(&cd, cyc, (u32)~0);
231 static void __init omap_init_clocksource(unsigned long rate)
233 static char err[] __initdata = KERN_ERR
234 "%s: can't register clocksource!\n";
236 omap_mpu_timer_start(1, ~0, 1);
237 init_sched_clock(&cd, mpu_update_sched_clock, 32, rate);
239 if (clocksource_register_hz(&clocksource_mpu, rate))
240 printk(err, clocksource_mpu.name);
243 static void __init omap_mpu_timer_init(void)
245 struct clk *ck_ref = clk_get(NULL, "ck_ref");
248 BUG_ON(IS_ERR(ck_ref));
250 rate = clk_get_rate(ck_ref);
256 omap_init_mpu_timer(rate);
257 omap_init_clocksource(rate);
261 static inline void omap_mpu_timer_init(void)
263 pr_err("Bogus timer, should not happen\n");
265 #endif /* CONFIG_OMAP_MPU_TIMER */
267 #if defined(CONFIG_OMAP_MPU_TIMER) && defined(CONFIG_OMAP_32K_TIMER)
268 static unsigned long long (*preferred_sched_clock)(void);
270 unsigned long long notrace sched_clock(void)
272 if (!preferred_sched_clock)
275 return preferred_sched_clock();
278 static inline void preferred_sched_clock_init(bool use_32k_sched_clock)
280 if (use_32k_sched_clock)
281 preferred_sched_clock = omap_32k_sched_clock;
283 preferred_sched_clock = omap_mpu_sched_clock;
286 static inline void preferred_sched_clock_init(bool use_32k_sched_clcok)
291 static inline int omap_32k_timer_usable(void)
295 if (cpu_is_omap730() || cpu_is_omap15xx())
298 #ifdef CONFIG_OMAP_32K_TIMER
299 res = omap_32k_timer_init();
306 * ---------------------------------------------------------------------------
307 * Timer initialization
308 * ---------------------------------------------------------------------------
310 static void __init omap_timer_init(void)
312 if (omap_32k_timer_usable()) {
313 preferred_sched_clock_init(1);
315 omap_mpu_timer_init();
316 preferred_sched_clock_init(0);
320 struct sys_timer omap_timer = {
321 .init = omap_timer_init,