arch/arm/mach-omap1/time.c

   1 /*
   2  * linux/arch/arm/mach-omap1/time.c
   3  *
   4  * OMAP Timers
   5  *
   6  * Copyright (C) 2004 Nokia Corporation
   7  * Partial timer rewrite and additional dynamic tick timer support by
   8  * Tony Lindgen <tony@atomide.com> and
   9  * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *
  11  * MPU timer code based on the older MPU timer code for OMAP
  12  * Copyright (C) 2000 RidgeRun, Inc.
  13  * Author: Greg Lonnon <glonnon@ridgerun.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify it
  16  * under the terms of the GNU General Public License as published by the
  17  * Free Software Foundation; either version 2 of the License, or (at your
  18  * option) any later version.
  19  *
  20  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  21  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  22  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  23  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  26  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  27  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * You should have received a copy of the  GNU General Public License along
  32  * with this program; if not, write  to the Free Software Foundation, Inc.,
  33  * 675 Mass Ave, Cambridge, MA 02139, USA.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/init.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/spinlock.h>
  41 #include <linux/clk.h>
  42 #include <linux/err.h>
  43 #include <linux/clocksource.h>
  44 #include <linux/clockchips.h>
  45 #include <linux/io.h>
  46
  47 #include <asm/system.h>
  48 #include <mach/hardware.h>
  49 #include <asm/leds.h>
  50 #include <asm/irq.h>
  51 #include <asm/sched_clock.h>
  52
  53 #include <asm/mach/irq.h>
  54 #include <asm/mach/time.h>
  55
  56 #include <plat/common.h>
  57
  58 #ifdef CONFIG_OMAP_MPU_TIMER
  59
  60 #define OMAP_MPU_TIMER_BASE             OMAP_MPU_TIMER1_BASE
  61 #define OMAP_MPU_TIMER_OFFSET           0x100
  62
  63 typedef struct {
  64         u32 cntl;                       /* CNTL_TIMER, R/W */
  65         u32 load_tim;                   /* LOAD_TIM,   W */
  66         u32 read_tim;                   /* READ_TIM,   R */
  67 } omap_mpu_timer_regs_t;
  68
  69 #define omap_mpu_timer_base(n)                                                  \
  70 ((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE +        \
  71                                  (n)*OMAP_MPU_TIMER_OFFSET))
  72
  73 static inline unsigned long notrace omap_mpu_timer_read(int nr)
  74 {
  75         omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
  76         return readl(&timer->read_tim);
  77 }
  78
  79 static inline void omap_mpu_set_autoreset(int nr)
  80 {
  81         omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
  82
  83         writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl);
  84 }
  85
  86 static inline void omap_mpu_remove_autoreset(int nr)
  87 {
  88         omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
  89
  90         writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl);
  91 }
  92
  93 static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
  94                                         int autoreset)
  95 {
  96         omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
  97         unsigned int timerflags = MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST;
  98
  99         if (autoreset)
 100                 timerflags |= MPU_TIMER_AR;
 101
 102         writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl);
 103         udelay(1);
 104         writel(load_val, &timer->load_tim);
 105         udelay(1);
 106         writel(timerflags, &timer->cntl);
 107 }
 108
 109 static inline void omap_mpu_timer_stop(int nr)
 110 {
 111         omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
 112
 113         writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl);
 114 }
 115
 116 /*
 117  * ---------------------------------------------------------------------------
 118  * MPU timer 1 ... count down to zero, interrupt, reload
 119  * ---------------------------------------------------------------------------
 120  */
 121 static int omap_mpu_set_next_event(unsigned long cycles,
 122                                    struct clock_event_device *evt)
 123 {
 124         omap_mpu_timer_start(0, cycles, 0);
 125         return 0;
 126 }
 127
 128 static void omap_mpu_set_mode(enum clock_event_mode mode,
 129                               struct clock_event_device *evt)
 130 {
 131         switch (mode) {
 132         case CLOCK_EVT_MODE_PERIODIC:
 133                 omap_mpu_set_autoreset(0);
 134                 break;
 135         case CLOCK_EVT_MODE_ONESHOT:
 136                 omap_mpu_timer_stop(0);
 137                 omap_mpu_remove_autoreset(0);
 138                 break;
 139         case CLOCK_EVT_MODE_UNUSED:
 140         case CLOCK_EVT_MODE_SHUTDOWN:
 141         case CLOCK_EVT_MODE_RESUME:
 142                 break;
 143         }
 144 }
 145
 146 static struct clock_event_device clockevent_mpu_timer1 = {
 147         .name           = "mpu_timer1",
 148         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 149         .shift          = 32,
 150         .set_next_event = omap_mpu_set_next_event,
 151         .set_mode       = omap_mpu_set_mode,
 152 };
 153
 154 static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
 155 {
 156         struct clock_event_device *evt = &clockevent_mpu_timer1;
 157
 158         evt->event_handler(evt);
 159
 160         return IRQ_HANDLED;
 161 }
 162
 163 static struct irqaction omap_mpu_timer1_irq = {
 164         .name           = "mpu_timer1",
 165         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 166         .handler        = omap_mpu_timer1_interrupt,
 167 };
 168
 169 static __init void omap_init_mpu_timer(unsigned long rate)
 170 {
 171         setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
 172         omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
 173
 174         clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC,
 175                                             clockevent_mpu_timer1.shift);
 176         clockevent_mpu_timer1.max_delta_ns =
 177                 clockevent_delta2ns(-1, &clockevent_mpu_timer1);
 178         clockevent_mpu_timer1.min_delta_ns =
 179                 clockevent_delta2ns(1, &clockevent_mpu_timer1);
 180
 181         clockevent_mpu_timer1.cpumask = cpumask_of(0);
 182         clockevents_register_device(&clockevent_mpu_timer1);
 183 }
 184
 185
 186 /*
 187  * ---------------------------------------------------------------------------
 188  * MPU timer 2 ... free running 32-bit clock source and scheduler clock
 189  * ---------------------------------------------------------------------------
 190  */
 191
 192 static u32 notrace omap_mpu_read_sched_clock(void)
 193 {
 194         return ~omap_mpu_timer_read(1);
 195 }
 196
 197 static void __init omap_init_clocksource(unsigned long rate)
 198 {
 199         omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(1);
 200         static char err[] __initdata = KERN_ERR
 201                         "%s: can't register clocksource!\n";
 202
 203         omap_mpu_timer_start(1, ~0, 1);
 204         setup_sched_clock(omap_mpu_read_sched_clock, 32, rate);
 205
 206         if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate,
 207                         300, 32, clocksource_mmio_readl_down))
 208                 printk(err, "mpu_timer2");
 209 }
 210
 211 static void __init omap_mpu_timer_init(void)
 212 {
 213         struct clk      *ck_ref = clk_get(NULL, "ck_ref");
 214         unsigned long   rate;
 215
 216         BUG_ON(IS_ERR(ck_ref));
 217
 218         rate = clk_get_rate(ck_ref);
 219         clk_put(ck_ref);
 220
 221         /* PTV = 0 */
 222         rate /= 2;
 223
 224         omap_init_mpu_timer(rate);
 225         omap_init_clocksource(rate);
 226 }
 227
 228 #else
 229 static inline void omap_mpu_timer_init(void)
 230 {
 231         pr_err("Bogus timer, should not happen\n");
 232 }
 233 #endif  /* CONFIG_OMAP_MPU_TIMER */
 234
 235 static inline int omap_32k_timer_usable(void)
 236 {
 237         int res = false;
 238
 239         if (cpu_is_omap730() || cpu_is_omap15xx())
 240                 return res;
 241
 242 #ifdef CONFIG_OMAP_32K_TIMER
 243         res = omap_32k_timer_init();
 244 #endif
 245
 246         return res;
 247 }
 248
 249 /*
 250  * ---------------------------------------------------------------------------
 251  * Timer initialization
 252  * ---------------------------------------------------------------------------
 253  */
 254 static void __init omap1_timer_init(void)
 255 {
 256         if (!omap_32k_timer_usable())
 257                 omap_mpu_timer_init();
 258 }
 259
 260 struct sys_timer omap1_timer = {
 261         .init           = omap1_timer_init,
 262 };