arch/arm/mach-omap1/clock_data.c

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock_data.c
   3  *
   4  *  Copyright (C) 2004 - 2005, 2009 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/clk.h>
  15 #include <linux/io.h>
  16
  17 #include <asm/mach-types.h>  /* for machine_is_* */
  18
  19 #include <plat/clock.h>
  20 #include <plat/cpu.h>
  21 #include <plat/clkdev_omap.h>
  22 #include <plat/usb.h>   /* for OTG_BASE */
  23
  24 #include "clock.h"
  25
  26 /*------------------------------------------------------------------------
  27  * Omap1 clocks
  28  *-------------------------------------------------------------------------*/
  29
  30 /* XXX is this necessary? */
  31 static struct clk dummy_ck = {
  32         .name   = "dummy",
  33         .ops    = &clkops_dummy,
  34         .flags  = RATE_FIXED,
  35 };
  36
  37 static struct clk ck_ref = {
  38         .name           = "ck_ref",
  39         .ops            = &clkops_null,
  40         .rate           = 12000000,
  41 };
  42
  43 static struct clk ck_dpll1 = {
  44         .name           = "ck_dpll1",
  45         .ops            = &clkops_null,
  46         .parent         = &ck_ref,
  47 };
  48
  49 /*
  50  * FIXME: This clock seems to be necessary but no-one has asked for its
  51  * activation.  [ FIX: SoSSI, SSR ]
  52  */
  53 static struct arm_idlect1_clk ck_dpll1out = {
  54         .clk = {
  55                 .name           = "ck_dpll1out",
  56                 .ops            = &clkops_generic,
  57                 .parent         = &ck_dpll1,
  58                 .flags          = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
  59                                   ENABLE_ON_INIT,
  60                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
  61                 .enable_bit     = EN_CKOUT_ARM,
  62                 .recalc         = &followparent_recalc,
  63         },
  64         .idlect_shift   = 12,
  65 };
  66
  67 static struct clk sossi_ck = {
  68         .name           = "ck_sossi",
  69         .ops            = &clkops_generic,
  70         .parent         = &ck_dpll1out.clk,
  71         .flags          = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
  72         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
  73         .enable_bit     = 16,
  74         .recalc         = &omap1_sossi_recalc,
  75         .set_rate       = &omap1_set_sossi_rate,
  76 };
  77
  78 static struct clk arm_ck = {
  79         .name           = "arm_ck",
  80         .ops            = &clkops_null,
  81         .parent         = &ck_dpll1,
  82         .rate_offset    = CKCTL_ARMDIV_OFFSET,
  83         .recalc         = &omap1_ckctl_recalc,
  84         .round_rate     = omap1_clk_round_rate_ckctl_arm,
  85         .set_rate       = omap1_clk_set_rate_ckctl_arm,
  86 };
  87
  88 static struct arm_idlect1_clk armper_ck = {
  89         .clk = {
  90                 .name           = "armper_ck",
  91                 .ops            = &clkops_generic,
  92                 .parent         = &ck_dpll1,
  93                 .flags          = CLOCK_IDLE_CONTROL,
  94                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
  95                 .enable_bit     = EN_PERCK,
  96                 .rate_offset    = CKCTL_PERDIV_OFFSET,
  97                 .recalc         = &omap1_ckctl_recalc,
  98                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
  99                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 100         },
 101         .idlect_shift   = 2,
 102 };
 103
 104 /*
 105  * FIXME: This clock seems to be necessary but no-one has asked for its
 106  * activation.  [ GPIO code for 1510 ]
 107  */
 108 static struct clk arm_gpio_ck = {
 109         .name           = "arm_gpio_ck",
 110         .ops            = &clkops_generic,
 111         .parent         = &ck_dpll1,
 112         .flags          = ENABLE_ON_INIT,
 113         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 114         .enable_bit     = EN_GPIOCK,
 115         .recalc         = &followparent_recalc,
 116 };
 117
 118 static struct arm_idlect1_clk armxor_ck = {
 119         .clk = {
 120                 .name           = "armxor_ck",
 121                 .ops            = &clkops_generic,
 122                 .parent         = &ck_ref,
 123                 .flags          = CLOCK_IDLE_CONTROL,
 124                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 125                 .enable_bit     = EN_XORPCK,
 126                 .recalc         = &followparent_recalc,
 127         },
 128         .idlect_shift   = 1,
 129 };
 130
 131 static struct arm_idlect1_clk armtim_ck = {
 132         .clk = {
 133                 .name           = "armtim_ck",
 134                 .ops            = &clkops_generic,
 135                 .parent         = &ck_ref,
 136                 .flags          = CLOCK_IDLE_CONTROL,
 137                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 138                 .enable_bit     = EN_TIMCK,
 139                 .recalc         = &followparent_recalc,
 140         },
 141         .idlect_shift   = 9,
 142 };
 143
 144 static struct arm_idlect1_clk armwdt_ck = {
 145         .clk = {
 146                 .name           = "armwdt_ck",
 147                 .ops            = &clkops_generic,
 148                 .parent         = &ck_ref,
 149                 .flags          = CLOCK_IDLE_CONTROL,
 150                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 151                 .enable_bit     = EN_WDTCK,
 152                 .recalc         = &omap1_watchdog_recalc,
 153         },
 154         .idlect_shift   = 0,
 155 };
 156
 157 static struct clk arminth_ck16xx = {
 158         .name           = "arminth_ck",
 159         .ops            = &clkops_null,
 160         .parent         = &arm_ck,
 161         .recalc         = &followparent_recalc,
 162         /* Note: On 16xx the frequency can be divided by 2 by programming
 163          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 164          *
 165          * 1510 version is in TC clocks.
 166          */
 167 };
 168
 169 static struct clk dsp_ck = {
 170         .name           = "dsp_ck",
 171         .ops            = &clkops_generic,
 172         .parent         = &ck_dpll1,
 173         .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
 174         .enable_bit     = EN_DSPCK,
 175         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 176         .recalc         = &omap1_ckctl_recalc,
 177         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 178         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 179 };
 180
 181 static struct clk dspmmu_ck = {
 182         .name           = "dspmmu_ck",
 183         .ops            = &clkops_null,
 184         .parent         = &ck_dpll1,
 185         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 186         .recalc         = &omap1_ckctl_recalc,
 187         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 188         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 189 };
 190
 191 static struct clk dspper_ck = {
 192         .name           = "dspper_ck",
 193         .ops            = &clkops_dspck,
 194         .parent         = &ck_dpll1,
 195         .enable_reg     = DSP_IDLECT2,
 196         .enable_bit     = EN_PERCK,
 197         .rate_offset    = CKCTL_PERDIV_OFFSET,
 198         .recalc         = &omap1_ckctl_recalc_dsp_domain,
 199         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 200         .set_rate       = &omap1_clk_set_rate_dsp_domain,
 201 };
 202
 203 static struct clk dspxor_ck = {
 204         .name           = "dspxor_ck",
 205         .ops            = &clkops_dspck,
 206         .parent         = &ck_ref,
 207         .enable_reg     = DSP_IDLECT2,
 208         .enable_bit     = EN_XORPCK,
 209         .recalc         = &followparent_recalc,
 210 };
 211
 212 static struct clk dsptim_ck = {
 213         .name           = "dsptim_ck",
 214         .ops            = &clkops_dspck,
 215         .parent         = &ck_ref,
 216         .enable_reg     = DSP_IDLECT2,
 217         .enable_bit     = EN_DSPTIMCK,
 218         .recalc         = &followparent_recalc,
 219 };
 220
 221 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
 222 static struct arm_idlect1_clk tc_ck = {
 223         .clk = {
 224                 .name           = "tc_ck",
 225                 .ops            = &clkops_null,
 226                 .parent         = &ck_dpll1,
 227                 .flags          = CLOCK_IDLE_CONTROL,
 228                 .rate_offset    = CKCTL_TCDIV_OFFSET,
 229                 .recalc         = &omap1_ckctl_recalc,
 230                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 231                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 232         },
 233         .idlect_shift   = 6,
 234 };
 235
 236 static struct clk arminth_ck1510 = {
 237         .name           = "arminth_ck",
 238         .ops            = &clkops_null,
 239         .parent         = &tc_ck.clk,
 240         .recalc         = &followparent_recalc,
 241         /* Note: On 1510 the frequency follows TC_CK
 242          *
 243          * 16xx version is in MPU clocks.
 244          */
 245 };
 246
 247 static struct clk tipb_ck = {
 248         /* No-idle controlled by "tc_ck" */
 249         .name           = "tipb_ck",
 250         .ops            = &clkops_null,
 251         .parent         = &tc_ck.clk,
 252         .recalc         = &followparent_recalc,
 253 };
 254
 255 static struct clk l3_ocpi_ck = {
 256         /* No-idle controlled by "tc_ck" */
 257         .name           = "l3_ocpi_ck",
 258         .ops            = &clkops_generic,
 259         .parent         = &tc_ck.clk,
 260         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 261         .enable_bit     = EN_OCPI_CK,
 262         .recalc         = &followparent_recalc,
 263 };
 264
 265 static struct clk tc1_ck = {
 266         .name           = "tc1_ck",
 267         .ops            = &clkops_generic,
 268         .parent         = &tc_ck.clk,
 269         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 270         .enable_bit     = EN_TC1_CK,
 271         .recalc         = &followparent_recalc,
 272 };
 273
 274 /*
 275  * FIXME: This clock seems to be necessary but no-one has asked for its
 276  * activation.  [ pm.c (SRAM), CCP, Camera ]
 277  */
 278 static struct clk tc2_ck = {
 279         .name           = "tc2_ck",
 280         .ops            = &clkops_generic,
 281         .parent         = &tc_ck.clk,
 282         .flags          = ENABLE_ON_INIT,
 283         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 284         .enable_bit     = EN_TC2_CK,
 285         .recalc         = &followparent_recalc,
 286 };
 287
 288 static struct clk dma_ck = {
 289         /* No-idle controlled by "tc_ck" */
 290         .name           = "dma_ck",
 291         .ops            = &clkops_null,
 292         .parent         = &tc_ck.clk,
 293         .recalc         = &followparent_recalc,
 294 };
 295
 296 static struct clk dma_lcdfree_ck = {
 297         .name           = "dma_lcdfree_ck",
 298         .ops            = &clkops_null,
 299         .parent         = &tc_ck.clk,
 300         .recalc         = &followparent_recalc,
 301 };
 302
 303 static struct arm_idlect1_clk api_ck = {
 304         .clk = {
 305                 .name           = "api_ck",
 306                 .ops            = &clkops_generic,
 307                 .parent         = &tc_ck.clk,
 308                 .flags          = CLOCK_IDLE_CONTROL,
 309                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 310                 .enable_bit     = EN_APICK,
 311                 .recalc         = &followparent_recalc,
 312         },
 313         .idlect_shift   = 8,
 314 };
 315
 316 static struct arm_idlect1_clk lb_ck = {
 317         .clk = {
 318                 .name           = "lb_ck",
 319                 .ops            = &clkops_generic,
 320                 .parent         = &tc_ck.clk,
 321                 .flags          = CLOCK_IDLE_CONTROL,
 322                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 323                 .enable_bit     = EN_LBCK,
 324                 .recalc         = &followparent_recalc,
 325         },
 326         .idlect_shift   = 4,
 327 };
 328
 329 static struct clk rhea1_ck = {
 330         .name           = "rhea1_ck",
 331         .ops            = &clkops_null,
 332         .parent         = &tc_ck.clk,
 333         .recalc         = &followparent_recalc,
 334 };
 335
 336 static struct clk rhea2_ck = {
 337         .name           = "rhea2_ck",
 338         .ops            = &clkops_null,
 339         .parent         = &tc_ck.clk,
 340         .recalc         = &followparent_recalc,
 341 };
 342
 343 static struct clk lcd_ck_16xx = {
 344         .name           = "lcd_ck",
 345         .ops            = &clkops_generic,
 346         .parent         = &ck_dpll1,
 347         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 348         .enable_bit     = EN_LCDCK,
 349         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 350         .recalc         = &omap1_ckctl_recalc,
 351         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 352         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 353 };
 354
 355 static struct arm_idlect1_clk lcd_ck_1510 = {
 356         .clk = {
 357                 .name           = "lcd_ck",
 358                 .ops            = &clkops_generic,
 359                 .parent         = &ck_dpll1,
 360                 .flags          = CLOCK_IDLE_CONTROL,
 361                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 362                 .enable_bit     = EN_LCDCK,
 363                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
 364                 .recalc         = &omap1_ckctl_recalc,
 365                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 366                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 367         },
 368         .idlect_shift   = 3,
 369 };
 370
 371 static struct clk uart1_1510 = {
 372         .name           = "uart1_ck",
 373         .ops            = &clkops_null,
 374         /* Direct from ULPD, no real parent */
 375         .parent         = &armper_ck.clk,
 376         .rate           = 12000000,
 377         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 378         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 379         .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
 380         .set_rate       = &omap1_set_uart_rate,
 381         .recalc         = &omap1_uart_recalc,
 382 };
 383
 384 static struct uart_clk uart1_16xx = {
 385         .clk    = {
 386                 .name           = "uart1_ck",
 387                 .ops            = &clkops_uart,
 388                 /* Direct from ULPD, no real parent */
 389                 .parent         = &armper_ck.clk,
 390                 .rate           = 48000000,
 391                 .flags          = RATE_FIXED | ENABLE_REG_32BIT |
 392                                   CLOCK_NO_IDLE_PARENT,
 393                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 394                 .enable_bit     = 29,
 395         },
 396         .sysc_addr      = 0xfffb0054,
 397 };
 398
 399 static struct clk uart2_ck = {
 400         .name           = "uart2_ck",
 401         .ops            = &clkops_null,
 402         /* Direct from ULPD, no real parent */
 403         .parent         = &armper_ck.clk,
 404         .rate           = 12000000,
 405         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 406         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 407         .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
 408         .set_rate       = &omap1_set_uart_rate,
 409         .recalc         = &omap1_uart_recalc,
 410 };
 411
 412 static struct clk uart3_1510 = {
 413         .name           = "uart3_ck",
 414         .ops            = &clkops_null,
 415         /* Direct from ULPD, no real parent */
 416         .parent         = &armper_ck.clk,
 417         .rate           = 12000000,
 418         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 419         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 420         .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
 421         .set_rate       = &omap1_set_uart_rate,
 422         .recalc         = &omap1_uart_recalc,
 423 };
 424
 425 static struct uart_clk uart3_16xx = {
 426         .clk    = {
 427                 .name           = "uart3_ck",
 428                 .ops            = &clkops_uart,
 429                 /* Direct from ULPD, no real parent */
 430                 .parent         = &armper_ck.clk,
 431                 .rate           = 48000000,
 432                 .flags          = RATE_FIXED | ENABLE_REG_32BIT |
 433                                   CLOCK_NO_IDLE_PARENT,
 434                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 435                 .enable_bit     = 31,
 436         },
 437         .sysc_addr      = 0xfffb9854,
 438 };
 439
 440 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 441         .name           = "usb_clko",
 442         .ops            = &clkops_generic,
 443         /* Direct from ULPD, no parent */
 444         .rate           = 6000000,
 445         .flags          = RATE_FIXED | ENABLE_REG_32BIT,
 446         .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
 447         .enable_bit     = USB_MCLK_EN_BIT,
 448 };
 449
 450 static struct clk usb_hhc_ck1510 = {
 451         .name           = "usb_hhc_ck",
 452         .ops            = &clkops_generic,
 453         /* Direct from ULPD, no parent */
 454         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 455         .flags          = RATE_FIXED | ENABLE_REG_32BIT,
 456         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 457         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 458 };
 459
 460 static struct clk usb_hhc_ck16xx = {
 461         .name           = "usb_hhc_ck",
 462         .ops            = &clkops_generic,
 463         /* Direct from ULPD, no parent */
 464         .rate           = 48000000,
 465         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 466         .flags          = RATE_FIXED | ENABLE_REG_32BIT,
 467         .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
 468         .enable_bit     = 8 /* UHOST_EN */,
 469 };
 470
 471 static struct clk usb_dc_ck = {
 472         .name           = "usb_dc_ck",
 473         .ops            = &clkops_generic,
 474         /* Direct from ULPD, no parent */
 475         .rate           = 48000000,
 476         .flags          = RATE_FIXED,
 477         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 478         .enable_bit     = 4,
 479 };
 480
 481 static struct clk usb_dc_ck7xx = {
 482         .name           = "usb_dc_ck",
 483         .ops            = &clkops_generic,
 484         /* Direct from ULPD, no parent */
 485         .rate           = 48000000,
 486         .flags          = RATE_FIXED,
 487         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 488         .enable_bit     = 8,
 489 };
 490
 491 static struct clk mclk_1510 = {
 492         .name           = "mclk",
 493         .ops            = &clkops_generic,
 494         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 495         .rate           = 12000000,
 496         .flags          = RATE_FIXED,
 497         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 498         .enable_bit     = 6,
 499 };
 500
 501 static struct clk mclk_16xx = {
 502         .name           = "mclk",
 503         .ops            = &clkops_generic,
 504         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 505         .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
 506         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 507         .set_rate       = &omap1_set_ext_clk_rate,
 508         .round_rate     = &omap1_round_ext_clk_rate,
 509         .init           = &omap1_init_ext_clk,
 510 };
 511
 512 static struct clk bclk_1510 = {
 513         .name           = "bclk",
 514         .ops            = &clkops_generic,
 515         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 516         .rate           = 12000000,
 517         .flags          = RATE_FIXED,
 518 };
 519
 520 static struct clk bclk_16xx = {
 521         .name           = "bclk",
 522         .ops            = &clkops_generic,
 523         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 524         .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
 525         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 526         .set_rate       = &omap1_set_ext_clk_rate,
 527         .round_rate     = &omap1_round_ext_clk_rate,
 528         .init           = &omap1_init_ext_clk,
 529 };
 530
 531 static struct clk mmc1_ck = {
 532         .name           = "mmc_ck",
 533         .ops            = &clkops_generic,
 534         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 535         .parent         = &armper_ck.clk,
 536         .rate           = 48000000,
 537         .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 538         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 539         .enable_bit     = 23,
 540 };
 541
 542 static struct clk mmc2_ck = {
 543         .name           = "mmc_ck",
 544         .id             = 1,
 545         .ops            = &clkops_generic,
 546         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 547         .parent         = &armper_ck.clk,
 548         .rate           = 48000000,
 549         .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 550         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 551         .enable_bit     = 20,
 552 };
 553
 554 static struct clk mmc3_ck = {
 555         .name           = "mmc_ck",
 556         .id             = 2,
 557         .ops            = &clkops_generic,
 558         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 559         .parent         = &armper_ck.clk,
 560         .rate           = 48000000,
 561         .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 562         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 563         .enable_bit     = 12,
 564 };
 565
 566 static struct clk virtual_ck_mpu = {
 567         .name           = "mpu",
 568         .ops            = &clkops_null,
 569         .parent         = &arm_ck, /* Is smarter alias for */
 570         .recalc         = &followparent_recalc,
 571         .set_rate       = &omap1_select_table_rate,
 572         .round_rate     = &omap1_round_to_table_rate,
 573 };
 574
 575 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
 576 remains active during MPU idle whenever this is enabled */
 577 static struct clk i2c_fck = {
 578         .name           = "i2c_fck",
 579         .id             = 1,
 580         .ops            = &clkops_null,
 581         .flags          = CLOCK_NO_IDLE_PARENT,
 582         .parent         = &armxor_ck.clk,
 583         .recalc         = &followparent_recalc,
 584 };
 585
 586 static struct clk i2c_ick = {
 587         .name           = "i2c_ick",
 588         .id             = 1,
 589         .ops            = &clkops_null,
 590         .flags          = CLOCK_NO_IDLE_PARENT,
 591         .parent         = &armper_ck.clk,
 592         .recalc         = &followparent_recalc,
 593 };
 594
 595 /*
 596  * clkdev integration
 597  */
 598
 599 static struct omap_clk omap_clks[] = {
 600         /* non-ULPD clocks */
 601         CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310 | CK_7XX),
 602         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310 | CK_7XX),
 603         /* CK_GEN1 clocks */
 604         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
 605         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
 606         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
 607         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 608         CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
 609         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
 610         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
 611         CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
 612         CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
 613         CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
 614         CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
 615         CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
 616         /* CK_GEN2 clocks */
 617         CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
 618         CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
 619         CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
 620         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 621         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
 622         /* CK_GEN3 clocks */
 623         CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_7XX),
 624         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
 625         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX | CK_7XX),
 626         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
 627         CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
 628         CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
 629         CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
 630         CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310 | CK_7XX),
 631         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
 632         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
 633         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
 634         CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_7XX),
 635         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
 636         /* ULPD clocks */
 637         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
 638         CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
 639         CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
 640         CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
 641         CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
 642         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
 643         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
 644         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
 645         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
 646         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck7xx,  CK_7XX),
 647         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
 648         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
 649         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
 650         CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
 651         CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
 652         CLK("mmci-omap.0", "fck",       &mmc3_ck,       CK_7XX),
 653         CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
 654         CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
 655         CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
 656         /* Virtual clocks */
 657         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
 658         CLK("i2c_omap.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310 | CK_7XX),
 659         CLK("i2c_omap.1", "ick",        &i2c_ick,       CK_16XX),
 660         CLK("i2c_omap.1", "ick",        &dummy_ck,      CK_1510 | CK_310 | CK_7XX),
 661         CLK("omap1_spi100k.1", "fck",   &dummy_ck,      CK_7XX),
 662         CLK("omap1_spi100k.1", "ick",   &dummy_ck,      CK_7XX),
 663         CLK("omap1_spi100k.2", "fck",   &dummy_ck,      CK_7XX),
 664         CLK("omap1_spi100k.2", "ick",   &dummy_ck,      CK_7XX),
 665         CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
 666         CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
 667         CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
 668         CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
 669         CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
 670         CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
 671         CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
 672         CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 673         CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 674         CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 675 };
 676
 677 /*
 678  * init
 679  */
 680
 681 static struct clk_functions omap1_clk_functions = {
 682         .clk_enable             = omap1_clk_enable,
 683         .clk_disable            = omap1_clk_disable,
 684         .clk_round_rate         = omap1_clk_round_rate,
 685         .clk_set_rate           = omap1_clk_set_rate,
 686         .clk_disable_unused     = omap1_clk_disable_unused,
 687 };
 688
 689 int __init omap1_clk_init(void)
 690 {
 691         struct omap_clk *c;
 692         const struct omap_clock_config *info;
 693         int crystal_type = 0; /* Default 12 MHz */
 694         u32 reg, cpu_mask;
 695
 696 #ifdef CONFIG_DEBUG_LL
 697         /*
 698          * Resets some clocks that may be left on from bootloader,
 699          * but leaves serial clocks on.
 700          */
 701         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 702 #endif
 703
 704         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 705         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
 706         omap_writew(reg, SOFT_REQ_REG);
 707         if (!cpu_is_omap15xx())
 708                 omap_writew(0, SOFT_REQ_REG2);
 709
 710         clk_init(&omap1_clk_functions);
 711
 712         /* By default all idlect1 clocks are allowed to idle */
 713         arm_idlect1_mask = ~0;
 714
 715         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 716                 clk_preinit(c->lk.clk);
 717
 718         cpu_mask = 0;
 719         if (cpu_is_omap16xx())
 720                 cpu_mask |= CK_16XX;
 721         if (cpu_is_omap1510())
 722                 cpu_mask |= CK_1510;
 723         if (cpu_is_omap7xx())
 724                 cpu_mask |= CK_7XX;
 725         if (cpu_is_omap310())
 726                 cpu_mask |= CK_310;
 727
 728         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 729                 if (c->cpu & cpu_mask) {
 730                         clkdev_add(&c->lk);
 731                         clk_register(c->lk.clk);
 732                 }
 733
 734         /* Pointers to these clocks are needed by code in clock.c */
 735         api_ck_p = clk_get(NULL, "api_ck");
 736         ck_dpll1_p = clk_get(NULL, "ck_dpll1");
 737         ck_ref_p = clk_get(NULL, "ck_ref");
 738
 739         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 740         if (info != NULL) {
 741                 if (!cpu_is_omap15xx())
 742                         crystal_type = info->system_clock_type;
 743         }
 744
 745 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 746         ck_ref.rate = 13000000;
 747 #elif defined(CONFIG_ARCH_OMAP16XX)
 748         if (crystal_type == 2)
 749                 ck_ref.rate = 19200000;
 750 #endif
 751
 752         pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
 753                 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 754                 omap_readw(ARM_CKCTL));
 755
 756         /* We want to be in syncronous scalable mode */
 757         omap_writew(0x1000, ARM_SYSST);
 758
 759 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
 760         /* Use values set by bootloader. Determine PLL rate and recalculate
 761          * dependent clocks as if kernel had changed PLL or divisors.
 762          */
 763         {
 764                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 765
 766                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 767                 if (pll_ctl_val & 0x10) {
 768                         /* PLL enabled, apply multiplier and divisor */
 769                         if (pll_ctl_val & 0xf80)
 770                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 771                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 772                 } else {
 773                         /* PLL disabled, apply bypass divisor */
 774                         switch (pll_ctl_val & 0xc) {
 775                         case 0:
 776                                 break;
 777                         case 0x4:
 778                                 ck_dpll1.rate /= 2;
 779                                 break;
 780                         default:
 781                                 ck_dpll1.rate /= 4;
 782                                 break;
 783                         }
 784                 }
 785         }
 786 #else
 787         /* Find the highest supported frequency and enable it */
 788         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 789                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
 790                 /* Guess sane values (60MHz) */
 791                 omap_writew(0x2290, DPLL_CTL);
 792                 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
 793                 ck_dpll1.rate = 60000000;
 794         }
 795 #endif
 796         propagate_rate(&ck_dpll1);
 797         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 798         propagate_rate(&ck_ref);
 799         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
 800                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 801                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 802                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 803                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 804
 805 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
 806         /* Select slicer output as OMAP input clock */
 807         omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
 808 #endif
 809
 810         /* Amstrad Delta wants BCLK high when inactive */
 811         if (machine_is_ams_delta())
 812                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
 813                                 (1 << SDW_MCLK_INV_BIT),
 814                                 ULPD_CLOCK_CTRL);
 815
 816         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 817         /* (on 730, bit 13 must not be cleared) */
 818         if (cpu_is_omap7xx())
 819                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 820         else
 821                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 822
 823         /* Put DSP/MPUI into reset until needed */
 824         omap_writew(0, ARM_RSTCT1);
 825         omap_writew(1, ARM_RSTCT2);
 826         omap_writew(0x400, ARM_IDLECT1);
 827
 828         /*
 829          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 830          * of the ARM_IDLECT2 register must be set to zero. The power-on
 831          * default value of this bit is one.
 832          */
 833         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 834
 835         /*
 836          * Only enable those clocks we will need, let the drivers
 837          * enable other clocks as necessary
 838          */
 839         clk_enable(&armper_ck.clk);
 840         clk_enable(&armxor_ck.clk);
 841         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 842
 843         if (cpu_is_omap15xx())
 844                 clk_enable(&arm_gpio_ck);
 845
 846         return 0;
 847 }