arch/arm/mach-omap1/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.h
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
  14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
  15
  16 static int omap1_clk_enable_generic(struct clk * clk);
  17 static void omap1_clk_disable_generic(struct clk * clk);
  18 static void omap1_ckctl_recalc(struct clk * clk);
  19 static void omap1_watchdog_recalc(struct clk * clk);
  20 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
  21 static int omap1_clk_enable_dsp_domain(struct clk * clk);
  22 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
  23 static void omap1_clk_disable_dsp_domain(struct clk * clk);
  24 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
  25 static void omap1_uart_recalc(struct clk * clk);
  26 static int omap1_clk_enable_uart_functional(struct clk * clk);
  27 static void omap1_clk_disable_uart_functional(struct clk * clk);
  28 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
  29 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
  30 static void omap1_init_ext_clk(struct clk * clk);
  31 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
  32 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
  33 static int omap1_clk_enable(struct clk *clk);
  34 static void omap1_clk_disable(struct clk *clk);
  35
  36 struct mpu_rate {
  37         unsigned long           rate;
  38         unsigned long           xtal;
  39         unsigned long           pll_rate;
  40         __u16                   ckctl_val;
  41         __u16                   dpllctl_val;
  42 };
  43
  44 struct uart_clk {
  45         struct clk      clk;
  46         unsigned long   sysc_addr;
  47 };
  48
  49 /* Provide a method for preventing idling some ARM IDLECT clocks */
  50 struct arm_idlect1_clk {
  51         struct clk      clk;
  52         unsigned long   no_idle_count;
  53         __u8            idlect_shift;
  54 };
  55
  56 /* ARM_CKCTL bit shifts */
  57 #define CKCTL_PERDIV_OFFSET     0
  58 #define CKCTL_LCDDIV_OFFSET     2
  59 #define CKCTL_ARMDIV_OFFSET     4
  60 #define CKCTL_DSPDIV_OFFSET     6
  61 #define CKCTL_TCDIV_OFFSET      8
  62 #define CKCTL_DSPMMUDIV_OFFSET  10
  63 /*#define ARM_TIMXO             12*/
  64 #define EN_DSPCK                13
  65 /*#define ARM_INTHCK_SEL        14*/ /* Divide-by-2 for mpu inth_ck */
  66 /* DSP_CKCTL bit shifts */
  67 #define CKCTL_DSPPERDIV_OFFSET  0
  68
  69 /* ARM_IDLECT2 bit shifts */
  70 #define EN_WDTCK        0
  71 #define EN_XORPCK       1
  72 #define EN_PERCK        2
  73 #define EN_LCDCK        3
  74 #define EN_LBCK         4 /* Not on 1610/1710 */
  75 /*#define EN_HSABCK     5*/
  76 #define EN_APICK        6
  77 #define EN_TIMCK        7
  78 #define DMACK_REQ       8
  79 #define EN_GPIOCK       9 /* Not on 1610/1710 */
  80 /*#define EN_LBFREECK   10*/
  81 #define EN_CKOUT_ARM    11
  82
  83 /* ARM_IDLECT3 bit shifts */
  84 #define EN_OCPI_CK      0
  85 #define EN_TC1_CK       2
  86 #define EN_TC2_CK       4
  87
  88 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
  89 #define EN_DSPTIMCK     5
  90
  91 /* Various register defines for clock controls scattered around OMAP chip */
  92 #define USB_MCLK_EN_BIT         4       /* In ULPD_CLKC_CTRL */
  93 #define USB_HOST_HHC_UHOST_EN   9       /* In MOD_CONF_CTRL_0 */
  94 #define SWD_ULPD_PLL_CLK_REQ    1       /* In SWD_CLK_DIV_CTRL_SEL */
  95 #define COM_ULPD_PLL_CLK_REQ    1       /* In COM_CLK_DIV_CTRL_SEL */
  96 #define SWD_CLK_DIV_CTRL_SEL    0xfffe0874
  97 #define COM_CLK_DIV_CTRL_SEL    0xfffe0878
  98 #define SOFT_REQ_REG            0xfffe0834
  99 #define SOFT_REQ_REG2           0xfffe0880
 100
 101 /*-------------------------------------------------------------------------
 102  * Omap1 MPU rate table
 103  *-------------------------------------------------------------------------*/
 104 static struct mpu_rate rate_table[] = {
 105         /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
 106          * NOTE: Comment order here is different from bits in CKCTL value:
 107          * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
 108          */
 109 #if defined(CONFIG_OMAP_ARM_216MHZ)
 110         { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
 111 #endif
 112 #if defined(CONFIG_OMAP_ARM_195MHZ)
 113         { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
 114 #endif
 115 #if defined(CONFIG_OMAP_ARM_192MHZ)
 116         { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
 117         { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
 118         {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
 119         {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
 120         {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
 121 #endif
 122 #if defined(CONFIG_OMAP_ARM_182MHZ)
 123         { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
 124 #endif
 125 #if defined(CONFIG_OMAP_ARM_168MHZ)
 126         { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
 127 #endif
 128 #if defined(CONFIG_OMAP_ARM_150MHZ)
 129         { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
 130 #endif
 131 #if defined(CONFIG_OMAP_ARM_120MHZ)
 132         { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
 133 #endif
 134 #if defined(CONFIG_OMAP_ARM_96MHZ)
 135         {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
 136 #endif
 137 #if defined(CONFIG_OMAP_ARM_60MHZ)
 138         {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
 139 #endif
 140 #if defined(CONFIG_OMAP_ARM_30MHZ)
 141         {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
 142 #endif
 143         { 0, 0, 0, 0, 0 },
 144 };
 145
 146 /*-------------------------------------------------------------------------
 147  * Omap1 clocks
 148  *-------------------------------------------------------------------------*/
 149
 150 static struct clk ck_ref = {
 151         .name           = "ck_ref",
 152         .rate           = 12000000,
 153         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 154                           ALWAYS_ENABLED,
 155         .enable         = &omap1_clk_enable_generic,
 156         .disable        = &omap1_clk_disable_generic,
 157 };
 158
 159 static struct clk ck_dpll1 = {
 160         .name           = "ck_dpll1",
 161         .parent         = &ck_ref,
 162         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 163                           RATE_PROPAGATES | ALWAYS_ENABLED,
 164         .enable         = &omap1_clk_enable_generic,
 165         .disable        = &omap1_clk_disable_generic,
 166 };
 167
 168 static struct arm_idlect1_clk ck_dpll1out = {
 169         .clk = {
 170                 .name           = "ck_dpll1out",
 171                 .parent         = &ck_dpll1,
 172                 .flags          = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL,
 173                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 174                 .enable_bit     = EN_CKOUT_ARM,
 175                 .recalc         = &followparent_recalc,
 176                 .enable         = &omap1_clk_enable_generic,
 177                 .disable        = &omap1_clk_disable_generic,
 178         },
 179         .idlect_shift   = 12,
 180 };
 181
 182 static struct clk arm_ck = {
 183         .name           = "arm_ck",
 184         .parent         = &ck_dpll1,
 185         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 186                           RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
 187         .rate_offset    = CKCTL_ARMDIV_OFFSET,
 188         .recalc         = &omap1_ckctl_recalc,
 189         .enable         = &omap1_clk_enable_generic,
 190         .disable        = &omap1_clk_disable_generic,
 191 };
 192
 193 static struct arm_idlect1_clk armper_ck = {
 194         .clk = {
 195                 .name           = "armper_ck",
 196                 .parent         = &ck_dpll1,
 197                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 198                                   RATE_CKCTL | CLOCK_IDLE_CONTROL,
 199                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 200                 .enable_bit     = EN_PERCK,
 201                 .rate_offset    = CKCTL_PERDIV_OFFSET,
 202                 .recalc         = &omap1_ckctl_recalc,
 203                 .enable         = &omap1_clk_enable_generic,
 204                 .disable        = &omap1_clk_disable_generic,
 205         },
 206         .idlect_shift   = 2,
 207 };
 208
 209 static struct clk arm_gpio_ck = {
 210         .name           = "arm_gpio_ck",
 211         .parent         = &ck_dpll1,
 212         .flags          = CLOCK_IN_OMAP1510,
 213         .enable_reg     = (void __iomem *)ARM_IDLECT2,
 214         .enable_bit     = EN_GPIOCK,
 215         .recalc         = &followparent_recalc,
 216         .enable         = &omap1_clk_enable_generic,
 217         .disable        = &omap1_clk_disable_generic,
 218 };
 219
 220 static struct arm_idlect1_clk armxor_ck = {
 221         .clk = {
 222                 .name           = "armxor_ck",
 223                 .parent         = &ck_ref,
 224                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 225                                   CLOCK_IDLE_CONTROL,
 226                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 227                 .enable_bit     = EN_XORPCK,
 228                 .recalc         = &followparent_recalc,
 229                 .enable         = &omap1_clk_enable_generic,
 230                 .disable        = &omap1_clk_disable_generic,
 231         },
 232         .idlect_shift   = 1,
 233 };
 234
 235 static struct arm_idlect1_clk armtim_ck = {
 236         .clk = {
 237                 .name           = "armtim_ck",
 238                 .parent         = &ck_ref,
 239                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 240                                   CLOCK_IDLE_CONTROL,
 241                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 242                 .enable_bit     = EN_TIMCK,
 243                 .recalc         = &followparent_recalc,
 244                 .enable         = &omap1_clk_enable_generic,
 245                 .disable        = &omap1_clk_disable_generic,
 246         },
 247         .idlect_shift   = 9,
 248 };
 249
 250 static struct arm_idlect1_clk armwdt_ck = {
 251         .clk = {
 252                 .name           = "armwdt_ck",
 253                 .parent         = &ck_ref,
 254                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 255                                   CLOCK_IDLE_CONTROL,
 256                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 257                 .enable_bit     = EN_WDTCK,
 258                 .recalc         = &omap1_watchdog_recalc,
 259                 .enable         = &omap1_clk_enable_generic,
 260                 .disable        = &omap1_clk_disable_generic,
 261         },
 262         .idlect_shift   = 0,
 263 };
 264
 265 static struct clk arminth_ck16xx = {
 266         .name           = "arminth_ck",
 267         .parent         = &arm_ck,
 268         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 269         .recalc         = &followparent_recalc,
 270         /* Note: On 16xx the frequency can be divided by 2 by programming
 271          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 272          *
 273          * 1510 version is in TC clocks.
 274          */
 275         .enable         = &omap1_clk_enable_generic,
 276         .disable        = &omap1_clk_disable_generic,
 277 };
 278
 279 static struct clk dsp_ck = {
 280         .name           = "dsp_ck",
 281         .parent         = &ck_dpll1,
 282         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 283                           RATE_CKCTL,
 284         .enable_reg     = (void __iomem *)ARM_CKCTL,
 285         .enable_bit     = EN_DSPCK,
 286         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 287         .recalc         = &omap1_ckctl_recalc,
 288         .enable         = &omap1_clk_enable_generic,
 289         .disable        = &omap1_clk_disable_generic,
 290 };
 291
 292 static struct clk dspmmu_ck = {
 293         .name           = "dspmmu_ck",
 294         .parent         = &ck_dpll1,
 295         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 296                           RATE_CKCTL | ALWAYS_ENABLED,
 297         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 298         .recalc         = &omap1_ckctl_recalc,
 299         .enable         = &omap1_clk_enable_generic,
 300         .disable        = &omap1_clk_disable_generic,
 301 };
 302
 303 static struct clk dspper_ck = {
 304         .name           = "dspper_ck",
 305         .parent         = &ck_dpll1,
 306         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 307                           RATE_CKCTL | VIRTUAL_IO_ADDRESS,
 308         .enable_reg     = (void __iomem *)DSP_IDLECT2,
 309         .enable_bit     = EN_PERCK,
 310         .rate_offset    = CKCTL_PERDIV_OFFSET,
 311         .recalc         = &omap1_ckctl_recalc_dsp_domain,
 312         .set_rate       = &omap1_clk_set_rate_dsp_domain,
 313         .enable         = &omap1_clk_enable_dsp_domain,
 314         .disable        = &omap1_clk_disable_dsp_domain,
 315 };
 316
 317 static struct clk dspxor_ck = {
 318         .name           = "dspxor_ck",
 319         .parent         = &ck_ref,
 320         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 321                           VIRTUAL_IO_ADDRESS,
 322         .enable_reg     = (void __iomem *)DSP_IDLECT2,
 323         .enable_bit     = EN_XORPCK,
 324         .recalc         = &followparent_recalc,
 325         .enable         = &omap1_clk_enable_dsp_domain,
 326         .disable        = &omap1_clk_disable_dsp_domain,
 327 };
 328
 329 static struct clk dsptim_ck = {
 330         .name           = "dsptim_ck",
 331         .parent         = &ck_ref,
 332         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 333                           VIRTUAL_IO_ADDRESS,
 334         .enable_reg     = (void __iomem *)DSP_IDLECT2,
 335         .enable_bit     = EN_DSPTIMCK,
 336         .recalc         = &followparent_recalc,
 337         .enable         = &omap1_clk_enable_dsp_domain,
 338         .disable        = &omap1_clk_disable_dsp_domain,
 339 };
 340
 341 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
 342 static struct arm_idlect1_clk tc_ck = {
 343         .clk = {
 344                 .name           = "tc_ck",
 345                 .parent         = &ck_dpll1,
 346                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 347                                   CLOCK_IN_OMAP730 | RATE_CKCTL |
 348                                   RATE_PROPAGATES | ALWAYS_ENABLED |
 349                                   CLOCK_IDLE_CONTROL,
 350                 .rate_offset    = CKCTL_TCDIV_OFFSET,
 351                 .recalc         = &omap1_ckctl_recalc,
 352                 .enable         = &omap1_clk_enable_generic,
 353                 .disable        = &omap1_clk_disable_generic,
 354         },
 355         .idlect_shift   = 6,
 356 };
 357
 358 static struct clk arminth_ck1510 = {
 359         .name           = "arminth_ck",
 360         .parent         = &tc_ck.clk,
 361         .flags          = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
 362         .recalc         = &followparent_recalc,
 363         /* Note: On 1510 the frequency follows TC_CK
 364          *
 365          * 16xx version is in MPU clocks.
 366          */
 367         .enable         = &omap1_clk_enable_generic,
 368         .disable        = &omap1_clk_disable_generic,
 369 };
 370
 371 static struct clk tipb_ck = {
 372         /* No-idle controlled by "tc_ck" */
 373         .name           = "tibp_ck",
 374         .parent         = &tc_ck.clk,
 375         .flags          = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
 376         .recalc         = &followparent_recalc,
 377         .enable         = &omap1_clk_enable_generic,
 378         .disable        = &omap1_clk_disable_generic,
 379 };
 380
 381 static struct clk l3_ocpi_ck = {
 382         /* No-idle controlled by "tc_ck" */
 383         .name           = "l3_ocpi_ck",
 384         .parent         = &tc_ck.clk,
 385         .flags          = CLOCK_IN_OMAP16XX,
 386         .enable_reg     = (void __iomem *)ARM_IDLECT3,
 387         .enable_bit     = EN_OCPI_CK,
 388         .recalc         = &followparent_recalc,
 389         .enable         = &omap1_clk_enable_generic,
 390         .disable        = &omap1_clk_disable_generic,
 391 };
 392
 393 static struct clk tc1_ck = {
 394         .name           = "tc1_ck",
 395         .parent         = &tc_ck.clk,
 396         .flags          = CLOCK_IN_OMAP16XX,
 397         .enable_reg     = (void __iomem *)ARM_IDLECT3,
 398         .enable_bit     = EN_TC1_CK,
 399         .recalc         = &followparent_recalc,
 400         .enable         = &omap1_clk_enable_generic,
 401         .disable        = &omap1_clk_disable_generic,
 402 };
 403
 404 static struct clk tc2_ck = {
 405         .name           = "tc2_ck",
 406         .parent         = &tc_ck.clk,
 407         .flags          = CLOCK_IN_OMAP16XX,
 408         .enable_reg     = (void __iomem *)ARM_IDLECT3,
 409         .enable_bit     = EN_TC2_CK,
 410         .recalc         = &followparent_recalc,
 411         .enable         = &omap1_clk_enable_generic,
 412         .disable        = &omap1_clk_disable_generic,
 413 };
 414
 415 static struct clk dma_ck = {
 416         /* No-idle controlled by "tc_ck" */
 417         .name           = "dma_ck",
 418         .parent         = &tc_ck.clk,
 419         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 420                           ALWAYS_ENABLED,
 421         .recalc         = &followparent_recalc,
 422         .enable         = &omap1_clk_enable_generic,
 423         .disable        = &omap1_clk_disable_generic,
 424 };
 425
 426 static struct clk dma_lcdfree_ck = {
 427         .name           = "dma_lcdfree_ck",
 428         .parent         = &tc_ck.clk,
 429         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 430         .recalc         = &followparent_recalc,
 431         .enable         = &omap1_clk_enable_generic,
 432         .disable        = &omap1_clk_disable_generic,
 433 };
 434
 435 static struct arm_idlect1_clk api_ck = {
 436         .clk = {
 437                 .name           = "api_ck",
 438                 .parent         = &tc_ck.clk,
 439                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 440                                   CLOCK_IDLE_CONTROL,
 441                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 442                 .enable_bit     = EN_APICK,
 443                 .recalc         = &followparent_recalc,
 444                 .enable         = &omap1_clk_enable_generic,
 445                 .disable        = &omap1_clk_disable_generic,
 446         },
 447         .idlect_shift   = 8,
 448 };
 449
 450 static struct arm_idlect1_clk lb_ck = {
 451         .clk = {
 452                 .name           = "lb_ck",
 453                 .parent         = &tc_ck.clk,
 454                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IDLE_CONTROL,
 455                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 456                 .enable_bit     = EN_LBCK,
 457                 .recalc         = &followparent_recalc,
 458                 .enable         = &omap1_clk_enable_generic,
 459                 .disable        = &omap1_clk_disable_generic,
 460         },
 461         .idlect_shift   = 4,
 462 };
 463
 464 static struct clk rhea1_ck = {
 465         .name           = "rhea1_ck",
 466         .parent         = &tc_ck.clk,
 467         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 468         .recalc         = &followparent_recalc,
 469         .enable         = &omap1_clk_enable_generic,
 470         .disable        = &omap1_clk_disable_generic,
 471 };
 472
 473 static struct clk rhea2_ck = {
 474         .name           = "rhea2_ck",
 475         .parent         = &tc_ck.clk,
 476         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 477         .recalc         = &followparent_recalc,
 478         .enable         = &omap1_clk_enable_generic,
 479         .disable        = &omap1_clk_disable_generic,
 480 };
 481
 482 static struct clk lcd_ck_16xx = {
 483         .name           = "lcd_ck",
 484         .parent         = &ck_dpll1,
 485         .flags          = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
 486         .enable_reg     = (void __iomem *)ARM_IDLECT2,
 487         .enable_bit     = EN_LCDCK,
 488         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 489         .recalc         = &omap1_ckctl_recalc,
 490         .enable         = &omap1_clk_enable_generic,
 491         .disable        = &omap1_clk_disable_generic,
 492 };
 493
 494 static struct arm_idlect1_clk lcd_ck_1510 = {
 495         .clk = {
 496                 .name           = "lcd_ck",
 497                 .parent         = &ck_dpll1,
 498                 .flags          = CLOCK_IN_OMAP1510 | RATE_CKCTL |
 499                                   CLOCK_IDLE_CONTROL,
 500                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 501                 .enable_bit     = EN_LCDCK,
 502                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
 503                 .recalc         = &omap1_ckctl_recalc,
 504                 .enable         = &omap1_clk_enable_generic,
 505                 .disable        = &omap1_clk_disable_generic,
 506         },
 507         .idlect_shift   = 3,
 508 };
 509
 510 static struct clk uart1_1510 = {
 511         .name           = "uart1_ck",
 512         /* Direct from ULPD, no real parent */
 513         .parent         = &armper_ck.clk,
 514         .rate           = 12000000,
 515         .flags          = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT |
 516                           ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
 517         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 518         .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
 519         .set_rate       = &omap1_set_uart_rate,
 520         .recalc         = &omap1_uart_recalc,
 521         .enable         = &omap1_clk_enable_generic,
 522         .disable        = &omap1_clk_disable_generic,
 523 };
 524
 525 static struct uart_clk uart1_16xx = {
 526         .clk    = {
 527                 .name           = "uart1_ck",
 528                 /* Direct from ULPD, no real parent */
 529                 .parent         = &armper_ck.clk,
 530                 .rate           = 48000000,
 531                 .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED |
 532                                   ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 533                 .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 534                 .enable_bit     = 29,
 535                 .enable         = &omap1_clk_enable_uart_functional,
 536                 .disable        = &omap1_clk_disable_uart_functional,
 537         },
 538         .sysc_addr      = 0xfffb0054,
 539 };
 540
 541 static struct clk uart2_ck = {
 542         .name           = "uart2_ck",
 543         /* Direct from ULPD, no real parent */
 544         .parent         = &armper_ck.clk,
 545         .rate           = 12000000,
 546         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 547                           ENABLE_REG_32BIT | ALWAYS_ENABLED |
 548                           CLOCK_NO_IDLE_PARENT,
 549         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 550         .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
 551         .set_rate       = &omap1_set_uart_rate,
 552         .recalc         = &omap1_uart_recalc,
 553         .enable         = &omap1_clk_enable_generic,
 554         .disable        = &omap1_clk_disable_generic,
 555 };
 556
 557 static struct clk uart3_1510 = {
 558         .name           = "uart3_ck",
 559         /* Direct from ULPD, no real parent */
 560         .parent         = &armper_ck.clk,
 561         .rate           = 12000000,
 562         .flags          = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT |
 563                           ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
 564         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 565         .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
 566         .set_rate       = &omap1_set_uart_rate,
 567         .recalc         = &omap1_uart_recalc,
 568         .enable         = &omap1_clk_enable_generic,
 569         .disable        = &omap1_clk_disable_generic,
 570 };
 571
 572 static struct uart_clk uart3_16xx = {
 573         .clk    = {
 574                 .name           = "uart3_ck",
 575                 /* Direct from ULPD, no real parent */
 576                 .parent         = &armper_ck.clk,
 577                 .rate           = 48000000,
 578                 .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED |
 579                                   ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 580                 .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 581                 .enable_bit     = 31,
 582                 .enable         = &omap1_clk_enable_uart_functional,
 583                 .disable        = &omap1_clk_disable_uart_functional,
 584         },
 585         .sysc_addr      = 0xfffb9854,
 586 };
 587
 588 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 589         .name           = "usb_clko",
 590         /* Direct from ULPD, no parent */
 591         .rate           = 6000000,
 592         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 593                           RATE_FIXED | ENABLE_REG_32BIT,
 594         .enable_reg     = (void __iomem *)ULPD_CLOCK_CTRL,
 595         .enable_bit     = USB_MCLK_EN_BIT,
 596         .enable         = &omap1_clk_enable_generic,
 597         .disable        = &omap1_clk_disable_generic,
 598 };
 599
 600 static struct clk usb_hhc_ck1510 = {
 601         .name           = "usb_hhc_ck",
 602         /* Direct from ULPD, no parent */
 603         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 604         .flags          = CLOCK_IN_OMAP1510 |
 605                           RATE_FIXED | ENABLE_REG_32BIT,
 606         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 607         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 608         .enable         = &omap1_clk_enable_generic,
 609         .disable        = &omap1_clk_disable_generic,
 610 };
 611
 612 static struct clk usb_hhc_ck16xx = {
 613         .name           = "usb_hhc_ck",
 614         /* Direct from ULPD, no parent */
 615         .rate           = 48000000,
 616         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 617         .flags          = CLOCK_IN_OMAP16XX |
 618                           RATE_FIXED | ENABLE_REG_32BIT,
 619         .enable_reg     = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
 620         .enable_bit     = 8 /* UHOST_EN */,
 621         .enable         = &omap1_clk_enable_generic,
 622         .disable        = &omap1_clk_disable_generic,
 623 };
 624
 625 static struct clk usb_dc_ck = {
 626         .name           = "usb_dc_ck",
 627         /* Direct from ULPD, no parent */
 628         .rate           = 48000000,
 629         .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED,
 630         .enable_reg     = (void __iomem *)SOFT_REQ_REG,
 631         .enable_bit     = 4,
 632         .enable         = &omap1_clk_enable_generic,
 633         .disable        = &omap1_clk_disable_generic,
 634 };
 635
 636 static struct clk mclk_1510 = {
 637         .name           = "mclk",
 638         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 639         .rate           = 12000000,
 640         .flags          = CLOCK_IN_OMAP1510 | RATE_FIXED,
 641         .enable         = &omap1_clk_enable_generic,
 642         .disable        = &omap1_clk_disable_generic,
 643 };
 644
 645 static struct clk mclk_16xx = {
 646         .name           = "mclk",
 647         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 648         .flags          = CLOCK_IN_OMAP16XX,
 649         .enable_reg     = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
 650         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 651         .set_rate       = &omap1_set_ext_clk_rate,
 652         .round_rate     = &omap1_round_ext_clk_rate,
 653         .init           = &omap1_init_ext_clk,
 654         .enable         = &omap1_clk_enable_generic,
 655         .disable        = &omap1_clk_disable_generic,
 656 };
 657
 658 static struct clk bclk_1510 = {
 659         .name           = "bclk",
 660         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 661         .rate           = 12000000,
 662         .flags          = CLOCK_IN_OMAP1510 | RATE_FIXED,
 663         .enable         = &omap1_clk_enable_generic,
 664         .disable        = &omap1_clk_disable_generic,
 665 };
 666
 667 static struct clk bclk_16xx = {
 668         .name           = "bclk",
 669         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 670         .flags          = CLOCK_IN_OMAP16XX,
 671         .enable_reg     = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
 672         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 673         .set_rate       = &omap1_set_ext_clk_rate,
 674         .round_rate     = &omap1_round_ext_clk_rate,
 675         .init           = &omap1_init_ext_clk,
 676         .enable         = &omap1_clk_enable_generic,
 677         .disable        = &omap1_clk_disable_generic,
 678 };
 679
 680 static struct clk mmc1_ck = {
 681         .name           = "mmc1_ck",
 682         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 683         .parent         = &armper_ck.clk,
 684         .rate           = 48000000,
 685         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 686                           RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 687         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 688         .enable_bit     = 23,
 689         .enable         = &omap1_clk_enable_generic,
 690         .disable        = &omap1_clk_disable_generic,
 691 };
 692
 693 static struct clk mmc2_ck = {
 694         .name           = "mmc2_ck",
 695         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 696         .parent         = &armper_ck.clk,
 697         .rate           = 48000000,
 698         .flags          = CLOCK_IN_OMAP16XX |
 699                           RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 700         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 701         .enable_bit     = 20,
 702         .enable         = &omap1_clk_enable_generic,
 703         .disable        = &omap1_clk_disable_generic,
 704 };
 705
 706 static struct clk virtual_ck_mpu = {
 707         .name           = "mpu",
 708         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 709                           VIRTUAL_CLOCK | ALWAYS_ENABLED,
 710         .parent         = &arm_ck, /* Is smarter alias for */
 711         .recalc         = &followparent_recalc,
 712         .set_rate       = &omap1_select_table_rate,
 713         .round_rate     = &omap1_round_to_table_rate,
 714         .enable         = &omap1_clk_enable_generic,
 715         .disable        = &omap1_clk_disable_generic,
 716 };
 717
 718 static struct clk * onchip_clks[] = {
 719         /* non-ULPD clocks */
 720         &ck_ref,
 721         &ck_dpll1,
 722         /* CK_GEN1 clocks */
 723         &ck_dpll1out.clk,
 724         &arm_ck,
 725         &armper_ck.clk,
 726         &arm_gpio_ck,
 727         &armxor_ck.clk,
 728         &armtim_ck.clk,
 729         &armwdt_ck.clk,
 730         &arminth_ck1510,  &arminth_ck16xx,
 731         /* CK_GEN2 clocks */
 732         &dsp_ck,
 733         &dspmmu_ck,
 734         &dspper_ck,
 735         &dspxor_ck,
 736         &dsptim_ck,
 737         /* CK_GEN3 clocks */
 738         &tc_ck.clk,
 739         &tipb_ck,
 740         &l3_ocpi_ck,
 741         &tc1_ck,
 742         &tc2_ck,
 743         &dma_ck,
 744         &dma_lcdfree_ck,
 745         &api_ck.clk,
 746         &lb_ck.clk,
 747         &rhea1_ck,
 748         &rhea2_ck,
 749         &lcd_ck_16xx,
 750         &lcd_ck_1510.clk,
 751         /* ULPD clocks */
 752         &uart1_1510,
 753         &uart1_16xx.clk,
 754         &uart2_ck,
 755         &uart3_1510,
 756         &uart3_16xx.clk,
 757         &usb_clko,
 758         &usb_hhc_ck1510, &usb_hhc_ck16xx,
 759         &usb_dc_ck,
 760         &mclk_1510,  &mclk_16xx,
 761         &bclk_1510,  &bclk_16xx,
 762         &mmc1_ck,
 763         &mmc2_ck,
 764         /* Virtual clocks */
 765         &virtual_ck_mpu,
 766 };
 767
 768 #endif