arch/arm/mach-omap1/clock.c

   1 //kernel/linux-omap-fsample/arch/arm/mach-omap1/clock.c#2 - edit change 3808 (text)
   2 /*
   3  *  linux/arch/arm/mach-omap1/clock.c
   4  *
   5  *  Copyright (C) 2004 - 2005 Nokia corporation
   6  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   7  *
   8  *  Modified to use omap shared clock framework by
   9  *  Tony Lindgren <tony@atomide.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/list.h>
  18 #include <linux/errno.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21
  22 #include <asm/io.h>
  23
  24 #include <asm/arch/cpu.h>
  25 #include <asm/arch/usb.h>
  26 #include <asm/arch/clock.h>
  27 #include <asm/arch/sram.h>
  28
  29 #include "clock.h"
  30
  31 __u32 arm_idlect1_mask;
  32
  33 /*-------------------------------------------------------------------------
  34  * Omap1 specific clock functions
  35  *-------------------------------------------------------------------------*/
  36
  37 static void omap1_watchdog_recalc(struct clk * clk)
  38 {
  39         clk->rate = clk->parent->rate / 14;
  40 }
  41
  42 static void omap1_uart_recalc(struct clk * clk)
  43 {
  44         unsigned int val = omap_readl(clk->enable_reg);
  45         if (val & clk->enable_bit)
  46                 clk->rate = 48000000;
  47         else
  48                 clk->rate = 12000000;
  49 }
  50
  51 static int omap1_clk_enable_dsp_domain(struct clk *clk)
  52 {
  53         int retval;
  54
  55         retval = omap1_clk_enable(&api_ck.clk);
  56         if (!retval) {
  57                 retval = omap1_clk_enable_generic(clk);
  58                 omap1_clk_disable(&api_ck.clk);
  59         }
  60
  61         return retval;
  62 }
  63
  64 static void omap1_clk_disable_dsp_domain(struct clk *clk)
  65 {
  66         if (omap1_clk_enable(&api_ck.clk) == 0) {
  67                 omap1_clk_disable_generic(clk);
  68                 omap1_clk_disable(&api_ck.clk);
  69         }
  70 }
  71
  72 static int omap1_clk_enable_uart_functional(struct clk *clk)
  73 {
  74         int ret;
  75         struct uart_clk *uclk;
  76
  77         ret = omap1_clk_enable_generic(clk);
  78         if (ret == 0) {
  79                 /* Set smart idle acknowledgement mode */
  80                 uclk = (struct uart_clk *)clk;
  81                 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
  82                             uclk->sysc_addr);
  83         }
  84
  85         return ret;
  86 }
  87
  88 static void omap1_clk_disable_uart_functional(struct clk *clk)
  89 {
  90         struct uart_clk *uclk;
  91
  92         /* Set force idle acknowledgement mode */
  93         uclk = (struct uart_clk *)clk;
  94         omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
  95
  96         omap1_clk_disable_generic(clk);
  97 }
  98
  99 static void omap1_clk_allow_idle(struct clk *clk)
 100 {
 101         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 102
 103         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 104                 return;
 105
 106         if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
 107                 arm_idlect1_mask |= 1 << iclk->idlect_shift;
 108 }
 109
 110 static void omap1_clk_deny_idle(struct clk *clk)
 111 {
 112         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 113
 114         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 115                 return;
 116
 117         if (iclk->no_idle_count++ == 0)
 118                 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
 119 }
 120
 121 static __u16 verify_ckctl_value(__u16 newval)
 122 {
 123         /* This function checks for following limitations set
 124          * by the hardware (all conditions must be true):
 125          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 126          * ARM_CK >= TC_CK
 127          * DSP_CK >= TC_CK
 128          * DSPMMU_CK >= TC_CK
 129          *
 130          * In addition following rules are enforced:
 131          * LCD_CK <= TC_CK
 132          * ARMPER_CK <= TC_CK
 133          *
 134          * However, maximum frequencies are not checked for!
 135          */
 136         __u8 per_exp;
 137         __u8 lcd_exp;
 138         __u8 arm_exp;
 139         __u8 dsp_exp;
 140         __u8 tc_exp;
 141         __u8 dspmmu_exp;
 142
 143         per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
 144         lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
 145         arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
 146         dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
 147         tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
 148         dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
 149
 150         if (dspmmu_exp < dsp_exp)
 151                 dspmmu_exp = dsp_exp;
 152         if (dspmmu_exp > dsp_exp+1)
 153                 dspmmu_exp = dsp_exp+1;
 154         if (tc_exp < arm_exp)
 155                 tc_exp = arm_exp;
 156         if (tc_exp < dspmmu_exp)
 157                 tc_exp = dspmmu_exp;
 158         if (tc_exp > lcd_exp)
 159                 lcd_exp = tc_exp;
 160         if (tc_exp > per_exp)
 161                 per_exp = tc_exp;
 162
 163         newval &= 0xf000;
 164         newval |= per_exp << CKCTL_PERDIV_OFFSET;
 165         newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
 166         newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
 167         newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
 168         newval |= tc_exp << CKCTL_TCDIV_OFFSET;
 169         newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
 170
 171         return newval;
 172 }
 173
 174 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
 175 {
 176         /* Note: If target frequency is too low, this function will return 4,
 177          * which is invalid value. Caller must check for this value and act
 178          * accordingly.
 179          *
 180          * Note: This function does not check for following limitations set
 181          * by the hardware (all conditions must be true):
 182          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 183          * ARM_CK >= TC_CK
 184          * DSP_CK >= TC_CK
 185          * DSPMMU_CK >= TC_CK
 186          */
 187         unsigned long realrate;
 188         struct clk * parent;
 189         unsigned  dsor_exp;
 190
 191         if (unlikely(!(clk->flags & RATE_CKCTL)))
 192                 return -EINVAL;
 193
 194         parent = clk->parent;
 195         if (unlikely(parent == 0))
 196                 return -EIO;
 197
 198         realrate = parent->rate;
 199         for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
 200                 if (realrate <= rate)
 201                         break;
 202
 203                 realrate /= 2;
 204         }
 205
 206         return dsor_exp;
 207 }
 208
 209 static void omap1_ckctl_recalc(struct clk * clk)
 210 {
 211         int dsor;
 212
 213         /* Calculate divisor encoded as 2-bit exponent */
 214         dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
 215
 216         if (unlikely(clk->rate == clk->parent->rate / dsor))
 217                 return; /* No change, quick exit */
 218         clk->rate = clk->parent->rate / dsor;
 219
 220         if (unlikely(clk->flags & RATE_PROPAGATES))
 221                 propagate_rate(clk);
 222 }
 223
 224 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
 225 {
 226         int dsor;
 227
 228         /* Calculate divisor encoded as 2-bit exponent
 229          *
 230          * The clock control bits are in DSP domain,
 231          * so api_ck is needed for access.
 232          * Note that DSP_CKCTL virt addr = phys addr, so
 233          * we must use __raw_readw() instead of omap_readw().
 234          */
 235         omap1_clk_enable(&api_ck.clk);
 236         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
 237         omap1_clk_disable(&api_ck.clk);
 238
 239         if (unlikely(clk->rate == clk->parent->rate / dsor))
 240                 return; /* No change, quick exit */
 241         clk->rate = clk->parent->rate / dsor;
 242
 243         if (unlikely(clk->flags & RATE_PROPAGATES))
 244                 propagate_rate(clk);
 245 }
 246
 247 /* MPU virtual clock functions */
 248 static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
 249 {
 250         /* Find the highest supported frequency <= rate and switch to it */
 251         struct mpu_rate * ptr;
 252
 253         if (clk != &virtual_ck_mpu)
 254                 return -EINVAL;
 255
 256         for (ptr = rate_table; ptr->rate; ptr++) {
 257                 if (ptr->xtal != ck_ref.rate)
 258                         continue;
 259
 260                 /* DPLL1 cannot be reprogrammed without risking system crash */
 261                 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
 262                         continue;
 263
 264                 /* Can check only after xtal frequency check */
 265                 if (ptr->rate <= rate)
 266                         break;
 267         }
 268
 269         if (!ptr->rate)
 270                 return -EINVAL;
 271
 272         /*
 273          * In most cases we should not need to reprogram DPLL.
 274          * Reprogramming the DPLL is tricky, it must be done from SRAM.
 275          * (on 730, bit 13 must always be 1)
 276          */
 277         if (cpu_is_omap730())
 278                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
 279         else
 280                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 281
 282         ck_dpll1.rate = ptr->pll_rate;
 283         propagate_rate(&ck_dpll1);
 284         return 0;
 285 }
 286
 287 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
 288 {
 289         int  ret = -EINVAL;
 290         int  dsor_exp;
 291         __u16  regval;
 292
 293         if (clk->flags & RATE_CKCTL) {
 294                 dsor_exp = calc_dsor_exp(clk, rate);
 295                 if (dsor_exp > 3)
 296                         dsor_exp = -EINVAL;
 297                 if (dsor_exp < 0)
 298                         return dsor_exp;
 299
 300                 regval = __raw_readw(DSP_CKCTL);
 301                 regval &= ~(3 << clk->rate_offset);
 302                 regval |= dsor_exp << clk->rate_offset;
 303                 __raw_writew(regval, DSP_CKCTL);
 304                 clk->rate = clk->parent->rate / (1 << dsor_exp);
 305                 ret = 0;
 306         }
 307
 308         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
 309                 propagate_rate(clk);
 310
 311         return ret;
 312 }
 313
 314 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
 315 {
 316         /* Find the highest supported frequency <= rate */
 317         struct mpu_rate * ptr;
 318         long  highest_rate;
 319
 320         if (clk != &virtual_ck_mpu)
 321                 return -EINVAL;
 322
 323         highest_rate = -EINVAL;
 324
 325         for (ptr = rate_table; ptr->rate; ptr++) {
 326                 if (ptr->xtal != ck_ref.rate)
 327                         continue;
 328
 329                 highest_rate = ptr->rate;
 330
 331                 /* Can check only after xtal frequency check */
 332                 if (ptr->rate <= rate)
 333                         break;
 334         }
 335
 336         return highest_rate;
 337 }
 338
 339 static unsigned calc_ext_dsor(unsigned long rate)
 340 {
 341         unsigned dsor;
 342
 343         /* MCLK and BCLK divisor selection is not linear:
 344          * freq = 96MHz / dsor
 345          *
 346          * RATIO_SEL range: dsor <-> RATIO_SEL
 347          * 0..6: (RATIO_SEL+2) <-> (dsor-2)
 348          * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
 349          * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
 350          * can not be used.
 351          */
 352         for (dsor = 2; dsor < 96; ++dsor) {
 353                 if ((dsor & 1) && dsor > 8)
 354                         continue;
 355                 if (rate >= 96000000 / dsor)
 356                         break;
 357         }
 358         return dsor;
 359 }
 360
 361 /* Only needed on 1510 */
 362 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
 363 {
 364         unsigned int val;
 365
 366         val = omap_readl(clk->enable_reg);
 367         if (rate == 12000000)
 368                 val &= ~(1 << clk->enable_bit);
 369         else if (rate == 48000000)
 370                 val |= (1 << clk->enable_bit);
 371         else
 372                 return -EINVAL;
 373         omap_writel(val, clk->enable_reg);
 374         clk->rate = rate;
 375
 376         return 0;
 377 }
 378
 379 /* External clock (MCLK & BCLK) functions */
 380 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
 381 {
 382         unsigned dsor;
 383         __u16 ratio_bits;
 384
 385         dsor = calc_ext_dsor(rate);
 386         clk->rate = 96000000 / dsor;
 387         if (dsor > 8)
 388                 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
 389         else
 390                 ratio_bits = (dsor - 2) << 2;
 391
 392         ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
 393         omap_writew(ratio_bits, clk->enable_reg);
 394
 395         return 0;
 396 }
 397
 398 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
 399 {
 400         return 96000000 / calc_ext_dsor(rate);
 401 }
 402
 403 static void omap1_init_ext_clk(struct clk * clk)
 404 {
 405         unsigned dsor;
 406         __u16 ratio_bits;
 407
 408         /* Determine current rate and ensure clock is based on 96MHz APLL */
 409         ratio_bits = omap_readw(clk->enable_reg) & ~1;
 410         omap_writew(ratio_bits, clk->enable_reg);
 411
 412         ratio_bits = (ratio_bits & 0xfc) >> 2;
 413         if (ratio_bits > 6)
 414                 dsor = (ratio_bits - 6) * 2 + 8;
 415         else
 416                 dsor = ratio_bits + 2;
 417
 418         clk-> rate = 96000000 / dsor;
 419 }
 420
 421 static int omap1_clk_enable(struct clk *clk)
 422 {
 423         int ret = 0;
 424         if (clk->usecount++ == 0) {
 425                 if (likely(clk->parent)) {
 426                         ret = omap1_clk_enable(clk->parent);
 427
 428                         if (unlikely(ret != 0)) {
 429                                 clk->usecount--;
 430                                 return ret;
 431                         }
 432
 433                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 434                                 if (!cpu_is_omap24xx())
 435                                         omap1_clk_deny_idle(clk->parent);
 436                 }
 437
 438                 ret = clk->enable(clk);
 439
 440                 if (unlikely(ret != 0) && clk->parent) {
 441                         omap1_clk_disable(clk->parent);
 442                         clk->usecount--;
 443                 }
 444         }
 445
 446         return ret;
 447 }
 448
 449 static void omap1_clk_disable(struct clk *clk)
 450 {
 451         if (clk->usecount > 0 && !(--clk->usecount)) {
 452                 clk->disable(clk);
 453                 if (likely(clk->parent)) {
 454                         omap1_clk_disable(clk->parent);
 455                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 456                                 if (!cpu_is_omap24xx())
 457                                         omap1_clk_allow_idle(clk->parent);
 458                 }
 459         }
 460 }
 461
 462 static int omap1_clk_enable_generic(struct clk *clk)
 463 {
 464         __u16 regval16;
 465         __u32 regval32;
 466
 467         if (clk->flags & ALWAYS_ENABLED)
 468                 return 0;
 469
 470         if (unlikely(clk->enable_reg == 0)) {
 471                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 472                        clk->name);
 473                 return 0;
 474         }
 475
 476         if (clk->flags & ENABLE_REG_32BIT) {
 477                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 478                         regval32 = __raw_readl(clk->enable_reg);
 479                         regval32 |= (1 << clk->enable_bit);
 480                         __raw_writel(regval32, clk->enable_reg);
 481                 } else {
 482                         regval32 = omap_readl(clk->enable_reg);
 483                         regval32 |= (1 << clk->enable_bit);
 484                         omap_writel(regval32, clk->enable_reg);
 485                 }
 486         } else {
 487                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 488                         regval16 = __raw_readw(clk->enable_reg);
 489                         regval16 |= (1 << clk->enable_bit);
 490                         __raw_writew(regval16, clk->enable_reg);
 491                 } else {
 492                         regval16 = omap_readw(clk->enable_reg);
 493                         regval16 |= (1 << clk->enable_bit);
 494                         omap_writew(regval16, clk->enable_reg);
 495                 }
 496         }
 497
 498         return 0;
 499 }
 500
 501 static void omap1_clk_disable_generic(struct clk *clk)
 502 {
 503         __u16 regval16;
 504         __u32 regval32;
 505
 506         if (clk->enable_reg == 0)
 507                 return;
 508
 509         if (clk->flags & ENABLE_REG_32BIT) {
 510                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 511                         regval32 = __raw_readl(clk->enable_reg);
 512                         regval32 &= ~(1 << clk->enable_bit);
 513                         __raw_writel(regval32, clk->enable_reg);
 514                 } else {
 515                         regval32 = omap_readl(clk->enable_reg);
 516                         regval32 &= ~(1 << clk->enable_bit);
 517                         omap_writel(regval32, clk->enable_reg);
 518                 }
 519         } else {
 520                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 521                         regval16 = __raw_readw(clk->enable_reg);
 522                         regval16 &= ~(1 << clk->enable_bit);
 523                         __raw_writew(regval16, clk->enable_reg);
 524                 } else {
 525                         regval16 = omap_readw(clk->enable_reg);
 526                         regval16 &= ~(1 << clk->enable_bit);
 527                         omap_writew(regval16, clk->enable_reg);
 528                 }
 529         }
 530 }
 531
 532 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 533 {
 534         int dsor_exp;
 535
 536         if (clk->flags & RATE_FIXED)
 537                 return clk->rate;
 538
 539         if (clk->flags & RATE_CKCTL) {
 540                 dsor_exp = calc_dsor_exp(clk, rate);
 541                 if (dsor_exp < 0)
 542                         return dsor_exp;
 543                 if (dsor_exp > 3)
 544                         dsor_exp = 3;
 545                 return clk->parent->rate / (1 << dsor_exp);
 546         }
 547
 548         if(clk->round_rate != 0)
 549                 return clk->round_rate(clk, rate);
 550
 551         return clk->rate;
 552 }
 553
 554 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 555 {
 556         int  ret = -EINVAL;
 557         int  dsor_exp;
 558         __u16  regval;
 559
 560         if (clk->set_rate)
 561                 ret = clk->set_rate(clk, rate);
 562         else if (clk->flags & RATE_CKCTL) {
 563                 dsor_exp = calc_dsor_exp(clk, rate);
 564                 if (dsor_exp > 3)
 565                         dsor_exp = -EINVAL;
 566                 if (dsor_exp < 0)
 567                         return dsor_exp;
 568
 569                 regval = omap_readw(ARM_CKCTL);
 570                 regval &= ~(3 << clk->rate_offset);
 571                 regval |= dsor_exp << clk->rate_offset;
 572                 regval = verify_ckctl_value(regval);
 573                 omap_writew(regval, ARM_CKCTL);
 574                 clk->rate = clk->parent->rate / (1 << dsor_exp);
 575                 ret = 0;
 576         }
 577
 578         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
 579                 propagate_rate(clk);
 580
 581         return ret;
 582 }
 583
 584 /*-------------------------------------------------------------------------
 585  * Omap1 clock reset and init functions
 586  *-------------------------------------------------------------------------*/
 587
 588 #ifdef CONFIG_OMAP_RESET_CLOCKS
 589 /*
 590  * Resets some clocks that may be left on from bootloader,
 591  * but leaves serial clocks on. See also omap_late_clk_reset().
 592  */
 593 static inline void omap1_early_clk_reset(void)
 594 {
 595         //omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 596 }
 597
 598 static int __init omap1_late_clk_reset(void)
 599 {
 600         /* Turn off all unused clocks */
 601         struct clk *p;
 602         __u32 regval32;
 603
 604         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 605         regval32 = omap_readw(SOFT_REQ_REG) & (1 << 4);
 606         omap_writew(regval32, SOFT_REQ_REG);
 607         omap_writew(0, SOFT_REQ_REG2);
 608
 609         list_for_each_entry(p, &clocks, node) {
 610                 if (p->usecount > 0 || (p->flags & ALWAYS_ENABLED) ||
 611                         p->enable_reg == 0)
 612                         continue;
 613
 614                 /* Clocks in the DSP domain need api_ck. Just assume bootloader
 615                  * has not enabled any DSP clocks */
 616                 if ((u32)p->enable_reg == DSP_IDLECT2) {
 617                         printk(KERN_INFO "Skipping reset check for DSP domain "
 618                                "clock \"%s\"\n", p->name);
 619                         continue;
 620                 }
 621
 622                 /* Is the clock already disabled? */
 623                 if (p->flags & ENABLE_REG_32BIT) {
 624                         if (p->flags & VIRTUAL_IO_ADDRESS)
 625                                 regval32 = __raw_readl(p->enable_reg);
 626                         else
 627                                 regval32 = omap_readl(p->enable_reg);
 628                 } else {
 629                         if (p->flags & VIRTUAL_IO_ADDRESS)
 630                                 regval32 = __raw_readw(p->enable_reg);
 631                         else
 632                                 regval32 = omap_readw(p->enable_reg);
 633                 }
 634
 635                 if ((regval32 & (1 << p->enable_bit)) == 0)
 636                         continue;
 637
 638                 /* FIXME: This clock seems to be necessary but no-one
 639                  * has asked for its activation. */
 640                 if (p == &tc2_ck         // FIX: pm.c (SRAM), CCP, Camera
 641                     || p == &ck_dpll1out.clk // FIX: SoSSI, SSR
 642                     || p == &arm_gpio_ck // FIX: GPIO code for 1510
 643                     ) {
 644                         printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
 645                                p->name);
 646                         continue;
 647                 }
 648
 649                 printk(KERN_INFO "Disabling unused clock \"%s\"... ", p->name);
 650                 p->disable(p);
 651                 printk(" done\n");
 652         }
 653
 654         return 0;
 655 }
 656 late_initcall(omap1_late_clk_reset);
 657
 658 #else
 659 #define omap1_early_clk_reset() {}
 660 #endif
 661
 662 static struct clk_functions omap1_clk_functions = {
 663         .clk_enable             = omap1_clk_enable,
 664         .clk_disable            = omap1_clk_disable,
 665         .clk_round_rate         = omap1_clk_round_rate,
 666         .clk_set_rate           = omap1_clk_set_rate,
 667 };
 668
 669 int __init omap1_clk_init(void)
 670 {
 671         struct clk ** clkp;
 672         const struct omap_clock_config *info;
 673         int crystal_type = 0; /* Default 12 MHz */
 674
 675         omap1_early_clk_reset();
 676         clk_init(&omap1_clk_functions);
 677
 678         /* By default all idlect1 clocks are allowed to idle */
 679         arm_idlect1_mask = ~0;
 680
 681         for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
 682                 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
 683                         clk_register(*clkp);
 684                         continue;
 685                 }
 686
 687                 if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
 688                         clk_register(*clkp);
 689                         continue;
 690                 }
 691
 692                 if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
 693                         clk_register(*clkp);
 694                         continue;
 695                 }
 696
 697                 if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) {
 698                         clk_register(*clkp);
 699                         continue;
 700                 }
 701         }
 702
 703         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 704         if (info != NULL) {
 705                 if (!cpu_is_omap1510())
 706                         crystal_type = info->system_clock_type;
 707         }
 708
 709 #if defined(CONFIG_ARCH_OMAP730)
 710         ck_ref.rate = 13000000;
 711 #elif defined(CONFIG_ARCH_OMAP16XX)
 712         if (crystal_type == 2)
 713                 ck_ref.rate = 19200000;
 714 #endif
 715
 716         printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
 717                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 718                omap_readw(ARM_CKCTL));
 719
 720         /* We want to be in syncronous scalable mode */
 721         omap_writew(0x1000, ARM_SYSST);
 722
 723 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
 724         /* Use values set by bootloader. Determine PLL rate and recalculate
 725          * dependent clocks as if kernel had changed PLL or divisors.
 726          */
 727         {
 728                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 729
 730                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 731                 if (pll_ctl_val & 0x10) {
 732                         /* PLL enabled, apply multiplier and divisor */
 733                         if (pll_ctl_val & 0xf80)
 734                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 735                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 736                 } else {
 737                         /* PLL disabled, apply bypass divisor */
 738                         switch (pll_ctl_val & 0xc) {
 739                         case 0:
 740                                 break;
 741                         case 0x4:
 742                                 ck_dpll1.rate /= 2;
 743                                 break;
 744                         default:
 745                                 ck_dpll1.rate /= 4;
 746                                 break;
 747                         }
 748                 }
 749         }
 750         propagate_rate(&ck_dpll1);
 751 #else
 752         /* Find the highest supported frequency and enable it */
 753         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 754                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
 755                 /* Guess sane values (60MHz) */
 756                 omap_writew(0x2290, DPLL_CTL);
 757                 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
 758                 ck_dpll1.rate = 60000000;
 759                 propagate_rate(&ck_dpll1);
 760         }
 761 #endif
 762         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 763         propagate_rate(&ck_ref);
 764         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
 765                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 766                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 767                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 768                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 769
 770 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
 771         /* Select slicer output as OMAP input clock */
 772         omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
 773 #endif
 774
 775         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 776         /* (on 730, bit 13 must not be cleared) */
 777         if (cpu_is_omap730())
 778                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 779         else
 780                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 781
 782         /* Put DSP/MPUI into reset until needed */
 783         omap_writew(0, ARM_RSTCT1);
 784         omap_writew(1, ARM_RSTCT2);
 785         omap_writew(0x400, ARM_IDLECT1);
 786
 787         /*
 788          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 789          * of the ARM_IDLECT2 register must be set to zero. The power-on
 790          * default value of this bit is one.
 791          */
 792         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 793
 794         /*
 795          * Only enable those clocks we will need, let the drivers
 796          * enable other clocks as necessary
 797          */
 798         clk_enable(&armper_ck.clk);
 799         clk_enable(&armxor_ck.clk);
 800         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 801
 802         if (cpu_is_omap15xx())
 803                 clk_enable(&arm_gpio_ck);
 804
 805         return 0;
 806 }
 807