2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
11 * Create static mapping between physical to virtual memory.
15 #include <linux/init.h>
17 #include <asm/mach/map.h>
19 #include <mach/hardware.h>
20 #include <mach/common.h>
21 #include <mach/devices-common.h>
22 #include <mach/iomux-v3.h>
25 * Define the MX50 memory map.
27 static struct map_desc mx50_io_desc[] __initdata = {
28 imx_map_entry(MX50, TZIC, MT_DEVICE),
29 imx_map_entry(MX50, SPBA0, MT_DEVICE),
30 imx_map_entry(MX50, AIPS1, MT_DEVICE),
31 imx_map_entry(MX50, AIPS2, MT_DEVICE),
35 * Define the MX51 memory map.
37 static struct map_desc mx51_io_desc[] __initdata = {
38 imx_map_entry(MX51, IRAM, MT_DEVICE),
39 imx_map_entry(MX51, DEBUG, MT_DEVICE),
40 imx_map_entry(MX51, AIPS1, MT_DEVICE),
41 imx_map_entry(MX51, SPBA0, MT_DEVICE),
42 imx_map_entry(MX51, AIPS2, MT_DEVICE),
46 * Define the MX53 memory map.
48 static struct map_desc mx53_io_desc[] __initdata = {
49 imx_map_entry(MX53, AIPS1, MT_DEVICE),
50 imx_map_entry(MX53, SPBA0, MT_DEVICE),
51 imx_map_entry(MX53, AIPS2, MT_DEVICE),
55 * This function initializes the memory map. It is called during the
56 * system startup to create static physical to virtual memory mappings
59 void __init mx50_map_io(void)
61 iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
64 void __init mx51_map_io(void)
66 iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
69 void __init mx53_map_io(void)
71 iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
74 void __init imx50_init_early(void)
76 mxc_set_cpu_type(MXC_CPU_MX50);
77 mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
78 mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
81 void __init imx51_init_early(void)
83 mxc_set_cpu_type(MXC_CPU_MX51);
84 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
85 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
88 void __init imx53_init_early(void)
90 mxc_set_cpu_type(MXC_CPU_MX53);
91 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
92 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
95 void __init mx50_init_irq(void)
97 tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
100 void __init mx51_init_irq(void)
102 unsigned long tzic_addr;
103 void __iomem *tzic_virt;
105 if (mx51_revision() < IMX_CHIP_REVISION_2_0)
106 tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
108 tzic_addr = MX51_TZIC_BASE_ADDR;
110 tzic_virt = ioremap(tzic_addr, SZ_16K);
112 panic("unable to map TZIC interrupt controller\n");
114 tzic_init_irq(tzic_virt);
117 void __init mx53_init_irq(void)
119 unsigned long tzic_addr;
120 void __iomem *tzic_virt;
122 tzic_addr = MX53_TZIC_BASE_ADDR;
124 tzic_virt = ioremap(tzic_addr, SZ_16K);
126 panic("unable to map TZIC interrupt controller\n");
128 tzic_init_irq(tzic_virt);
131 static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
133 .uart_2_mcu_addr = 817,
134 .mcu_2_app_addr = 747,
135 .mcu_2_shp_addr = 961,
136 .ata_2_mcu_addr = 1473,
137 .mcu_2_ata_addr = 1392,
138 .app_2_per_addr = 1033,
139 .app_2_mcu_addr = 683,
140 .shp_2_per_addr = 1251,
141 .shp_2_mcu_addr = 892,
144 static struct sdma_platform_data imx51_sdma_pdata __initdata = {
145 .fw_name = "sdma-imx51.bin",
146 .script_addrs = &imx51_sdma_script,
149 static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
151 .app_2_mcu_addr = 683,
152 .mcu_2_app_addr = 747,
153 .uart_2_mcu_addr = 817,
154 .shp_2_mcu_addr = 891,
155 .mcu_2_shp_addr = 960,
156 .uartsh_2_mcu_addr = 1032,
157 .spdif_2_mcu_addr = 1100,
158 .mcu_2_spdif_addr = 1134,
159 .firi_2_mcu_addr = 1193,
160 .mcu_2_firi_addr = 1290,
163 static struct sdma_platform_data imx53_sdma_pdata __initdata = {
164 .fw_name = "sdma-imx53.bin",
165 .script_addrs = &imx53_sdma_script,
168 void __init imx50_soc_init(void)
170 /* i.mx50 has the i.mx31 type gpio */
171 mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
172 mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
173 mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
174 mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
175 mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
176 mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
179 void __init imx51_soc_init(void)
181 /* i.mx51 has the i.mx31 type gpio */
182 mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH);
183 mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH);
184 mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH);
185 mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH);
187 /* i.mx51 has the i.mx35 type sdma */
188 imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
191 void __init imx53_soc_init(void)
193 /* i.mx53 has the i.mx31 type gpio */
194 mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
195 mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
196 mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
197 mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
198 mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
199 mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
200 mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
202 /* i.mx53 has the i.mx35 type sdma */
203 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);