2 * Copyright (C) 2009 Sascha Hauer, Pengutronix
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/types.h>
16 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/mtd/physmap.h>
20 #include <linux/mtd/plat-ram.h>
21 #include <linux/memory.h>
22 #include <linux/gpio.h>
23 #include <linux/smc911x.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/i2c.h>
27 #include <linux/i2c/at24.h>
28 #include <linux/usb/otg.h>
29 #include <linux/usb/ulpi.h>
31 #include <asm/mach-types.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/time.h>
34 #include <asm/mach/map.h>
36 #include <mach/hardware.h>
37 #include <mach/common.h>
38 #include <mach/iomux-mx35.h>
40 #include <mach/mx3fb.h>
41 #include <mach/ulpi.h>
42 #include <mach/audmux.h>
44 #include "devices-imx35.h"
47 static const struct fb_videomode fb_modedb[] = {
50 .name = "Sharp-LQ035Q7",
61 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
62 .vmode = FB_VMODE_NONINTERLACED,
77 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
78 .vmode = FB_VMODE_NONINTERLACED,
83 static struct ipu_platform_data mx3_ipu_data = {
84 .irq_base = MXC_IPU_IRQ_START,
87 static struct mx3fb_platform_data mx3fb_pdata = {
88 .dma_dev = &mx3_ipu.dev,
89 .name = "Sharp-LQ035Q7",
91 .num_modes = ARRAY_SIZE(fb_modedb),
94 static struct physmap_flash_data pcm043_flash_data = {
98 static struct resource pcm043_flash_resource = {
101 .flags = IORESOURCE_MEM,
104 static struct platform_device pcm043_flash = {
105 .name = "physmap-flash",
108 .platform_data = &pcm043_flash_data,
110 .resource = &pcm043_flash_resource,
114 static const struct imxuart_platform_data uart_pdata __initconst = {
115 .flags = IMXUART_HAVE_RTSCTS,
118 static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
122 static struct at24_platform_data board_eeprom = {
125 .flags = AT24_FLAG_ADDR16,
128 static struct i2c_board_info pcm043_i2c_devices[] = {
130 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
131 .platform_data = &board_eeprom,
133 I2C_BOARD_INFO("pcf8563", 0x51),
137 static struct platform_device *devices[] __initdata = {
141 static iomux_v3_cfg_t pcm043_pads[] = {
143 MX35_PAD_CTS1__UART1_CTS,
144 MX35_PAD_RTS1__UART1_RTS,
145 MX35_PAD_TXD1__UART1_TXD_MUX,
146 MX35_PAD_RXD1__UART1_RXD_MUX,
148 MX35_PAD_CTS2__UART2_CTS,
149 MX35_PAD_RTS2__UART2_RTS,
150 MX35_PAD_TXD2__UART2_TXD_MUX,
151 MX35_PAD_RXD2__UART2_RXD_MUX,
153 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
154 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
155 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
156 MX35_PAD_FEC_COL__FEC_COL,
157 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
158 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
159 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
160 MX35_PAD_FEC_MDC__FEC_MDC,
161 MX35_PAD_FEC_MDIO__FEC_MDIO,
162 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
163 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
164 MX35_PAD_FEC_CRS__FEC_CRS,
165 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
166 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
167 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
168 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
169 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
170 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
172 MX35_PAD_I2C1_CLK__I2C1_SCL,
173 MX35_PAD_I2C1_DAT__I2C1_SDA,
175 MX35_PAD_LD0__IPU_DISPB_DAT_0,
176 MX35_PAD_LD1__IPU_DISPB_DAT_1,
177 MX35_PAD_LD2__IPU_DISPB_DAT_2,
178 MX35_PAD_LD3__IPU_DISPB_DAT_3,
179 MX35_PAD_LD4__IPU_DISPB_DAT_4,
180 MX35_PAD_LD5__IPU_DISPB_DAT_5,
181 MX35_PAD_LD6__IPU_DISPB_DAT_6,
182 MX35_PAD_LD7__IPU_DISPB_DAT_7,
183 MX35_PAD_LD8__IPU_DISPB_DAT_8,
184 MX35_PAD_LD9__IPU_DISPB_DAT_9,
185 MX35_PAD_LD10__IPU_DISPB_DAT_10,
186 MX35_PAD_LD11__IPU_DISPB_DAT_11,
187 MX35_PAD_LD12__IPU_DISPB_DAT_12,
188 MX35_PAD_LD13__IPU_DISPB_DAT_13,
189 MX35_PAD_LD14__IPU_DISPB_DAT_14,
190 MX35_PAD_LD15__IPU_DISPB_DAT_15,
191 MX35_PAD_LD16__IPU_DISPB_DAT_16,
192 MX35_PAD_LD17__IPU_DISPB_DAT_17,
193 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
194 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
195 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
196 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
197 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
198 MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
199 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
201 MX35_PAD_ATA_CS0__GPIO2_6,
203 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
204 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
206 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
207 MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
208 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
209 MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
211 MX35_PAD_TX5_RX0__CAN2_TXCAN,
212 MX35_PAD_TX4_RX1__CAN2_RXCAN,
214 MX35_PAD_SD1_CMD__ESDHC1_CMD,
215 MX35_PAD_SD1_CLK__ESDHC1_CLK,
216 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
217 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
218 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
219 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
222 #define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31)
223 #define AC97_GPIO_TXD IMX_GPIO_NR(2, 28)
224 #define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
226 static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
228 iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
229 iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
232 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
234 printk("failed to get GPIO_TXFS: %d\n", ret);
238 mxc_iomux_v3_setup_pad(txfs_gpio);
241 gpio_direction_output(AC97_GPIO_TXFS, 1);
243 gpio_set_value(AC97_GPIO_TXFS, 0);
245 gpio_free(AC97_GPIO_TXFS);
246 mxc_iomux_v3_setup_pad(txfs);
249 static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
251 iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
252 iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
253 iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
254 iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
255 iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
258 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
262 ret = gpio_request(AC97_GPIO_TXD, "SSI");
266 ret = gpio_request(AC97_GPIO_RESET, "SSI");
270 mxc_iomux_v3_setup_pad(txfs_gpio);
271 mxc_iomux_v3_setup_pad(txd_gpio);
272 mxc_iomux_v3_setup_pad(reset_gpio);
274 gpio_direction_output(AC97_GPIO_TXFS, 0);
275 gpio_direction_output(AC97_GPIO_TXD, 0);
278 gpio_direction_output(AC97_GPIO_RESET, 0);
280 gpio_direction_output(AC97_GPIO_RESET, 1);
282 mxc_iomux_v3_setup_pad(txd);
283 mxc_iomux_v3_setup_pad(txfs);
285 gpio_free(AC97_GPIO_RESET);
287 gpio_free(AC97_GPIO_TXD);
289 gpio_free(AC97_GPIO_TXFS);
292 printk("%s failed with %d\n", __func__, ret);
296 static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
297 .ac97_reset = pcm043_ac97_cold_reset,
298 .ac97_warm_reset = pcm043_ac97_warm_reset,
299 .flags = IMX_SSI_USE_AC97,
302 static const struct mxc_nand_platform_data
303 pcm037_nand_board_info __initconst = {
308 static int pcm043_otg_init(struct platform_device *pdev)
310 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
313 static struct mxc_usbh_platform_data otg_pdata __initdata = {
314 .init = pcm043_otg_init,
315 .portsc = MXC_EHCI_MODE_UTMI,
318 static int pcm043_usbh1_init(struct platform_device *pdev)
320 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
321 MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
324 static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
325 .init = pcm043_usbh1_init,
326 .portsc = MXC_EHCI_MODE_SERIAL,
329 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
330 .operating_mode = FSL_USB2_DR_DEVICE,
331 .phy_mode = FSL_USB2_PHY_UTMI,
334 static int otg_mode_host;
336 static int __init pcm043_otg_mode(char *options)
338 if (!strcmp(options, "host"))
340 else if (!strcmp(options, "device"))
343 pr_info("otg_mode neither \"host\" nor \"device\". "
344 "Defaulting to device\n");
347 __setup("otg_mode=", pcm043_otg_mode);
350 * Board specific initialization.
352 static void __init pcm043_init(void)
354 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
356 mxc_audmux_v2_configure_port(3,
357 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
358 MXC_AUDMUX_V2_PTCR_TFSEL(0) |
359 MXC_AUDMUX_V2_PTCR_TFSDIR,
360 MXC_AUDMUX_V2_PDCR_RXDSEL(0));
362 mxc_audmux_v2_configure_port(0,
363 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
364 MXC_AUDMUX_V2_PTCR_TCSEL(3) |
365 MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
366 MXC_AUDMUX_V2_PDCR_RXDSEL(3));
369 platform_add_devices(devices, ARRAY_SIZE(devices));
370 imx35_add_imx2_wdt(NULL);
372 imx35_add_imx_uart0(&uart_pdata);
373 imx35_add_mxc_nand(&pcm037_nand_board_info);
374 imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
376 imx35_add_imx_uart1(&uart_pdata);
378 i2c_register_board_info(0, pcm043_i2c_devices,
379 ARRAY_SIZE(pcm043_i2c_devices));
381 imx35_add_imx_i2c0(&pcm043_i2c0_data);
383 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
384 mxc_register_device(&mx3_fb, &mx3fb_pdata);
387 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
388 ULPI_OTG_DRVVBUS_EXT);
390 imx35_add_mxc_ehci_otg(&otg_pdata);
392 imx35_add_mxc_ehci_hs(&usbh1_pdata);
395 imx35_add_fsl_usb2_udc(&otg_device_pdata);
397 imx35_add_flexcan1(NULL);
398 imx35_add_sdhci_esdhc_imx(0, NULL);
401 static void __init pcm043_timer_init(void)
406 struct sys_timer pcm043_timer = {
407 .init = pcm043_timer_init,
410 MACHINE_START(PCM043, "Phytec Phycore pcm043")
411 /* Maintainer: Pengutronix */
412 .boot_params = MX3x_PHYS_OFFSET + 0x100,
413 .map_io = mx35_map_io,
414 .init_early = imx35_init_early,
415 .init_irq = mx35_init_irq,
416 .timer = &pcm043_timer,
417 .init_machine = pcm043_init,