2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/clk.h>
20 #include <linux/serial_8250.h>
21 #include <linux/gpio.h>
22 #include <linux/i2c.h>
23 #include <linux/irq.h>
25 #include <asm/mach-types.h>
26 #include <asm/mach/arch.h>
27 #include <asm/mach/time.h>
28 #include <asm/memory.h>
29 #include <asm/mach/map.h>
30 #include <mach/common.h>
31 #include <mach/board-mx31ads.h>
32 #include <mach/iomux-mx3.h>
34 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
35 #include <linux/mfd/wm8350/audio.h>
36 #include <linux/mfd/wm8350/core.h>
37 #include <linux/mfd/wm8350/pmic.h>
40 #include "devices-imx31.h"
43 /* PBC Board interrupt status register */
44 #define PBC_INTSTATUS 0x000016
46 /* PBC Board interrupt current status register */
47 #define PBC_INTCURR_STATUS 0x000018
49 /* PBC Interrupt mask register set address */
50 #define PBC_INTMASK_SET 0x00001A
52 /* PBC Interrupt mask register clear address */
53 #define PBC_INTMASK_CLEAR 0x00001C
56 #define PBC_SC16C652_UARTA 0x010000
59 #define PBC_SC16C652_UARTB 0x010010
61 #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
62 #define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
63 #define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
64 #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
66 #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
68 #define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
69 #define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
71 #define MXC_MAX_EXP_IO_LINES 16
73 * This file contains the board-specific initialization routines.
77 * The serial port definition structure.
79 static struct plat_serial8250_port serial_platform_data[] = {
81 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
82 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
83 .irq = EXPIO_INT_XUART_INTA,
87 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
89 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
90 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
91 .irq = EXPIO_INT_XUART_INTB,
95 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
100 static struct platform_device serial_device = {
101 .name = "serial8250",
104 .platform_data = serial_platform_data,
108 static int __init mxc_init_extuart(void)
110 return platform_device_register(&serial_device);
113 static const struct imxuart_platform_data uart_pdata __initconst = {
114 .flags = IMXUART_HAVE_RTSCTS,
117 static unsigned int uart_pins[] = {
124 static inline void mxc_init_imx_uart(void)
126 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
127 imx31_add_imx_uart0(&uart_pdata);
130 static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
136 imr_val = __raw_readw(PBC_INTMASK_SET_REG);
137 int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
139 expio_irq = MXC_EXP_IO_BASE;
140 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
141 if ((int_valid & 1) == 0)
144 generic_handle_irq(expio_irq);
149 * Disable an expio pin's interrupt by setting the bit in the imr.
150 * @param irq an expio virtual irq number
152 static void expio_mask_irq(struct irq_data *d)
154 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
155 /* mask the interrupt */
156 __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
157 __raw_readw(PBC_INTMASK_CLEAR_REG);
161 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
162 * @param irq an expanded io virtual irq number
164 static void expio_ack_irq(struct irq_data *d)
166 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
167 /* clear the interrupt status */
168 __raw_writew(1 << expio, PBC_INTSTATUS_REG);
172 * Enable a expio pin's interrupt by clearing the bit in the imr.
173 * @param irq a expio virtual irq number
175 static void expio_unmask_irq(struct irq_data *d)
177 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
178 /* unmask the interrupt */
179 __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
182 static struct irq_chip expio_irq_chip = {
183 .name = "EXPIO(CPLD)",
184 .irq_ack = expio_ack_irq,
185 .irq_mask = expio_mask_irq,
186 .irq_unmask = expio_unmask_irq,
189 static void __init mx31ads_init_expio(void)
193 printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
196 * Configure INT line as GPIO input
198 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
200 /* disable the interrupt and clear the status */
201 __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
202 __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
203 for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
205 set_irq_chip(i, &expio_irq_chip);
206 set_irq_handler(i, handle_level_irq);
207 set_irq_flags(i, IRQF_VALID);
209 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
210 set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
213 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
214 /* This section defines setup for the Wolfson Microelectronics
215 * 1133-EV1 PMU/audio board. When other PMU boards are supported the
216 * regulator definitions may be shared with them, but for now they can
217 * only be used with this board so would generate warnings about
218 * unused statics and some of the configuration is specific to this
223 static struct regulator_consumer_supply sw1a_consumers[] = {
229 static struct regulator_init_data sw1a_data = {
234 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
235 REGULATOR_CHANGE_MODE,
236 .valid_modes_mask = REGULATOR_MODE_NORMAL |
240 .mode = REGULATOR_MODE_NORMAL,
243 .initial_state = PM_SUSPEND_MEM,
247 .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
248 .consumer_supplies = sw1a_consumers,
251 /* System IO - High */
252 static struct regulator_init_data viohi_data = {
259 .mode = REGULATOR_MODE_NORMAL,
262 .initial_state = PM_SUSPEND_MEM,
268 /* System IO - Low */
269 static struct regulator_init_data violo_data = {
276 .mode = REGULATOR_MODE_NORMAL,
279 .initial_state = PM_SUSPEND_MEM,
286 static struct regulator_init_data sw2a_data = {
291 .valid_modes_mask = REGULATOR_MODE_NORMAL,
294 .mode = REGULATOR_MODE_NORMAL,
298 .mode = REGULATOR_MODE_NORMAL,
303 .initial_state = PM_SUSPEND_MEM,
307 static struct regulator_init_data ldo1_data = {
309 .name = "VCAM/VMMC1/VMMC2",
312 .valid_modes_mask = REGULATOR_MODE_NORMAL,
313 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
318 static struct regulator_consumer_supply ldo2_consumers[] = {
319 { .supply = "AVDD", .dev_name = "1-001a" },
320 { .supply = "HPVDD", .dev_name = "1-001a" },
324 static struct regulator_init_data ldo2_data = {
326 .name = "VESIM/VSIM/AVDD",
329 .valid_modes_mask = REGULATOR_MODE_NORMAL,
330 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
333 .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
334 .consumer_supplies = ldo2_consumers,
338 static struct regulator_init_data vdig_data = {
343 .valid_modes_mask = REGULATOR_MODE_NORMAL,
351 static struct regulator_init_data ldo4_data = {
353 .name = "VRF1/CVDD_2.775",
356 .valid_modes_mask = REGULATOR_MODE_NORMAL,
363 static struct wm8350_led_platform_data wm8350_led_data = {
364 .name = "wm8350:white",
365 .default_trigger = "heartbeat",
369 static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
370 .vmid_discharge_msecs = 1000,
372 .cap_discharge_msecs = 700,
373 .vmid_charge_msecs = 700,
374 .vmid_s_curve = WM8350_S_CURVE_SLOW,
375 .dis_out4 = WM8350_DISCHARGE_SLOW,
376 .dis_out3 = WM8350_DISCHARGE_SLOW,
377 .dis_out2 = WM8350_DISCHARGE_SLOW,
378 .dis_out1 = WM8350_DISCHARGE_SLOW,
379 .vroi_out4 = WM8350_TIE_OFF_500R,
380 .vroi_out3 = WM8350_TIE_OFF_500R,
381 .vroi_out2 = WM8350_TIE_OFF_500R,
382 .vroi_out1 = WM8350_TIE_OFF_500R,
384 .codec_current_on = WM8350_CODEC_ISEL_1_0,
385 .codec_current_standby = WM8350_CODEC_ISEL_0_5,
386 .codec_current_charge = WM8350_CODEC_ISEL_1_5,
389 static int mx31_wm8350_init(struct wm8350 *wm8350)
391 wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
392 WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
393 WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
394 WM8350_GPIO_DEBOUNCE_ON);
396 wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
397 WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
398 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
399 WM8350_GPIO_DEBOUNCE_ON);
401 wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
402 WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
403 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
404 WM8350_GPIO_DEBOUNCE_OFF);
406 wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
407 WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
408 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
409 WM8350_GPIO_DEBOUNCE_OFF);
411 wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
412 WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
413 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
414 WM8350_GPIO_DEBOUNCE_OFF);
416 wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
417 WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
418 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
419 WM8350_GPIO_DEBOUNCE_OFF);
421 wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
422 WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
423 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
424 WM8350_GPIO_DEBOUNCE_OFF);
426 wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
427 wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
428 wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
429 wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
430 wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
431 wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
432 wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
433 wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
436 wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
437 WM8350_DC5_ERRACT_SHUTDOWN_CONV);
438 wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
439 WM8350_ISINK_FLASH_DISABLE,
440 WM8350_ISINK_FLASH_TRIG_BIT,
441 WM8350_ISINK_FLASH_DUR_32MS,
442 WM8350_ISINK_FLASH_ON_INSTANT,
443 WM8350_ISINK_FLASH_OFF_INSTANT,
444 WM8350_ISINK_FLASH_MODE_EN);
445 wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
446 WM8350_ISINK_MODE_BOOST,
447 WM8350_ISINK_ILIM_NORMAL,
449 WM8350_DC5_FBSRC_ISINKA);
450 wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
453 wm8350->codec.platform_data = &imx32ads_wm8350_setup;
455 regulator_has_full_constraints();
460 static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
461 .init = mx31_wm8350_init,
462 .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
466 static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
467 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
469 I2C_BOARD_INFO("wm8350", 0x1a),
470 .platform_data = &mx31_wm8350_pdata,
471 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
476 static void mxc_init_i2c(void)
478 i2c_register_board_info(1, mx31ads_i2c1_devices,
479 ARRAY_SIZE(mx31ads_i2c1_devices));
481 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
482 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
484 imx31_add_imx_i2c1(NULL);
487 static unsigned int ssi_pins[] = {
490 MX31_PIN_SRXD5__SRXD5,
491 MX31_PIN_STXD5__STXD5,
494 static void mxc_init_audio(void)
496 imx31_add_imx_ssi(0, NULL);
497 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
501 * This structure defines static mappings for the i.MX31ADS board.
503 static struct map_desc mx31ads_io_desc[] __initdata = {
505 .virtual = MX31_CS4_BASE_ADDR_VIRT,
506 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
507 .length = MX31_CS4_SIZE / 2,
513 * Set up static virtual mappings.
515 static void __init mx31ads_map_io(void)
518 iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
521 static void __init mx31ads_init_irq(void)
524 mx31ads_init_expio();
528 * Board specific initialization.
530 static void __init mxc_board_init(void)
538 static void __init mx31ads_timer_init(void)
540 mx31_clocks_init(26000000);
543 static struct sys_timer mx31ads_timer = {
544 .init = mx31ads_timer_init,
548 * The following uses standard kernel macros defined in arch.h in order to
549 * initialize __mach_desc_MX31ADS data structure.
551 MACHINE_START(MX31ADS, "Freescale MX31ADS")
552 /* Maintainer: Freescale Semiconductor, Inc. */
553 .boot_params = MX3x_PHYS_OFFSET + 0x100,
554 .map_io = mx31ads_map_io,
555 .init_early = imx31_init_early,
556 .init_irq = mx31ads_init_irq,
557 .timer = &mx31ads_timer,
558 .init_machine = mxc_board_init,