arch/arm/mach-mx3/mach-mx31ads.c

   1 /*
   2  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   4  *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/init.h>
  23 #include <linux/clk.h>
  24 #include <linux/serial_8250.h>
  25 #include <linux/gpio.h>
  26 #include <linux/i2c.h>
  27 #include <linux/irq.h>
  28
  29 #include <mach/hardware.h>
  30 #include <asm/mach-types.h>
  31 #include <asm/mach/arch.h>
  32 #include <asm/mach/time.h>
  33 #include <asm/memory.h>
  34 #include <asm/mach/map.h>
  35 #include <mach/common.h>
  36 #include <mach/board-mx31ads.h>
  37 #include <mach/imx-uart.h>
  38 #include <mach/iomux-mx3.h>
  39
  40 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
  41 #include <linux/mfd/wm8350/audio.h>
  42 #include <linux/mfd/wm8350/core.h>
  43 #include <linux/mfd/wm8350/pmic.h>
  44 #endif
  45
  46 #include "devices.h"
  47
  48 /*!
  49  * @file mx31ads.c
  50  *
  51  * @brief This file contains the board-specific initialization routines.
  52  *
  53  * @ingroup System
  54  */
  55
  56 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
  57 /*!
  58  * The serial port definition structure.
  59  */
  60 static struct plat_serial8250_port serial_platform_data[] = {
  61         {
  62                 .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
  63                 .mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
  64                 .irq      = EXPIO_INT_XUART_INTA,
  65                 .uartclk  = 14745600,
  66                 .regshift = 0,
  67                 .iotype   = UPIO_MEM,
  68                 .flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
  69         }, {
  70                 .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
  71                 .mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
  72                 .irq      = EXPIO_INT_XUART_INTB,
  73                 .uartclk  = 14745600,
  74                 .regshift = 0,
  75                 .iotype   = UPIO_MEM,
  76                 .flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
  77         },
  78         {},
  79 };
  80
  81 static struct platform_device serial_device = {
  82         .name   = "serial8250",
  83         .id     = 0,
  84         .dev    = {
  85                 .platform_data = serial_platform_data,
  86         },
  87 };
  88
  89 static int __init mxc_init_extuart(void)
  90 {
  91         return platform_device_register(&serial_device);
  92 }
  93 #else
  94 static inline int mxc_init_extuart(void)
  95 {
  96         return 0;
  97 }
  98 #endif
  99
 100 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
 101 static struct imxuart_platform_data uart_pdata = {
 102         .flags = IMXUART_HAVE_RTSCTS,
 103 };
 104
 105 static unsigned int uart_pins[] = {
 106         MX31_PIN_CTS1__CTS1,
 107         MX31_PIN_RTS1__RTS1,
 108         MX31_PIN_TXD1__TXD1,
 109         MX31_PIN_RXD1__RXD1
 110 };
 111
 112 static inline void mxc_init_imx_uart(void)
 113 {
 114         mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
 115         mxc_register_device(&mxc_uart_device0, &uart_pdata);
 116 }
 117 #else /* !SERIAL_IMX */
 118 static inline void mxc_init_imx_uart(void)
 119 {
 120 }
 121 #endif /* !SERIAL_IMX */
 122
 123 static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
 124 {
 125         u32 imr_val;
 126         u32 int_valid;
 127         u32 expio_irq;
 128
 129         imr_val = __raw_readw(PBC_INTMASK_SET_REG);
 130         int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
 131
 132         expio_irq = MXC_EXP_IO_BASE;
 133         for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
 134                 if ((int_valid & 1) == 0)
 135                         continue;
 136
 137                 generic_handle_irq(expio_irq);
 138         }
 139 }
 140
 141 /*
 142  * Disable an expio pin's interrupt by setting the bit in the imr.
 143  * @param irq           an expio virtual irq number
 144  */
 145 static void expio_mask_irq(u32 irq)
 146 {
 147         u32 expio = MXC_IRQ_TO_EXPIO(irq);
 148         /* mask the interrupt */
 149         __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
 150         __raw_readw(PBC_INTMASK_CLEAR_REG);
 151 }
 152
 153 /*
 154  * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
 155  * @param irq           an expanded io virtual irq number
 156  */
 157 static void expio_ack_irq(u32 irq)
 158 {
 159         u32 expio = MXC_IRQ_TO_EXPIO(irq);
 160         /* clear the interrupt status */
 161         __raw_writew(1 << expio, PBC_INTSTATUS_REG);
 162 }
 163
 164 /*
 165  * Enable a expio pin's interrupt by clearing the bit in the imr.
 166  * @param irq           a expio virtual irq number
 167  */
 168 static void expio_unmask_irq(u32 irq)
 169 {
 170         u32 expio = MXC_IRQ_TO_EXPIO(irq);
 171         /* unmask the interrupt */
 172         __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
 173 }
 174
 175 static struct irq_chip expio_irq_chip = {
 176         .name = "EXPIO(CPLD)",
 177         .ack = expio_ack_irq,
 178         .mask = expio_mask_irq,
 179         .unmask = expio_unmask_irq,
 180 };
 181
 182 static void __init mx31ads_init_expio(void)
 183 {
 184         int i;
 185
 186         printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
 187
 188         /*
 189          * Configure INT line as GPIO input
 190          */
 191         mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
 192
 193         /* disable the interrupt and clear the status */
 194         __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
 195         __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
 196         for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
 197              i++) {
 198                 set_irq_chip(i, &expio_irq_chip);
 199                 set_irq_handler(i, handle_level_irq);
 200                 set_irq_flags(i, IRQF_VALID);
 201         }
 202         set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
 203         set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
 204 }
 205
 206 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
 207 /* This section defines setup for the Wolfson Microelectronics
 208  * 1133-EV1 PMU/audio board.  When other PMU boards are supported the
 209  * regulator definitions may be shared with them, but for now they can
 210  * only be used with this board so would generate warnings about
 211  * unused statics and some of the configuration is specific to this
 212  * module.
 213  */
 214
 215 /* CPU */
 216 static struct regulator_consumer_supply sw1a_consumers[] = {
 217         {
 218                 .supply = "cpu_vcc",
 219         }
 220 };
 221
 222 static struct regulator_init_data sw1a_data = {
 223         .constraints = {
 224                 .name = "SW1A",
 225                 .min_uV = 1275000,
 226                 .max_uV = 1600000,
 227                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 228                                   REGULATOR_CHANGE_MODE,
 229                 .valid_modes_mask = REGULATOR_MODE_NORMAL |
 230                                     REGULATOR_MODE_FAST,
 231                 .state_mem = {
 232                          .uV = 1400000,
 233                          .mode = REGULATOR_MODE_NORMAL,
 234                          .enabled = 1,
 235                  },
 236                 .initial_state = PM_SUSPEND_MEM,
 237                 .always_on = 1,
 238                 .boot_on = 1,
 239         },
 240         .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
 241         .consumer_supplies = sw1a_consumers,
 242 };
 243
 244 /* System IO - High */
 245 static struct regulator_init_data viohi_data = {
 246         .constraints = {
 247                 .name = "VIOHO",
 248                 .min_uV = 2800000,
 249                 .max_uV = 2800000,
 250                 .state_mem = {
 251                          .uV = 2800000,
 252                          .mode = REGULATOR_MODE_NORMAL,
 253                          .enabled = 1,
 254                  },
 255                 .initial_state = PM_SUSPEND_MEM,
 256                 .always_on = 1,
 257                 .boot_on = 1,
 258         },
 259 };
 260
 261 /* System IO - Low */
 262 static struct regulator_init_data violo_data = {
 263         .constraints = {
 264                 .name = "VIOLO",
 265                 .min_uV = 1800000,
 266                 .max_uV = 1800000,
 267                 .state_mem = {
 268                          .uV = 1800000,
 269                          .mode = REGULATOR_MODE_NORMAL,
 270                          .enabled = 1,
 271                  },
 272                 .initial_state = PM_SUSPEND_MEM,
 273                 .always_on = 1,
 274                 .boot_on = 1,
 275         },
 276 };
 277
 278 /* DDR RAM */
 279 static struct regulator_init_data sw2a_data = {
 280         .constraints = {
 281                 .name = "SW2A",
 282                 .min_uV = 1800000,
 283                 .max_uV = 1800000,
 284                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 285                 .state_mem = {
 286                          .uV = 1800000,
 287                          .mode = REGULATOR_MODE_NORMAL,
 288                          .enabled = 1,
 289                  },
 290                 .state_disk = {
 291                          .mode = REGULATOR_MODE_NORMAL,
 292                          .enabled = 0,
 293                  },
 294                 .always_on = 1,
 295                 .boot_on = 1,
 296                 .initial_state = PM_SUSPEND_MEM,
 297         },
 298 };
 299
 300 static struct regulator_init_data ldo1_data = {
 301         .constraints = {
 302                 .name = "VCAM/VMMC1/VMMC2",
 303                 .min_uV = 2800000,
 304                 .max_uV = 2800000,
 305                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 306                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 307                 .apply_uV = 1,
 308         },
 309 };
 310
 311 static struct regulator_consumer_supply ldo2_consumers[] = {
 312         { .supply = "AVDD", .dev_name = "1-001a" },
 313         { .supply = "HPVDD", .dev_name = "1-001a" },
 314 };
 315
 316 /* CODEC and SIM */
 317 static struct regulator_init_data ldo2_data = {
 318         .constraints = {
 319                 .name = "VESIM/VSIM/AVDD",
 320                 .min_uV = 3300000,
 321                 .max_uV = 3300000,
 322                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 323                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 324                 .apply_uV = 1,
 325         },
 326         .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
 327         .consumer_supplies = ldo2_consumers,
 328 };
 329
 330 /* General */
 331 static struct regulator_init_data vdig_data = {
 332         .constraints = {
 333                 .name = "VDIG",
 334                 .min_uV = 1500000,
 335                 .max_uV = 1500000,
 336                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 337                 .apply_uV = 1,
 338                 .always_on = 1,
 339                 .boot_on = 1,
 340         },
 341 };
 342
 343 /* Tranceivers */
 344 static struct regulator_init_data ldo4_data = {
 345         .constraints = {
 346                 .name = "VRF1/CVDD_2.775",
 347                 .min_uV = 2500000,
 348                 .max_uV = 2500000,
 349                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 350                 .apply_uV = 1,
 351                 .always_on = 1,
 352                 .boot_on = 1,
 353         },
 354 };
 355
 356 static struct wm8350_led_platform_data wm8350_led_data = {
 357         .name            = "wm8350:white",
 358         .default_trigger = "heartbeat",
 359         .max_uA          = 27899,
 360 };
 361
 362 static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
 363         .vmid_discharge_msecs = 1000,
 364         .drain_msecs = 30,
 365         .cap_discharge_msecs = 700,
 366         .vmid_charge_msecs = 700,
 367         .vmid_s_curve = WM8350_S_CURVE_SLOW,
 368         .dis_out4 = WM8350_DISCHARGE_SLOW,
 369         .dis_out3 = WM8350_DISCHARGE_SLOW,
 370         .dis_out2 = WM8350_DISCHARGE_SLOW,
 371         .dis_out1 = WM8350_DISCHARGE_SLOW,
 372         .vroi_out4 = WM8350_TIE_OFF_500R,
 373         .vroi_out3 = WM8350_TIE_OFF_500R,
 374         .vroi_out2 = WM8350_TIE_OFF_500R,
 375         .vroi_out1 = WM8350_TIE_OFF_500R,
 376         .vroi_enable = 0,
 377         .codec_current_on = WM8350_CODEC_ISEL_1_0,
 378         .codec_current_standby = WM8350_CODEC_ISEL_0_5,
 379         .codec_current_charge = WM8350_CODEC_ISEL_1_5,
 380 };
 381
 382 static int mx31_wm8350_init(struct wm8350 *wm8350)
 383 {
 384         wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
 385                            WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
 386                            WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
 387                            WM8350_GPIO_DEBOUNCE_ON);
 388
 389         wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
 390                            WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
 391                            WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
 392                            WM8350_GPIO_DEBOUNCE_ON);
 393
 394         wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
 395                            WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
 396                            WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
 397                            WM8350_GPIO_DEBOUNCE_OFF);
 398
 399         wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
 400                            WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
 401                            WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
 402                            WM8350_GPIO_DEBOUNCE_OFF);
 403
 404         wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
 405                            WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
 406                            WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
 407                            WM8350_GPIO_DEBOUNCE_OFF);
 408
 409         wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
 410                            WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
 411                            WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
 412                            WM8350_GPIO_DEBOUNCE_OFF);
 413
 414         wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
 415                            WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
 416                            WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
 417                            WM8350_GPIO_DEBOUNCE_OFF);
 418
 419         wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
 420         wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
 421         wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
 422         wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
 423         wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
 424         wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
 425         wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
 426         wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
 427
 428         /* LEDs */
 429         wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
 430                              WM8350_DC5_ERRACT_SHUTDOWN_CONV);
 431         wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
 432                                WM8350_ISINK_FLASH_DISABLE,
 433                                WM8350_ISINK_FLASH_TRIG_BIT,
 434                                WM8350_ISINK_FLASH_DUR_32MS,
 435                                WM8350_ISINK_FLASH_ON_INSTANT,
 436                                WM8350_ISINK_FLASH_OFF_INSTANT,
 437                                WM8350_ISINK_FLASH_MODE_EN);
 438         wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
 439                                WM8350_ISINK_MODE_BOOST,
 440                                WM8350_ISINK_ILIM_NORMAL,
 441                                WM8350_DC5_RMP_20V,
 442                                WM8350_DC5_FBSRC_ISINKA);
 443         wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
 444                             &wm8350_led_data);
 445
 446         wm8350->codec.platform_data = &imx32ads_wm8350_setup;
 447
 448         regulator_has_full_constraints();
 449
 450         return 0;
 451 }
 452
 453 static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
 454         .init = mx31_wm8350_init,
 455         .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
 456 };
 457 #endif
 458
 459 #if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE)
 460 static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
 461 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
 462         {
 463                 I2C_BOARD_INFO("wm8350", 0x1a),
 464                 .platform_data = &mx31_wm8350_pdata,
 465                 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
 466         },
 467 #endif
 468 };
 469
 470 static void mxc_init_i2c(void)
 471 {
 472         i2c_register_board_info(1, mx31ads_i2c1_devices,
 473                                 ARRAY_SIZE(mx31ads_i2c1_devices));
 474
 475         mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
 476         mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
 477
 478         mxc_register_device(&mxc_i2c_device1, NULL);
 479 }
 480 #else
 481 static void mxc_init_i2c(void)
 482 {
 483 }
 484 #endif
 485
 486 static unsigned int ssi_pins[] = {
 487         MX31_PIN_SFS5__SFS5,
 488         MX31_PIN_SCK5__SCK5,
 489         MX31_PIN_SRXD5__SRXD5,
 490         MX31_PIN_STXD5__STXD5,
 491 };
 492
 493 static void mxc_init_audio(void)
 494 {
 495         mxc_register_device(&imx_ssi_device0, NULL);
 496         mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
 497 }
 498
 499 /*!
 500  * This structure defines static mappings for the i.MX31ADS board.
 501  */
 502 static struct map_desc mx31ads_io_desc[] __initdata = {
 503         {
 504                 .virtual        = MX31_CS4_BASE_ADDR_VIRT,
 505                 .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
 506                 .length         = MX31_CS4_SIZE / 2,
 507                 .type           = MT_DEVICE
 508         },
 509 };
 510
 511 /*!
 512  * Set up static virtual mappings.
 513  */
 514 static void __init mx31ads_map_io(void)
 515 {
 516         mx31_map_io();
 517         iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
 518 }
 519
 520 static void __init mx31ads_init_irq(void)
 521 {
 522         mx31_init_irq();
 523         mx31ads_init_expio();
 524 }
 525
 526 /*!
 527  * Board specific initialization.
 528  */
 529 static void __init mxc_board_init(void)
 530 {
 531         mxc_init_extuart();
 532         mxc_init_imx_uart();
 533         mxc_init_i2c();
 534         mxc_init_audio();
 535 }
 536
 537 static void __init mx31ads_timer_init(void)
 538 {
 539         mx31_clocks_init(26000000);
 540 }
 541
 542 static struct sys_timer mx31ads_timer = {
 543         .init   = mx31ads_timer_init,
 544 };
 545
 546 /*
 547  * The following uses standard kernel macros defined in arch.h in order to
 548  * initialize __mach_desc_MX31ADS data structure.
 549  */
 550 MACHINE_START(MX31ADS, "Freescale MX31ADS")
 551         /* Maintainer: Freescale Semiconductor, Inc. */
 552         .phys_io        = MX31_AIPS1_BASE_ADDR,
 553         .io_pg_offst    = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
 554         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
 555         .map_io         = mx31ads_map_io,
 556         .init_irq       = mx31ads_init_irq,
 557         .init_machine   = mxc_board_init,
 558         .timer          = &mx31ads_timer,
 559 MACHINE_END