2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/types.h>
20 #include <linux/init.h>
21 #include <linux/clk.h>
22 #include <linux/irq.h>
23 #include <linux/gpio.h>
24 #include <linux/smsc911x.h>
25 #include <linux/platform_device.h>
27 #include <mach/hardware.h>
28 #include <asm/mach-types.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/time.h>
31 #include <asm/memory.h>
32 #include <asm/mach/map.h>
33 #include <mach/common.h>
34 #include <mach/board-mx31_3ds.h>
35 #include <mach/imx-uart.h>
36 #include <mach/iomux-mx3.h>
37 #include <mach/mxc_nand.h>
44 * @brief This file contains the board-specific initialization routines.
49 static int mx31_3ds_pins[] = {
55 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
57 MX31_PIN_CSPI2_SCLK__SCLK,
58 MX31_PIN_CSPI2_MOSI__MOSI,
59 MX31_PIN_CSPI2_MISO__MISO,
60 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
61 MX31_PIN_CSPI2_SS0__SS0,
62 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
66 static int spi1_internal_chipselect[] = {
71 static struct spi_imx_master spi1_pdata = {
72 .chipselect = spi1_internal_chipselect,
73 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
79 static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
82 #ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
87 static struct imxuart_platform_data uart_pdata = {
88 .flags = IMXUART_HAVE_RTSCTS,
92 * Support for the SMSC9217 on the Debug board.
95 static struct smsc911x_platform_config smsc911x_config = {
96 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
97 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
98 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
99 .phy_interface = PHY_INTERFACE_MODE_MII,
102 static struct resource smsc911x_resources[] = {
104 .start = LAN9217_BASE_ADDR,
105 .end = LAN9217_BASE_ADDR + 0xff,
106 .flags = IORESOURCE_MEM,
108 .start = EXPIO_INT_ENET,
109 .end = EXPIO_INT_ENET,
110 .flags = IORESOURCE_IRQ,
114 static struct platform_device smsc911x_device = {
117 .num_resources = ARRAY_SIZE(smsc911x_resources),
118 .resource = smsc911x_resources,
120 .platform_data = &smsc911x_config,
125 * Routines for the CPLD on the debug board. It contains a CPLD handling
126 * LEDs, switches, interrupts for Ethernet.
129 static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
135 imr_val = __raw_readw(CPLD_INT_MASK_REG);
136 int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
138 expio_irq = MXC_EXP_IO_BASE;
139 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
140 if ((int_valid & 1) == 0)
142 generic_handle_irq(expio_irq);
147 * Disable an expio pin's interrupt by setting the bit in the imr.
148 * @param irq an expio virtual irq number
150 static void expio_mask_irq(uint32_t irq)
153 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
155 /* mask the interrupt */
156 reg = __raw_readw(CPLD_INT_MASK_REG);
158 __raw_writew(reg, CPLD_INT_MASK_REG);
162 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
163 * @param irq an expanded io virtual irq number
165 static void expio_ack_irq(uint32_t irq)
167 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
169 /* clear the interrupt status */
170 __raw_writew(1 << expio, CPLD_INT_RESET_REG);
171 __raw_writew(0, CPLD_INT_RESET_REG);
172 /* mask the interrupt */
177 * Enable a expio pin's interrupt by clearing the bit in the imr.
178 * @param irq a expio virtual irq number
180 static void expio_unmask_irq(uint32_t irq)
183 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
185 /* unmask the interrupt */
186 reg = __raw_readw(CPLD_INT_MASK_REG);
187 reg &= ~(1 << expio);
188 __raw_writew(reg, CPLD_INT_MASK_REG);
191 static struct irq_chip expio_irq_chip = {
192 .ack = expio_ack_irq,
193 .mask = expio_mask_irq,
194 .unmask = expio_unmask_irq,
197 static int __init mx31_3ds_init_expio(void)
202 /* Check if there's a debug board connected */
203 if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
204 (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
205 (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
206 /* No Debug board found */
210 pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
211 __raw_readw(CPLD_CODE_VER_REG));
214 * Configure INT line as GPIO input
216 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
218 pr_warning("could not get LAN irq gpio\n");
220 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
222 /* Disable the interrupts and clear the status */
223 __raw_writew(0, CPLD_INT_MASK_REG);
224 __raw_writew(0xFFFF, CPLD_INT_RESET_REG);
225 __raw_writew(0, CPLD_INT_RESET_REG);
226 __raw_writew(0x1F, CPLD_INT_MASK_REG);
227 for (i = MXC_EXP_IO_BASE;
228 i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
230 set_irq_chip(i, &expio_irq_chip);
231 set_irq_handler(i, handle_level_irq);
232 set_irq_flags(i, IRQF_VALID);
234 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
235 set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
241 * This structure defines the MX31 memory map.
243 static struct map_desc mx31_3ds_io_desc[] __initdata = {
245 .virtual = MX31_CS5_BASE_ADDR_VIRT,
246 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
247 .length = MX31_CS5_SIZE,
253 * Set up static virtual mappings.
255 static void __init mx31_3ds_map_io(void)
258 iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
262 * Board specific initialization.
264 static void __init mxc_board_init(void)
266 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
269 mxc_register_device(&mxc_uart_device0, &uart_pdata);
270 mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
271 mxc_register_device(&mxc_spi_device1, &spi1_pdata);
273 if (!mx31_3ds_init_expio())
274 platform_device_register(&smsc911x_device);
277 static void __init mx31_3ds_timer_init(void)
279 mx31_clocks_init(26000000);
282 static struct sys_timer mx31_3ds_timer = {
283 .init = mx31_3ds_timer_init,
287 * The following uses standard kernel macros defined in arch.h in order to
288 * initialize __mach_desc_MX31_3DS data structure.
290 MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
291 /* Maintainer: Freescale Semiconductor, Inc. */
292 .phys_io = MX31_AIPS1_BASE_ADDR,
293 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
294 .boot_params = MX3x_PHYS_OFFSET + 0x100,
295 .map_io = mx31_3ds_map_io,
296 .init_irq = mx31_init_irq,
297 .init_machine = mxc_board_init,
298 .timer = &mx31_3ds_timer,