arch/arm/mach-mx3/devices.c

   1 /*
   2  * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor,
  17  * Boston, MA  02110-1301, USA.
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/serial.h>
  24 #include <linux/gpio.h>
  25 #include <mach/hardware.h>
  26 #include <mach/irqs.h>
  27 #include <mach/common.h>
  28 #include <mach/mx3_camera.h>
  29
  30 #include "devices.h"
  31
  32 #ifdef CONFIG_ARCH_MX31
  33 static struct resource mxcsdhc0_resources[] = {
  34         {
  35                 .start = MX31_MMC_SDHC1_BASE_ADDR,
  36                 .end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
  37                 .flags = IORESOURCE_MEM,
  38         }, {
  39                 .start = MX31_INT_MMC_SDHC1,
  40                 .end = MX31_INT_MMC_SDHC1,
  41                 .flags = IORESOURCE_IRQ,
  42         },
  43 };
  44
  45 static struct resource mxcsdhc1_resources[] = {
  46         {
  47                 .start = MX31_MMC_SDHC2_BASE_ADDR,
  48                 .end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
  49                 .flags = IORESOURCE_MEM,
  50         }, {
  51                 .start = MX31_INT_MMC_SDHC2,
  52                 .end = MX31_INT_MMC_SDHC2,
  53                 .flags = IORESOURCE_IRQ,
  54         },
  55 };
  56
  57 struct platform_device mxcsdhc_device0 = {
  58         .name = "mxc-mmc",
  59         .id = 0,
  60         .num_resources = ARRAY_SIZE(mxcsdhc0_resources),
  61         .resource = mxcsdhc0_resources,
  62 };
  63
  64 struct platform_device mxcsdhc_device1 = {
  65         .name = "mxc-mmc",
  66         .id = 1,
  67         .num_resources = ARRAY_SIZE(mxcsdhc1_resources),
  68         .resource = mxcsdhc1_resources,
  69 };
  70
  71 static struct resource rnga_resources[] = {
  72         {
  73                 .start = MX3x_RNGA_BASE_ADDR,
  74                 .end = MX3x_RNGA_BASE_ADDR + 0x28,
  75                 .flags = IORESOURCE_MEM,
  76         },
  77 };
  78
  79 struct platform_device mxc_rnga_device = {
  80         .name = "mxc_rnga",
  81         .id = -1,
  82         .num_resources = 1,
  83         .resource = rnga_resources,
  84 };
  85 #endif /* CONFIG_ARCH_MX31 */
  86
  87 /* i.MX31 Image Processing Unit */
  88
  89 /* The resource order is important! */
  90 static struct resource mx3_ipu_rsrc[] = {
  91         {
  92                 .start = MX3x_IPU_CTRL_BASE_ADDR,
  93                 .end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F,
  94                 .flags = IORESOURCE_MEM,
  95         }, {
  96                 .start = MX3x_IPU_CTRL_BASE_ADDR + 0x88,
  97                 .end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3,
  98                 .flags = IORESOURCE_MEM,
  99         }, {
 100                 .start = MX3x_INT_IPU_SYN,
 101                 .end = MX3x_INT_IPU_SYN,
 102                 .flags = IORESOURCE_IRQ,
 103         }, {
 104                 .start = MX3x_INT_IPU_ERR,
 105                 .end = MX3x_INT_IPU_ERR,
 106                 .flags = IORESOURCE_IRQ,
 107         },
 108 };
 109
 110 struct platform_device mx3_ipu = {
 111         .name = "ipu-core",
 112         .id = -1,
 113         .num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
 114         .resource = mx3_ipu_rsrc,
 115 };
 116
 117 static struct resource fb_resources[] = {
 118         {
 119                 .start  = MX3x_IPU_CTRL_BASE_ADDR + 0xB4,
 120                 .end    = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF,
 121                 .flags  = IORESOURCE_MEM,
 122         },
 123 };
 124
 125 struct platform_device mx3_fb = {
 126         .name           = "mx3_sdc_fb",
 127         .id             = -1,
 128         .num_resources  = ARRAY_SIZE(fb_resources),
 129         .resource       = fb_resources,
 130         .dev            = {
 131                 .coherent_dma_mask = DMA_BIT_MASK(32),
 132        },
 133 };
 134
 135 static struct resource camera_resources[] = {
 136         {
 137                 .start  = MX3x_IPU_CTRL_BASE_ADDR + 0x60,
 138                 .end    = MX3x_IPU_CTRL_BASE_ADDR + 0x87,
 139                 .flags  = IORESOURCE_MEM,
 140         },
 141 };
 142
 143 struct platform_device mx3_camera = {
 144         .name           = "mx3-camera",
 145         .id             = 0,
 146         .num_resources  = ARRAY_SIZE(camera_resources),
 147         .resource       = camera_resources,
 148         .dev            = {
 149                 .coherent_dma_mask = DMA_BIT_MASK(32),
 150         },
 151 };
 152
 153 static struct resource otg_resources[] = {
 154         {
 155                 .start  = MX31_OTG_BASE_ADDR,
 156                 .end    = MX31_OTG_BASE_ADDR + 0x1ff,
 157                 .flags  = IORESOURCE_MEM,
 158         }, {
 159                 .start  = MX31_INT_USB3,
 160                 .end    = MX31_INT_USB3,
 161                 .flags  = IORESOURCE_IRQ,
 162         },
 163 };
 164
 165 static u64 otg_dmamask = DMA_BIT_MASK(32);
 166
 167 /* OTG gadget device */
 168 struct platform_device mxc_otg_udc_device = {
 169         .name           = "fsl-usb2-udc",
 170         .id             = -1,
 171         .dev            = {
 172                 .dma_mask               = &otg_dmamask,
 173                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 174         },
 175         .resource       = otg_resources,
 176         .num_resources  = ARRAY_SIZE(otg_resources),
 177 };
 178
 179 /* OTG host */
 180 struct platform_device mxc_otg_host = {
 181         .name = "mxc-ehci",
 182         .id = 0,
 183         .dev = {
 184                 .coherent_dma_mask = 0xffffffff,
 185                 .dma_mask = &otg_dmamask,
 186         },
 187         .resource = otg_resources,
 188         .num_resources = ARRAY_SIZE(otg_resources),
 189 };
 190
 191 /* USB host 1 */
 192
 193 static u64 usbh1_dmamask = ~(u32)0;
 194
 195 static struct resource mxc_usbh1_resources[] = {
 196         {
 197                 .start = MX31_OTG_BASE_ADDR + 0x200,
 198                 .end = MX31_OTG_BASE_ADDR + 0x3ff,
 199                 .flags = IORESOURCE_MEM,
 200         }, {
 201                 .start = MX31_INT_USB1,
 202                 .end = MX31_INT_USB1,
 203                 .flags = IORESOURCE_IRQ,
 204         },
 205 };
 206
 207 struct platform_device mxc_usbh1 = {
 208         .name = "mxc-ehci",
 209         .id = 1,
 210         .dev = {
 211                 .coherent_dma_mask = 0xffffffff,
 212                 .dma_mask = &usbh1_dmamask,
 213         },
 214         .resource = mxc_usbh1_resources,
 215         .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
 216 };
 217
 218 #ifdef CONFIG_ARCH_MX31
 219 /* USB host 2 */
 220 static u64 usbh2_dmamask = ~(u32)0;
 221
 222 static struct resource mxc_usbh2_resources[] = {
 223         {
 224                 .start = MX31_OTG_BASE_ADDR + 0x400,
 225                 .end = MX31_OTG_BASE_ADDR + 0x5ff,
 226                 .flags = IORESOURCE_MEM,
 227         }, {
 228                 .start = MX31_INT_USB2,
 229                 .end = MX31_INT_USB2,
 230                 .flags = IORESOURCE_IRQ,
 231         },
 232 };
 233
 234 struct platform_device mxc_usbh2 = {
 235         .name = "mxc-ehci",
 236         .id = 2,
 237         .dev = {
 238                 .coherent_dma_mask = 0xffffffff,
 239                 .dma_mask = &usbh2_dmamask,
 240         },
 241         .resource = mxc_usbh2_resources,
 242         .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
 243 };
 244 #endif
 245
 246 static struct resource imx_wdt_resources[] = {
 247         {
 248                 .flags = IORESOURCE_MEM,
 249         },
 250 };
 251
 252 struct platform_device imx_wdt_device0 = {
 253         .name           = "imx2-wdt",
 254         .id             = 0,
 255         .num_resources  = ARRAY_SIZE(imx_wdt_resources),
 256         .resource       = imx_wdt_resources,
 257 };
 258
 259 static struct resource imx_rtc_resources[] = {
 260         {
 261                 .start  = MX31_RTC_BASE_ADDR,
 262                 .end    = MX31_RTC_BASE_ADDR + 0x3fff,
 263                 .flags  = IORESOURCE_MEM,
 264         },
 265         {
 266                 .start  = MX31_INT_RTC,
 267                 .flags  = IORESOURCE_IRQ,
 268         },
 269 };
 270
 271 struct platform_device imx_rtc_device0 = {
 272         .name           = "mxc_rtc",
 273         .id             = -1,
 274         .num_resources  = ARRAY_SIZE(imx_rtc_resources),
 275         .resource       = imx_rtc_resources,
 276 };
 277
 278 static struct resource imx_kpp_resources[] = {
 279         {
 280                 .start  = MX3x_KPP_BASE_ADDR,
 281                 .end    = MX3x_KPP_BASE_ADDR + 0xf,
 282                 .flags  = IORESOURCE_MEM
 283         }, {
 284                 .start  = MX3x_INT_KPP,
 285                 .end    = MX3x_INT_KPP,
 286                 .flags  = IORESOURCE_IRQ,
 287         },
 288 };
 289
 290 struct platform_device imx_kpp_device = {
 291         .name = "imx-keypad",
 292         .id = -1,
 293         .num_resources = ARRAY_SIZE(imx_kpp_resources),
 294         .resource = imx_kpp_resources,
 295 };
 296
 297 static int __init mx3_devices_init(void)
 298 {
 299 #if defined(CONFIG_ARCH_MX31)
 300         if (cpu_is_mx31()) {
 301                 imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
 302                 imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
 303                 mxc_register_device(&mxc_rnga_device, NULL);
 304         }
 305 #endif
 306 #if defined(CONFIG_ARCH_MX35)
 307         if (cpu_is_mx35()) {
 308                 otg_resources[0].start = MX35_OTG_BASE_ADDR;
 309                 otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
 310                 otg_resources[1].start = MX35_INT_USBOTG;
 311                 otg_resources[1].end = MX35_INT_USBOTG;
 312                 mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
 313                 mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
 314                 mxc_usbh1_resources[1].start = MX35_INT_USBHS;
 315                 mxc_usbh1_resources[1].end = MX35_INT_USBHS;
 316                 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
 317                 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
 318         }
 319 #endif
 320
 321         return 0;
 322 }
 323
 324 subsys_initcall(mx3_devices_init);